US20190184480A1 - Precise Alignment and Decal Bonding of a Pattern of Solder Preforms to a Surface - Google Patents

Precise Alignment and Decal Bonding of a Pattern of Solder Preforms to a Surface Download PDF

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Publication number
US20190184480A1
US20190184480A1 US16/218,459 US201816218459A US2019184480A1 US 20190184480 A1 US20190184480 A1 US 20190184480A1 US 201816218459 A US201816218459 A US 201816218459A US 2019184480 A1 US2019184480 A1 US 2019184480A1
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United States
Prior art keywords
solder
release tape
pattern
preforms
bonding
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US16/218,459
Inventor
Raymond C.Y. Auyeung
Joseph C. Prestigiacomo
Michael S. Osofsky
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US Department of Navy
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US Department of Navy
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Priority to US16/218,459 priority Critical patent/US20190184480A1/en
Assigned to THE GOVERNMENT OF THE UNITED STATES OF AMERICA, AS REPRESENTED BY THE SECRETARY OF THE NAVY reassignment THE GOVERNMENT OF THE UNITED STATES OF AMERICA, AS REPRESENTED BY THE SECRETARY OF THE NAVY ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: AUYEUNG, RAYMOND, OSOFSKY, MICHAEL, PRESTIGIACOMO, Joseph
Publication of US20190184480A1 publication Critical patent/US20190184480A1/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01B—CABLES; CONDUCTORS; INSULATORS; SELECTION OF MATERIALS FOR THEIR CONDUCTIVE, INSULATING OR DIELECTRIC PROPERTIES
    • H01B12/00—Superconductive or hyperconductive conductors, cables, or transmission lines
    • H01B12/02—Superconductive or hyperconductive conductors, cables, or transmission lines characterised by their form
    • H01B12/06—Films or wires on bases or cores
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K3/00—Tools, devices, or special appurtenances for soldering, e.g. brazing, or unsoldering, not specially adapted for particular methods
    • B23K3/06—Solder feeding devices; Solder melting pans
    • B23K3/0607—Solder feeding devices
    • B23K3/0623—Solder feeding devices for shaped solder piece feeding, e.g. preforms, bumps, balls, pellets, droplets
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K1/00—Soldering, e.g. brazing, or unsoldering
    • B23K1/0008—Soldering, e.g. brazing, or unsoldering specially adapted for particular articles or work
    • B23K1/0016—Brazing of electronic components
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
    • B23K35/02—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by mechanical features, e.g. shape
    • B23K35/0222—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by mechanical features, e.g. shape for use in soldering, brazing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01B—CABLES; CONDUCTORS; INSULATORS; SELECTION OF MATERIALS FOR THEIR CONDUCTIVE, INSULATING OR DIELECTRIC PROPERTIES
    • H01B13/00—Apparatus or processes specially adapted for manufacturing conductors or cables
    • H01B13/0036—Details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
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    • H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
    • H01L21/681—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment using optical controlling means
    • H—ELECTRICITY
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    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/6838—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping with gripping and holding devices using a vacuum; Bernoulli devices
    • H—ELECTRICITY
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H01L39/24—
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457—Solder materials or compositions; Methods of application thereof
    • H05K3/3478—Applying solder preforms; Transferring prefabricated solder patterns
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00—Superconducting devices
    • H10N60/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00—Superconducting devices
    • H10N60/01—Manufacture or treatment
    • H10N60/0268—Manufacture or treatment of devices comprising copper oxide
    • H10N60/0661—Processes performed after copper oxide formation, e.g. patterning
    • H10N60/0688—Etching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00—Superconducting devices
    • H10N60/01—Manufacture or treatment
    • H10N60/0268—Manufacture or treatment of devices comprising copper oxide
    • H10N60/0801—Manufacture or treatment of filaments or composite wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00—Superconducting devices
    • H10N60/20—Permanent superconducting devices
    • H10N60/203—Permanent superconducting devices comprising high-Tc ceramic materials
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K2101/00—Articles made by soldering, welding or cutting
    • B23K2101/36—Electric or electronic devices
    • B23K2101/42—Printed circuits
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
    • B23K35/22—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by the composition or nature of the material
    • B23K35/24—Selection of soldering or welding materials proper
    • B23K35/26—Selection of soldering or welding materials proper with the principal constituent melting at less than 400 degrees C
    • B23K35/264—Bi as the principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68309—Auxiliary support including alignment aids
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/03001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
    • H01L2224/03003—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for holding or transferring a preform
    • H—ELECTRICITY
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/031—Manufacture and pre-treatment of the bonding area preform
    • H01L2224/0311—Shaping
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/05109—Indium [In] as principal constituent
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/05113—Bismuth [Bi] as principal constituent
    • H—ELECTRICITY
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    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/05—Patterning and lithography; Masks; Details of resist
    • H05K2203/0502—Patterning and lithography
    • H05K2203/0531—Decalcomania, i.e. transfer of a pattern detached from its carrier before affixing the pattern to the substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/10—Using electric, magnetic and electromagnetic fields; Using laser light
    • H05K2203/107—Using laser light
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    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
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    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/15—Position of the PCB during processing
    • H05K2203/1545—Continuous processing, i.e. involving rolls moving a band-like or solid carrier along a continuous production path
    • H—ELECTRICITY
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    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/16—Inspection; Monitoring; Aligning
    • H05K2203/167—Using mechanical means for positioning, alignment or registration, e.g. using rod-in-hole alignment
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E40/00—Technologies for an efficient electrical power generation, transmission or distribution
    • Y02E40/60—Superconducting electric elements or equipment; Power systems integrating superconducting elements or equipment
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P80/00—Climate change mitigation technologies for sector-wide applications
    • Y02P80/30—Reducing waste in manufacturing processes; Calculations of released waste quantities

Definitions

  • This disclosure concerns precise alignment and decal bonding of a pattern of solder preforms to a surface.
  • surface and ‘sample’, ‘receiving’ and ‘target’ will be used interchangeably in this invention.
  • Solder preforms are precisely formed elements of solder available commercially in various sizes, shapes, thickness and compositions (with or without flux) that deliver a consistent volume of solder to a joint area.
  • An alternative method of placing a high volume of solder preforms is to use a fixture with a matching pattern to the pad/connector locations on a receiving surface.
  • Another high volume placement method is to use an array of preforms all connected together with thin links of solder. These links are designed to melt and reflow completely back to the solder preform mass without leaving any solder residue that would cause electrical shorting.
  • Solder preforms are traditionally made by stamping solder wire or foils into the desired shape.
  • One problem associated with stamping is the curvature of the surface of the preform caused by the forces acting on it during the stamping process.
  • the curved surface may reduce the seal between the preform and the vacuum nozzle in an SMT machine resulting in less reliable pick-up and release of the preform. This curvature worsens as the thickness of the preform decreases.
  • solder preforms have been used to minimize waste of material and decrease raised edges or burrs in the preform after stamping.
  • solder preforms were cut individually and not aligned to any pre-defined pattern in a receiving surface.
  • Solder preforms can be placed over a receiving pattern of interest by loading the preforms in a matching pattern of openings in a locating plate and then releasing the preforms by mechanical, vibratory, air or sound pressure means.
  • the preforms also rely on tacky media on the receiving surface such as solder paste to separate the preforms from the locating plate and to adhere to the receiving surface.
  • the existing techniques place patterns of solder preforms of a predefined regular shape and size on a receiving surface by first loading and securing the preforms mechanically on a recessed holder consisting of an array of openings (such as a stencil or channels), then aligning them over the receiving pattern and releasing the preforms by various actuating means.
  • the shape and size of each solder preform is usually fixed for the entire receiving pattern and not easily changed without redesigning and refabricating the recessed holder.
  • the preform shape is regular in that the preform can land on the receiving sample in any spatial orientation.
  • solder landing area of the receiving pattern This simplifies the loading of the preforms and operation of the release apparatus but requires the solder landing area of the receiving pattern to be symmetric and regular in shape in both two and three dimensions.
  • Irregularly shaped and very thin ( ⁇ 0.25 mm) solder preforms that may be required for highly specialized applications may not be easily handled by current techniques.
  • spatial tolerance or variation in the placement of the solder preforms from current techniques Very thin ( ⁇ 0.2 mm thick) and low mass solder preforms are required for fine electronics circuitry (such as high-temperature superconducting (HTS) tapes or foils) and placing them on a receiving sample with high precision ( ⁇ tens of microns tolerance) is a long-standing problem with the prior art techniques.
  • HTS high-temperature superconducting
  • a new and an efficient method for depositing a pattern of such solder preforms onto a receiving surface is required.
  • This disclosure describes a method for placing a pattern of solder preforms simultaneously at multiple locations and bonding them onto a surface with microscopic precision.
  • This new process described herein is an efficient and scalable method for bonding electrical circuit patterns at specific locations between an upper and lower surface.
  • the pattern of solder preforms is fabricated on a release tape and has indexed alignment holes at prescribed locations.
  • This indexed tape design allows simple integration into a reel-to-reel system for commercial applications.
  • This method is especially applicable to solder bonding the overlay of filaments from upper and lower high-temperature superconducting (HTS) tapes.
  • HTS high-temperature superconducting
  • This method can also be generalized to allow parallel solder bonding of microscopic features at precise locations between any two overlaid adjacent surfaces.
  • This disclosure teaches methods and products concerning precise alignment and decal bonding of a pattern of solder preforms to a surface.
  • This new process described herein is an efficient and scalable method for bonding electrical circuit patterns at specific locations between an upper and lower surface.
  • the pattern of solder preforms is fabricated on a release tape and has indexed alignment holes at prescribed locations.
  • This indexed tape design allows simple integration into a reel-to-reel system for commercial applications.
  • This method is especially applicable to solder bonding the overlay of filaments from upper and lower high-temperature superconducting (HTS) tapes.
  • HTS high-temperature superconducting
  • This method can also be generalized to allow parallel solder bonding of microscopic features at precise locations between any two overlaid adjacent surfaces.
  • the pattern of solder preforms is prefabricated on a release tape.
  • solder preform release tape has indexed registration holes that are aligned with those on a receiving surface.
  • this method is adaptable to a reel-to-reel manufacturing system.
  • this method can apply and bond patterns of solder preforms to electrically connect current-carrying filaments in an HTS tape structure.
  • the Decal Imprinting and Bonding of Solder (DIBS) process consists of three steps—the fabrication of the solder preforms (shape and spacing) on the release tape, the alignment and placement of the release tape over a target surface, and release of the individual solder preforms from the release tape onto the target surface and their subsequent bonding to the target surface.
  • the solder preforms can be detached from the release tape and bonded to the target surface by mechanical, thermal or photonic means.
  • a strip of semiconductor dicing tape such as ‘low-tack blue’
  • Components attached to ‘low tack blue’ dicing tape can be removed mechanically.
  • Other types of dicing tape can use heat (Nitto “Revalpha”) or UV light (DU-300) to lower its adhesion properties in order to release its attached components.
  • a strip of dicing or release tape about the same size and shape as the target surface is secured to a stable surface (e.g. vacuum chuck).
  • a ribbon of solder of fixed thickness e.g. Indium Bismuth eutectic
  • the same laser is used to drill indexing holes into the release tape outside the solder bonding area.
  • the laser drilling of the index holes and the laser perforation of the solder preforms must be done in the same setup without physically disturbing the release tape.
  • the solder ribbon can be carefully peeled off the release tape, leaving behind the pattern of the desired solder preforms.
  • the size, shape and location of indexing holes of the release tape can be adapted for use in a reel-to-reel system, for example, regularly-spaced holes along both edges of the tape to match index pins on a reel.
  • solder preform tape can now be guided over the corresponding indexing pins of an alignment jig, which holds the target surface, and the solder side placed over and pressed onto the target surface.
  • Solder preforms such as InBi, can be mechanically released from the dicing tape and then pressure and/or thermally treated to bond to a compatible surface in a single step. The release tape can then be removed leaving behind a precisely spaced pattern of solder preforms on the target surface. Note that additional layers or tapes with the same pattern of indexing holes can now be precisely aligned and placed over this first layer of solder preforms.
  • FIG. 1 shows a finished blue ‘low tack’ release tape with a set of solder preforms ready for use.
  • the keys to ensuring high placement accuracy of the solder pattern onto a receiving surface are: 1) to fabricate indexing holes in both the release tape containing the solder preforms and the receiving surface(s) and 2) to fabricate the ‘complementary’ indexing pins on an alignment jig.
  • the alignment jig is a device or structure that helps align and assemble all the separate components together on a 2-D planar or 3-D curved surface with high precision. With judicious choice of indexing holes and pins, individual components are aligned to less than 50 microns spatial tolerance. Other methods of indexing components such as mechanical means (e.g. notches, holes, guides) or optical means (e.g. laser, LED, lamp) can be used. As long as there is a ‘complementary’ structure on the alignment jig to match the indexed component, then high spatial accuracy can be maintained.
  • FIG. 1 illustrates a photograph of ‘blue low-tack’ dicing/release tape with solder preforms.
  • FIG. 2 illustrates step-by-step diagram of the general DIBS process.
  • This disclosure teaches precise alignment and decal bonding of a pattern of solder preforms to a surface.
  • This invention fabricates arbitrarily-shaped solder elements in an arbitrary pattern onto a release tape layer and then places all of them with microscopic precision onto a surface at the same time.
  • DIBS Decal Imprinting and Bonding of Solder
  • DIBS Decal Imprinting and Bonding of Solder
  • solder preforms can be detached from the release tape and bonded to the target surface by mechanical, thermal or photonic means.
  • a strip of semiconductor dicing tape such as ‘low-tack blue’ is used as the support structure for the solder preforms. Components attached to low tack blue' dicing tape can be removed mechanically.
  • Other types of dicing tape can use heat (Nitto “Revalpha”) or UV light (DU-300) to lower its adhesion properties in order to release its attached components.
  • a strip of dicing or release tape about the same size and shape as the target surface is secured to a stable surface, for example a vacuum chuck.
  • a ribbon of solder of fixed thickness e.g. Indium Bismuth eutectic is pressed onto the release tape.
  • the same laser is used to drill indexing holes into the release tape outside the solder bonding area.
  • the laser drilling of the index holes and the laser perforation of the solder preforms can be done in the same setup without physically disturbing the release tape.
  • the solder ribbon can be carefully peeled off the release tape, leaving behind the pattern of the desired solder preforms.
  • the size, shape and location of indexing holes of the release tape can be adapted for use in a reel-to-reel system (e.g. regularly-spaced holes along both edges of the tape to match index pins on a reel).
  • This solder preform tape can now be guided over the corresponding indexing pins of an alignment jig, which holds the receiving surface, and the solder side placed over and pressed onto receiving surface.
  • Solder preforms such as In 2 Bi, can be mechanically released from the dicing tape and pressure and thermally treated to bond to a compatible surface in a single step.
  • FIG. 1 shows a finished blue ‘low tack’ release tape with a set of solder preforms ready for use.
  • This invention enables multiple solder preforms of arbitrary size and shape to be fabricated at precise locations on a release tape. This prescribed pattern of solder preforms matches the location of the corresponding “bond pads” and makes the solder process highly parallel in nature.
  • the current invention overcomes these limitations by increasing flexibility in design and increasing the processing speed.
  • the thin dimensions of the release tape and the indexing feature of this invention are easily adaptable to a reel-to-reel or sheet-to-sheet environment.
  • the adhesion of the release tape can be thermally or UV light de-activated as stated earlier. Therefore heat or a UV light source (lamp or laser) could be used carefully to release the solder preforms from the release tape onto a receiving surface.
  • Other solder material besides Indium Bismuth can be used and may require additional heat treatment to bond to the receiving surface before the release tape can be removed.
  • the materials used in this invention consist of a solder ribbon, for example In 2 Bi that is 2 mil thick, but can be any other consistent composition or thickness that will work with the DIBS process.
  • a semiconductor (release) tape with low tackiness or adhesion and leaves no or minimal residue is required for holding the solder ribbon or elements.
  • a receiving sample or surface of interest with pre-machined indexing or registration holes is required to receive the solder elements.
  • An alignment jig or fixture with indexing pins is required to align and receive the sample and release tape.
  • a laser micromachining system is also required to fabricate the solder preform tape and to fabricate the indexing holes.
  • the system includes:
  • Solder preforms are now bonded to the sample surface and ready for further processing if needed.
  • Solder preforms deliver a precise amount and shape of solder for attaching electronic circuitry.
  • Current methods to emplace the preforms are distinguished by low- or high-volume applications.
  • Low-volume applications employ manual placement of solder preforms using a tweezer or suction tool.
  • High-volume methods place the preforms (all of the same size) onto tape-and-reel packages or trays, which can be removed and placed elsewhere by an automated pick-and-place system. Manual placement is slow and pick-and-place systems cannot handle very small and fragile components.
  • high-speed multiple-head pick-and-place machines exist, the increasing complexity and density of circuitry require ever decreasing solder preform size with wider variety, demands that go beyond the capabilities of current pick-and-place machines.
  • both methods place the solder preforms in their final locations in a serial manner which limits their processing speeds.
  • This invention teaches a method to place a consistent volume and shape of solder in multiple precise locations simultaneously on a surface.
  • This invention provides a method for placing a pattern of solder preforms (or elements) of well-defined shape and size simultaneously at multiple locations on a surface and bonding them to a surface with high spatial resolution and accuracy.
  • the pattern of solder preforms is fabricated with a high-speed scanning laser beam on a release (layer or) tape and has indexed alignment holes at user-defined locations.
  • This indexed tape design allows for placing solder preforms onto and simple integration into a reel-to-reel or sheet-to-sheet system.
  • This method is especially applicable to solder bonding the sets of filaments originating from separate high-temperature superconducting (HTS) tape or ribbon structures.
  • This method can also be generalized to allow solder bonding of microscopic features at precise locations between any two adjacent surfaces in intimate contact.
  • This invention enables multiple solder preforms of arbitrary size and shape to be fabricated at precise locations on a release tape.
  • This prescribed pattern of solder preforms matches the location of the corresponding “bond pads” and makes the solder process highly parallel in nature.
  • Current solder technology allows only preforms that are all the same size and shape on a tape reel. They are then placed onto pad locations by a ‘pick-and-place’ machine in a serial manner.
  • the current invention overcomes these limitations by increasing flexibility in design and increasing the processing speed.
  • the thin dimensions of the release tape and the indexing feature of this invention easily lends itself to a reel-to-reel environment and future commercial potential.
  • the adhesion of the release tape can be thermally or UV light de-activated. Therefore heat or a UV source, for example a lamp or a laser, can be used carefully to release the solder preforms onto a receiving surface.
  • a UV source for example a lamp or a laser
  • Other solder material besides InBi can be used and may require additional heat treatment to bond to the receiving surface before the release tape can be removed.

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Abstract

A method of making precise alignment and decal bonding of a pattern of solder preforms to a surface comprising cutting and placing a length of a solder ribbon onto a semiconductor release tape forming a solder ribbon and semiconductor release tape combination, placing the solder ribbon and semiconductor release tape combination on a vacuum chuck on X-Y stage pair in a laser micromachining system, adjusting the working distance, laser-cutting an outline, peeling off the solder ribbon, allowing the desired solder shape to remain, creating indexing holes, providing a target surface on an alignment fixture with indexing pins, aligning the indexing holes, placing the semiconductor release tape with the desired solder shape on the target surface, pressing the desired solder shape onto the target surface, removing the release tape, and making a pattern of the desired solder shape with precise alignment and decal bonding on the target surface.

Description

    REFERENCE TO RELATED APPLICATION
  • This application is a non-provisional of, and claims priority to and the benefits of, U.S. Provisional Patent Application No. 62/598,541 filed on Dec. 14, 2017 and U.S. Provisional Patent Application No. 62/598,539 filed on Dec. 14, 2017 and U.S. Provisional Patent Application No. 62/728,650 filed on Sep. 07, 2018, the entireties of each are hereby incorporated by reference.
    • BACKGROUND
  • This disclosure concerns precise alignment and decal bonding of a pattern of solder preforms to a surface. The terms ‘surface’ and ‘sample’, ‘receiving’ and ‘target’ will be used interchangeably in this invention.
  • With the increasing density and complexity of circuitry in modern microelectronics, there is a need to apply solder for attaching components in small precise amounts with tight spatial tolerances.
  • Solder preforms are precisely formed elements of solder available commercially in various sizes, shapes, thickness and compositions (with or without flux) that deliver a consistent volume of solder to a joint area.
  • Current methods to emplace these preforms are distinguished by low- or high-volume applications. Low-volume applications employ manual placement of solder preforms using a tweezer or suction tool. High-volume methods place prepackaged preforms (all of the same size and shape) onto tape-and-reel packages or trays used in an automated pick-and-place or surface mount technology (SMT) machine. Manual placement is slow and pick-and-place systems cannot handle very small and fragile components (limited to a few hundred microns thickness). The term ‘tape’ in this invention is generalized to mean structures that do or do not contain adhesive.
  • Although high-speed multiple-head pick-and-place machines exist, the increasing complexity and density of circuitry require ever decreasing solder preform size with wider variety, demands that go beyond the capabilities of current pick-and-place machines.
  • Ultimately, both prior art methods place the solder preforms in their final locations in a serial manner which limits their processing speeds.
  • An alternative method of placing a high volume of solder preforms is to use a fixture with a matching pattern to the pad/connector locations on a receiving surface. Another high volume placement method is to use an array of preforms all connected together with thin links of solder. These links are designed to melt and reflow completely back to the solder preform mass without leaving any solder residue that would cause electrical shorting. Although both these prior art methods can process solder preforms simultaneously, they cannot be easily implemented in a roll-to-roll environment used for manufacturing tapes.
  • Solder preforms are traditionally made by stamping solder wire or foils into the desired shape. One problem associated with stamping is the curvature of the surface of the preform caused by the forces acting on it during the stamping process. The curved surface may reduce the seal between the preform and the vacuum nozzle in an SMT machine resulting in less reliable pick-up and release of the preform. This curvature worsens as the thickness of the preform decreases.
  • Laser manufacturing of solder preforms has been used to minimize waste of material and decrease raised edges or burrs in the preform after stamping. However the solder preforms were cut individually and not aligned to any pre-defined pattern in a receiving surface.
  • Solder preforms can be placed over a receiving pattern of interest by loading the preforms in a matching pattern of openings in a locating plate and then releasing the preforms by mechanical, vibratory, air or sound pressure means. The preforms also rely on tacky media on the receiving surface such as solder paste to separate the preforms from the locating plate and to adhere to the receiving surface.
  • The existing techniques place patterns of solder preforms of a predefined regular shape and size on a receiving surface by first loading and securing the preforms mechanically on a recessed holder consisting of an array of openings (such as a stencil or channels), then aligning them over the receiving pattern and releasing the preforms by various actuating means. In these prior art techniques, the shape and size of each solder preform is usually fixed for the entire receiving pattern and not easily changed without redesigning and refabricating the recessed holder. In these prior art techniques, the preform shape is regular in that the preform can land on the receiving sample in any spatial orientation. This simplifies the loading of the preforms and operation of the release apparatus but requires the solder landing area of the receiving pattern to be symmetric and regular in shape in both two and three dimensions. Irregularly shaped and very thin (<0.25 mm) solder preforms that may be required for highly specialized applications may not be easily handled by current techniques. In addition, there is no mention of spatial tolerance or variation in the placement of the solder preforms from current techniques. Very thin (<0.2 mm thick) and low mass solder preforms are required for fine electronics circuitry (such as high-temperature superconducting (HTS) tapes or foils) and placing them on a receiving sample with high precision (<tens of microns tolerance) is a long-standing problem with the prior art techniques.
  • A new and an efficient method for depositing a pattern of such solder preforms onto a receiving surface is required.
  • This disclosure describes a method for placing a pattern of solder preforms simultaneously at multiple locations and bonding them onto a surface with microscopic precision.
  • This new process described herein is an efficient and scalable method for bonding electrical circuit patterns at specific locations between an upper and lower surface. The pattern of solder preforms is fabricated on a release tape and has indexed alignment holes at prescribed locations. This indexed tape design allows simple integration into a reel-to-reel system for commercial applications. This method is especially applicable to solder bonding the overlay of filaments from upper and lower high-temperature superconducting (HTS) tapes. This method can also be generalized to allow parallel solder bonding of microscopic features at precise locations between any two overlaid adjacent surfaces.
    • SUMMARY OF DISCLOSURE Description
  • This disclosure teaches methods and products concerning precise alignment and decal bonding of a pattern of solder preforms to a surface.
  • This new process described herein is an efficient and scalable method for bonding electrical circuit patterns at specific locations between an upper and lower surface. The pattern of solder preforms is fabricated on a release tape and has indexed alignment holes at prescribed locations. This indexed tape design allows simple integration into a reel-to-reel system for commercial applications. This method is especially applicable to solder bonding the overlay of filaments from upper and lower high-temperature superconducting (HTS) tapes. This method can also be generalized to allow parallel solder bonding of microscopic features at precise locations between any two overlaid adjacent surfaces.
  • It is an object of the invention to provide a method for placing a pattern of solder preforms simultaneously at multiple locations and bonding them onto a surface with microscopic precision.
  • It is a further object of the invention that the pattern of solder preforms is prefabricated on a release tape.
  • It is a further object of the invention that the solder preform release tape has indexed registration holes that are aligned with those on a receiving surface.
  • It is a further object of the invention that this method is adaptable to a reel-to-reel manufacturing system.
  • It is a further object of the invention that this method can apply and bond patterns of solder preforms to electrically connect current-carrying filaments in an HTS tape structure.
  • The Decal Imprinting and Bonding of Solder (DIBS) process consists of three steps—the fabrication of the solder preforms (shape and spacing) on the release tape, the alignment and placement of the release tape over a target surface, and release of the individual solder preforms from the release tape onto the target surface and their subsequent bonding to the target surface. The solder preforms can be detached from the release tape and bonded to the target surface by mechanical, thermal or photonic means.
  • To fabricate the solder release tape, a strip of semiconductor dicing tape, such as ‘low-tack blue’, is used as the support structure for the solder preforms. Components attached to ‘low tack blue’ dicing tape can be removed mechanically. Other types of dicing tape can use heat (Nitto “Revalpha”) or UV light (DU-300) to lower its adhesion properties in order to release its attached components. A strip of dicing or release tape about the same size and shape as the target surface is secured to a stable surface (e.g. vacuum chuck). Next, a ribbon of solder of fixed thickness (e.g. Indium Bismuth eutectic) is pressed onto the release tape. A UV (λ=355 nm) laser is then focused onto the solder and perforates the perimeter of the desired solder preforms without damaging the underlying release tape. To ensure precise alignment of the release tape (and the solder preforms) to the target surface, the same laser is used to drill indexing holes into the release tape outside the solder bonding area. The laser drilling of the index holes and the laser perforation of the solder preforms must be done in the same setup without physically disturbing the release tape. Afterwards, the solder ribbon can be carefully peeled off the release tape, leaving behind the pattern of the desired solder preforms. Note that the size, shape and location of indexing holes of the release tape can be adapted for use in a reel-to-reel system, for example, regularly-spaced holes along both edges of the tape to match index pins on a reel.
  • This solder preform tape can now be guided over the corresponding indexing pins of an alignment jig, which holds the target surface, and the solder side placed over and pressed onto the target surface. Solder preforms such as InBi, can be mechanically released from the dicing tape and then pressure and/or thermally treated to bond to a compatible surface in a single step. The release tape can then be removed leaving behind a precisely spaced pattern of solder preforms on the target surface. Note that additional layers or tapes with the same pattern of indexing holes can now be precisely aligned and placed over this first layer of solder preforms. FIG. 1 shows a finished blue ‘low tack’ release tape with a set of solder preforms ready for use.
  • The keys to ensuring high placement accuracy of the solder pattern onto a receiving surface are: 1) to fabricate indexing holes in both the release tape containing the solder preforms and the receiving surface(s) and 2) to fabricate the ‘complementary’ indexing pins on an alignment jig. The alignment jig is a device or structure that helps align and assemble all the separate components together on a 2-D planar or 3-D curved surface with high precision. With judicious choice of indexing holes and pins, individual components are aligned to less than 50 microns spatial tolerance. Other methods of indexing components such as mechanical means (e.g. notches, holes, guides) or optical means (e.g. laser, LED, lamp) can be used. As long as there is a ‘complementary’ structure on the alignment jig to match the indexed component, then high spatial accuracy can be maintained.
    • DESCRIPTION OF THE DRAWINGS
  • The following description and drawings set forth certain illustrative implementations of the disclosure in detail, which are indicative of several exemplary ways in which the various principles of the disclosure may be carried out. The illustrated examples, however, are not exhaustive of the many possible embodiments of the disclosure. Other objects, advantages and novel features of the disclosure will be set forth in the following detailed description when considered in conjunction with the drawings.
  • FIG. 1 illustrates a photograph of ‘blue low-tack’ dicing/release tape with solder preforms.
  • FIG. 2 illustrates step-by-step diagram of the general DIBS process.
    •  DETAILED DESCRIPTION OF THE INVENTION
  • This disclosure teaches precise alignment and decal bonding of a pattern of solder preforms to a surface.
  • This invention fabricates arbitrarily-shaped solder elements in an arbitrary pattern onto a release tape layer and then places all of them with microscopic precision onto a surface at the same time.
    • Example 1 Decal Imprinting and Bonding of Solder (DIBS)
  • This invention, which can be termed “Decal Imprinting and Bonding of Solder” (DIBS) consists of three steps—the fabrication of the solder preforms (shape and spacing) on the release (layer or) tape, the alignment and placement of the release tape over a target surface, and release of the individual solder preforms from the release tape onto the target surface and their subsequent bonding to the target surface.
  • The solder preforms can be detached from the release tape and bonded to the target surface by mechanical, thermal or photonic means.
    • Example 2
  • To fabricate the solder release tape, a strip of semiconductor dicing tape, such as ‘low-tack blue’ is used as the support structure for the solder preforms. Components attached to low tack blue' dicing tape can be removed mechanically. Other types of dicing tape can use heat (Nitto “Revalpha”) or UV light (DU-300) to lower its adhesion properties in order to release its attached components.
  • A strip of dicing or release tape about the same size and shape as the target surface is secured to a stable surface, for example a vacuum chuck.
  • Next, a ribbon of solder of fixed thickness (e.g. Indium Bismuth eutectic) is pressed onto the release tape.
  • A UV (λ=355 nm) laser is then focused onto the solder and perforates the perimeter or outline of the desired solder preforms without damaging the underlying release tape.
  • To ensure precise alignment of the release tape (and the solder preforms) to the target surface, the same laser is used to drill indexing holes into the release tape outside the solder bonding area. The laser drilling of the index holes and the laser perforation of the solder preforms can be done in the same setup without physically disturbing the release tape.
  • Afterwards, the solder ribbon can be carefully peeled off the release tape, leaving behind the pattern of the desired solder preforms. Note that the size, shape and location of indexing holes of the release tape can be adapted for use in a reel-to-reel system (e.g. regularly-spaced holes along both edges of the tape to match index pins on a reel).
    • Example 3
  • This solder preform tape can now be guided over the corresponding indexing pins of an alignment jig, which holds the receiving surface, and the solder side placed over and pressed onto receiving surface.
  • Solder preforms such as In2Bi, can be mechanically released from the dicing tape and pressure and thermally treated to bond to a compatible surface in a single step.
  • The release tape can then be removed leaving behind a precisely spaced pattern of solder preforms on the target surface. Note that additional layers or tapes with the same pattern of indexing holes can now be precisely aligned and placed over this first layer of solder preforms. FIG. 1 shows a finished blue ‘low tack’ release tape with a set of solder preforms ready for use.
  • This invention enables multiple solder preforms of arbitrary size and shape to be fabricated at precise locations on a release tape. This prescribed pattern of solder preforms matches the location of the corresponding “bond pads” and makes the solder process highly parallel in nature.
  • Current solder technology allows only preforms that are all the same size and shape on a tape reel. They are then placed onto pad locations by a ‘pick-and-place’ machine in a serial manner.
  • The current invention overcomes these limitations by increasing flexibility in design and increasing the processing speed.
  • In addition, the thin dimensions of the release tape and the indexing feature of this invention are easily adaptable to a reel-to-reel or sheet-to-sheet environment.
  • The adhesion of the release tape can be thermally or UV light de-activated as stated earlier. Therefore heat or a UV light source (lamp or laser) could be used carefully to release the solder preforms from the release tape onto a receiving surface. Other solder material besides Indium Bismuth can be used and may require additional heat treatment to bond to the receiving surface before the release tape can be removed.
    • Example 4
  • The materials used in this invention consist of a solder ribbon, for example In2Bi that is 2 mil thick, but can be any other consistent composition or thickness that will work with the DIBS process.
  • A semiconductor (release) tape with low tackiness or adhesion and leaves no or minimal residue is required for holding the solder ribbon or elements.
  • A receiving sample or surface of interest with pre-machined indexing or registration holes is required to receive the solder elements.
  • An alignment jig or fixture with indexing pins is required to align and receive the sample and release tape.
  • A laser micromachining system is also required to fabricate the solder preform tape and to fabricate the indexing holes. The system includes:
      • a) A laser—preferably pulsed UV (355 nm wavelength, 30-70 ns pulsewidth, >10 kHz repetition rate), but can be other laser type that can cut solder ribbon without melting or deforming it.
      • b) Beam control, optical, and motion control components consisting of a) fast-scanning galvanometric (galvo) mirrors, laser pulse amplitude and timing control, high-precision and accuracy X-Y translation stage pair, vacuum chuck, parfocal optical inspection camera, and stage, and mirror scanning software.
    Example 5
  • A. Fabrication of the release tape:
      • 1) Cut and place desired length of solder ribbon onto the semiconductor release tape.
      • 2) Place on vacuum chuck on X-Y stage pair in laser micromachining system.
      • 3) Adjust working distance of galvo from solder by focusing optical image on camera.
      • 4) After optimizing laser energy and scan parameters on other surrogate tapes, laser-cut the outline (perimeter) of the desired solder shapes and pattern to a depth that does not damage the release tape.
      • 5) Carefully peel the solder ribbon off the release tape while leaving behind the desired solder (preform) elements.
      • 6) Laser cut indexing holes through the release tape that matches those on the receiving surface.
  • B) Application of solder preforms to sample:
      • 1) Place receiving sample with the bonding surface face up over the indexing pins on an alignment jig.
      • 2) Align the indexing holes on the release tape with the indexing pins of the alignment jig and emplace the release tape with the solder preforms facing the receiving sample.
      • 3) Press the solder preforms onto the surface and remove the release tape by mechanical, thermal, or photonic means.
  • Solder preforms are now bonded to the sample surface and ready for further processing if needed.
  • Solder preforms deliver a precise amount and shape of solder for attaching electronic circuitry. Current methods to emplace the preforms are distinguished by low- or high-volume applications. Low-volume applications employ manual placement of solder preforms using a tweezer or suction tool. High-volume methods place the preforms (all of the same size) onto tape-and-reel packages or trays, which can be removed and placed elsewhere by an automated pick-and-place system. Manual placement is slow and pick-and-place systems cannot handle very small and fragile components. Although high-speed multiple-head pick-and-place machines exist, the increasing complexity and density of circuitry require ever decreasing solder preform size with wider variety, demands that go beyond the capabilities of current pick-and-place machines. Ultimately, both methods place the solder preforms in their final locations in a serial manner which limits their processing speeds.
  • This invention teaches a method to place a consistent volume and shape of solder in multiple precise locations simultaneously on a surface.
  • This invention provides a method for placing a pattern of solder preforms (or elements) of well-defined shape and size simultaneously at multiple locations on a surface and bonding them to a surface with high spatial resolution and accuracy.
  • It is an efficient and scalable method of solder bonding 2-D and 3-D features of an electronic circuit, especially on flexible samples.
  • The pattern of solder preforms is fabricated with a high-speed scanning laser beam on a release (layer or) tape and has indexed alignment holes at user-defined locations. This indexed tape design allows for placing solder preforms onto and simple integration into a reel-to-reel or sheet-to-sheet system.
  • This method is especially applicable to solder bonding the sets of filaments originating from separate high-temperature superconducting (HTS) tape or ribbon structures. This method can also be generalized to allow solder bonding of microscopic features at precise locations between any two adjacent surfaces in intimate contact.
  • This invention enables multiple solder preforms of arbitrary size and shape to be fabricated at precise locations on a release tape. This prescribed pattern of solder preforms matches the location of the corresponding “bond pads” and makes the solder process highly parallel in nature. Current solder technology allows only preforms that are all the same size and shape on a tape reel. They are then placed onto pad locations by a ‘pick-and-place’ machine in a serial manner.
  • The current invention overcomes these limitations by increasing flexibility in design and increasing the processing speed.
  • In addition, the thin dimensions of the release tape and the indexing feature of this invention easily lends itself to a reel-to-reel environment and future commercial potential.
  • The adhesion of the release tape can be thermally or UV light de-activated. Therefore heat or a UV source, for example a lamp or a laser, can be used carefully to release the solder preforms onto a receiving surface. Other solder material besides InBi can be used and may require additional heat treatment to bond to the receiving surface before the release tape can be removed.
  • The above examples are merely illustrative of several possible embodiments of various aspects of the present disclosure, wherein equivalent alterations and/or modifications will occur to others skilled in the art upon reading and understanding this specification and the annexed drawings. In addition, although a particular feature of the disclosure may have been illustrated and/or described with respect to only one of several implementations, such feature may be combined with one or more other features of the other implementations as may be desired and advantageous for any given or particular application. Also, to the extent that the terms “including”, “includes”, “having”, “has”, “with”, or variants thereof are used in the detailed description and/or in the claims, such terms are intended to be inclusive in a manner similar to the term “comprising”.

Claims (16)

What we claim is:
1. A method of making precise alignment and decal bonding of a pattern of solder preforms to a surface comprising:
cutting and placing a length of a solder ribbon onto a semiconductor release tape forming a solder ribbon and semiconductor release tape combination;
placing the solder ribbon and semiconductor release tape combination on a vacuum chuck on an X-Y stage pair in a laser micromachining system;
adjusting the working distance of the galvo from the solder ribbon of the solder ribbon and semiconductor release tape combination by focusing the optical image on camera;
laser-cutting an outline or perimeter of a desired solder shape pattern of elements on the solder ribbon and semiconductor release tape combination;
creating indexing holes through the release tape while maintaining the spatial alignment of the solder ribbon and semiconductor release tape combination;
peeling off the solder ribbon from the semiconductor release tape;
allowing the desired solder shape pattern of elements to remain on the semiconductor release tape;
providing a target or receiving surface on an alignment fixture with indexing pins;
aligning the indexing holes on the release tape with the indexing pins of the alignment fixture;
placing the semiconductor release tape with the desired solder shape pattern of elements on a target surface;
pressing the desired solder shape pattern of elements onto the target surface;
removing the release tape; and
making a pattern of the desired solder shape pattern of elements with precise alignment and decal bonding on the target surface.
2. The method of making precise alignment and decal bonding of a pattern of solder preforms to a surface of claim 1
wherein the step of laser-cutting an outline or perimeter of a desired solder shape is to a depth that maintains the integrity of the release tape.
3. The method of making precise alignment and decal bonding of a pattern of solder preforms to a surface of claim 1
wherein the step of laser-cutting an outline or perimeter of a desired solder shape is to a depth to the surface of the release tape.
4. The method of making precise alignment and decal bonding of a pattern of solder preforms to a surface of claim 3
wherein the creating indexing holes through the release tape is by laser cutting.
5. The method of making precise alignment and decal bonding of a pattern of solder preforms to a surface of claim 1
wherein the target surface has target surface indexing holes and further comprising the step of
aligning the indexing holes with the target surface indexing holes.
6. The method of making precise alignment and decal bonding of a pattern of solder preforms to a surface of claim 1
further comprising the step of
aligning the indexing holes with indexing pins on a reel.
7. The method of making precise alignment and decal bonding of a pattern of solder preforms to a surface of claim 1
further comprising the step of
utilizing the method in a reel-to-reel system.
8. The method of making precise alignment and decal bonding of a pattern of solder preforms to a surface of claim 1
wherein the step of removing the release tape is by mechanical, thermal, or photonic means.
9. The method of making precise alignment and decal bonding of a pattern of solder preforms to a surface of claim 1 further comprising the steps of:
placing a receiving sample with the bonding surface face up over the indexing pins on an alignment jig;
aligning the indexing holes on the release tape with the indexing pins of the alignment jig;
emplacing the release tape with the solder preforms facing the receiving sample;
pressing the solder preforms onto the surface; and
removing the release tape by mechanical, thermal, or photonic means.
10. The method of making precise alignment and decal bonding of a pattern of solder preforms to a surface of claim 1
further comprising the step of
making solder bonds of an electronic circuit on a flexible substrate.
11. The method of making precise alignment and decal bonding of a pattern of solder preforms to a surface of claim 1
wherein the solder preforms are placed on a surface with less than 50 microns spatial accuracy.
12. The method of making precise alignment and decal bonding of a pattern of solder preforms to a surface of claim 1
further comprising the step of
bonding electrical elements or structures originating from separate layers.
13. The method of making precise alignment and decal bonding of a pattern of solder preforms to a surface of claim 1
further comprising the step of
bonding superconducting elements or structures originating from separate layers.
14. The method of making precise alignment and decal bonding of a pattern of solder preforms to a surface of claim 6
wherein an alignment jig aligns and assembles separate components on a 2-D planar or 3-D curved surface with precision.
15. The product of the process of making precise alignment and decal bonding of a pattern of solder preforms to a surface comprising the steps of:
cutting and placing a length of a solder ribbon onto a semiconductor release tape forming a solder ribbon and semiconductor release tape combination;
placing the solder ribbon and semiconductor release tape combination on a vacuum chuck on X-Y stage pair in a laser micromachining system;
adjusting the working distance of the galvo from the solder ribbon of the solder ribbon and semiconductor release tape combination by focusing the optical image on camera;
laser-cutting an outline or perimeter of a desired solder shape pattern on the solder ribbon and semiconductor release tape combination;
creating indexing holes through the release tape while maintaining the spatial alignment of the solder ribbon and semiconductor release tape combination;
peeling off the solder ribbon from the semiconductor release tape;
allowing the desired solder shape elements to remain on the semiconductor release tape;
providing a target surface on an alignment fixture with indexing pins;
aligning the indexing holes on the release tape with the indexing pins of the alignment fixture;
placing the semiconductor release tape with the desired solder shape elements on the target surface;
pressing the desired solder shape elements onto the target surface;
removing the release tape; and
making a pattern of the desired solder shape elements with precise alignment and decal bonding on the target surface.
16. The product of the process of making precise alignment and decal bonding of a pattern of solder preforms to a surface of claim 15 further comprising the steps of:
placing a receiving sample with the bonding surface face up over the indexing pins on an alignment jig;
aligning the indexing holes on the release tape with the indexing pins of the alignment jig;
emplacing the release tape with the solder preforms facing the receiving sample;
pressing the solder preforms onto the surface; and
removing the release tape by mechanical, thermal, or photonic means.
US16/218,459 2017-12-14 2018-12-12 Precise Alignment and Decal Bonding of a Pattern of Solder Preforms to a Surface Abandoned US20190184480A1 (en)

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US201762598541P 2017-12-14 2017-12-14
US201762598539P 2017-12-14 2017-12-14
US201862728650P 2018-09-07 2018-09-07
US16/218,459 US20190184480A1 (en) 2017-12-14 2018-12-12 Precise Alignment and Decal Bonding of a Pattern of Solder Preforms to a Surface

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US16/218,459 Abandoned US20190184480A1 (en) 2017-12-14 2018-12-12 Precise Alignment and Decal Bonding of a Pattern of Solder Preforms to a Surface
US17/975,465 Active US11711983B2 (en) 2017-12-14 2022-10-27 High-temperature superconducting striated tape combinations

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EP3723934A1 (en) 2020-10-21
US20230081740A1 (en) 2023-03-16
EP3724898A1 (en) 2020-10-21
JP2021516443A (en) 2021-07-01
EP3723934A4 (en) 2021-09-22
CA3088977A1 (en) 2019-06-20
JP2021514842A (en) 2021-06-17
WO2019118651A1 (en) 2019-06-20
WO2019118650A1 (en) 2019-06-20
US11711983B2 (en) 2023-07-25
KR20200099555A (en) 2020-08-24
US20190189888A1 (en) 2019-06-20
CA3089491A1 (en) 2019-06-20
US11600762B2 (en) 2023-03-07
EP3724898A4 (en) 2021-09-15

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