US20190138081A1 - Method for Managing Central Processing Unit and Related Products - Google Patents

Method for Managing Central Processing Unit and Related Products Download PDF

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Publication number
US20190138081A1
US20190138081A1 US16/122,400 US201816122400A US2019138081A1 US 20190138081 A1 US20190138081 A1 US 20190138081A1 US 201816122400 A US201816122400 A US 201816122400A US 2019138081 A1 US2019138081 A1 US 2019138081A1
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cpu
prediction
lpm
accuracy rate
target
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Yuanqing Zeng
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Guangdong Oppo Mobile Telecommunications Corp Ltd
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Guangdong Oppo Mobile Telecommunications Corp Ltd
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Assigned to GUANGDONG OPPO MOBILE TELECOMMUNICATIONS CORP., LTD. reassignment GUANGDONG OPPO MOBILE TELECOMMUNICATIONS CORP., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: ZENG, Yuanqing
Priority to US16/245,366 priority Critical patent/US10444822B2/en
Publication of US20190138081A1 publication Critical patent/US20190138081A1/en
Abandoned legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3287—Power saving characterised by the action undertaken by switching off individual functional units in the computer system
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality
    • G06F1/3228—Monitoring task completion, e.g. by use of idle timers, stop commands or wait commands
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/3003—Monitoring arrangements specially adapted to the computing system or computing system component being monitored
    • G06F11/3024—Monitoring arrangements specially adapted to the computing system or computing system component being monitored where the computing system component is a central processing unit [CPU]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/3055—Monitoring arrangements for monitoring the status of the computing system or of the computing system component, e.g. monitoring if the computing system is on, off, available, not available
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
    • G06F11/3466—Performance evaluation by tracing or monitoring
    • G06F11/3495—Performance evaluation by tracing or monitoring for systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N5/00—Computing arrangements using knowledge-based models
    • G06N5/04—Inference or reasoning models
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality
    • G06F1/3215—Monitoring of peripheral devices
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the counting a prediction accuracy rate of predicting the CPU entering a LPM by using the first prediction condition includes: determining a response time of the CPU in a target LPM, after determining the timer value as a prediction condition to predict the next wake-up moment of the CPU and the CPU entering the target LPM; determining whether the response time of the CPU in the target LPM is between a sleep time of the CPU in the target LPM and the timer value of the CPU; determining the prediction as an inaccurate prediction based on a determination that the response time of the CPU in the target LPM is between the sleep time of the CPU in the target LPM and the timer value of the CPU; counting the prediction accuracy rate after predicting the next wake-up moment of the CPU by using the timer value as the prediction condition for a pre-determined number of times.
  • the counting the prediction accuracy rate includes: counting the prediction accuracy rate by determining situations corresponding to accurate predictions as an accurate set and determining situations that do not belong to the accurate set as corresponding to inaccurate predictions.
  • the at least one processor carrying out the action of counting a prediction accuracy rate of predicting the CPU entering a LPM by using the first prediction condition is caused to carry out actions, including: determining the prediction as an accurate prediction, based on a determination including one of the following: the response time of the CPU in target LPM is longer than the sleep time of the CPU in the LPM and the timer value of the CPU; the response time of the CPU in the target LPM is less than the sleep time of the CPU in the LPM and the timer value of the CPU; a difference between the sleep time of the CPU in the LPM and the timer value of the CPU is less than a pre-determined threshold; counting the prediction accuracy rate after predicting the next wake-up moment of the CPU by using the timer value as the prediction condition for a pre-determined number of times.
  • the at least one processor carrying out the action of counting the prediction accuracy rate is caused to carry out actions, including: counting the prediction accuracy rate by determining situations corresponding to accurate predictions and inaccurate predictions as a full set and counting a proportion of the accurate predictions in the full set.
  • the implementations of the present discourse also provide another solution of how to count the prediction accuracy rate.
  • the prediction accuracy rate of predicting the CPU entering the LPM by using the first prediction condition is counted as follows.
  • a prediction is determined as an accurate prediction, if: the response time of the CPU in the target LPM is longer than the sleep time of the CPU in the LPM and the timer value of the CPU (here, the sleep time of the CPU in the target LPM can refer to the end of the seep time, and the response time of the CPU in the target LPM may refer to a moment that the CPU responds to an interrupt, that is, the moment that the CPU responds to the interrupt is after both the end of the seep time of the CPU in the LPM and the timer value of the CPU); or, the response time of the CPU in the LPM is less than the sleep time of the CPU in the LPM and the timer value of the CPU (here, the sleep time of the CPU in the target LPM can refer to the end of the seep time, and the response time of the CPU in the target LPM may refer to a moment that the CPU responds to an interrupt, that is, the moment that the CPU responds to the interrupt is before both the end of the seep time of the CPU in the LPM and the
  • the prediction accuracy rate can be also counted by determining situations corresponding to accurate predictions as an accurate set and determining situations that do not belong to the accurate set as inaccurate predictions without considering how to determine a prediction as an inaccurate prediction. Therefore, solutions of how to determine a prediction as an accurate prediction and solutions of how to determine a prediction as an inaccurate prediction can exist independently. At the same time, these two solutions can both be considered together.
  • a scheduler of an operating system can accurately assign tasks to an appropriate CPU, the power consumption and scheduling overhead of the system can be reduced, and operating performance of the system can be improved.
  • the implementations of the present disclosure provide a new LPM Governor algorithm, which allows reducing power consumption and improving performance of a multi-core system.
  • the design principle is as follows. Comparison between the last time that the CPU was in the LPM and the last value of the timer of the system is conducted. When both the last time and the last value are in a same range of response time in the LPM, it indicates that prediction of the next wake-up moment of the CPU by using the termer of the system is accurate; otherwise, it indicates that prediction of the next wake-up moment of the CPU by using the termer of the system is inaccurate.
  • the LPM Governor algorithm counts the comparison results of past several times (for example, five times) to determine the prediction accuracy rate.
  • the LPM Governor algorithm uses the response time of the CPU in different LPMs as a comparison threshold, so that a decision for CPU state switching can directly reflect different characteristics of the CPU, and the pertinence and accuracy are better. In a scenario where the CPU is woken up frequently (that is, there are more interrupts), the LPM Governor algorithm can maintain high CPU performance while maintaining low power consumption.
  • the prediction accuracy by using the timer value can be evaluated by comparing the timer of the system and the wake-up moment of the CPU.
  • a predicted value can be corrected in real time in scenarios where interrupts occur frequently, so that the next wake-up moment of the CPU can be predicted accurately, thereby making the CPU to enter a more appropriate LPM and maintaining a better CPU performance while keeping low power consumption as much as possible.
  • the CPU is operable with several classical LPMs.
  • the CPU in different LPMs has different response time and power consumption characteristic. For example, in a waiting-for-interrupt (WFI) mode, the CPU has the fastest response but the largest power consumption; in a suspending/retention mode, the CPU has moderate response and moderate power consumption; in a power-down mode, the CPU responds the slowest but the most power-efficient.
  • WFI waiting-for-interrupt
  • the WFI mode is appropriate.
  • the power-down mode is appropriate for a system in a long-term sleep mode.
  • Main factors that affect the next wake-up moment of the CPU include a timer and an interrupt, which will be described below.
  • Each CPU has its own timer. Drivers, kernel modules, and applications, etc. can set different timers according to their own needs.
  • the timer of the CPU usually refers to the timer that will expire recently.
  • Li represent a certain LPM, such as WFI, suspend, etc.
  • TLi represent response time of the CPU corresponding to a certain LPM Li
  • SLi represent sleep time the CPU in a certain LPM Li
  • Ttimer represent a timer value of the CPU
  • Eli represent a predicted next wake-up moment of the CPU.
  • the process includes the following operations.
  • the prediction by using Ttimer is determined as an accurate prediction, proceed to operations at block 206 .
  • Ttimer is used to predict the next wake-up moment of the CPU and a predicted value Eli is obtained, and then proceed to operations at block 210 .
  • a mode with the lowest power consumption and satisfying a condition (TLi ⁇ ELi) is found from among all LPMs.
  • the time determining sub-unit 401 is configured to determine a response time of the CPU in a target LPM.
  • the accuracy determining sub-unit 402 is configured to determine whether the response time of the CPU in the target LPM is between a sleep time of the CPU in the target LPM and the timer value of the CPU; determine the prediction as an inaccurate prediction if the response time of the CPU in the target LPM is between the sleep time of the CPU in the target LPM and the timer value of the CPU.
  • a scheduler of an operating system can accurately assign tasks to an appropriate CPU, the power consumption and scheduling overhead of the system can be reduced, and operating performance of the system can be improved.
  • the implementations of the present discourse also provide a solution of how to count the prediction accuracy rate specifically.
  • the processor 501 configured to count the prediction accuracy rate of predicting the CPU entering the LPM by using the first prediction condition is further configured to: determine a response time of the CPU in a target LPM, after the timer value is determined as a prediction condition to predict the next wake-up moment of the CPU and the CPU enters the target LPM; determine whether a response time of the CPU in the target LPM is between a sleep time of the CPU in the target LPM and the timer value of the CPU; determine the prediction as an inaccurate prediction if the response time of the CPU in the target LPM is between the sleep time of the CPU in the target LPM and the timer value of the CPU.

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  • General Engineering & Computer Science (AREA)
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US16/122,400 2016-05-31 2018-09-05 Method for Managing Central Processing Unit and Related Products Abandoned US20190138081A1 (en)

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CN201610380645.1A CN106055079B (zh) 2016-05-31 2016-05-31 一种中央处理器的管理方法、及装置
CN201610380645.1 2016-05-31
PCT/CN2017/086453 WO2017206858A1 (zh) 2016-05-31 2017-05-27 一种中央处理器的管理方法、及相关产品

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113900910A (zh) * 2021-12-08 2022-01-07 北京新唐思创教育科技有限公司 应用程序监控方法、装置、存储介质和电子设备
US11385811B2 (en) 2020-02-10 2022-07-12 Samsung Electronics Co., Ltd. Storage device and method of operating the same
US20230368325A1 (en) * 2022-05-16 2023-11-16 Qualcomm Incorporated Technique to optimize power and performance of xr workload

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106055079B (zh) * 2016-05-31 2017-11-24 广东欧珀移动通信有限公司 一种中央处理器的管理方法、及装置
CN108806673B (zh) * 2017-05-04 2021-01-15 北京猎户星空科技有限公司 一种智能设备控制方法、装置及智能设备
US20210051110A1 (en) * 2017-05-10 2021-02-18 Telefonaktiebolaget Lm Ericsson (Publ) Communication Node and Method for Handling Communications between Nodes of a System
CN111443792B (zh) * 2019-01-16 2023-05-09 阿里巴巴集团控股有限公司 处理器的功耗控制方法、装置以及电子和存储设备
US20230031388A1 (en) * 2021-07-30 2023-02-02 Advanced Micro Devices, Inc. On-demand ip initialization within power states

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6725067B1 (en) * 2000-03-24 2004-04-20 International Business Machines Corporation Method and system for restarting a reference clock of a mobile station after a sleep period with a zero mean time error
US20100115309A1 (en) * 2007-03-26 2010-05-06 Freescale Semiconductor, Inc. Anticipation of power on of a mobile device
US20110161627A1 (en) * 2009-12-28 2011-06-30 Song Justin J Mechanisms to avoid inefficient core hopping and provide hardware assisted low-power state selection
US20150286271A1 (en) * 2014-04-03 2015-10-08 Samsung Electronics Co., Ltd. System and method for predicting a central processing unit idle pattern for power saving in a modem system on chip
US20150370311A1 (en) * 2014-06-20 2015-12-24 Advanced Micro Devices, Inc. Decoupled entry and exit prediction for power gating
US20160321183A1 (en) * 2015-05-01 2016-11-03 Advanced Micro Devices, Inc. Early cache prefetching in preparation for exit from idle mode

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7017060B2 (en) * 2001-03-19 2006-03-21 Intel Corporation Power management system that changes processor level if processor utilization crosses threshold over a period that is different for switching up or down
US8024590B2 (en) * 2007-12-10 2011-09-20 Intel Corporation Predicting future power level states for processor cores
US8468377B2 (en) * 2008-10-22 2013-06-18 Microsoft Corporation Conserving power using predictive modelling and signaling
JP5324340B2 (ja) * 2009-06-29 2013-10-23 ルネサスエレクトロニクス株式会社 マイクロコンピュータ
US9563250B2 (en) * 2009-12-16 2017-02-07 Qualcomm Incorporated System and method for controlling central processing unit power based on inferred workload parallelism
US9235251B2 (en) * 2010-01-11 2016-01-12 Qualcomm Incorporated Dynamic low power mode implementation for computing devices
US20130290758A1 (en) * 2010-01-11 2013-10-31 Qualcomm Incorporated Sleep mode latency scaling and dynamic run time adjustment
EP2798436B1 (en) * 2011-12-27 2017-05-17 INTEL Corporation Power management using reward-based sleep state selection
US8775838B2 (en) * 2012-02-01 2014-07-08 Texas Instruments Incorporated Limiting the number of unexpected wakeups in a computer system implementing a power-saving preemptive wakeup method from historical data
US8938631B2 (en) * 2012-06-30 2015-01-20 International Business Machines Corporation Energy efficient implementation of read-copy update for light workloads running on systems with many processors
US9442557B2 (en) * 2012-11-28 2016-09-13 Advanced Micro Devices, Inc. Using a linear prediction to configure an idle state of an entity in a computing device
US9110671B2 (en) * 2012-12-21 2015-08-18 Advanced Micro Devices, Inc. Idle phase exit prediction
CN103218033B (zh) * 2013-03-28 2015-11-25 小米科技有限责任公司 一种唤醒硬件设备的方法及装置
US9131445B2 (en) * 2013-05-15 2015-09-08 Nvidia Corporation Low power mode exit latency predictor for real-time asymmetric multiprocessor systems
CN104184907B (zh) * 2013-05-27 2017-12-15 腾讯科技（深圳）有限公司 终端应用软件在待机状态下的唤醒数据的检测方法及终端
US9851777B2 (en) * 2014-01-02 2017-12-26 Advanced Micro Devices, Inc. Power gating based on cache dirtiness
US9720487B2 (en) * 2014-01-10 2017-08-01 Advanced Micro Devices, Inc. Predicting power management state duration on a per-process basis and modifying cache size based on the predicted duration
US20160314024A1 (en) * 2015-04-24 2016-10-27 Mediatek Inc. Clearance mode in a multicore processor system
CN106055079B (zh) * 2016-05-31 2017-11-24 广东欧珀移动通信有限公司 一种中央处理器的管理方法、及装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6725067B1 (en) * 2000-03-24 2004-04-20 International Business Machines Corporation Method and system for restarting a reference clock of a mobile station after a sleep period with a zero mean time error
US20100115309A1 (en) * 2007-03-26 2010-05-06 Freescale Semiconductor, Inc. Anticipation of power on of a mobile device
US20110161627A1 (en) * 2009-12-28 2011-06-30 Song Justin J Mechanisms to avoid inefficient core hopping and provide hardware assisted low-power state selection
US20150286271A1 (en) * 2014-04-03 2015-10-08 Samsung Electronics Co., Ltd. System and method for predicting a central processing unit idle pattern for power saving in a modem system on chip
US20150370311A1 (en) * 2014-06-20 2015-12-24 Advanced Micro Devices, Inc. Decoupled entry and exit prediction for power gating
US20160321183A1 (en) * 2015-05-01 2016-11-03 Advanced Micro Devices, Inc. Early cache prefetching in preparation for exit from idle mode

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11385811B2 (en) 2020-02-10 2022-07-12 Samsung Electronics Co., Ltd. Storage device and method of operating the same
CN113900910A (zh) * 2021-12-08 2022-01-07 北京新唐思创教育科技有限公司 应用程序监控方法、装置、存储介质和电子设备
US20230368325A1 (en) * 2022-05-16 2023-11-16 Qualcomm Incorporated Technique to optimize power and performance of xr workload
US12045910B2 (en) * 2022-05-16 2024-07-23 Qualcomm Incorporated Technique to optimize power and performance of XR workload

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CN106055079B (zh) 2017-11-24
EP3401757A4 (en) 2019-03-06
US10444822B2 (en) 2019-10-15
EP3401757B1 (en) 2023-02-15
WO2017206858A1 (zh) 2017-12-07
CN106055079A (zh) 2016-10-26
US20190146573A1 (en) 2019-05-16

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