US20190131220A1 - Substrate structure, semiconductor package structure including the same, and semiconductor process for manufacturing the same - Google Patents
Substrate structure, semiconductor package structure including the same, and semiconductor process for manufacturing the same Download PDFInfo
- Publication number
- US20190131220A1 US20190131220A1 US15/795,201 US201715795201A US2019131220A1 US 20190131220 A1 US20190131220 A1 US 20190131220A1 US 201715795201 A US201715795201 A US 201715795201A US 2019131220 A1 US2019131220 A1 US 2019131220A1
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- United States
- Prior art keywords
- circuit layer
- conductive pillar
- layer
- substrate structure
- pads
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 239000004065 semiconductor Substances 0.000 title claims description 98
- 238000000034 method Methods 0.000 title description 44
- 238000004519 manufacturing process Methods 0.000 title description 10
- 239000010410 layer Substances 0.000 claims abstract description 271
- 239000011241 protective layer Substances 0.000 claims description 42
- 229910000679 solder Inorganic materials 0.000 claims description 27
- 239000008393 encapsulating agent Substances 0.000 claims description 21
- 239000002344 surface layer Substances 0.000 abstract 1
- 229910052751 metal Inorganic materials 0.000 description 30
- 239000002184 metal Substances 0.000 description 30
- 239000000463 material Substances 0.000 description 29
- 229920002120 photoresistant polymer Polymers 0.000 description 21
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 9
- 239000004642 Polyimide Substances 0.000 description 9
- 229910052802 copper Inorganic materials 0.000 description 9
- 239000010949 copper Substances 0.000 description 9
- 229920001721 polyimide Polymers 0.000 description 9
- 238000009713 electroplating Methods 0.000 description 8
- 239000004593 Epoxy Substances 0.000 description 7
- 150000002739 metals Chemical class 0.000 description 6
- 238000001459 lithography Methods 0.000 description 5
- 239000003989 dielectric material Substances 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 239000004743 Polypropylene Substances 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- 229920001155 polypropylene Polymers 0.000 description 3
- 239000012790 adhesive layer Substances 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
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- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
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- 238000005549 size reduction Methods 0.000 description 1
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- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
Definitions
- the present disclosure relates to a substrate structure, a semiconductor package structure and a manufacturing method, and to a substrate structure including at least one tapered conductive pillar, a semiconductor package structure including the substrate structure, and a method for manufacturing the substrate structure.
- functionality improvement and size reduction can be achieved by changing the materials thereof, or by changing the structural design thereof.
- the materials of the electronic device are changed, the settings or parameters of production equipment and the manufacturing methods may be modified accordingly, which can be complicated and expensive as compared to adjusting the structural design thereof.
- An efficient way for improving functionality and reducing size of the electronic device is achieved by a structural design with a reduced line width/line space (L/S) and increasing a number of, or density of, circuit layers.
- L/S line width/line space
- I/O input/output
- a substrate structure includes a dielectric layer, a first circuit layer, a second circuit layer and at least one conductive pillar.
- the dielectric layer includes a first surface and a second surface opposite to the first surface.
- the first circuit layer is disposed adjacent to the first surface of the dielectric layer.
- the second circuit layer is disposed adjacent to the second surface of the dielectric layer and electrically connected to the first circuit layer.
- the second circuit layer includes a plurality of pads and at least one trace disposed between two adjacent pads of the plurality of pads.
- the conductive pillar is tapered downwardly and disposed on one of the pads of the plurality of pads. A portion of the second surface of the dielectric layer is exposed from the second circuit layer.
- a semiconductor package structure includes a substrate structure, a semiconductor die and an encapsulant.
- the substrate structure includes a dielectric layer, a first circuit layer, a second circuit layer and at least one conductive pillar.
- the dielectric layer includes a first surface and a second surface opposite to the first surface.
- the first circuit layer is disposed adjacent to the first surface of the dielectric layer.
- the second circuit layer is disposed on the second surface of the dielectric layer and electrically connected to the first circuit layer.
- the second circuit layer includes a plurality of pads and at least one trace disposed between two adjacent pads of the plurality of pads.
- the conductive pillar is tapered downwardly and disposed on one of the pads of the plurality of pads.
- the semiconductor die is electrically connected to the at least one conductive pillar of the substrate structure.
- the encapsulant is disposed between the substrate structure and the semiconductor die, and directly contacts a portion of the second circuit layer.
- a semiconductor process includes (a) forming a first circuit layer; (b) forming a second circuit layer electrically connected to the first circuit layer, wherein the second circuit layer includes a plurality of pads and at least one trace disposed between two adjacent pads of the plurality of pads; (c) forming a first photoresist layer on the second circuit layer, the first photoresist layer defining one or more recesses; (d) forming at least one conductive pillar tapered downwardly in at least one of the recesses of the first photoresist layer and electrically connected to at least one of the pads of the plurality of pads; and (e) removing the first photoresist layer to form a substrate structure.
- FIG. 1 illustrates a cross-sectional view of an example of a substrate structure according to some embodiments of the present disclosure.
- FIG. 2 illustrates a cross-sectional view of an example of a substrate structure according to some embodiments of the present disclosure.
- FIG. 3 illustrates an enlarged view of an area “A” shown in FIG. 2 .
- FIG. 4 illustrates a cross-sectional view of an example of a semiconductor package structure according to some embodiments of the present disclosure.
- FIG. 5 illustrates a cross-sectional view of an example of a semiconductor package structure according to some embodiments of the present disclosure.
- FIG. 6 illustrates a cross-sectional view of an example of a semiconductor package structure according to some embodiments of the present disclosure.
- FIG. 7 illustrates one or more stages of an example of a semiconductor process according to some embodiments of the present disclosure.
- FIG. 8 illustrates one or more stages of an example of a semiconductor process according to some embodiments of the present disclosure.
- FIG. 9 illustrates one or more stages of an example of a semiconductor process according to some embodiments of the present disclosure.
- FIG. 10 illustrates one or more stages of an example of a semiconductor process according to some embodiments of the present disclosure.
- FIG. 11 illustrates one or more stages of an example of a semiconductor process according to some embodiments of the present disclosure.
- FIG. 12 illustrates one or more stages of an example of a semiconductor process according to some embodiments of the present disclosure.
- FIG. 13 illustrates one or more stages of an example of a semiconductor process according to some embodiments of the present disclosure.
- FIG. 14 illustrates one or more stages of an example of a semiconductor process according to some embodiments of the present disclosure.
- FIG. 15 illustrates one or more stages of an example of a semiconductor process according to some embodiments of the present disclosure.
- FIG. 16 illustrates one or more stages of an example of a semiconductor process according to some embodiments of the present disclosure.
- FIG. 17 illustrates one or more stages of an example of a semiconductor process according to some embodiments of the present disclosure.
- FIG. 18 illustrates one or more stages of an example of a semiconductor process according to some embodiments of the present disclosure.
- FIG. 19 illustrates one or more stages of an example of a semiconductor process according to some embodiments of the present disclosure.
- FIG. 20 illustrates one or more stages of an example of a semiconductor process according to some embodiments of the present disclosure.
- FIG. 21 illustrates one or more stages of an example of a semiconductor process according to some embodiments of the present disclosure.
- FIG. 22 illustrates one or more stages of an example of a semiconductor process according to some embodiments of the present disclosure.
- FIG. 23 illustrates a schematic perspective view of an example of a combination of a carrier, a substrate structure and a plurality of semiconductor dice.
- FIG. 24 illustrates a schematic perspective view of another example of a combination of a carrier, a substrate structure and a plurality of semiconductor dice.
- FIG. 25 illustrates one or more stages of an example of a semiconductor process according to some embodiments of the present disclosure.
- FIG. 26 illustrates one or more stages of an example of a semiconductor process according to some embodiments of the present disclosure.
- FIG. 27 illustrates one or more stages of an example of a semiconductor process according to some embodiments of the present disclosure.
- first and second features are formed or disposed in direct contact
- additional features may be formed or disposed between the first and second features, such that the first and second features may not be in direct contact
- present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
- At least some embodiments of the present disclosure disclose a substrate structure including at least one tapered conductive pillar. At least some embodiments of the present disclosure further disclose a semiconductor package structure including the substrate structure, and techniques for manufacturing the substrate structure and/or the semiconductor package structure.
- the traces and the bump pads for external connection can be disposed at a same level. Since the bump pads are provided with sufficient area for external connection, a line width/line space (L/S) of such a substrate structure can be correspondingly limited. Besides, when a semiconductor die is connected to the bump pads of the substrate structure by using solder structures, overflow of the solder may readily occur, which can result in bridges between the bump pads and the adjacent traces.
- L/S line width/line space
- bump pads and the traces are disposed separately at different layers to avoid such bridges therebetween.
- such design can increase manufacturing cost and total thickness of the substrate structure due to the additional layer(s).
- conductive pillars protruding from the circuit layer for connecting to a semiconductor die such that solder structures and trace are not disposed at a same level. Accordingly, bridges caused by solder overflow can be avoided.
- the conductive pillars can be in a columnar shape with a consistent radius. For such pillars, when the area of the upper surface of the conductive pillar is sufficient for retaining the solder, the lower surface of the conductive pillar can occupy a large area of the circuit layer, resulting in a specification of a narrow line width/line space (L/S), which can be challenging to implement.
- L/S narrow line width/line space
- one or more embodiments of the present disclosure provides a substrate structure including at least one tapered conductive pillar.
- the tapered conductive pillar provides a larger upper surface which is at least sufficient for connection with a semiconductor die, and a smaller lower surface to reduce an occupied area of a circuit layer on which the conductive pillar is disposed.
- FIG. 1 illustrates a cross-sectional view of an example of a substrate structure 1 according to some embodiments of the present disclosure.
- the substrate structure 1 includes a dielectric layer 2 , a first circuit layer 3 , a second circuit layer 4 , a plurality of inner vias 12 , at least one conductive pillar 5 and a protective layer 16 .
- the dielectric layer 2 has a first surface 21 and a second surface 22 opposite to the first surface 21 .
- the dielectric layer 2 may include an insulating material or a dielectric material, such as, for example, polypropylene (PP). It is noted that the dielectric layer 2 may include, or be formed from, a cured photoimageable dielectric (PID) material such as epoxy or polyimide (PI) including photoinitiators.
- PID cured photoimageable dielectric
- the dielectric layer 2 defines a plurality of through holes 20 extending between the first surface 21 and the second surface 22 . In some embodiments, a thickness of the dielectric layer 2 may be in a range of about 3 micrometers ( ⁇ m) to about 10 ⁇ m.
- the first circuit layer 3 is disposed adjacent to the first surface 21 of the dielectric layer 2 .
- the first circuit layer 3 is embedded in the dielectric layer 2 and exposed from the first surface 21 of the dielectric layer 2 .
- the first circuit layer 3 is a patterned conductive circuit layer.
- a material of the first circuit layer 3 may include a conductive metal, such as copper, or another metal or combination of metals.
- the first circuit layer 3 may be formed by etching a metal layer.
- the line width/line space (L/S) of the first circuit layer 3 may be greater than about 7 ⁇ m/about 7 ⁇ m (e.g.
- a thickness of the first circuit layer 3 may be in a range of about 2 ⁇ m to about 5 ⁇ m. As shown in FIG. 1 , the first circuit layer 3 may have a substantially consistent thickness, and a bottom surface of the first circuit layer 3 may be substantially coplanar with the first surface 21 of the dielectric layer 2 . One or more portions of a top surface of the first circuit layer 3 are exposed by the through holes 20 of the dielectric layer 2 .
- the second circuit layer 4 is disposed adjacent to the second surface 22 of the dielectric layer 2 and electrically connected to the first circuit layer 3 .
- the second circuit layer 4 is disposed on the second surface 22 of the dielectric layer 2 , while a portion of the second surface 22 of the dielectric layer 2 is a free surface that is not covered by any other portion or component of the substrate structure 1 (or, in some implementations, not covered by any element or material), or is exposed from the second circuit layer 4 .
- the second circuit layer 4 is includes a redistribution layer (RDL).
- the second circuit layer 4 has an upper surface 41 , and includes a plurality of pads 44 and at least one trace 46 .
- the trace 46 is connected (electrically connected and/or physically connected) to at least one of the pads 44 and is disposed between two adjacent pads 44 .
- a material of the second circuit layer 4 may include a conductive metal, such as copper, or another metal or combination of metals, and may be formed or disposed by electroplating.
- Each of the inner vias 12 is disposed in a respective one of the through holes 20 of the dielectric layer 2 and extends between the first circuit layer 3 and the second circuit layer 4 .
- the second circuit layer 4 is electrically connected to the first circuit layer 3 through the inner vias 12 .
- the vias 12 may be formed concurrently with the second circuit layer 4 .
- a line width/line space (L/S) of the second circuit layer 4 is less than a line width/line space (L/S) of the first circuit layer 3 .
- the line width/line space (L/S) of the second circuit layer 4 may be less than about 7 ⁇ m/about 7 ⁇ m, such as less than about 5 ⁇ m/about 5 ⁇ m, less than about 3 ⁇ m/about 3 ⁇ m, or less than about 2 ⁇ m/about 2 ⁇ m.
- a thickness of the second circuit layer 4 may be in a range of about 4 ⁇ m to about 6 ⁇ m.
- a thickness of the first circuit layer 3 is less than a thickness of the second circuit layer 4 , which can balance warpage of the substrate structure 1 caused by connection of a semiconductor die 62 (e.g. as shown in FIG. 4 ) to the second circuit layer 4 .
- a roughness (Ra) of the upper surface 41 of the second circuit layer 4 may be less than about 50 nanometer (nm), such as less than about 40 nm or less than about 30 nm.
- a seed layer 14 may be disposed between the second circuit layer 4 and the dielectric layer 2 , and between the inner vias 12 and the dielectric layer 2 .
- the seed layer 14 is covered (e.g. is completely covered) by the second circuit layer 4 and the inner vias 12 .
- the seed layer 14 may include, for example, titanium and/or copper, another metal, or an alloy thereof, and may be formed or disposed by sputtering.
- the conductive pillar 5 is tapered downwardly towards the second surface 22 (e.g. a width of the conductive pillar 5 decreases, e.g. monotonically decreases) from an upper portion of the conductive pillar 5 to a lower portion of the conductive pillar 5 ) and disposed on one of the pads 44 of the second circuit layer 4 .
- the conductive pillar 5 is directly disposed on the one of the pads 44 of the second circuit layer 4 .
- the conductive pillar 5 has an upper surface 51 , a lower surface 52 and a sidewall 53 .
- the lower surface 52 is opposite to the upper surface 51
- the sidewall 53 extends between the lower surface 52 and the upper surface 51 .
- the lower surface 52 of the conductive pillar 5 is connected to and physically contacts the respective pad 44 of the second circuit layer 4 .
- the conductive pillar 5 may be shaped as a circular truncated cone.
- the upper surface 51 and the lower surface 52 may be substantially circular.
- a material of the conductive pillar 5 may include a conductive metal, such as copper, or another metal or combination of metals, and may be formed or disposed by electroplating.
- the material of the conductive pillar 5 may be the same as the material of the second circuit layer 4 .
- there is no seed layer between the conductive pillar 5 and the upper surface 41 of the second circuit layer 4 the conductive pillar 5 can grow directly from the upper surface 41 of the second circuit layer 4 , and thus lattices of the second circuit layer 4 and the conductive pillars 5 may be continuous (e.g. the second circuit layer 4 and at least one of the conductive pillars 5 may share a solid or crystalline lattice).
- the conductive pillar 5 and the second circuit layer 4 may be a continuous structure without a boundary therebetween (e.g. may constitute a monolithic structure).
- the conductive pillar 5 is directly located on part of the second circuit layer 4 , and the lattice of the conductive pillar 5 is the same as that of the second circuit layer 4 .
- the conductive pillar 5 includes electroplated copper, which is directly formed on the upper surface 41 of the second circuit layer 4 by electroplating.
- a focused ion beam FIB
- the conductive pillar 5 is tapered from the upper surface 51 to the lower surface 52 .
- a width W 1 of the upper surface 51 is greater than a width W 2 of the lower surface 52 , for example, at least about 1.05 times greater, at least about 1.1 times greater, at least about 1.2 times greater, or at least about 1.3 times greater.
- the shape of the conductive pillar 5 from the cross-sectional view as shown in FIG. 1 is substantially a trapezoid (e.g. a trapezoid with a concave upper surface), and the width of the conductive pillar 5 decreases from the upper surface 51 toward the lower surface 52 .
- an angle ⁇ is defined by the sidewall 53 of the conductive pillar 5 and an upper surface 41 of the second circuit layer 4 .
- the angle ⁇ is equal to or greater than about 60 degrees but less than about 90 degrees.
- the angle ⁇ is equal to or greater than about 65 degrees but less than about 87 degrees; equal to or greater than about 70 degrees but less than about 85 degrees; or equal to or greater than about 75 degrees but less than about 82 degrees.
- an edge e.g. a top edge of an upper portion (e.g. the upper surface 51 ) of the conductive pillar 5 is directly located above the trace 46 of the second circuit layer 4 .
- the conductive pillar 5 is a monolithic structure, and the sidewall 53 thereof is a continuous surface. In some embodiments, a maximum height of the conductive pillar 5 may be in a range of about 50 ⁇ m to about 100 ⁇ m.
- the upper surface 51 of the conductive pillar 5 is concave toward the second circuit layer 4 . That is, the upper portion of the conductive pillar 5 is substantially in a bowl shape.
- the conductive pillar 5 can retain or receive a solder structure 626 of the semiconductor die 62 in the concave upper surface 51 so as to prevent a bridge between the conductive pillar 5 and the trace 46 .
- the protective layer 16 is disposed on the first surface 21 of the dielectric layer 2 and the first circuit layer 3 .
- the protective layer 16 may include, or be formed from, a cured PID material such as epoxy or a PI including photoinitiators, or a solder resist layer.
- the protective layer 16 defines an opening 160 extending through the protective layer 16 . A portion of the first circuit layer 3 is exposed in the opening 160 for external connection.
- a thickness of the protective layer 16 may be in a range of about 25 ⁇ m to about 90 ⁇ m.
- the conductive pillar 5 is tapered downwardly, the upper surface 51 is large enough to retain the solder structure 626 thereon when connecting to the semiconductor die 62 (as shown in FIG. 4 ), avoiding a potential short circuit caused by overflow of the solder of the solder structure 626 .
- the lower surface 52 of the conductive pillar is smaller than the upper surface 51 , and thus a size of the pad 44 on which the lower surface 52 is disposed can be correspondingly reduced. Accordingly, the pads 44 occupy a relatively small area of the second surface 22 of the dielectric layer 2 , as compared to implementations that omit a tapered conductive pillar 5 , while the remaining area of the second surface 22 of the dielectric layer 2 can be increased.
- the line width/line space (L/S) of the second circuit layer 4 can thus be larger than would otherwise be the case, which provides for use of less costly or faster lithography techniques or processes.
- FIG. 2 illustrates a cross-sectional view of an example of a substrate structure 1 a according to some embodiments of the present disclosure.
- FIG. 3 illustrates an enlarged view of the area “A” shown in FIG. 2 .
- the substrate structure 1 a is similar to the substrate structure 1 shown in FIG. 1 , except that the structure of a first circuit layer 3 a of the substrate structure 1 a is different from the first circuit layer 3 of the substrate structure 1 in FIG. 1 .
- the first circuit layer 3 a includes a first portion 31 and a second portion 32 surrounding the first portion 31 .
- the first portion 31 has a surface 311
- the second portion 32 has a surface 321 .
- the surface 321 of the second portion 32 is substantially coplanar with the first surface 21 of the dielectric layer 2 .
- the surface 311 of the first portion 31 is recessed from the first surface 21 of the dielectric layer 2 and the surface 321 of the second portion 32 . That is, the first circuit layer 3 a defines a recess portion 34 corresponding to the first portion 31 .
- the protective layer 16 covers the second portion 32 of the first circuit layer 3 a.
- the opening 160 of the protective layer 16 corresponds to the first portion 31 of the first circuit layer 3 a. Accordingly, the opening 160 defined by the protective layer 16 exposes (e.g. completely exposes) the first portion 31 of the first circuit layer 3 a, and the recess portion 34 of the first circuit layer 3 a is substantially co-extensive with the opening 160 of the protective layer 16 .
- a width W 3 of the opening 160 of the protective layer 16 is substantially equal to a width W 4 of the recess portion 34 of the first circuit layer 3 a.
- the recess portion 34 of the first circuit layer 3 a provides enlarged contacting area between the solder ball and the first circuit layer 3 a.
- FIG. 4 illustrates a cross-sectional view of an example of a semiconductor package structure 6 according to some embodiments of the present disclosure.
- the semiconductor package structure 6 includes a substrate structure 1 , a semiconductor die 62 , an encapsulant 64 and a solder ball 18 .
- the substrate structure 1 shown in FIG. 4 is similar to the substrate structure 1 shown in FIG. 1 .
- the semiconductor die 62 is disposed on the substrate structure 1 and electrically connected to the conductive pillar 5 of the substrate structure 1 .
- a thickness of the semiconductor die 62 may be about 500 ⁇ m (e.g. may be in a range of about 400 ⁇ m to about 600 ⁇ m).
- the semiconductor die 62 includes an active surface 621 , a side surface 623 , at least one bump 624 and at least one solder structure 626 .
- the active surface 621 of the semiconductor die 62 faces the substrate structure 1 .
- the bump 624 of the semiconductor die 62 is disposed on the active surface 621 , and is connected to the conductive pillar 5 of the substrate structure 1 through the solder structure 626 .
- the solder structure 626 is disposed between the conductive pillar 5 and the bump 624 .
- a width W 1 of the upper surface of the conductive pillar 5 is greater than a width W 5 of the bump 624 of the die 62 .
- the solder structure 626 contacts the upper surface 51 of the conductive pillar 5 .
- the encapsulant 64 for example, a molding compound, is disposed between the substrate structure 1 and the semiconductor die 62 , and directly contacts a portion of the second circuit layer 4 .
- the encapsulant 64 may cover the active surface 621 of the semiconductor die 62 without covering the side surface 623 of the semiconductor die 62 .
- a side surface 641 of the encapsulant 64 may be substantially coplanar with the side surface 623 of the semiconductor die 62 .
- the encapsulant 64 covers (e.g. completely covers) a sidewall 53 of the conductive pillar 5 .
- the encapsulant 64 directly contacts the sidewall 53 of the conductive pillar 5 .
- the encapsulant 64 contacts a portion of the second surface 22 of the dielectric layer 2 of the substrate structure 1 .
- a thickness of the encapsulant 64 may be in a range of about 60 ⁇ m to about 150 ⁇ m.
- the solder ball 18 is disposed in the opening 160 of the protective layer 16 of the substrate structure 1 .
- the solder ball 18 is attached and electrically connected to the first circuit layer 3 and protrudes from the protective layer 16 for external connection.
- the substrate structure 1 of the semiconductor package structure 6 can be replaced by the substrate structure 1 a shown in FIG. 2 and FIG. 3 .
- FIG. 5 illustrates a cross-sectional view of an example of a semiconductor package structure 6 a according to some embodiments of the present disclosure.
- the semiconductor package structure 6 a is similar to the semiconductor package structure 6 shown in FIG. 4 , except that the encapsulant 64 further covers the side surface 623 of the semiconductor die 62 .
- FIG. 6 illustrates a cross-sectional view of an example of a semiconductor package structure 6 b including a substrate structure 1 b according to some embodiments of the present disclosure.
- the semiconductor package structure 6 b including the substrate structure 1 b is similar to the semiconductor package structure 6 including the substrate structure 1 shown in FIG. 4 , except that the substrate structure 1 b of the semiconductor package structure 6 b includes an additional dielectric layer 2 a and an intermediate circuit layer 4 a respectively similar to the dielectric layer 2 and the second circuit layer 4 .
- the additional dielectric layer 2 a is disposed between the dielectric layer 2 and the first circuit layer 3 .
- the intermediate circuit layer 4 a is disposed between the dielectric layer 2 and the additional dielectric layer 2 a, and is electrically connected to the first circuit layer 3 and the second circuit layer 4 .
- the substrate structure 1 b of the semiconductor package structure 6 b may include more than one additional dielectric layer 2 a and/or more than one intermediate circuit layer 4 a.
- FIG. 7 through FIG. 26 illustrate a semiconductor process according to some embodiments of the present disclosure.
- the semiconductor process is for manufacturing a substrate structure such as the substrate structure 1 shown in FIG. 1 , and/or a semiconductor package structure such as the semiconductor structure 6 a shown in FIG. 5 .
- the protective layer 16 may include a PID material, such as epoxy or a PI including photoinitiators, or a solder resist layer.
- the metal layer 81 may include copper or other conductive metals or an alloy thereof.
- the protective layer 16 has a first side 161 and a second side 162 opposite to the first side 161 .
- the metal layer 81 is disposed on the first side 161 of the protective layer 16 .
- the protective layer 16 is exposed to a pattern of light.
- a mask 82 is disposed adjacent to the second side 162 of the protective layer 16 , so as to cover a portion of the protective layer 16 .
- the protective layer 16 is exposed to a radiation source 83 .
- an etching process is conducted to the metal layer 81 to reduce a thickness of the metal layer 81 (e.g. before developing the protective layer 16 ). Since the protective layer 16 is not yet developed, the protective layer 16 can readily support the thinned metal layer 81 .
- the protective layer 16 is then developed by a developer from the second side 162 . That is, the protective layer 16 is patterned, and a portion 811 of the metal layer 82 is exposed from the protective layer 16 .
- the protective layer 16 defines at least one opening 160 extending through the protective layer 16 . The portion 811 of the metal layer 81 is exposed in the opening 160 of the protective layer 16 .
- a carrier 86 is attached to the second side 162 of the protective layer 16 through an adhesive layer 84 for support.
- a first photoresist material 88 is applied on the metal layer 81 .
- the first photoresist material 88 may include a PID material, such as epoxy or a PI including photoinitiators.
- the first photoresist material 88 is patterned (e.g., by a lithography technique) to form at least one rigid portion 89 .
- the metal layer 81 is patterned (e.g., by etching with the rigid portion 89 serving as a mask), to form a first circuit layer 3 .
- the rigid portion 89 is then removed, (e.g., by stripping).
- a dielectric material 90 is applied on and covers the first side 161 of the protective layer 16 and the first circuit layer 3 .
- the dielectric material 90 may include PP, or a PID material such as epoxy or a PI including photoinitiators.
- the dielectric material 90 is patterned (e.g., by a lithography technique) to form a dielectric layer 2 on the first circuit layer 3 .
- the dielectric layer 2 has a first surface 21 and a second surface 22 opposite to the first surface 21 , and the first surface 21 is disposed on the first side 161 of the protective layer 16 .
- the dielectric layer 2 defines a plurality of through holes 20 extending between the first surface 21 and the second surface 22 to expose portions of the first circuit layer 3 .
- a seed layer 14 is formed (e.g., by sputtering) on the second surface 22 of the dielectric layer 2 and in the through holes 20 of the dielectric layer 2 to contact the first circuit layer 3 .
- a second photoresist material 92 is provided or applied on the seed layer 14 .
- the second photoresist material 92 may include a PID material, such as epoxy or a PI including photoinitiators.
- the second photoresist material 92 is patterned (e.g., by a lithography technique) to form a first photoresist layer 93 on the seed layer 14 .
- a second circuit layer 4 is formed (e.g., by electroplating) on the seed layer 14 and in recesses of the first photoresist layer 93 .
- the second circuit layer 4 is electrically connected to the first circuit layer 3 .
- the second circuit layer 4 includes a plurality of pads 44 and at least one trace 46 .
- the trace 46 is connected to at least one of the pads 44 and is disposed between two adjacent pads 44 .
- a material of the second circuit layer 4 may include a conductive metal, such as copper, or another metal or combination of metals, and may be formed or disposed by electroplating.
- a plurality of inner vias 12 are respectively disposed (e.g., by electroplating) in ones of the through holes 20 of the dielectric layer 2 to connect the first circuit layer 3 and the second circuit layer 4 .
- the inner vias 12 can be formed concurrently with the second circuit layer 4 .
- a third photoresist material 94 is disposed on the first photoresist layer 93 and the second circuit layer 4 .
- the third photoresist material 94 may include a PID material, such as epoxy or a polyimide PI including photoinitiators.
- the third photoresist material 94 is patterned (e.g., by a lithography technique) to form a second photoresist layer 95 on the second circuit layer 4 .
- the second photoresist layer 95 defines at least one opening 951 to expose a portion of an upper surface 41 of the pad 44 of the second circuit layer 4 .
- at least one conductive pillar 5 tapered downwardly is formed in the opening 951 of the second photoresist layer 95 and electrically connected to one of the pads 44 of the second circuit layer 4 .
- the conductive pillar 5 may be directly disposed on the one of the pads 44 of the second circuit layer 4 .
- the conductive pillar 5 has an upper surface 51 , a lower surface 52 opposite to the upper surface 51 , and a sidewall 53 .
- a material of the conductive pillar 5 may include a conductive metal, such as copper, or another metal or combination of metals, and may be formed or disposed by electroplating.
- the material of the conductive pillar 5 may be the same as the material of the second circuit layer 4 .
- there is no seed layer between the conductive pillar 5 and the upper surface 41 of the second circuit layer 4 the conductive pillar 5 can grow directly from the upper surface 41 of the second circuit layer 4 , and lattices of the second circuit layer 4 and the conductive pillars 5 may be continuous.
- the conductive pillar 5 and the second circuit layer 4 may be continuous without a boundary therebetween.
- the conductive pillar 5 is directly located on a portion of the second circuit layer 4 , wherein the lattice of the conductive pillar 5 is the same as that of the second circuit layer 4 (e.g. the conductive pillar 5 and the second circuit layer 4 share a lattice).
- the conductive pillar 5 is made from electroplated copper, which is directly formed on the upper surface 41 of the second circuit layer 4 by electroplating.
- a width of the upper surface 51 is greater than a width of the lower surface 52 , and the upper surface 51 of the conductive pillar 5 is concave.
- An angle ⁇ defined by the sidewall 53 of the conductive pillar 5 and the upper surface 41 of the second circuit layer 4 is equal to or greater than about 60 degrees but less than about 90 degrees.
- an edge (e.g. a top edge) of an upper portion (e.g. the upper surface 51 ) of the conductive pillar 5 is directly located above the trace 46 of the second circuit layer 4 .
- the first photoresist layer 93 and the second photoresist layer 95 are removed (e.g., by stripping).
- a portion of the seed layer 14 which is not covered by the second circuit layer 4 and the inner vias 12 is removed (e.g., by etching). Accordingly, a substrate structure 1 as shown in FIG. 1 is formed on the carrier 86 and attached to the carrier 86 by the adhesive layer 84 .
- the semiconductor die 62 has an active surface 621 and a side surface 623 , and includes at least one bump 624 and at least one solder structure 626 connected to the at least one bump 624 .
- the semiconductor die 62 is disposed on and connected to the substrate structure 1 (e.g., by a reflow process).
- the active surface 621 of the semiconductor die 62 faces the substrate structure 1 .
- the semiconductor die 62 is electrically connected to the conductive pillar 5 of the substrate structure 1 .
- the bump 624 of the semiconductor die 62 is connected to the conductive pillar 5 of the substrate structure 1 through the solder structure 626 .
- the solder structure 626 contacts the upper surface 51 of the conductive pillar 5 .
- a width W 1 of the upper surface of the conductive pillar 5 is greater than a width W 5 of the bump 624 of the die 62 .
- FIG. 23 illustrates a schematic perspective view of an example of a combination of a carrier 86 , a substrate structure 1 and a plurality of semiconductor dice 62 (e.g. as depicted in FIG. 22 ) according to some embodiments of the present disclosure.
- the shapes of the substrate structure 1 and the carrier 86 may be, for example, rectangular or square.
- FIG. 24 illustrates a schematic perspective view of another example of a combination of a carrier 86 a, a substrate structure 1 c and a plurality of semiconductor dice 6 according to some embodiments of the present disclosure.
- the shapes of the substrate structure 1 c and the carrier 86 a may be, for example, circular or elliptical.
- an encapsulant 64 is disposed or formed between a semiconductor die 62 and a substrate structure 1 , and directly contacts a portion of a second circuit layer 4 .
- the encapsulant 64 may cover an active surface 621 and a side surface 623 of the semiconductor die 62 .
- the encapsulant 64 covers (e.g. completely covers) the sidewall 53 of the conductive pillar 5 .
- the encapsulant 64 directly contacts the sidewall 53 of the conductive pillar 5 .
- the encapsulant 64 contacts a portion of the second surface 22 of the dielectric layer 2 of the substrate structure 1 .
- the carrier 86 and the adhesion layer 84 are removed. Then, a solder ball 18 is disposed in the opening 160 of the protective layer 16 and attached to the first circuit layer 3 for external connection. Then, a singulation process is performed, thus forming the semiconductor package structure 6 a as shown in FIG. 5 .
- the semiconductor dice 62 shown in FIG. 23 or FIG. 24 may be replaced by a single wafer.
- the encapsulant 64 may not cover the side surface 623 of the semiconductor die 62 , and a side surface 641 of the encapsulant 64 may be substantially coplanar with the side surface 623 of the semiconductor die 62 , forming the semiconductor package structure 6 as shown in FIG. 4
- FIG. 27 illustrates a semiconductor process according to some embodiments of the present disclosure.
- the semiconductor process is for manufacturing a substrate structure such as the substrate structure 1 a shown in FIG. 2 and FIG. 3 , and/or a semiconductor package structure including such substrate structure.
- FIG. 27 depicts a stage subsequent to that depicted in FIG. 9 .
- the protective layer 16 is developed by a developer.
- the protective layer 16 defines an opening 160 extending through the protective layer 16 .
- a portion 811 a of the metal layer 81 exposed in the opening 160 of the protective layer 16 is also etched.
- the portion 811 a of the metal layer 81 is slightly recessed to form a recess portion 34 .
- the stages subsequent to FIG. 27 of the illustrated process are similar to the stages illustrated in FIG. 11 through FIG. 26 .
- the portion 811 a forms the first portion 31 of the first circuit layer 3 , thus forming the substrate structure 1 a as shown in FIG. 2 and FIG. 3 and/or the semiconductor package structure including the same.
- the terms “approximately,” “substantially,” “substantial” and “about” are used to describe and account for small variations. When used in conjunction with an event or circumstance, the terms can refer to instances in which the event or circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation.
- the terms can refer to a range of variation less than or equal to ⁇ 10% of that numerical value, such as less than or equal to ⁇ 5%, less than or equal to ⁇ 4%, less than or equal to ⁇ 3%, less than or equal to ⁇ 2%, less than or equal to ⁇ 1%, less than or equal to ⁇ 0.5%, less than or equal to ⁇ 0.1%, or less than or equal to ⁇ 0.05%.
- two numerical values can be deemed to be “substantially” the same or equal if a difference between the values is less than or equal to ⁇ 10% of an average of the values, such as less than or equal to ⁇ 5%, less than or equal to ⁇ 4%, less than or equal to ⁇ 3%, less than or equal to ⁇ 2%, less than or equal to ⁇ 1%, less than or equal to ⁇ 0.5%, less than or equal to ⁇ 0.1%, or less than or equal to ⁇ 0.05%.
- substantially parallel can refer to a range of angular variation relative to 0° that is less than or equal to ⁇ 10°, such as less than or equal to ⁇ 5°, less than or equal to ⁇ 4°, less than or equal to ⁇ 3°, less than or equal to ⁇ 2°, less than or equal to ⁇ 1°, less than or equal to ⁇ 0.5°, less than or equal to ⁇ 0.1°, or less than or equal to ⁇ 0.05°.
- substantially perpendicular can refer to a range of angular variation relative to 90° that is less than or equal to ⁇ 10°, such as less than or equal to ⁇ 5°, less than or equal to ⁇ 4°, less than or equal to ⁇ 3°, less than or equal to ⁇ 2°, less than or equal to ⁇ 1°, less than or equal to ⁇ 0.5°, less than or equal to ⁇ 0.1°, or less than or equal to ⁇ 0.05°.
- a surface can be deemed to be planar or substantially planar if a difference between a highest point and a lowest point of the surface is no greater than 5 no greater than 2 no greater than 1 or no greater than 0.5
- Two surfaces can be deemed to be coplanar or substantially coplanar if a displacement between the two surfaces is no greater than 5 ⁇ m, no greater than 2 ⁇ m, no greater than 1 ⁇ m, or no greater than 0.5 ⁇ m.
- a component provided “on” or “over” another component can encompass cases where the former component is directly on (e.g., in physical contact with) the latter component, as well as cases where one or more intervening components are located between the former component and the latter component.
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Abstract
Description
- The present disclosure relates to a substrate structure, a semiconductor package structure and a manufacturing method, and to a substrate structure including at least one tapered conductive pillar, a semiconductor package structure including the substrate structure, and a method for manufacturing the substrate structure.
- In an electronic device, functionality improvement and size reduction can be achieved by changing the materials thereof, or by changing the structural design thereof. When the materials of the electronic device are changed, the settings or parameters of production equipment and the manufacturing methods may be modified accordingly, which can be complicated and expensive as compared to adjusting the structural design thereof. An efficient way for improving functionality and reducing size of the electronic device is achieved by a structural design with a reduced line width/line space (L/S) and increasing a number of, or density of, circuit layers. However, an input/output (I/O) count and a total thickness of such an electronic device are issues of concern.
- In some embodiments, according to an aspect, a substrate structure includes a dielectric layer, a first circuit layer, a second circuit layer and at least one conductive pillar. The dielectric layer includes a first surface and a second surface opposite to the first surface. The first circuit layer is disposed adjacent to the first surface of the dielectric layer. The second circuit layer is disposed adjacent to the second surface of the dielectric layer and electrically connected to the first circuit layer. The second circuit layer includes a plurality of pads and at least one trace disposed between two adjacent pads of the plurality of pads. The conductive pillar is tapered downwardly and disposed on one of the pads of the plurality of pads. A portion of the second surface of the dielectric layer is exposed from the second circuit layer.
- In some embodiments, according to another aspect, a semiconductor package structure includes a substrate structure, a semiconductor die and an encapsulant. The substrate structure includes a dielectric layer, a first circuit layer, a second circuit layer and at least one conductive pillar. The dielectric layer includes a first surface and a second surface opposite to the first surface. The first circuit layer is disposed adjacent to the first surface of the dielectric layer. The second circuit layer is disposed on the second surface of the dielectric layer and electrically connected to the first circuit layer. The second circuit layer includes a plurality of pads and at least one trace disposed between two adjacent pads of the plurality of pads. The conductive pillar is tapered downwardly and disposed on one of the pads of the plurality of pads. The semiconductor die is electrically connected to the at least one conductive pillar of the substrate structure. The encapsulant is disposed between the substrate structure and the semiconductor die, and directly contacts a portion of the second circuit layer.
- In some embodiments, according to another aspect, a semiconductor process includes (a) forming a first circuit layer; (b) forming a second circuit layer electrically connected to the first circuit layer, wherein the second circuit layer includes a plurality of pads and at least one trace disposed between two adjacent pads of the plurality of pads; (c) forming a first photoresist layer on the second circuit layer, the first photoresist layer defining one or more recesses; (d) forming at least one conductive pillar tapered downwardly in at least one of the recesses of the first photoresist layer and electrically connected to at least one of the pads of the plurality of pads; and (e) removing the first photoresist layer to form a substrate structure.
- Aspects of some embodiments of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that various structures may not be drawn to scale, and dimensions of the various structures may be arbitrarily increased or reduced for clarity of discussion.
-
FIG. 1 illustrates a cross-sectional view of an example of a substrate structure according to some embodiments of the present disclosure. -
FIG. 2 illustrates a cross-sectional view of an example of a substrate structure according to some embodiments of the present disclosure. -
FIG. 3 illustrates an enlarged view of an area “A” shown inFIG. 2 . -
FIG. 4 illustrates a cross-sectional view of an example of a semiconductor package structure according to some embodiments of the present disclosure. -
FIG. 5 illustrates a cross-sectional view of an example of a semiconductor package structure according to some embodiments of the present disclosure. -
FIG. 6 illustrates a cross-sectional view of an example of a semiconductor package structure according to some embodiments of the present disclosure. -
FIG. 7 illustrates one or more stages of an example of a semiconductor process according to some embodiments of the present disclosure. -
FIG. 8 illustrates one or more stages of an example of a semiconductor process according to some embodiments of the present disclosure. -
FIG. 9 illustrates one or more stages of an example of a semiconductor process according to some embodiments of the present disclosure. -
FIG. 10 illustrates one or more stages of an example of a semiconductor process according to some embodiments of the present disclosure. -
FIG. 11 illustrates one or more stages of an example of a semiconductor process according to some embodiments of the present disclosure. -
FIG. 12 illustrates one or more stages of an example of a semiconductor process according to some embodiments of the present disclosure. -
FIG. 13 illustrates one or more stages of an example of a semiconductor process according to some embodiments of the present disclosure. -
FIG. 14 illustrates one or more stages of an example of a semiconductor process according to some embodiments of the present disclosure. -
FIG. 15 illustrates one or more stages of an example of a semiconductor process according to some embodiments of the present disclosure. -
FIG. 16 illustrates one or more stages of an example of a semiconductor process according to some embodiments of the present disclosure. -
FIG. 17 illustrates one or more stages of an example of a semiconductor process according to some embodiments of the present disclosure. -
FIG. 18 illustrates one or more stages of an example of a semiconductor process according to some embodiments of the present disclosure. -
FIG. 19 illustrates one or more stages of an example of a semiconductor process according to some embodiments of the present disclosure. -
FIG. 20 illustrates one or more stages of an example of a semiconductor process according to some embodiments of the present disclosure. -
FIG. 21 illustrates one or more stages of an example of a semiconductor process according to some embodiments of the present disclosure. -
FIG. 22 illustrates one or more stages of an example of a semiconductor process according to some embodiments of the present disclosure. -
FIG. 23 illustrates a schematic perspective view of an example of a combination of a carrier, a substrate structure and a plurality of semiconductor dice. -
FIG. 24 illustrates a schematic perspective view of another example of a combination of a carrier, a substrate structure and a plurality of semiconductor dice. -
FIG. 25 illustrates one or more stages of an example of a semiconductor process according to some embodiments of the present disclosure. -
FIG. 26 illustrates one or more stages of an example of a semiconductor process according to some embodiments of the present disclosure. -
FIG. 27 illustrates one or more stages of an example of a semiconductor process according to some embodiments of the present disclosure. - Common reference numerals are used throughout the drawings and the detailed description to indicate the same or similar components. Embodiments of the present disclosure will be readily understood from the following detailed description taken in conjunction with the accompanying drawings.
- The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to explain certain aspects of the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed or disposed in direct contact, and may also include embodiments in which additional features may be formed or disposed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
- At least some embodiments of the present disclosure disclose a substrate structure including at least one tapered conductive pillar. At least some embodiments of the present disclosure further disclose a semiconductor package structure including the substrate structure, and techniques for manufacturing the substrate structure and/or the semiconductor package structure.
- In a substrate structure, the traces and the bump pads for external connection can be disposed at a same level. Since the bump pads are provided with sufficient area for external connection, a line width/line space (L/S) of such a substrate structure can be correspondingly limited. Besides, when a semiconductor die is connected to the bump pads of the substrate structure by using solder structures, overflow of the solder may readily occur, which can result in bridges between the bump pads and the adjacent traces.
- In one or more implementations, bump pads and the traces are disposed separately at different layers to avoid such bridges therebetween. However, such design can increase manufacturing cost and total thickness of the substrate structure due to the additional layer(s).
- Other implementations provide for conductive pillars protruding from the circuit layer for connecting to a semiconductor die, such that solder structures and trace are not disposed at a same level. Accordingly, bridges caused by solder overflow can be avoided. However, the conductive pillars can be in a columnar shape with a consistent radius. For such pillars, when the area of the upper surface of the conductive pillar is sufficient for retaining the solder, the lower surface of the conductive pillar can occupy a large area of the circuit layer, resulting in a specification of a narrow line width/line space (L/S), which can be challenging to implement.
- To address at least the above concerns, one or more embodiments of the present disclosure provides a substrate structure including at least one tapered conductive pillar. The tapered conductive pillar provides a larger upper surface which is at least sufficient for connection with a semiconductor die, and a smaller lower surface to reduce an occupied area of a circuit layer on which the conductive pillar is disposed.
-
FIG. 1 illustrates a cross-sectional view of an example of asubstrate structure 1 according to some embodiments of the present disclosure. Thesubstrate structure 1 includes adielectric layer 2, afirst circuit layer 3, asecond circuit layer 4, a plurality ofinner vias 12, at least oneconductive pillar 5 and aprotective layer 16. - The
dielectric layer 2 has afirst surface 21 and asecond surface 22 opposite to thefirst surface 21. Thedielectric layer 2 may include an insulating material or a dielectric material, such as, for example, polypropylene (PP). It is noted that thedielectric layer 2 may include, or be formed from, a cured photoimageable dielectric (PID) material such as epoxy or polyimide (PI) including photoinitiators. Thedielectric layer 2 defines a plurality of throughholes 20 extending between thefirst surface 21 and thesecond surface 22. In some embodiments, a thickness of thedielectric layer 2 may be in a range of about 3 micrometers (μm) to about 10 μm. - The
first circuit layer 3 is disposed adjacent to thefirst surface 21 of thedielectric layer 2. For example, thefirst circuit layer 3 is embedded in thedielectric layer 2 and exposed from thefirst surface 21 of thedielectric layer 2. In some embodiments, thefirst circuit layer 3 is a patterned conductive circuit layer. A material of thefirst circuit layer 3 may include a conductive metal, such as copper, or another metal or combination of metals. In some embodiments, thefirst circuit layer 3 may be formed by etching a metal layer. In some embodiments, the line width/line space (L/S) of thefirst circuit layer 3 may be greater than about 7 μm/about 7 μm (e.g. may be greater than about 8 μm/about 8 μm, may be greater than about 9 μm/about 9 μm, or may be greater than about 10 μm/about 10 μm), and a thickness of thefirst circuit layer 3 may be in a range of about 2 μm to about 5 μm. As shown inFIG. 1 , thefirst circuit layer 3 may have a substantially consistent thickness, and a bottom surface of thefirst circuit layer 3 may be substantially coplanar with thefirst surface 21 of thedielectric layer 2. One or more portions of a top surface of thefirst circuit layer 3 are exposed by the throughholes 20 of thedielectric layer 2. - The
second circuit layer 4 is disposed adjacent to thesecond surface 22 of thedielectric layer 2 and electrically connected to thefirst circuit layer 3. For example, thesecond circuit layer 4 is disposed on thesecond surface 22 of thedielectric layer 2, while a portion of thesecond surface 22 of thedielectric layer 2 is a free surface that is not covered by any other portion or component of the substrate structure 1 (or, in some implementations, not covered by any element or material), or is exposed from thesecond circuit layer 4. In some embodiments, thesecond circuit layer 4 is includes a redistribution layer (RDL). Thesecond circuit layer 4 has anupper surface 41, and includes a plurality ofpads 44 and at least onetrace 46. Thetrace 46 is connected (electrically connected and/or physically connected) to at least one of thepads 44 and is disposed between twoadjacent pads 44. A material of thesecond circuit layer 4 may include a conductive metal, such as copper, or another metal or combination of metals, and may be formed or disposed by electroplating. Each of theinner vias 12 is disposed in a respective one of the throughholes 20 of thedielectric layer 2 and extends between thefirst circuit layer 3 and thesecond circuit layer 4. Thus, thesecond circuit layer 4 is electrically connected to thefirst circuit layer 3 through theinner vias 12. Thevias 12 may be formed concurrently with thesecond circuit layer 4. In some embodiments, a line width/line space (L/S) of thesecond circuit layer 4 is less than a line width/line space (L/S) of thefirst circuit layer 3. The line width/line space (L/S) of thesecond circuit layer 4 may be less than about 7 μm/about 7 μm, such as less than about 5 μm/about 5 μm, less than about 3 μm/about 3 μm, or less than about 2 μm/about 2 μm. In some embodiments, a thickness of thesecond circuit layer 4 may be in a range of about 4 μm to about 6 μm. Thus, a thickness of thefirst circuit layer 3 is less than a thickness of thesecond circuit layer 4, which can balance warpage of thesubstrate structure 1 caused by connection of a semiconductor die 62 (e.g. as shown inFIG. 4 ) to thesecond circuit layer 4. A roughness (Ra) of theupper surface 41 of thesecond circuit layer 4 may be less than about 50 nanometer (nm), such as less than about 40 nm or less than about 30 nm. In some embodiments, aseed layer 14 may be disposed between thesecond circuit layer 4 and thedielectric layer 2, and between theinner vias 12 and thedielectric layer 2. Theseed layer 14 is covered (e.g. is completely covered) by thesecond circuit layer 4 and theinner vias 12. Theseed layer 14 may include, for example, titanium and/or copper, another metal, or an alloy thereof, and may be formed or disposed by sputtering. - The
conductive pillar 5 is tapered downwardly towards the second surface 22 (e.g. a width of theconductive pillar 5 decreases, e.g. monotonically decreases) from an upper portion of theconductive pillar 5 to a lower portion of the conductive pillar 5) and disposed on one of thepads 44 of thesecond circuit layer 4. In some embodiments, theconductive pillar 5 is directly disposed on the one of thepads 44 of thesecond circuit layer 4. Theconductive pillar 5 has anupper surface 51, alower surface 52 and asidewall 53. Thelower surface 52 is opposite to theupper surface 51, and thesidewall 53 extends between thelower surface 52 and theupper surface 51. In some embodiments, thelower surface 52 of theconductive pillar 5 is connected to and physically contacts therespective pad 44 of thesecond circuit layer 4. In some embodiments, theconductive pillar 5 may be shaped as a circular truncated cone. Theupper surface 51 and thelower surface 52 may be substantially circular. - A material of the
conductive pillar 5 may include a conductive metal, such as copper, or another metal or combination of metals, and may be formed or disposed by electroplating. The material of theconductive pillar 5 may be the same as the material of thesecond circuit layer 4. In some embodiments, there is no seed layer between theconductive pillar 5 and theupper surface 41 of thesecond circuit layer 4, theconductive pillar 5 can grow directly from theupper surface 41 of thesecond circuit layer 4, and thus lattices of thesecond circuit layer 4 and theconductive pillars 5 may be continuous (e.g. thesecond circuit layer 4 and at least one of theconductive pillars 5 may share a solid or crystalline lattice). In some embodiments, theconductive pillar 5 and thesecond circuit layer 4 may be a continuous structure without a boundary therebetween (e.g. may constitute a monolithic structure). In one or more embodiments, theconductive pillar 5 is directly located on part of thesecond circuit layer 4, and the lattice of theconductive pillar 5 is the same as that of thesecond circuit layer 4. In some embodiments, theconductive pillar 5 includes electroplated copper, which is directly formed on theupper surface 41 of thesecond circuit layer 4 by electroplating. Therefore, it can be seen by using, for example, a focused ion beam (FIB), that an interface between theconductive pillar 5 and thesecond circuit layer 4 is not visible or non-existent, and theconductive pillar 5 and thesecond circuit layer 4 have the same lattice. - The
conductive pillar 5 is tapered from theupper surface 51 to thelower surface 52. A width W1 of theupper surface 51 is greater than a width W2 of thelower surface 52, for example, at least about 1.05 times greater, at least about 1.1 times greater, at least about 1.2 times greater, or at least about 1.3 times greater. Thus, the shape of theconductive pillar 5 from the cross-sectional view as shown inFIG. 1 is substantially a trapezoid (e.g. a trapezoid with a concave upper surface), and the width of theconductive pillar 5 decreases from theupper surface 51 toward thelower surface 52. In addition, an angle θ is defined by thesidewall 53 of theconductive pillar 5 and anupper surface 41 of thesecond circuit layer 4. The angle θ is equal to or greater than about 60 degrees but less than about 90 degrees. For example, the angle θ is equal to or greater than about 65 degrees but less than about 87 degrees; equal to or greater than about 70 degrees but less than about 85 degrees; or equal to or greater than about 75 degrees but less than about 82 degrees. In some embodiments, an edge (e.g. a top edge) of an upper portion (e.g. the upper surface 51) of theconductive pillar 5 is directly located above thetrace 46 of thesecond circuit layer 4. In some embodiments, theconductive pillar 5 is a monolithic structure, and thesidewall 53 thereof is a continuous surface. In some embodiments, a maximum height of theconductive pillar 5 may be in a range of about 50 μm to about 100 μm. - In some embodiments, the
upper surface 51 of theconductive pillar 5 is concave toward thesecond circuit layer 4. That is, the upper portion of theconductive pillar 5 is substantially in a bowl shape. When thesubstrate structure 1 is connected to a semiconductor die 62 (as shown inFIG. 4 ), theconductive pillar 5 can retain or receive asolder structure 626 of the semiconductor die 62 in the concaveupper surface 51 so as to prevent a bridge between theconductive pillar 5 and thetrace 46. - The
protective layer 16 is disposed on thefirst surface 21 of thedielectric layer 2 and thefirst circuit layer 3. Theprotective layer 16 may include, or be formed from, a cured PID material such as epoxy or a PI including photoinitiators, or a solder resist layer. Theprotective layer 16 defines anopening 160 extending through theprotective layer 16. A portion of thefirst circuit layer 3 is exposed in theopening 160 for external connection. In some embodiments, a thickness of theprotective layer 16 may be in a range of about 25 μm to about 90 μm. - In the
substrate structure 1, since theconductive pillar 5 is tapered downwardly, theupper surface 51 is large enough to retain thesolder structure 626 thereon when connecting to the semiconductor die 62 (as shown inFIG. 4 ), avoiding a potential short circuit caused by overflow of the solder of thesolder structure 626. Thelower surface 52 of the conductive pillar is smaller than theupper surface 51, and thus a size of thepad 44 on which thelower surface 52 is disposed can be correspondingly reduced. Accordingly, thepads 44 occupy a relatively small area of thesecond surface 22 of thedielectric layer 2, as compared to implementations that omit a taperedconductive pillar 5, while the remaining area of thesecond surface 22 of thedielectric layer 2 can be increased. The line width/line space (L/S) of thesecond circuit layer 4 can thus be larger than would otherwise be the case, which provides for use of less costly or faster lithography techniques or processes. -
FIG. 2 illustrates a cross-sectional view of an example of a substrate structure 1 a according to some embodiments of the present disclosure.FIG. 3 illustrates an enlarged view of the area “A” shown inFIG. 2 . The substrate structure 1 a is similar to thesubstrate structure 1 shown inFIG. 1 , except that the structure of afirst circuit layer 3 a of the substrate structure 1 a is different from thefirst circuit layer 3 of thesubstrate structure 1 inFIG. 1 . - The
first circuit layer 3 a includes afirst portion 31 and asecond portion 32 surrounding thefirst portion 31. Thefirst portion 31 has asurface 311, and thesecond portion 32 has asurface 321. In some embodiments, thesurface 321 of thesecond portion 32 is substantially coplanar with thefirst surface 21 of thedielectric layer 2. Thesurface 311 of thefirst portion 31 is recessed from thefirst surface 21 of thedielectric layer 2 and thesurface 321 of thesecond portion 32. That is, thefirst circuit layer 3 a defines arecess portion 34 corresponding to thefirst portion 31. - The
protective layer 16 covers thesecond portion 32 of thefirst circuit layer 3 a. Theopening 160 of theprotective layer 16 corresponds to thefirst portion 31 of thefirst circuit layer 3 a. Accordingly, theopening 160 defined by theprotective layer 16 exposes (e.g. completely exposes) thefirst portion 31 of thefirst circuit layer 3 a, and therecess portion 34 of thefirst circuit layer 3 a is substantially co-extensive with theopening 160 of theprotective layer 16. In some embodiments, as shown inFIG. 3 , a width W3 of theopening 160 of theprotective layer 16 is substantially equal to a width W4 of therecess portion 34 of thefirst circuit layer 3 a. In one or more embodiments in which a solder ball is disposed in theopening 160 of theprotective layer 16 and attached to thefirst circuit layer 3 a, therecess portion 34 of thefirst circuit layer 3 a provides enlarged contacting area between the solder ball and thefirst circuit layer 3 a. -
FIG. 4 illustrates a cross-sectional view of an example of asemiconductor package structure 6 according to some embodiments of the present disclosure. Thesemiconductor package structure 6 includes asubstrate structure 1, asemiconductor die 62, anencapsulant 64 and asolder ball 18. - The
substrate structure 1 shown inFIG. 4 is similar to thesubstrate structure 1 shown inFIG. 1 . The semiconductor die 62 is disposed on thesubstrate structure 1 and electrically connected to theconductive pillar 5 of thesubstrate structure 1. In some embodiments, a thickness of the semiconductor die 62 may be about 500 μm (e.g. may be in a range of about 400 μm to about 600 μm). The semiconductor die 62 includes anactive surface 621, aside surface 623, at least onebump 624 and at least onesolder structure 626. Theactive surface 621 of the semiconductor die 62 faces thesubstrate structure 1. Thebump 624 of the semiconductor die 62 is disposed on theactive surface 621, and is connected to theconductive pillar 5 of thesubstrate structure 1 through thesolder structure 626. In other words, thesolder structure 626 is disposed between theconductive pillar 5 and thebump 624. A width W1 of the upper surface of theconductive pillar 5 is greater than a width W5 of thebump 624 of thedie 62. In some embodiments, thesolder structure 626 contacts theupper surface 51 of theconductive pillar 5. - The
encapsulant 64, for example, a molding compound, is disposed between thesubstrate structure 1 and the semiconductor die 62, and directly contacts a portion of thesecond circuit layer 4. Theencapsulant 64 may cover theactive surface 621 of the semiconductor die 62 without covering theside surface 623 of the semiconductor die 62. As shown inFIG. 4 , aside surface 641 of theencapsulant 64 may be substantially coplanar with theside surface 623 of the semiconductor die 62. In some embodiments, theencapsulant 64 covers (e.g. completely covers) asidewall 53 of theconductive pillar 5. For example, theencapsulant 64 directly contacts thesidewall 53 of theconductive pillar 5. In some embodiments, theencapsulant 64 contacts a portion of thesecond surface 22 of thedielectric layer 2 of thesubstrate structure 1. In some embodiments, a thickness of theencapsulant 64 may be in a range of about 60 μm to about 150 μm. - The
solder ball 18 is disposed in theopening 160 of theprotective layer 16 of thesubstrate structure 1. Thesolder ball 18 is attached and electrically connected to thefirst circuit layer 3 and protrudes from theprotective layer 16 for external connection. In some embodiments, thesubstrate structure 1 of thesemiconductor package structure 6 can be replaced by the substrate structure 1 a shown inFIG. 2 andFIG. 3 . -
FIG. 5 illustrates a cross-sectional view of an example of asemiconductor package structure 6 a according to some embodiments of the present disclosure. Thesemiconductor package structure 6 a is similar to thesemiconductor package structure 6 shown inFIG. 4 , except that theencapsulant 64 further covers theside surface 623 of the semiconductor die 62. -
FIG. 6 illustrates a cross-sectional view of an example of asemiconductor package structure 6 b including asubstrate structure 1 b according to some embodiments of the present disclosure. Thesemiconductor package structure 6 b including thesubstrate structure 1 b is similar to thesemiconductor package structure 6 including thesubstrate structure 1 shown inFIG. 4 , except that thesubstrate structure 1 b of thesemiconductor package structure 6 b includes an additionaldielectric layer 2 a and anintermediate circuit layer 4 a respectively similar to thedielectric layer 2 and thesecond circuit layer 4. The additionaldielectric layer 2 a is disposed between thedielectric layer 2 and thefirst circuit layer 3. Theintermediate circuit layer 4 a is disposed between thedielectric layer 2 and the additionaldielectric layer 2 a, and is electrically connected to thefirst circuit layer 3 and thesecond circuit layer 4. In other embodiments, thesubstrate structure 1 b of thesemiconductor package structure 6 b may include more than oneadditional dielectric layer 2 a and/or more than oneintermediate circuit layer 4 a. -
FIG. 7 throughFIG. 26 illustrate a semiconductor process according to some embodiments of the present disclosure. In some embodiments, the semiconductor process is for manufacturing a substrate structure such as thesubstrate structure 1 shown inFIG. 1 , and/or a semiconductor package structure such as thesemiconductor structure 6 a shown inFIG. 5 . - Referring
FIG. 7 , aprotective layer 16 and ametal layer 81 are provided. Theprotective layer 16 may include a PID material, such as epoxy or a PI including photoinitiators, or a solder resist layer. Themetal layer 81 may include copper or other conductive metals or an alloy thereof. Theprotective layer 16 has afirst side 161 and asecond side 162 opposite to thefirst side 161. Themetal layer 81 is disposed on thefirst side 161 of theprotective layer 16. - Referring to
FIG. 8 , theprotective layer 16 is exposed to a pattern of light. For example, amask 82 is disposed adjacent to thesecond side 162 of theprotective layer 16, so as to cover a portion of theprotective layer 16. Then, theprotective layer 16 is exposed to aradiation source 83. - Referring to
FIG. 9 , an etching process is conducted to themetal layer 81 to reduce a thickness of the metal layer 81 (e.g. before developing the protective layer 16). Since theprotective layer 16 is not yet developed, theprotective layer 16 can readily support the thinnedmetal layer 81. - Referring to
FIG. 10 , theprotective layer 16 is then developed by a developer from thesecond side 162. That is, theprotective layer 16 is patterned, and aportion 811 of themetal layer 82 is exposed from theprotective layer 16. For example, theprotective layer 16 defines at least oneopening 160 extending through theprotective layer 16. Theportion 811 of themetal layer 81 is exposed in theopening 160 of theprotective layer 16. - Referring to
FIG. 11 , acarrier 86 is attached to thesecond side 162 of theprotective layer 16 through anadhesive layer 84 for support. - Referring to
FIG. 12 , afirst photoresist material 88 is applied on themetal layer 81. Thefirst photoresist material 88 may include a PID material, such as epoxy or a PI including photoinitiators. - Referring to
FIG. 13 , thefirst photoresist material 88 is patterned (e.g., by a lithography technique) to form at least onerigid portion 89. - Referring to
FIG. 14 , themetal layer 81 is patterned (e.g., by etching with therigid portion 89 serving as a mask), to form afirst circuit layer 3. Therigid portion 89 is then removed, (e.g., by stripping). Then, a dielectric material 90 is applied on and covers thefirst side 161 of theprotective layer 16 and thefirst circuit layer 3. The dielectric material 90 may include PP, or a PID material such as epoxy or a PI including photoinitiators. - Referring to
FIG. 15 , the dielectric material 90 is patterned (e.g., by a lithography technique) to form adielectric layer 2 on thefirst circuit layer 3. Thedielectric layer 2 has afirst surface 21 and asecond surface 22 opposite to thefirst surface 21, and thefirst surface 21 is disposed on thefirst side 161 of theprotective layer 16. Thedielectric layer 2 defines a plurality of throughholes 20 extending between thefirst surface 21 and thesecond surface 22 to expose portions of thefirst circuit layer 3. Then, aseed layer 14 is formed (e.g., by sputtering) on thesecond surface 22 of thedielectric layer 2 and in the throughholes 20 of thedielectric layer 2 to contact thefirst circuit layer 3. - Referring to
FIG. 16 , asecond photoresist material 92 is provided or applied on theseed layer 14. Thesecond photoresist material 92 may include a PID material, such as epoxy or a PI including photoinitiators. - Referring to
FIG. 17 , thesecond photoresist material 92 is patterned (e.g., by a lithography technique) to form afirst photoresist layer 93 on theseed layer 14. Then, asecond circuit layer 4 is formed (e.g., by electroplating) on theseed layer 14 and in recesses of thefirst photoresist layer 93. Thesecond circuit layer 4 is electrically connected to thefirst circuit layer 3. Thesecond circuit layer 4 includes a plurality ofpads 44 and at least onetrace 46. Thetrace 46 is connected to at least one of thepads 44 and is disposed between twoadjacent pads 44. A material of thesecond circuit layer 4 may include a conductive metal, such as copper, or another metal or combination of metals, and may be formed or disposed by electroplating. In addition, a plurality ofinner vias 12 are respectively disposed (e.g., by electroplating) in ones of the throughholes 20 of thedielectric layer 2 to connect thefirst circuit layer 3 and thesecond circuit layer 4. Theinner vias 12 can be formed concurrently with thesecond circuit layer 4. - Referring to
FIG. 18 , athird photoresist material 94 is disposed on thefirst photoresist layer 93 and thesecond circuit layer 4. Thethird photoresist material 94 may include a PID material, such as epoxy or a polyimide PI including photoinitiators. - Referring to
FIG. 19 , thethird photoresist material 94 is patterned (e.g., by a lithography technique) to form asecond photoresist layer 95 on thesecond circuit layer 4. Thesecond photoresist layer 95 defines at least oneopening 951 to expose a portion of anupper surface 41 of thepad 44 of thesecond circuit layer 4. Then, at least oneconductive pillar 5 tapered downwardly is formed in theopening 951 of thesecond photoresist layer 95 and electrically connected to one of thepads 44 of thesecond circuit layer 4. Theconductive pillar 5 may be directly disposed on the one of thepads 44 of thesecond circuit layer 4. Theconductive pillar 5 has anupper surface 51, alower surface 52 opposite to theupper surface 51, and asidewall 53. A material of theconductive pillar 5 may include a conductive metal, such as copper, or another metal or combination of metals, and may be formed or disposed by electroplating. The material of theconductive pillar 5 may be the same as the material of thesecond circuit layer 4. In some embodiments, there is no seed layer between theconductive pillar 5 and theupper surface 41 of thesecond circuit layer 4, theconductive pillar 5 can grow directly from theupper surface 41 of thesecond circuit layer 4, and lattices of thesecond circuit layer 4 and theconductive pillars 5 may be continuous. In some embodiments, theconductive pillar 5 and thesecond circuit layer 4 may be continuous without a boundary therebetween. Theconductive pillar 5 is directly located on a portion of thesecond circuit layer 4, wherein the lattice of theconductive pillar 5 is the same as that of the second circuit layer 4 (e.g. theconductive pillar 5 and thesecond circuit layer 4 share a lattice). In this embodiment, theconductive pillar 5 is made from electroplated copper, which is directly formed on theupper surface 41 of thesecond circuit layer 4 by electroplating. Therefore, it can be seen by using, for example, a focused ion beam (FIB), that an interface between theconductive pillar 5 and thesecond circuit layer 4 is not visible (or is non-existent), and theconductive pillar 5 and thesecond circuit layer 4 have the same lattice. In some embodiments, as shown inFIG. 19 , a width of theupper surface 51 is greater than a width of thelower surface 52, and theupper surface 51 of theconductive pillar 5 is concave. An angle θ defined by thesidewall 53 of theconductive pillar 5 and theupper surface 41 of thesecond circuit layer 4 is equal to or greater than about 60 degrees but less than about 90 degrees. In some embodiments, an edge (e.g. a top edge) of an upper portion (e.g. the upper surface 51) of theconductive pillar 5 is directly located above thetrace 46 of thesecond circuit layer 4. - Referring to
FIG. 20 , thefirst photoresist layer 93 and thesecond photoresist layer 95 are removed (e.g., by stripping). A portion of theseed layer 14 which is not covered by thesecond circuit layer 4 and theinner vias 12 is removed (e.g., by etching). Accordingly, asubstrate structure 1 as shown inFIG. 1 is formed on thecarrier 86 and attached to thecarrier 86 by theadhesive layer 84. - Referring to
FIG. 21 , asemiconductor die 62 is provided. The semiconductor die 62 has anactive surface 621 and aside surface 623, and includes at least onebump 624 and at least onesolder structure 626 connected to the at least onebump 624. - Referring to
FIG. 22 , the semiconductor die 62 is disposed on and connected to the substrate structure 1 (e.g., by a reflow process). Theactive surface 621 of the semiconductor die 62 faces thesubstrate structure 1. The semiconductor die 62 is electrically connected to theconductive pillar 5 of thesubstrate structure 1. Thebump 624 of the semiconductor die 62 is connected to theconductive pillar 5 of thesubstrate structure 1 through thesolder structure 626. In some embodiments, thesolder structure 626 contacts theupper surface 51 of theconductive pillar 5. A width W1 of the upper surface of theconductive pillar 5 is greater than a width W5 of thebump 624 of thedie 62. -
FIG. 23 illustrates a schematic perspective view of an example of a combination of acarrier 86, asubstrate structure 1 and a plurality of semiconductor dice 62 (e.g. as depicted inFIG. 22 ) according to some embodiments of the present disclosure. The shapes of thesubstrate structure 1 and thecarrier 86 may be, for example, rectangular or square. -
FIG. 24 illustrates a schematic perspective view of another example of a combination of a carrier 86 a, a substrate structure 1 c and a plurality ofsemiconductor dice 6 according to some embodiments of the present disclosure. The shapes of the substrate structure 1 c and the carrier 86 a may be, for example, circular or elliptical. - Referring to
FIG. 25 , anencapsulant 64 is disposed or formed between asemiconductor die 62 and asubstrate structure 1, and directly contacts a portion of asecond circuit layer 4. Theencapsulant 64 may cover anactive surface 621 and aside surface 623 of the semiconductor die 62. In some embodiments, theencapsulant 64 covers (e.g. completely covers) thesidewall 53 of theconductive pillar 5. For example, theencapsulant 64 directly contacts thesidewall 53 of theconductive pillar 5. In some embodiments, theencapsulant 64 contacts a portion of thesecond surface 22 of thedielectric layer 2 of thesubstrate structure 1. - Referring to
FIG. 26 , thecarrier 86 and theadhesion layer 84 are removed. Then, asolder ball 18 is disposed in theopening 160 of theprotective layer 16 and attached to thefirst circuit layer 3 for external connection. Then, a singulation process is performed, thus forming thesemiconductor package structure 6 a as shown inFIG. 5 . In other embodiments, thesemiconductor dice 62 shown inFIG. 23 orFIG. 24 may be replaced by a single wafer. Hence, after the singulation process, theencapsulant 64 may not cover theside surface 623 of the semiconductor die 62, and aside surface 641 of theencapsulant 64 may be substantially coplanar with theside surface 623 of the semiconductor die 62, forming thesemiconductor package structure 6 as shown inFIG. 4 -
FIG. 27 illustrates a semiconductor process according to some embodiments of the present disclosure. In some embodiments, the semiconductor process is for manufacturing a substrate structure such as the substrate structure 1 a shown inFIG. 2 andFIG. 3 , and/or a semiconductor package structure including such substrate structure. - The initial stages of the illustrated process are the same as the stages illustrated in
FIG. 7 throughFIG. 9 .FIG. 27 depicts a stage subsequent to that depicted inFIG. 9 . Referring toFIG. 27 , theprotective layer 16 is developed by a developer. Theprotective layer 16 defines anopening 160 extending through theprotective layer 16. During the devolving process, aportion 811 a of themetal layer 81 exposed in theopening 160 of theprotective layer 16 is also etched. Hence, theportion 811 a of themetal layer 81 is slightly recessed to form arecess portion 34. - The stages subsequent to
FIG. 27 of the illustrated process are similar to the stages illustrated inFIG. 11 throughFIG. 26 . Theportion 811 a forms thefirst portion 31 of thefirst circuit layer 3, thus forming the substrate structure 1 a as shown inFIG. 2 andFIG. 3 and/or the semiconductor package structure including the same. - Spatial descriptions, such as “above,” “below,” “up,” “left,” “right,” “down,” “top,” “bottom,” “vertical,” “horizontal,” “side,” “higher,” “lower,” “upper,” “over,” “under,” and so forth, are indicated with respect to the orientation shown in the figures unless otherwise specified. It should be understood that the spatial descriptions used herein are for purposes of illustration only, and that practical implementations of the structures described herein can be spatially arranged in any orientation or manner, provided that the merits of embodiments of this disclosure are not deviated from by such an arrangement.
- As used herein, the terms “approximately,” “substantially,” “substantial” and “about” are used to describe and account for small variations. When used in conjunction with an event or circumstance, the terms can refer to instances in which the event or circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation. For example, when used in conjunction with a numerical value, the terms can refer to a range of variation less than or equal to ±10% of that numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, two numerical values can be deemed to be “substantially” the same or equal if a difference between the values is less than or equal to ±10% of an average of the values, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, “substantially” parallel can refer to a range of angular variation relative to 0° that is less than or equal to ±10°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°. For example, “substantially” perpendicular can refer to a range of angular variation relative to 90° that is less than or equal to ±10°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°. For example, a surface can be deemed to be planar or substantially planar if a difference between a highest point and a lowest point of the surface is no greater than 5 no greater than 2 no greater than 1 or no greater than 0.5
- Two surfaces can be deemed to be coplanar or substantially coplanar if a displacement between the two surfaces is no greater than 5μm, no greater than 2μm, no greater than 1 μm, or no greater than 0.5 μm.
- As used herein, the singular terms “a,” “an,” and “the” may include plural referents unless the context clearly dictates otherwise. In the description of some embodiments, a component provided “on” or “over” another component can encompass cases where the former component is directly on (e.g., in physical contact with) the latter component, as well as cases where one or more intervening components are located between the former component and the latter component.
- Additionally, amounts, ratios, and other numerical values are sometimes presented herein in a range format. It is to be understood that such range format is used for convenience and brevity and should be understood flexibly to include numerical values explicitly specified as limits of a range, but also to include all individual numerical values or sub-ranges encompassed within that range as if each numerical value and sub-range is explicitly specified.
- While the present disclosure has been described and illustrated with reference to specific embodiments thereof, these descriptions and illustrations are not limiting. It should be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The illustrations may not be necessarily drawn to scale. There may be distinctions between the artistic renditions in the present disclosure and the actual apparatus due to manufacturing processes and tolerances. There may be other embodiments of the present disclosure which are not specifically illustrated. The specification and drawings are to be regarded as illustrative rather than restrictive. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to be within the scope of the claims appended hereto. While the methods disclosed herein have been described with reference to particular operations performed in a particular order, it will be understood that these operations may be combined, sub-divided, or re-ordered to form an equivalent method without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of the operations are not limitations of the present disclosure.
Claims (21)
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US15/795,201 US10276480B1 (en) | 2017-10-26 | 2017-10-26 | Semiconductor structure |
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US11508633B2 (en) * | 2020-05-28 | 2022-11-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package structure having taper-shaped conductive pillar and method of forming thereof |
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US10276402B2 (en) * | 2016-03-21 | 2019-04-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor package and manufacturing process thereof |
US11694976B2 (en) * | 2018-10-11 | 2023-07-04 | Intel Corporation | Bowl shaped pad |
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US7094676B1 (en) * | 2000-10-13 | 2006-08-22 | Bridge Semiconductor Corporation | Semiconductor chip assembly with embedded metal pillar |
US7190080B1 (en) * | 2000-10-13 | 2007-03-13 | Bridge Semiconductor Corporation | Semiconductor chip assembly with embedded metal pillar |
JPWO2011108308A1 (en) * | 2010-03-04 | 2013-06-24 | 日本電気株式会社 | Wiring board with built-in semiconductor element |
US8759691B2 (en) * | 2010-07-09 | 2014-06-24 | Ibiden Co., Ltd. | Wiring board and method for manufacturing the same |
TWM459517U (en) * | 2012-12-28 | 2013-08-11 | Unimicron Technology Corp | Package substrate |
CN104576596B (en) * | 2013-10-25 | 2019-01-01 | 日月光半导体制造股份有限公司 | Semiconductor substrate and its manufacturing method |
US9735134B2 (en) * | 2014-03-12 | 2017-08-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packages with through-vias having tapered ends |
US10079156B2 (en) * | 2014-11-07 | 2018-09-18 | Advanced Semiconductor Engineering, Inc. | Semiconductor package including dielectric layers defining via holes extending to component pads |
US9653336B2 (en) | 2015-03-18 | 2017-05-16 | Amkor Technology, Inc. | Semiconductor device and manufacturing method thereof |
US10049986B2 (en) * | 2015-10-30 | 2018-08-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package structures and methods of making the same |
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US11508633B2 (en) * | 2020-05-28 | 2022-11-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package structure having taper-shaped conductive pillar and method of forming thereof |
US20230054148A1 (en) * | 2020-05-28 | 2023-02-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package structure and method of forming thereof |
US11990383B2 (en) * | 2020-05-28 | 2024-05-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package structure having at least one die with a plurality of taper-shaped die connectors |
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