US20200258826A1 - Semiconductor package and semiconductor manufacturing process - Google Patents
Semiconductor package and semiconductor manufacturing process Download PDFInfo
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- US20200258826A1 US20200258826A1 US16/859,676 US202016859676A US2020258826A1 US 20200258826 A1 US20200258826 A1 US 20200258826A1 US 202016859676 A US202016859676 A US 202016859676A US 2020258826 A1 US2020258826 A1 US 2020258826A1
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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Definitions
- the present disclosure relates to the field of semiconductor package and semiconductor manufacturing process, and, more particularly, to a semiconductor package including an embedded trace substrate (ETS), and a semiconductor manufacturing process for manufacturing the same.
- ETS embedded trace substrate
- semiconductor chips are integrated with more electronic components to achieve improved electrical performance. Accordingly, the semiconductor chips are provided with more input/output (I/O) connections.
- I/O input/output
- sizes of the semiconductor chips and the semiconductor packages may correspondingly increase. Thus, the cost may correspondingly increase.
- a bonding pad density of semiconductor substrates used for carrying the semiconductor chips should correspondingly increase. Therefore, solder bridge and peeling between a conductive via and a bump pad are issues of concern.
- the formation of a through hole of a solder resist layer is difficult.
- a semiconductor package includes a semiconductor substrate structure, a semiconductor die and an encapsulant.
- the semiconductor substrate structure includes a dielectric structure, a first patterned conductive layer, a first insulation layer and a conductive post.
- the first patterned conductive layer is embedded in the dielectric structure.
- the first insulation layer is disposed on the dielectric structure.
- the first insulation layer defines an opening exposing the first patterned conductive layer.
- the conductive post is disposed in the opening.
- the conductive post connects to the first patterned conductive layer and protrudes from the first insulation layer.
- the first insulation layer has a first thickness at a first position and a second thickness at a second position, the first position is closer to the conductive post than the second position, and the first thickness is greater than the second thickness.
- the semiconductor die is electrically connected to the conductive post.
- the encapsulant covers the semiconductor die and at least a portion of the semiconductor substrate structure.
- a semiconductor package includes a semiconductor substrate structure.
- the semiconductor substrate structure includes a dielectric structure, a first patterned conductive layer, a first insulation layer and a conductive post.
- the first patterned conductive layer is embedded in the dielectric structure.
- the first insulation layer is disposed on the dielectric structure.
- the first insulation layer defines an opening exposing the first patterned conductive layer.
- the conductive post is disposed in the opening.
- the conductive post connects to the first patterned conductive layer and protrudes from the first insulation layer.
- the first insulation layer includes a protrusion portion surrounding the conductive post. An inclination angle between a top surface of the protrusion portion and a sidewall of the conductive post is less than 90 degrees.
- the semiconductor package also includes a semiconductor die and an encapsulant.
- the semiconductor die is electrically connected to the conductive post.
- the encapsulant covers the semiconductor die and at least a portion of the semiconductor substrate structure.
- a semiconductor manufacturing process includes: (a) providing a circuit structure, wherein the circuit structure includes a dielectric structure, a first patterned conductive layer and a plurality of conductive posts, the first patterned conductive layer is embedded in the dielectric structure, the conductive posts protrude from the first patterned conductive layer; (b) forming a first insulation layer on the dielectric structure to cover the conductive posts; and (c) thinning the first insulation layer so that the conductive posts protrude from the first insulation layer.
- FIG. 1 illustrates a cross-sectional view of a semiconductor package according to some embodiments of the present disclosure.
- FIG. 2 illustrates an enlarged view of a region “A” of the semiconductor package shown in FIG. 1 according to some embodiments of the present disclosure.
- FIG. 3 illustrates an enlarged view of a region of a semiconductor package according to some embodiments of the present disclosure.
- FIG. 4 illustrates an enlarged view of a region of a semiconductor package according to some embodiments of the present disclosure.
- FIG. 5 illustrates a cross-sectional view of a semiconductor package according to some embodiments of the present disclosure.
- FIG. 5A illustrates an enlarged view of a region “B” of the semiconductor package of FIG. 5 according to some embodiments of the present disclosure.
- FIG. 6 illustrates an enlarged view of a region of a semiconductor package according to some embodiments of the present disclosure.
- FIG. 7 illustrates a cross-sectional view of a semiconductor package according to some embodiments of the present disclosure.
- FIG. 8 illustrates a cross-sectional view of a semiconductor package according to some embodiments of the present disclosure.
- FIG. 9 , FIG. 10 , FIG. 11 , FIG. 12 , FIG. 13 , FIG. 14 , FIG. 15 , FIG. 16 , FIG. 17 , FIG. 18 and FIG. 19 illustrate a semiconductor manufacturing process according to some embodiments of the present disclosure.
- FIG. 20 , FIG. 21 , FIG. 22 , FIG. 23 , FIG. 24 , FIG. 25 , FIG. 26 and FIG. 27 illustrate a semiconductor manufacturing process according to some embodiments of the present disclosure.
- FIG. 28 , FIG. 29 , FIG. 30 , FIG. 31 , FIG. 32 , FIG. 33 , FIG. 34 , FIG. 35 , FIG. 36 and FIG. 37 illustrate a semiconductor manufacturing process according to some embodiments of the present disclosure.
- a semiconductor substrate used for carrying semiconductor chips may be an embedded trace substrate (ETS), which may include at least one dielectric layer and two or more patterned conductive layers embedded therein.
- ETS embedded trace substrate
- a first patterned conductive layer (including bump pads and traces) is formed in a dielectric layer firstly.
- a solder resist layer is formed on the dielectric layer to cover the first patterned conductive layer.
- through holes are formed in the solder resist layer to expose the bump pads of the first patterned conductive layer.
- a second patterned conductive layer is formed on the solder resist layer, and a plurality of conductive vias are formed in the through holes, so that the second patterned conductive layer is electrically connected to the first patterned conductive layer through the conductive vias.
- the disadvantages of the comparative ETS are as follows. Firstly, a pitch between the bump pads is small (e.g., about 90 ⁇ m), and a tolerance for registration of the through holes of the solder resist layer is small (e.g., about 5 ⁇ m). Thus, there is a risk that the conductive via may contact a trace between the bump pads. Secondly, a diameter of the through holes of the solder resist layer is small (e.g., about 20 ⁇ m); thus, it may be difficult to form such through holes of the solder resist layer. Thirdly, the second patterned conductive layer and the conductive vias are formed on the solder resist layer, which results in poor adhesion therebetween.
- the first patterned conductive layer and the second patterned conductive layer are formed by two separate plating operations, which increases manufacturing time and cost, and the bonding between the conductive vias and the bump pads of the first patterned conductive layer may be poor.
- warpage of the comparative ETS may occur easily during the manufacturing process.
- the solder resist layer is formed before the formation of the second patterned conductive layer and the conductive vias. Thus, during the following manufacturing process, the solder resist layer will be heated for a long time or for several cycles, which results in embrittlement and weakness of the solder resist layer.
- the present disclosure provides an improved semiconductor package including an ETS and improved techniques for manufacturing the ETS.
- metal posts and bump pads of a first patterned conductive layer are formed by a single (or one-time) plating operation, and then a solder resist layer is formed on a dielectric layer. Then, a portion of the solder resist layer is removed so that the metal posts protrude from the solder resist layer.
- the metal posts and the bump pads of the first patterned conductive layer are formed integrally and concurrently, which results in easier metal post formation. Shapes of the metal posts are uniform; thus, a co-planarity of top surfaces of the metal posts is excellent.
- solder resist layer there is no interface between the metal posts and the bump pads; thus, the bonding between the metal posts and the bump pads is excellent, which results in improved package reliability.
- a thickness of the solder resist layer may be controlled to a small value, which can reduce warpage of the ETS during the manufacturing process.
- the solder resist layer is formed after the formation of the metal posts. Thus, during the following manufacturing process, the solder resist layer will be heated for less time, so that a strength of the solder resist layer will not be adversely influenced.
- FIG. 1 illustrates a cross-sectional view of a semiconductor package 1 according to some embodiments of the present disclosure.
- the semiconductor package 1 includes a semiconductor substrate structure 2 , a semiconductor die 3 and an encapsulant 4 .
- the semiconductor substrate structure 2 may be an ETS, and includes a dielectric structure 20 , a first patterned conductive layer 22 , a first, top insulation layer 24 , a plurality of conductive posts 26 , a second patterned conductive layer 27 , a plurality of conductive vias 28 , a second, bottom insulation layer 29 and a plurality of external connectors 292 .
- the dielectric structure 20 may be, or may include, for example, monocrystalline silicon, polycrystalline silicon, amorphous silicon, other suitable inorganic materials, or a combination thereof.
- the dielectric structure 20 may be, or may include, for another example, a sheet made from pre-impregnated composite fibers.
- the dielectric structure 20 has a first surface (e.g., a top surface) 201 and a second surface (e.g., a bottom surface) 202 opposite to the first surface 201 .
- the first patterned conductive layer 22 is embedded in the dielectric structure 20 , and includes a plurality of bump pads 221 , a plurality of traces 222 , a first surface (e.g., a top surface) 223 and a second surface (e.g., a bottom surface) 224 opposite to the first surface 223 .
- a width of each bump pad 221 may be about 30 ⁇ m, and a pitch between the bump pads 221 may be, for example, about 90 ⁇ m.
- a line width/line space (L/S) of the traces 222 may be about 12 ⁇ m/about 12 ⁇ m.
- a material of the first patterned conductive layer 22 may be, or may include, a conductive metal such as copper.
- the first patterned conductive layer 22 is disposed adjacent to the first surface 201 of the dielectric structure 20 , and a portion (e.g., the first surface 223 ) of the first patterned conductive layer 22 is exposed from the first surface 201 of the dielectric structure 20 . That is, the dielectric structure 20 does not cover the first surface 223 of the first patterned conductive layer 22 .
- a distance between the second surface 224 of the first patterned conductive layer 22 and the second surface 202 of the dielectric structure 20 may be, for example, about 25 ⁇ m.
- the first insulation layer 24 may be a solder resist layer such as a solder mask layer.
- the first insulation layer 24 is disposed on the first surface 201 of the dielectric structure 20 to cover at least a portion of the dielectric structure 20 , and may contact the first patterned conductive layer 22 (including the bump pads 221 and the traces 222 ).
- the first insulation layer 24 defines a plurality of openings 241 corresponding to a first portion (e.g., the bump pads 221 ) of the first patterned conductive layer 22 .
- the conductive posts 26 are disposed in respective ones of the openings 241 of the first insulation layer 24 .
- a material of the conductive posts 26 may be, or may include, a conductive metal such as copper.
- One end of each of the conductive posts 26 connects to the first portion (e.g., the bump pads 221 ) of the first patterned conductive layer 22 , and the other end of each of the conductive posts 26 protrudes from the first insulation layer 24 .
- the conductive posts 26 and the first portion (e.g., the bump pads 221 ) of the first patterned conductive layer 22 are formed integrally and concurrently as a monolithic structure.
- the openings 241 of the first insulation layer 24 are defined by the conductive posts 26 .
- each conductive post 26 is formed before the formation of the first insulation layer 24 , which will be described in a manufacturing process as below.
- each conductive post 26 has a substantially consistent width. That is, a width of a portion of the conductive post 26 embedded in the first insulation layer 24 is substantially equal to a width of the other portion of the conductive post 26 protruding from the first insulation layer 24 .
- a height of each conductive post 26 may be about 12 ⁇ m to 16 ⁇ m.
- the second patterned conductive layer 27 is disposed on the second surface 202 of the dielectric structure 20 away from the first patterned conductive layer 22 , and may include a plurality of ball pads 271 .
- a material of the second patterned conductive layer 27 may be, or may include, a conductive metal such as copper.
- the conductive vias 28 are disposed in the dielectric structure 20 and electrically connect the first patterned conductive layer 22 and the second patterned conductive layer 27 . In some embodiments, the conductive vias 28 and the second patterned conductive layer 27 are formed integrally and concurrently as a monolithic structure.
- the bottom insulation layer 29 may be a solder resist layer such as a solder mask layer.
- the bottom insulation layer 29 is disposed on the second surface 202 of the dielectric structure 20 to cover at least a portion of the dielectric structure 20 , and may contact the second patterned conductive layer 27 (including the ball pads 271 ).
- the bottom insulation layer 29 defines a plurality of openings 291 to expose a portion (e.g., the ball pads 271 ) of the second patterned conductive layer 27 .
- the external connectors 292 such as solder balls, are disposed on the ball pads 271 of the second patterned conductive layer 27 in the openings 291 of the bottom insulation layer 29 for external connection.
- the semiconductor die 3 is electrically connected to the conductive posts 26 .
- the semiconductor die 3 includes a plurality of pillars 32 and a plurality of connectors 34 such as solder caps.
- Each of the connectors 34 is disposed on a tip of a respective one of the pillars 32 and connects to a respective one of the conductive posts 26 .
- a portion of the connector 34 may extend to a sidewall of the conductive post 26 so that the soldering capability and reliability are enhanced.
- the encapsulant 4 such as a molding compound, covers the semiconductor die 3 and a portion (e.g., the first insulation layer 24 ) of the semiconductor substrate structure 2 .
- the encapsulant 4 extends to a space between the semiconductor die 3 and the semiconductor substrate structure 2 so as to protect the conductive posts 26 , the pillars 32 and the connectors 34 .
- FIG. 2 illustrates an enlarged view of a region “A” of the semiconductor package 1 shown in FIG. 1 according to some embodiments of the present disclosure.
- the first insulation layer 24 has a first thickness T 1 at a first position P 1 and a second thickness T 2 at a second position P 2 .
- the first position P 1 is closer to the conductive post 26 than the second position P 2
- the first thickness T 1 is greater than the second thickness T 2 , such as where T 1 is greater than 1.1 times T 2 , or about 1.2 times or greater, or about 1.3 times or greater.
- the first insulation layer 24 has a plurality of protrusion portions 242 , and each of the protrusion portions 242 surrounds a respective one of the conductive posts 26 .
- a thickness of the protrusion portion 242 decreases with increasing distance from the conductive post 26 .
- a top surface 2421 of the protrusion portion 242 from a cross-sectional view is a substantially flat surface.
- An inclination angle ⁇ between the top surface 2421 of the protrusion portion 242 and a sidewall 261 of the conductive post 26 is less than 90 degrees, such as about 60 degrees or less, or about 45 degrees or less.
- the protrusion portions 242 may be formed as follows.
- the first insulation layer 24 is thinned by, for example, etching or a desmear process, and portions of the first insulation layer 24 surrounding the conductive posts 26 are removed to a lesser extent and will remain after the thinning process.
- the conductive posts 26 and the bump pads 221 of the first patterned conductive layer 22 are formed by a single (or one-time) plating operation, that is, the conductive posts 26 and the bump pads 221 of the first patterned conductive layer 22 are formed integrally and concurrently, which results in easier metal post formation.
- shapes of the conductive posts 26 are uniform; thus, a co-planarity of top surfaces of the metal posts 26 is excellent, which facilitates the bonding between the semiconductor die 3 and the conductive posts 26 .
- the bonding between the conductive posts 26 and the bump pads 221 is excellent (and a risk of peeling between the conductive posts 26 and the bump pads 221 is low), which results in improved package reliability.
- the formation of small through holes of the first insulation layer 24 may be omitted. Therefore, there will be no registration issue of the through holes of the first insulation layer 24 .
- the thickness of the first insulation layer 24 may be adjusted to a small value by thinning (e.g., etching), which can control warpage of the semiconductor substrate structure 2 during the manufacturing process.
- FIG. 3 illustrates an enlarged view of a region of a semiconductor package according to some embodiments of the present disclosure.
- the structure of FIG. 3 is similar in certain aspects to the structure as shown in FIG. 2 , with differences including a different structure of the first insulation layer 24 as compared to the first insulation layer 24 of FIG. 2 .
- the top surface 2421 of the protrusion portion 242 of the first insulation layer 24 from a cross-sectional view is a curved surface.
- FIG. 4 illustrates an enlarged view of a region of a semiconductor package according to some embodiments of the present disclosure.
- the structure of FIG. 4 is similar in certain aspects to the structure as shown in FIG. 2 , with differences including a different structure of the conductive posts 26 and bump pads 221 as compared to the conductive posts 26 and the bump pads 221 of FIG. 2 .
- a peripheral surface e.g., of the sidewall 261
- a top surface of the conductive post 26 and a top surface of the bump pad 221 are rough surfaces.
- the surface roughness (Ra or arithmetic average of a surface profile) of the peripheral surface and top surface of the conductive post 26 and the top surface of the bump pad 221 may be about 3 ⁇ m or greater, about 5 ⁇ m or greater, or about 10 ⁇ m or greater.
- the rough surfaces of the conductive post 26 and the bump pad 221 can enhance an adhesion between the first insulation layer 24 and the conductive post 26 and the bump pads 221 , so as to increase reliability.
- FIG. 5 illustrates a cross-sectional view of a semiconductor package 1 ′ according to some embodiments of the present disclosure.
- FIG. 5A illustrates an enlarged view of a region “B” of a semiconductor package of FIG. 5 .
- the semiconductor package 1 ′ of FIG. 5 is similar in certain aspects to the semiconductor package 1 as shown in FIG. 1 , with differences including a different structure of a semiconductor substrate structure 2 ′ as compared to the semiconductor substrate structure 2 of FIG. 1 .
- the semiconductor substrate structure 2 ′ includes a plurality of conductive posts 26 b , a plurality of bump pads 221 b , and a plurality of bonding pads 23 .
- Each conductive post 26 b includes a seed layer 211 and a conductive metal portion 212 in the opening 241 of the first insulation layer 24 .
- Each bump pad 221 b includes the seed layer 211 and the conductive metal portion 212 embedded in the dielectric structure 20 .
- Each bonding pad 23 is disposed on the respective conductive post 26 b .
- a width of the bonding pad 23 is greater than a width of the conductive post 26 b , so as to increase a bonding area between the connector 34 and the bonding pad 23 and, thereby, increase reliability.
- the protrusion portion 242 of the first insulation layer 24 may contact a peripheral surface of the bonding pad 23 .
- the seed layer 211 may be omitted.
- FIG. 6 illustrates an enlarged view of a region of a semiconductor package according to some embodiments of the present disclosure.
- the structure of FIG. 6 is similar in certain aspects to the structure as shown in FIG. 5A , with differences including a different structure of conductive posts 26 c , bump pads 221 c and bonding pads 23 a as compared to the conductive posts 26 b , the bump pads 221 b and bonding pads 23 of FIG. 5A .
- a peripheral surface the conductive post 26 c , a top surface of the bump pad 221 c , a peripheral surface and a top surface of the bonding pad 23 a are rough surfaces.
- a surface roughness (Ra) of the peripheral surface the conductive post 26 c , the top surface of the bump pad 221 c , and the peripheral surface and the top surface of the bonding pad 23 a may be about 3 ⁇ m or greater, about 5 ⁇ m or greater, or about 10 ⁇ m or greater.
- the rough surfaces of the conductive post 26 c , the bump pad 221 c , and the bonding pad 23 a can enhance an adhesion between the first insulation layer 24 and the conductive post 26 c , the bump pad 221 c and the bonding pad 23 a , so as to increase reliability.
- FIG. 7 illustrates a cross-sectional view of a semiconductor package 1 a according to some embodiments of the present disclosure.
- the semiconductor package 1 a of FIG. 7 is similar in certain aspects to the semiconductor package 1 as shown in FIG. 1 , with differences including a different structure of a semiconductor substrate structure 2 a as compared to the semiconductor substrate structure 2 of FIG. 1 .
- the semiconductor substrate structure 2 a further includes a third insulation layer 25 disposed on the first insulation layer 24 .
- the third insulation layer 25 may be a solder resist layer such as a solder mask layer, which may be the same as or different from the first insulation layer 24 .
- the third insulation layer 25 defines at least one accommodating opening 251 to accommodate at least two conductive posts 26 .
- a top surface of the third insulation layer 25 is higher than top surfaces of the conductive posts 26 , so as to prevent the conductive posts 26 from damage. Further, warpage of the semiconductor substrate structure 2 a may be controlled by adjusting a thickness of the third insulation layer 25 .
- FIG. 8 illustrates a cross-sectional view of a semiconductor package 1 b according to some embodiments of the present disclosure.
- the semiconductor package 1 b of FIG. 8 is similar in certain aspects to the semiconductor package 1 as shown in FIG. 1 , with differences including a different structure of a semiconductor substrate structure 2 b as compared to the semiconductor substrate structure 2 of FIG. 1 .
- the semiconductor substrate structure 2 b further includes conductive posts 26 d disposed on a portion of the traces 222 of the first patterned conductive layer 22 , and conductive posts 26 e disposed on the bump pads 221 of the first patterned conductive layer 22 .
- each of the conductive posts 26 d connects to the traces 222 of the first patterned conductive layer 22 , and the other end of each of the conductive posts 26 d protrudes from the first insulation layer 24 .
- the protrusion portions 242 of the first insulation layer 24 may surround the conductive posts 26 d , and may surround the conductive posts 26 e .
- the conductive posts 26 e may extend upward and beyond the semiconductor die 3 so that top ends or surfaces of the conductive posts 26 e are exposed from a top surface of the encapsulant 4 .
- the conductive posts 26 d , the traces 222 , the conductive posts 26 e and the bump pads 221 are formed integrally and concurrently.
- a height of the conductive posts 26 d may be substantially equal to or may be less than a height of the conductive post 26 e . It is noted that additional bonding pads (not shown) may be formed on top of the conductive posts 26 d.
- FIGS. 9 to 19 illustrate a semiconductor manufacturing process according to some embodiments of the present disclosure.
- a carrier 50 and a metal layer 52 e.g., a metal foil
- the metal layer 52 is disposed on one surface of the carrier 50 .
- FIGS. 9 to 19 describe the manufacturing process performed on one side of the carrier 50 . It is noted that the manufacturing process can be performed on the other side of the carrier 50 in a similar way.
- a photoresist layer 54 is formed on the metal layer 52 .
- the photoresist layer 54 may be a dry film. Then, the photoresist layer 54 is patterned by, for example, a photolithography process (including exposure and development) to form a plurality of remaining portions 541 .
- At least one intermediate metal layer 56 (e.g., a nickel layer 561 and a copper layer 562 ) is formed on portions of the metal layer 52 that are not covered by the remaining portions 541 of the photoresist layer 54 .
- the intermediate metal layer 56 includes the nickel layer 561 formed on the metal layer 52 by electrolytic plating and the copper layer 562 formed on the nickel layer 561 by plating.
- the remaining portions 541 of the photoresist layer 54 are removed by, for example, stripping, to leave the intermediate metal layer 56 (including the nickel layer 561 and the copper layer 562 ) on the metal layer 52 .
- a thickness of the intermediate metal layer 56 may be about 12 ⁇ m to about 16 ⁇ m.
- the intermediate layer 56 defines a plurality of through holes 563 to expose a portion of the metal layer 52 . It is noted that the through holes 563 of the intermediate layer 56 correspond to the conductive posts 26 of FIG. 1 .
- a photoresist layer 58 is formed on the intermediate layer 56 .
- the photoresist layer 58 may be a dry film.
- the photoresist layer 58 defines a first pattern 583 including a plurality of first openings 581 and a plurality of second openings 582 .
- the first openings 581 are communicated and aligned with the through holes 563 of the intermediate layer 56 to expose the through holes 563 .
- the second openings 582 expose a portion of the intermediate layer 56 . It is noted that the first openings 581 and the second openings 582 correspond to the bump pads 221 and the traces 222 of FIG. 1 , respectively.
- a metal e.g., copper
- the metal disposed in the first pattern 583 of the photoresist layer 58 forms the first patterned conductive layer 22 including the bump pads 221 and the traces 222 .
- the metal disposed in the through holes 563 of the intermediate layer 56 forms the conductive posts 26 . Therefore, the conductive posts 26 and the bump pads 221 are formed by a single (or one-time) plating operation, that is, the conductive posts 26 and the bump pads 221 are formed integrally and concurrently, which results in easier metal post formation.
- the photoresist layer 58 is removed by, for example, stripping.
- the dielectric structure 20 is formed on the intermediate layer 56 to cover the first patterned conductive layer 22 .
- the dielectric structure 20 has the first surface 201 and the second surface 202 opposite to the first surface 201 .
- a plurality of openings 203 are formed in the dielectric structure 20 from the second surface 202 to expose the bump pads 221 .
- a metal such as copper, is deposited or otherwise disposed (e.g., plated) in the openings 203 and on the dielectric structure 20 so as to form the conductive vias 28 and the second patterned conductive layer 27 .
- the second patterned conductive layer 27 is disposed on the second surface 202 of the dielectric structure 20 away from the first patterned conductive layer 22 , and may include the plurality of ball pads 271 .
- the conductive vias 28 are disposed in the openings 203 of the dielectric structure 20 and electrically connect the first patterned conductive layer 22 and the second patterned conductive layer 27 .
- the conductive vias 28 and the second patterned conductive layer 27 are formed integrally and concurrently.
- the carrier 50 is removed.
- the metal layer 52 and the intermediate layer 56 are removed by, for example, etching. Meanwhile, a circuit structure is obtained, wherein the circuit structure includes the dielectric structure 20 , the first patterned conductive layer 22 and the conductive posts 26 .
- the first patterned conductive layer 22 is embedded in the dielectric structure 20 , and the conductive posts 26 protrude from a portion (e.g., the bump pads 221 ) of the first patterned conductive layer 22 .
- a pretreatment process e.g., etching
- the bottom insulation layer 29 is formed on the second surface 202 of the dielectric structure 20 of the circuit structure to cover the second patterned conductive layer 27 and the dielectric structure 20 .
- the openings 291 are formed in the bottom insulation layer 29 to expose a portion (e.g., the ball pads 271 ) of the second patterned conductive layer 27 .
- the first insulation layer 24 is formed on the first surface 201 of the dielectric structure 20 of the circuit structure to cover the first surface 201 of the dielectric structure 20 and the conductive posts 26 .
- the openings 241 of the first insulation layer 24 are defined by the conductive posts 26 .
- the first insulation layer 24 is thinned from its top surface so that the conductive posts 26 protrude from the first insulation layer 24 by, for example, etching or a desmear process. Meanwhile, the semiconductor substrate structure 2 of FIG. 1 is obtained.
- the manufacturing process may further include the following stages.
- a semiconductor die 3 is electrically connected to the conductive posts 26 .
- an encapsulant 4 is formed to cover the semiconductor die 3 and a portion (e.g., the first insulation layer 24 ) of the semiconductor substrate structure 2 .
- a plurality of external connectors 292 are attached to the exposed portion (e.g., the ball pads 271 ) of the second patterned conductive layer 27 in the openings 291 of the bottom insulation layer 29 . Meanwhile, the semiconductor package 1 as shown in FIG. 1 is obtained.
- the manufacturing process may further include the following stages.
- the third insulation layer 25 is formed on the first insulation layer 24 , wherein the third insulation layer 25 defines at least one accommodating opening 251 to expose at least two conductive posts 26 . Meanwhile, the semiconductor package 1 a as shown in FIG. 7 is obtained.
- FIGS. 20 to 27 illustrate a semiconductor manufacturing process according to some embodiments of the present disclosure.
- the carrier 50 and the metal layer 52 are provided.
- a photoresist layer 62 is formed on the first metal layer 52 .
- the photoresist layer 62 may be a dry film.
- the photoresist layer 62 is patterned by, for example, a photolithography process (including exposure and development) to form a plurality of through holes 621 to expose a portion of the metal layer 52 .
- the photoresist layer 62 is also an intermediate layer. It is noted that the through holes 621 may be formed by laser drilling.
- a seed layer 64 is formed on the intermediate photoresist layer 62 (e.g., the intermediate layer) and in the through holes 621 .
- the photoresist layer 58 is formed on the seed layer 64 on the intermediate photoresist layer 62 (e.g., the intermediate layer).
- the photoresist layer 58 defines the first pattern 583 including the first openings 581 and the second openings 582 .
- the first openings 581 are communicated and aligned with the through holes 621 of the intermediate photoresist layer 62 to expose the through holes 621 .
- the second openings 582 expose a portion of the seed layer 64 on the intermediate photoresist layer 62 . It is noted that the first openings 581 and the second openings 582 correspond to the bump pads 221 and the traces 222 of FIG. 1 , respectively.
- a metal e.g., copper
- the metal disposed in the first pattern 583 of the photoresist layer 58 forms the first patterned conductive layer 22 including the bump pads 221 and the traces 222 .
- the metal disposed in the through holes 621 of the intermediate photoresist layer 62 forms the conductive posts 26 .
- the photoresist layer 58 is removed by, for example, stripping.
- the dielectric structure 20 is formed on the intermediate photoresist layer 62 to cover the first patterned conductive layer 22 . Then, the conductive vias 28 are formed in the openings 203 of the dielectric structure 20 , and the second patterned conductive layer 27 is formed on the second surface 202 of the dielectric structure 20 .
- the carrier 50 is removed.
- the metal layer 52 , the intermediate photoresist layer 62 and the seed layer 64 are removed by, for example, etching to result in the circuit structure as shown in FIG. 18 .
- the following stage is similar to the stage illustrated in FIG. 19 so as to obtain the semiconductor substrate structure 2 of FIG. 1 .
- FIGS. 28 to 37 illustrate a semiconductor manufacturing process according to some embodiments of the present disclosure. Referring to FIG. 28 , the carrier 50 and the metal layer 52 are provided.
- a photoresist layer 66 is formed on the metal layer 52 .
- the photoresist layer 66 may be a dry film.
- the photoresist layer 66 is patterned by, for example, a photolithography process (including exposure and development) to form a plurality of through holes 661 to expose a portion of the first metal layer 52 . It is noted that the through holes 661 correspond to the bonding pads 23 of FIG. 5 .
- a metal e.g., copper
- a metal is deposited or otherwise disposed on the metal layer 52 exposed in the through holes 661 of the photoresist layer 66 to form the bonding pads 23 of FIG. 5 .
- the intermediate photoresist layer 62 is formed on the photoresist layer 66 and the bonding pads 23 . Then, the intermediate photoresist layer 62 is patterned by, for example, a photolithography process (including exposure and development) to form a plurality of through holes 621 to expose a portion of the bonding pads 23 .
- a photolithography process including exposure and development
- the seed layer 211 is formed on the intermediate photoresist layer 62 and in the through holes 621 .
- the photoresist layer 58 is formed on the seed layer 211 on the intermediate photoresist layer 62 .
- the photoresist layer 58 defines the first pattern 583 including the first openings 581 and the second openings 582 .
- the first openings 581 are communicated and aligned with the through holes 621 of the intermediate photoresist layer 62 to expose the through holes 621 .
- the second openings 582 expose a portion of the seed layer 211 on the intermediate photoresist layer 62 .
- a conductive metal portion 212 (e.g., copper) is formed on the seed layer 211 in the first pattern 583 of the photoresist layer 58 and on the seed layer 211 in the through holes 621 of the intermediate photoresist layer 62 .
- the conductive metal portion 212 and the seed layer 211 in the first pattern 583 of the photoresist layer 58 form the first patterned conductive layer 22 including the bump pads 221 b and the traces 222 b .
- the conductive metal portion 212 and the seed layer 211 disposed in the through holes 621 of the intermediate photoresist layer 62 forms the conductive posts 26 b.
- the photoresist layer 58 is removed by, for example, stripping. Then, the exposed seed layer 211 is removed by, for example, etching.
- the dielectric structure 20 is formed on the intermediate photoresist layer 62 to cover the first patterned conductive layer 22 . Then, the conductive vias 28 are formed in the openings 203 of the dielectric structure 20 , and the second patterned conductive layer 27 is formed on the second surface 202 of the dielectric structure 20 .
- the carrier 50 and the metal layer 52 are removed by, for example, etching. Then, the photoresist layer 66 and the intermediate photoresist layer 62 are removed by, for example, stripping.
- the following stage is similar to the stage illustrated in FIG. 19 so as to obtain the semiconductor substrate structure 2 ′ of FIG. 5 .
- the terms “approximately,” “substantially,” “substantial” and “about” are used to describe and account for small variations. When used in conjunction with an event or circumstance, the terms can refer to instances in which the event or circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation.
- the terms can refer to a range of variation less than or equal to ⁇ 10% of that numerical value, such as less than or equal to ⁇ 5%, less than or equal to ⁇ 4%, less than or equal to ⁇ 3%, less than or equal to ⁇ 2%, less than or equal to ⁇ 1%, less than or equal to ⁇ 0.5%, less than or equal to ⁇ 0.1%, or less than or equal to ⁇ 0.05%.
- two numerical values can be deemed to be “substantially” the same or equal if a difference between the values is less than or equal to ⁇ 10% of an average of the values, such as less than or equal to ⁇ 5%, less than or equal to ⁇ 4%, less than or equal to ⁇ 3%, less than or equal to ⁇ 2%, less than or equal to ⁇ 1%, less than or equal to ⁇ 0.5%, less than or equal to ⁇ 0.1%, or less than or equal to ⁇ 0.05%.
- a component provided “on” or “over” another component can encompass cases where the former component is directly on (e.g., in physical or direct contact with) the latter component, as well as cases where one or more intervening components are located between the former component and the latter component.
Abstract
A semiconductor package includes a semiconductor substrate structure, a semiconductor die and an encapsulant. The semiconductor substrate structure includes a dielectric structure, a first patterned conductive layer, a first insulation layer and a conductive post. The first patterned conductive layer is embedded in the dielectric structure. The first insulation layer is disposed on the dielectric structure. The conductive post connects to the first patterned conductive layer and protrudes from the first insulation layer. The first insulation layer has a greater thickness at a position closer to the conductive post. The semiconductor die is electrically connected to the conductive post. The encapsulant covers the semiconductor die and at least a portion of the semiconductor substrate structure.
Description
- This application is a continuation of U.S. application Ser. No. 15/348,899, filed Nov. 10, 2016, the contents of which are incorporated herein by reference in their entirety.
- The present disclosure relates to the field of semiconductor package and semiconductor manufacturing process, and, more particularly, to a semiconductor package including an embedded trace substrate (ETS), and a semiconductor manufacturing process for manufacturing the same.
- Along with the rapid development of electronic industries and the progress of semiconductor processing technologies, semiconductor chips are integrated with more electronic components to achieve improved electrical performance. Accordingly, the semiconductor chips are provided with more input/output (I/O) connections. To achieve semiconductor packages while using semiconductor chips with increasing numbers of I/O connections, sizes of the semiconductor chips and the semiconductor packages may correspondingly increase. Thus, the cost may correspondingly increase. Alternatively, to miniaturize semiconductor packages while using semiconductor chips with increasing numbers of I/O connections, a bonding pad density of semiconductor substrates used for carrying the semiconductor chips should correspondingly increase. Therefore, solder bridge and peeling between a conductive via and a bump pad are issues of concern. In addition, the formation of a through hole of a solder resist layer is difficult.
- In some embodiments, a semiconductor package includes a semiconductor substrate structure, a semiconductor die and an encapsulant. The semiconductor substrate structure includes a dielectric structure, a first patterned conductive layer, a first insulation layer and a conductive post. The first patterned conductive layer is embedded in the dielectric structure. The first insulation layer is disposed on the dielectric structure. The first insulation layer defines an opening exposing the first patterned conductive layer. The conductive post is disposed in the opening. The conductive post connects to the first patterned conductive layer and protrudes from the first insulation layer. The first insulation layer has a first thickness at a first position and a second thickness at a second position, the first position is closer to the conductive post than the second position, and the first thickness is greater than the second thickness. The semiconductor die is electrically connected to the conductive post. The encapsulant covers the semiconductor die and at least a portion of the semiconductor substrate structure.
- In some embodiments, a semiconductor package includes a semiconductor substrate structure. The semiconductor substrate structure includes a dielectric structure, a first patterned conductive layer, a first insulation layer and a conductive post. The first patterned conductive layer is embedded in the dielectric structure. The first insulation layer is disposed on the dielectric structure. The first insulation layer defines an opening exposing the first patterned conductive layer. The conductive post is disposed in the opening. The conductive post connects to the first patterned conductive layer and protrudes from the first insulation layer. The first insulation layer includes a protrusion portion surrounding the conductive post. An inclination angle between a top surface of the protrusion portion and a sidewall of the conductive post is less than 90 degrees. In some embodiments, the semiconductor package also includes a semiconductor die and an encapsulant. The semiconductor die is electrically connected to the conductive post. The encapsulant covers the semiconductor die and at least a portion of the semiconductor substrate structure.
- In some embodiments, a semiconductor manufacturing process includes: (a) providing a circuit structure, wherein the circuit structure includes a dielectric structure, a first patterned conductive layer and a plurality of conductive posts, the first patterned conductive layer is embedded in the dielectric structure, the conductive posts protrude from the first patterned conductive layer; (b) forming a first insulation layer on the dielectric structure to cover the conductive posts; and (c) thinning the first insulation layer so that the conductive posts protrude from the first insulation layer.
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FIG. 1 illustrates a cross-sectional view of a semiconductor package according to some embodiments of the present disclosure. -
FIG. 2 illustrates an enlarged view of a region “A” of the semiconductor package shown inFIG. 1 according to some embodiments of the present disclosure. -
FIG. 3 illustrates an enlarged view of a region of a semiconductor package according to some embodiments of the present disclosure. -
FIG. 4 illustrates an enlarged view of a region of a semiconductor package according to some embodiments of the present disclosure. -
FIG. 5 illustrates a cross-sectional view of a semiconductor package according to some embodiments of the present disclosure. -
FIG. 5A illustrates an enlarged view of a region “B” of the semiconductor package ofFIG. 5 according to some embodiments of the present disclosure. -
FIG. 6 illustrates an enlarged view of a region of a semiconductor package according to some embodiments of the present disclosure. -
FIG. 7 illustrates a cross-sectional view of a semiconductor package according to some embodiments of the present disclosure. -
FIG. 8 illustrates a cross-sectional view of a semiconductor package according to some embodiments of the present disclosure. -
FIG. 9 ,FIG. 10 ,FIG. 11 ,FIG. 12 ,FIG. 13 ,FIG. 14 ,FIG. 15 ,FIG. 16 ,FIG. 17 ,FIG. 18 andFIG. 19 illustrate a semiconductor manufacturing process according to some embodiments of the present disclosure. -
FIG. 20 ,FIG. 21 ,FIG. 22 ,FIG. 23 ,FIG. 24 ,FIG. 25 ,FIG. 26 andFIG. 27 illustrate a semiconductor manufacturing process according to some embodiments of the present disclosure. -
FIG. 28 ,FIG. 29 ,FIG. 30 ,FIG. 31 ,FIG. 32 ,FIG. 33 ,FIG. 34 ,FIG. 35 ,FIG. 36 andFIG. 37 illustrate a semiconductor manufacturing process according to some embodiments of the present disclosure. - A semiconductor substrate used for carrying semiconductor chips may be an embedded trace substrate (ETS), which may include at least one dielectric layer and two or more patterned conductive layers embedded therein. In a manufacturing process of a comparative ETS, a first patterned conductive layer (including bump pads and traces) is formed in a dielectric layer firstly. Then, a solder resist layer is formed on the dielectric layer to cover the first patterned conductive layer. Then, through holes are formed in the solder resist layer to expose the bump pads of the first patterned conductive layer. Then, a second patterned conductive layer is formed on the solder resist layer, and a plurality of conductive vias are formed in the through holes, so that the second patterned conductive layer is electrically connected to the first patterned conductive layer through the conductive vias.
- The disadvantages of the comparative ETS are as follows. Firstly, a pitch between the bump pads is small (e.g., about 90 μm), and a tolerance for registration of the through holes of the solder resist layer is small (e.g., about 5 μm). Thus, there is a risk that the conductive via may contact a trace between the bump pads. Secondly, a diameter of the through holes of the solder resist layer is small (e.g., about 20 μm); thus, it may be difficult to form such through holes of the solder resist layer. Thirdly, the second patterned conductive layer and the conductive vias are formed on the solder resist layer, which results in poor adhesion therebetween. Fourthly, the first patterned conductive layer and the second patterned conductive layer are formed by two separate plating operations, which increases manufacturing time and cost, and the bonding between the conductive vias and the bump pads of the first patterned conductive layer may be poor. Fifthly, warpage of the comparative ETS may occur easily during the manufacturing process. Sixth, the solder resist layer is formed before the formation of the second patterned conductive layer and the conductive vias. Thus, during the following manufacturing process, the solder resist layer will be heated for a long time or for several cycles, which results in embrittlement and weakness of the solder resist layer.
- To address the above concerns, the present disclosure provides an improved semiconductor package including an ETS and improved techniques for manufacturing the ETS. In some embodiments of the present disclosure, metal posts and bump pads of a first patterned conductive layer are formed by a single (or one-time) plating operation, and then a solder resist layer is formed on a dielectric layer. Then, a portion of the solder resist layer is removed so that the metal posts protrude from the solder resist layer. The metal posts and the bump pads of the first patterned conductive layer are formed integrally and concurrently, which results in easier metal post formation. Shapes of the metal posts are uniform; thus, a co-planarity of top surfaces of the metal posts is excellent. Further, there is no interface between the metal posts and the bump pads; thus, the bonding between the metal posts and the bump pads is excellent, which results in improved package reliability. In addition, there is no need to form small through holes of the solder resist layer. Therefore, there will be no registration issue of the through holes of the solder resist layer. Furthermore, a thickness of the solder resist layer may be controlled to a small value, which can reduce warpage of the ETS during the manufacturing process. In addition, the solder resist layer is formed after the formation of the metal posts. Thus, during the following manufacturing process, the solder resist layer will be heated for less time, so that a strength of the solder resist layer will not be adversely influenced.
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FIG. 1 illustrates a cross-sectional view of asemiconductor package 1 according to some embodiments of the present disclosure. Thesemiconductor package 1 includes asemiconductor substrate structure 2, asemiconductor die 3 and anencapsulant 4. Thesemiconductor substrate structure 2 may be an ETS, and includes adielectric structure 20, a first patternedconductive layer 22, a first,top insulation layer 24, a plurality ofconductive posts 26, a second patternedconductive layer 27, a plurality ofconductive vias 28, a second,bottom insulation layer 29 and a plurality ofexternal connectors 292. - The
dielectric structure 20 may be, or may include, for example, monocrystalline silicon, polycrystalline silicon, amorphous silicon, other suitable inorganic materials, or a combination thereof. Thedielectric structure 20 may be, or may include, for another example, a sheet made from pre-impregnated composite fibers. Thedielectric structure 20 has a first surface (e.g., a top surface) 201 and a second surface (e.g., a bottom surface) 202 opposite to thefirst surface 201. - The first patterned
conductive layer 22 is embedded in thedielectric structure 20, and includes a plurality ofbump pads 221, a plurality oftraces 222, a first surface (e.g., a top surface) 223 and a second surface (e.g., a bottom surface) 224 opposite to thefirst surface 223. A width of eachbump pad 221 may be about 30 μm, and a pitch between thebump pads 221 may be, for example, about 90 μm. A line width/line space (L/S) of thetraces 222 may be about 12 μm/about 12 μm. A material of the first patternedconductive layer 22 may be, or may include, a conductive metal such as copper. The first patternedconductive layer 22 is disposed adjacent to thefirst surface 201 of thedielectric structure 20, and a portion (e.g., the first surface 223) of the first patternedconductive layer 22 is exposed from thefirst surface 201 of thedielectric structure 20. That is, thedielectric structure 20 does not cover thefirst surface 223 of the first patternedconductive layer 22. A distance between thesecond surface 224 of the first patternedconductive layer 22 and thesecond surface 202 of thedielectric structure 20 may be, for example, about 25 μm. - The
first insulation layer 24 may be a solder resist layer such as a solder mask layer. Thefirst insulation layer 24 is disposed on thefirst surface 201 of thedielectric structure 20 to cover at least a portion of thedielectric structure 20, and may contact the first patterned conductive layer 22 (including thebump pads 221 and the traces 222). Thefirst insulation layer 24 defines a plurality ofopenings 241 corresponding to a first portion (e.g., the bump pads 221) of the first patternedconductive layer 22. - The
conductive posts 26 are disposed in respective ones of theopenings 241 of thefirst insulation layer 24. A material of theconductive posts 26 may be, or may include, a conductive metal such as copper. One end of each of theconductive posts 26 connects to the first portion (e.g., the bump pads 221) of the first patternedconductive layer 22, and the other end of each of theconductive posts 26 protrudes from thefirst insulation layer 24. In some embodiments, theconductive posts 26 and the first portion (e.g., the bump pads 221) of the first patternedconductive layer 22 are formed integrally and concurrently as a monolithic structure. In some embodiments, theopenings 241 of thefirst insulation layer 24 are defined by the conductive posts 26. That is, theconductive posts 26 are formed before the formation of thefirst insulation layer 24, which will be described in a manufacturing process as below. In some embodiments, eachconductive post 26 has a substantially consistent width. That is, a width of a portion of theconductive post 26 embedded in thefirst insulation layer 24 is substantially equal to a width of the other portion of theconductive post 26 protruding from thefirst insulation layer 24. A height of eachconductive post 26 may be about 12 μm to 16 μm. - The second patterned
conductive layer 27 is disposed on thesecond surface 202 of thedielectric structure 20 away from the first patternedconductive layer 22, and may include a plurality ofball pads 271. A material of the second patternedconductive layer 27 may be, or may include, a conductive metal such as copper. Theconductive vias 28 are disposed in thedielectric structure 20 and electrically connect the first patternedconductive layer 22 and the second patternedconductive layer 27. In some embodiments, theconductive vias 28 and the second patternedconductive layer 27 are formed integrally and concurrently as a monolithic structure. - The
bottom insulation layer 29 may be a solder resist layer such as a solder mask layer. Thebottom insulation layer 29 is disposed on thesecond surface 202 of thedielectric structure 20 to cover at least a portion of thedielectric structure 20, and may contact the second patterned conductive layer 27 (including the ball pads 271). Thebottom insulation layer 29 defines a plurality ofopenings 291 to expose a portion (e.g., the ball pads 271) of the second patternedconductive layer 27. Theexternal connectors 292, such as solder balls, are disposed on theball pads 271 of the second patternedconductive layer 27 in theopenings 291 of thebottom insulation layer 29 for external connection. - The semiconductor die 3 is electrically connected to the conductive posts 26. In some embodiments, the semiconductor die 3 includes a plurality of
pillars 32 and a plurality ofconnectors 34 such as solder caps. Each of theconnectors 34 is disposed on a tip of a respective one of thepillars 32 and connects to a respective one of the conductive posts 26. As shown inFIG. 1 , a portion of theconnector 34 may extend to a sidewall of theconductive post 26 so that the soldering capability and reliability are enhanced. - The
encapsulant 4, such as a molding compound, covers the semiconductor die 3 and a portion (e.g., the first insulation layer 24) of thesemiconductor substrate structure 2. Theencapsulant 4 extends to a space between the semiconductor die 3 and thesemiconductor substrate structure 2 so as to protect theconductive posts 26, thepillars 32 and theconnectors 34. -
FIG. 2 illustrates an enlarged view of a region “A” of thesemiconductor package 1 shown inFIG. 1 according to some embodiments of the present disclosure. Thefirst insulation layer 24 has a first thickness T1 at a first position P1 and a second thickness T2 at a second position P2. The first position P1 is closer to theconductive post 26 than the second position P2, and the first thickness T1 is greater than the second thickness T2, such as where T1 is greater than 1.1 times T2, or about 1.2 times or greater, or about 1.3 times or greater. Thus, thefirst insulation layer 24 has a plurality ofprotrusion portions 242, and each of theprotrusion portions 242 surrounds a respective one of the conductive posts 26. A thickness of theprotrusion portion 242 decreases with increasing distance from theconductive post 26. As shown inFIG. 2 , atop surface 2421 of theprotrusion portion 242 from a cross-sectional view is a substantially flat surface. An inclination angle θ between thetop surface 2421 of theprotrusion portion 242 and asidewall 261 of theconductive post 26 is less than 90 degrees, such as about 60 degrees or less, or about 45 degrees or less. Theprotrusion portions 242 may be formed as follows. Thefirst insulation layer 24 is thinned by, for example, etching or a desmear process, and portions of thefirst insulation layer 24 surrounding theconductive posts 26 are removed to a lesser extent and will remain after the thinning process. - As shown in the embodiments illustrated in
FIGS. 1 and 2 , theconductive posts 26 and thebump pads 221 of the first patternedconductive layer 22 are formed by a single (or one-time) plating operation, that is, theconductive posts 26 and thebump pads 221 of the first patternedconductive layer 22 are formed integrally and concurrently, which results in easier metal post formation. In addition, shapes of theconductive posts 26 are uniform; thus, a co-planarity of top surfaces of the metal posts 26 is excellent, which facilitates the bonding between the semiconductor die 3 and the conductive posts 26. Further, there is no interface between theconductive posts 26 and thebump pads 221; thus, the bonding between theconductive posts 26 and thebump pads 221 is excellent (and a risk of peeling between theconductive posts 26 and thebump pads 221 is low), which results in improved package reliability. In addition, the formation of small through holes of thefirst insulation layer 24 may be omitted. Therefore, there will be no registration issue of the through holes of thefirst insulation layer 24. Furthermore, the thickness of thefirst insulation layer 24 may be adjusted to a small value by thinning (e.g., etching), which can control warpage of thesemiconductor substrate structure 2 during the manufacturing process. -
FIG. 3 illustrates an enlarged view of a region of a semiconductor package according to some embodiments of the present disclosure. The structure ofFIG. 3 is similar in certain aspects to the structure as shown inFIG. 2 , with differences including a different structure of thefirst insulation layer 24 as compared to thefirst insulation layer 24 ofFIG. 2 . As shown inFIG. 3 , thetop surface 2421 of theprotrusion portion 242 of thefirst insulation layer 24 from a cross-sectional view is a curved surface. -
FIG. 4 illustrates an enlarged view of a region of a semiconductor package according to some embodiments of the present disclosure. The structure ofFIG. 4 is similar in certain aspects to the structure as shown inFIG. 2 , with differences including a different structure of theconductive posts 26 andbump pads 221 as compared to theconductive posts 26 and thebump pads 221 ofFIG. 2 . As shown inFIG. 4 , a peripheral surface (e.g., of the sidewall 261) and a top surface of theconductive post 26 and a top surface of thebump pad 221 are rough surfaces. For example, the surface roughness (Ra or arithmetic average of a surface profile) of the peripheral surface and top surface of theconductive post 26 and the top surface of thebump pad 221 may be about 3 μm or greater, about 5 μm or greater, or about 10 μm or greater. The rough surfaces of theconductive post 26 and thebump pad 221 can enhance an adhesion between thefirst insulation layer 24 and theconductive post 26 and thebump pads 221, so as to increase reliability. -
FIG. 5 illustrates a cross-sectional view of asemiconductor package 1′ according to some embodiments of the present disclosure.FIG. 5A illustrates an enlarged view of a region “B” of a semiconductor package ofFIG. 5 . Thesemiconductor package 1′ ofFIG. 5 is similar in certain aspects to thesemiconductor package 1 as shown inFIG. 1 , with differences including a different structure of asemiconductor substrate structure 2′ as compared to thesemiconductor substrate structure 2 ofFIG. 1 . As shown inFIGS. 5 and 5A , thesemiconductor substrate structure 2′ includes a plurality ofconductive posts 26 b, a plurality ofbump pads 221 b, and a plurality ofbonding pads 23. Eachconductive post 26b includes aseed layer 211 and aconductive metal portion 212 in theopening 241 of thefirst insulation layer 24. Eachbump pad 221 b includes theseed layer 211 and theconductive metal portion 212 embedded in thedielectric structure 20. Eachbonding pad 23 is disposed on the respectiveconductive post 26 b. A width of thebonding pad 23 is greater than a width of theconductive post 26 b, so as to increase a bonding area between theconnector 34 and thebonding pad 23 and, thereby, increase reliability. It is noted that theprotrusion portion 242 of thefirst insulation layer 24 may contact a peripheral surface of thebonding pad 23. It is noted that theseed layer 211 may be omitted. -
FIG. 6 illustrates an enlarged view of a region of a semiconductor package according to some embodiments of the present disclosure. The structure ofFIG. 6 is similar in certain aspects to the structure as shown inFIG. 5A , with differences including a different structure ofconductive posts 26 c,bump pads 221 c andbonding pads 23 a as compared to theconductive posts 26 b, thebump pads 221 b andbonding pads 23 ofFIG. 5A . As shown inFIG. 6 , a peripheral surface theconductive post 26 c, a top surface of thebump pad 221 c, a peripheral surface and a top surface of thebonding pad 23 a are rough surfaces. For example, a surface roughness (Ra) of the peripheral surface theconductive post 26 c, the top surface of thebump pad 221 c, and the peripheral surface and the top surface of thebonding pad 23 a may be about 3 μm or greater, about 5 μm or greater, or about 10 μm or greater. The rough surfaces of theconductive post 26 c, thebump pad 221 c, and thebonding pad 23 a can enhance an adhesion between thefirst insulation layer 24 and theconductive post 26 c, thebump pad 221 c and thebonding pad 23 a, so as to increase reliability. -
FIG. 7 illustrates a cross-sectional view of a semiconductor package 1 a according to some embodiments of the present disclosure. The semiconductor package 1 a ofFIG. 7 is similar in certain aspects to thesemiconductor package 1 as shown inFIG. 1 , with differences including a different structure of asemiconductor substrate structure 2 a as compared to thesemiconductor substrate structure 2 ofFIG. 1 . As shown inFIG. 7 , thesemiconductor substrate structure 2 a further includes athird insulation layer 25 disposed on thefirst insulation layer 24. Thethird insulation layer 25 may be a solder resist layer such as a solder mask layer, which may be the same as or different from thefirst insulation layer 24. Thethird insulation layer 25 defines at least oneaccommodating opening 251 to accommodate at least twoconductive posts 26. A top surface of thethird insulation layer 25 is higher than top surfaces of theconductive posts 26, so as to prevent theconductive posts 26 from damage. Further, warpage of thesemiconductor substrate structure 2 a may be controlled by adjusting a thickness of thethird insulation layer 25. -
FIG. 8 illustrates a cross-sectional view of a semiconductor package 1 b according to some embodiments of the present disclosure. The semiconductor package 1 b ofFIG. 8 is similar in certain aspects to thesemiconductor package 1 as shown inFIG. 1 , with differences including a different structure of asemiconductor substrate structure 2 b as compared to thesemiconductor substrate structure 2 ofFIG. 1 . As shown inFIG. 8 , thesemiconductor substrate structure 2 b further includesconductive posts 26 d disposed on a portion of thetraces 222 of the first patternedconductive layer 22, andconductive posts 26 e disposed on thebump pads 221 of the first patternedconductive layer 22. One end of each of theconductive posts 26 d connects to thetraces 222 of the first patternedconductive layer 22, and the other end of each of theconductive posts 26 d protrudes from thefirst insulation layer 24. Theprotrusion portions 242 of thefirst insulation layer 24 may surround theconductive posts 26 d, and may surround theconductive posts 26 e. In some embodiments, theconductive posts 26 e may extend upward and beyond the semiconductor die 3 so that top ends or surfaces of theconductive posts 26 e are exposed from a top surface of theencapsulant 4. - In some embodiments, the
conductive posts 26 d, thetraces 222, theconductive posts 26 e and thebump pads 221 are formed integrally and concurrently. A height of theconductive posts 26 d may be substantially equal to or may be less than a height of theconductive post 26 e. It is noted that additional bonding pads (not shown) may be formed on top of theconductive posts 26 d. -
FIGS. 9 to 19 illustrate a semiconductor manufacturing process according to some embodiments of the present disclosure. Referring toFIG. 9 , acarrier 50 and a metal layer 52 (e.g., a metal foil) are provided. Themetal layer 52 is disposed on one surface of thecarrier 50. However, there may be another metal layer (not shown) disposed on another surface of thecarrier 50; thus, the manufacturing process can be performed on two sides of thecarrier 50.FIGS. 9 to 19 describe the manufacturing process performed on one side of thecarrier 50. It is noted that the manufacturing process can be performed on the other side of thecarrier 50 in a similar way. - Referring to
FIG. 10 , aphotoresist layer 54 is formed on themetal layer 52. Thephotoresist layer 54 may be a dry film. Then, thephotoresist layer 54 is patterned by, for example, a photolithography process (including exposure and development) to form a plurality of remainingportions 541. - Referring to
FIG. 11 , at least one intermediate metal layer 56 (e.g., anickel layer 561 and a copper layer 562) is formed on portions of themetal layer 52 that are not covered by the remainingportions 541 of thephotoresist layer 54. In some embodiments, theintermediate metal layer 56 includes thenickel layer 561 formed on themetal layer 52 by electrolytic plating and thecopper layer 562 formed on thenickel layer 561 by plating. - Referring to
FIG. 12 , the remainingportions 541 of thephotoresist layer 54 are removed by, for example, stripping, to leave the intermediate metal layer 56 (including thenickel layer 561 and the copper layer 562) on themetal layer 52. A thickness of theintermediate metal layer 56 may be about 12 μm to about 16 μm. Theintermediate layer 56 defines a plurality of throughholes 563 to expose a portion of themetal layer 52. It is noted that the throughholes 563 of theintermediate layer 56 correspond to theconductive posts 26 ofFIG. 1 . - Referring to
FIG. 13 , aphotoresist layer 58 is formed on theintermediate layer 56. Thephotoresist layer 58 may be a dry film. Thephotoresist layer 58 defines afirst pattern 583 including a plurality offirst openings 581 and a plurality ofsecond openings 582. Thefirst openings 581 are communicated and aligned with the throughholes 563 of theintermediate layer 56 to expose the throughholes 563. Thesecond openings 582 expose a portion of theintermediate layer 56. It is noted that thefirst openings 581 and thesecond openings 582 correspond to thebump pads 221 and thetraces 222 ofFIG. 1 , respectively. - Referring to
FIG. 14 , a metal (e.g., copper) is deposited or otherwise disposed on thefirst pattern 583 of thephotoresist layer 58 and in the throughholes 563 of theintermediate layer 56. The metal disposed in thefirst pattern 583 of thephotoresist layer 58 forms the first patternedconductive layer 22 including thebump pads 221 and thetraces 222. The metal disposed in the throughholes 563 of theintermediate layer 56 forms the conductive posts 26. Therefore, theconductive posts 26 and thebump pads 221 are formed by a single (or one-time) plating operation, that is, theconductive posts 26 and thebump pads 221 are formed integrally and concurrently, which results in easier metal post formation. - Referring to
FIG. 15 , thephotoresist layer 58 is removed by, for example, stripping. - Referring to
FIG. 16 , thedielectric structure 20 is formed on theintermediate layer 56 to cover the first patternedconductive layer 22. Thedielectric structure 20 has thefirst surface 201 and thesecond surface 202 opposite to thefirst surface 201. Then, a plurality ofopenings 203 are formed in thedielectric structure 20 from thesecond surface 202 to expose thebump pads 221. Then, a metal, such as copper, is deposited or otherwise disposed (e.g., plated) in theopenings 203 and on thedielectric structure 20 so as to form theconductive vias 28 and the second patternedconductive layer 27. The second patternedconductive layer 27 is disposed on thesecond surface 202 of thedielectric structure 20 away from the first patternedconductive layer 22, and may include the plurality ofball pads 271. Theconductive vias 28 are disposed in theopenings 203 of thedielectric structure 20 and electrically connect the first patternedconductive layer 22 and the second patternedconductive layer 27. In some embodiments, theconductive vias 28 and the second patternedconductive layer 27 are formed integrally and concurrently. - Referring to
FIG. 17 , thecarrier 50 is removed. - Referring to
FIG. 18 , themetal layer 52 and theintermediate layer 56 are removed by, for example, etching. Meanwhile, a circuit structure is obtained, wherein the circuit structure includes thedielectric structure 20, the first patternedconductive layer 22 and the conductive posts 26. The first patternedconductive layer 22 is embedded in thedielectric structure 20, and theconductive posts 26 protrude from a portion (e.g., the bump pads 221) of the first patternedconductive layer 22. In some embodiments, a pretreatment process (e.g., etching) may be conducted to roughen peripheral surfaces and top surfaces of theconductive posts 26 and top surfaces of thebump pads 221 as shown inFIG. 4 . - Referring to
FIG. 19 , thebottom insulation layer 29 is formed on thesecond surface 202 of thedielectric structure 20 of the circuit structure to cover the second patternedconductive layer 27 and thedielectric structure 20. Then, theopenings 291 are formed in thebottom insulation layer 29 to expose a portion (e.g., the ball pads 271) of the second patternedconductive layer 27. Then, thefirst insulation layer 24 is formed on thefirst surface 201 of thedielectric structure 20 of the circuit structure to cover thefirst surface 201 of thedielectric structure 20 and the conductive posts 26. Theopenings 241 of thefirst insulation layer 24 are defined by the conductive posts 26. - Then, the
first insulation layer 24 is thinned from its top surface so that theconductive posts 26 protrude from thefirst insulation layer 24 by, for example, etching or a desmear process. Meanwhile, thesemiconductor substrate structure 2 ofFIG. 1 is obtained. - In some embodiments, the manufacturing process may further include the following stages. A semiconductor die 3 is electrically connected to the conductive posts 26. Then, an
encapsulant 4 is formed to cover the semiconductor die 3 and a portion (e.g., the first insulation layer 24) of thesemiconductor substrate structure 2. Then, a plurality ofexternal connectors 292 are attached to the exposed portion (e.g., the ball pads 271) of the second patternedconductive layer 27 in theopenings 291 of thebottom insulation layer 29. Meanwhile, thesemiconductor package 1 as shown inFIG. 1 is obtained. - In some embodiments, the manufacturing process may further include the following stages. The
third insulation layer 25 is formed on thefirst insulation layer 24, wherein thethird insulation layer 25 defines at least oneaccommodating opening 251 to expose at least twoconductive posts 26. Meanwhile, the semiconductor package 1 a as shown inFIG. 7 is obtained. -
FIGS. 20 to 27 illustrate a semiconductor manufacturing process according to some embodiments of the present disclosure. Referring toFIG. 20 , thecarrier 50 and themetal layer 52 are provided. - Referring to
FIG. 21 , aphotoresist layer 62 is formed on thefirst metal layer 52. Thephotoresist layer 62 may be a dry film. Then, thephotoresist layer 62 is patterned by, for example, a photolithography process (including exposure and development) to form a plurality of throughholes 621 to expose a portion of themetal layer 52. Thephotoresist layer 62 is also an intermediate layer. It is noted that the throughholes 621 may be formed by laser drilling. - Referring to
FIG. 22 , aseed layer 64 is formed on the intermediate photoresist layer 62 (e.g., the intermediate layer) and in the throughholes 621. - Referring to
FIG. 23 , thephotoresist layer 58 is formed on theseed layer 64 on the intermediate photoresist layer 62 (e.g., the intermediate layer). Thephotoresist layer 58 defines thefirst pattern 583 including thefirst openings 581 and thesecond openings 582. Thefirst openings 581 are communicated and aligned with the throughholes 621 of theintermediate photoresist layer 62 to expose the throughholes 621. Thesecond openings 582 expose a portion of theseed layer 64 on theintermediate photoresist layer 62. It is noted that thefirst openings 581 and thesecond openings 582 correspond to thebump pads 221 and thetraces 222 ofFIG. 1 , respectively. - Referring to
FIG. 24 , a metal (e.g., copper) is deposited or otherwise disposed on theseed layer 64 in thefirst pattern 583 of thephotoresist layer 58 and on theseed layer 64 in the throughholes 621 of theintermediate photoresist layer 62. The metal disposed in thefirst pattern 583 of thephotoresist layer 58 forms the first patternedconductive layer 22 including thebump pads 221 and thetraces 222. The metal disposed in the throughholes 621 of theintermediate photoresist layer 62 forms the conductive posts 26. - Referring to
FIG. 25 , thephotoresist layer 58 is removed by, for example, stripping. - Referring to
FIG. 26 , thedielectric structure 20 is formed on theintermediate photoresist layer 62 to cover the first patternedconductive layer 22. Then, theconductive vias 28 are formed in theopenings 203 of thedielectric structure 20, and the second patternedconductive layer 27 is formed on thesecond surface 202 of thedielectric structure 20. - Referring to
FIG. 27 , thecarrier 50 is removed. - Then, the
metal layer 52, theintermediate photoresist layer 62 and theseed layer 64 are removed by, for example, etching to result in the circuit structure as shown inFIG. 18 . - Then, the following stage is similar to the stage illustrated in
FIG. 19 so as to obtain thesemiconductor substrate structure 2 ofFIG. 1 . -
FIGS. 28 to 37 illustrate a semiconductor manufacturing process according to some embodiments of the present disclosure. Referring toFIG. 28 , thecarrier 50 and themetal layer 52 are provided. - Referring to
FIG. 29 , aphotoresist layer 66 is formed on themetal layer 52. Thephotoresist layer 66 may be a dry film. Then, thephotoresist layer 66 is patterned by, for example, a photolithography process (including exposure and development) to form a plurality of throughholes 661 to expose a portion of thefirst metal layer 52. It is noted that the throughholes 661 correspond to thebonding pads 23 ofFIG. 5 . - Referring to
FIG. 30 , a metal (e.g., copper) is deposited or otherwise disposed on themetal layer 52 exposed in the throughholes 661 of thephotoresist layer 66 to form thebonding pads 23 ofFIG. 5 . - Referring to
FIG. 31 , theintermediate photoresist layer 62 is formed on thephotoresist layer 66 and thebonding pads 23. Then, theintermediate photoresist layer 62 is patterned by, for example, a photolithography process (including exposure and development) to form a plurality of throughholes 621 to expose a portion of thebonding pads 23. - Referring to
FIG. 32 , theseed layer 211 is formed on theintermediate photoresist layer 62 and in the throughholes 621. - Referring to
FIG. 33 , thephotoresist layer 58 is formed on theseed layer 211 on theintermediate photoresist layer 62. Thephotoresist layer 58 defines thefirst pattern 583 including thefirst openings 581 and thesecond openings 582. Thefirst openings 581 are communicated and aligned with the throughholes 621 of theintermediate photoresist layer 62 to expose the throughholes 621. Thesecond openings 582 expose a portion of theseed layer 211 on theintermediate photoresist layer 62. - Referring to
FIG. 34 , a conductive metal portion 212 (e.g., copper) is formed on theseed layer 211 in thefirst pattern 583 of thephotoresist layer 58 and on theseed layer 211 in the throughholes 621 of theintermediate photoresist layer 62. Theconductive metal portion 212 and theseed layer 211 in thefirst pattern 583 of thephotoresist layer 58 form the first patternedconductive layer 22 including thebump pads 221 b and thetraces 222 b. Theconductive metal portion 212 and theseed layer 211 disposed in the throughholes 621 of theintermediate photoresist layer 62 forms theconductive posts 26 b. - Referring to
FIG. 35 , thephotoresist layer 58 is removed by, for example, stripping. Then, the exposedseed layer 211 is removed by, for example, etching. - Referring to
FIG. 36 , thedielectric structure 20 is formed on theintermediate photoresist layer 62 to cover the first patternedconductive layer 22. Then, theconductive vias 28 are formed in theopenings 203 of thedielectric structure 20, and the second patternedconductive layer 27 is formed on thesecond surface 202 of thedielectric structure 20. - Referring to
FIG. 37 , thecarrier 50 and themetal layer 52 are removed by, for example, etching. Then, thephotoresist layer 66 and theintermediate photoresist layer 62 are removed by, for example, stripping. - Then, the following stage is similar to the stage illustrated in
FIG. 19 so as to obtain thesemiconductor substrate structure 2′ ofFIG. 5 . - Spatial descriptions, such as “above,” “below,” “up,” “left,” “right,” “down,” “top,” “bottom,” “vertical,” “horizontal,” “side,” “higher,” “lower,” “upper,” “over,” “under,” and so forth, are indicated with respect to the orientation shown in the figures unless otherwise specified. It should be understood that the spatial descriptions used herein are for purposes of illustration only, and that practical implementations of the structures described herein can be spatially arranged in any orientation or manner, provided that the merits of embodiments of this disclosure are not deviated by such arrangement.
- As used herein, the singular terms “a,” “an,” and “the” may include plural referents unless the context clearly dictates otherwise.
- As used herein, the terms “approximately,” “substantially,” “substantial” and “about” are used to describe and account for small variations. When used in conjunction with an event or circumstance, the terms can refer to instances in which the event or circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation. For example, when used in conjunction with a numerical value, the terms can refer to a range of variation less than or equal to ±10% of that numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, two numerical values can be deemed to be “substantially” the same or equal if a difference between the values is less than or equal to ±10% of an average of the values, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%.
- Additionally, amounts, ratios, and other numerical values are sometimes presented herein in a range format. It is to be understood that such range format is used for convenience and brevity and should be understood flexibly to include numerical values explicitly specified as limits of a range, but also to include all individual numerical values or sub-ranges encompassed within that range as if each numerical value and sub-range is explicitly specified.
- In the description of some embodiments, a component provided “on” or “over” another component can encompass cases where the former component is directly on (e.g., in physical or direct contact with) the latter component, as well as cases where one or more intervening components are located between the former component and the latter component.
- While the present disclosure has been described and illustrated with reference to specific embodiments thereof, these descriptions and illustrations do not limit the present disclosure. It should be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The illustrations may not be necessarily drawn to scale. There may be distinctions between the artistic renditions in the present disclosure and the actual apparatus due to manufacturing processes and tolerances. There may be other embodiments of the present disclosure which are not specifically illustrated. The specification and drawings are to be regarded as illustrative rather than restrictive. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to be within the scope of the claims appended hereto. While the methods disclosed herein have been described with reference to particular operations performed in a particular order, it will be understood that these operations may be combined, sub-divided, or re-ordered to form an equivalent method without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of the operations are not limitations of the present disclosure.
Claims (20)
1. A semiconductor structure, comprising:
a patterned conductive layer; and
an insulation layer covering the pattern conductive layer, wherein the insulation layer defines an opening exposing the first patterned conductive layer, and the first insulation layer comprises a protrusion portion surrounding the opening.
2. The semiconductor package according to claim 1 , wherein a top surface of the protrusion portion from a cross-sectional view is a curved surface.
3. The semiconductor package according to claim 1 , wherein a thickness of the protrusion portion decreases with increasing distance from the conductive post.
4. The semiconductor package according to claim 1 , wherein an inclination angle between a top surface of the protrusion portion and a sidewall of the conductive post is less than 90 degrees.
5. The semiconductor package according to claim 1 , further comprising a conductive post disposed in the opening, wherein the conductive post connects to the first patterned conductive layer.
6. The semiconductor package according to claim 5 , wherein a surface of the conductive post has a surface roughness (Ra) of greater than about 3 μm.
7. The semiconductor package according to claim 5 , wherein the conductive post has a recess which is recessed from a top surface of the conductive post.
8. The semiconductor package according to claim 5 , wherein the opening of the insulation layer is spanned by the conductive post.
9. The semiconductor package according to claim 1 , further comprising a substrate, wherein the patterned conductive layer is disposed on or embedded in the substrate, and the insulation layer is disposed on the substrate to cover the patterned conductive layer.
10. The semiconductor package according to claim 9 , wherein a material of the substrate includes silicon, glass or polymer.
11. A semiconductor structure, comprising:
a patterned conductive layer; and
an insulation layer covering the pattern conductive layer, wherein the insulation layer defines an opening exposing the first patterned conductive layer, the insulation layer has a first thickness at a first position and a second thickness at a second position, and the first thickness is greater than the second thickness.
12. The semiconductor package according to claim 11 , wherein the first position is closer to the opening than the second position is.
13. The semiconductor package according to claim 11 , wherein the first position of the insulation layer has a bottom surface, and the second position of the insulation layer has a bottom surface substantially coplanar with the bottom surface of the first position.
14. The semiconductor package according to claim 11 , further comprising a substrate, wherein the patterned conductive layer is disposed on or embedded in the substrate, and the insulation layer is disposed on the substrate to cover the patterned conductive layer.
15. The semiconductor package according to claim 14 , wherein a material of the substrate includes silicon, glass or polymer.
16. The semiconductor package according to claim 11 , further comprising a semiconductor die, wherein the patterned conductive layer is disposed on or embedded in the semiconductor die, and the insulation layer is disposed on the semiconductor die to cover the patterned conductive layer.
17. The semiconductor package according to claim 11 , further comprising a conductive post disposed in the opening, wherein a top surface of the conductive post is lower than a top surface of the insulation layer
18. The semiconductor package according to claim 17 , wherein the conductive post and the patterned conductive layer are formed integrally.
19. The semiconductor package according to claim 17 , wherein the conductive post has a consistent width.
20. The semiconductor package according to claim 17 , wherein the patterned conductive layer includes a bump pad and a trace, and the conductive post and the bump pad of the first patterned conductive layer are formed integrally.
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KR101195786B1 (en) | 2008-05-09 | 2012-11-05 | 고쿠리츠 다이가쿠 호진 큐슈 코교 다이가쿠 | Chip-size double side connection package and method for manufacturing the same |
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CN104576596B (en) | 2013-10-25 | 2019-01-01 | 日月光半导体制造股份有限公司 | Semiconductor substrate and its manufacturing method |
US9379076B2 (en) * | 2014-10-01 | 2016-06-28 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor device and manufacturing method thereof |
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- 2016-11-10 US US15/348,899 patent/US10636730B2/en active Active
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US10636730B2 (en) | 2020-04-28 |
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