US20170075834A1 - Storage device and interrupt generation method thereof - Google Patents

Storage device and interrupt generation method thereof Download PDF

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Publication number
US20170075834A1
US20170075834A1 US15/265,090 US201615265090A US2017075834A1 US 20170075834 A1 US20170075834 A1 US 20170075834A1 US 201615265090 A US201615265090 A US 201615265090A US 2017075834 A1 US2017075834 A1 US 2017075834A1
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Prior art keywords
interrupt
host
completion
completion queue
pointer
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Abandoned
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US15/265,090
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English (en)
Inventor
Hyunseok Cha
Sarath Kumar Kunnumpurathu Sivan
Jungsoo Ryoo
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Publication of US20170075834A1 publication Critical patent/US20170075834A1/en
Assigned to SAMSUNG ELECTRONICS CO., LTD. reassignment SAMSUNG ELECTRONICS CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KUNNUMPURATHUSIVAN, SARATH KUMAR, CHA, HYUNSEOK, RYOO, JUNGSOO
Priority to US17/071,411 priority Critical patent/US11561914B2/en
Abandoned legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1673—Details of memory controller using buffers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0683—Plurality of storage devices
    • G06F3/0688—Non-volatile semiconductor memory arrays

Definitions

  • Exemplary embodiments of the inventive concept relate to a semiconductor memory device, and more particularly, to a storage device and an interrupt generation method thereof.
  • a flash memory device is often used in electronic devices such as, for example, a computer, a smartphone, a personal digital assistant (PDA), a digital camera, a voice recorder, an MP3 player, a handheld PC, etc.
  • An example of a flash memory device is a solid state drive (SSD).
  • An SSD is commonly used in devices such as, for example, a server, a client, a data center, etc.
  • Serial AT Attachment (SATA), PCI Express (PCIe), Serial Attached SCSI (SAS), and NVM Express (NVMe) are common interfaces used for an SSD.
  • Host equipment including an SSD may include various computer systems.
  • an SSD may be connected to a server, a data center, a personal computer (PC), etc.
  • overhead of the host equipment may be caused by the frequent occurrence of interrupts, which may occur when, for example, the performance of the host equipment is relatively low, or a relatively high number of applications are driven on the host equipment.
  • Exemplary embodiments of the inventive concept provide a storage device which reduces an interrupt generation frequency, and an interrupt generation method thereof.
  • an interrupt generation method of a storage device includes executing a command provided by a host, writing a completion entry in a completion queue of the host upon completing execution of the command, and issuing an interrupt corresponding to the completion entry to the host in response to at least one of a first interrupt generation condition, a second interrupt generation condition, and a third interrupt generation condition being satisfied.
  • the first interrupt generation condition is satisfied when a difference between a tail pointer and a head pointer of the completion queue is equal to a first mismatch value.
  • the second interrupt generation condition is satisfied when the difference between the tail pointer and the head pointer is at least equal to an aggregation threshold.
  • the third interrupt generation condition is satisfied when an amount of time that has elapsed since a previous interrupt was issued exceeds a reference time.
  • a storage device includes a nonvolatile memory device and a storage controller configured to control the nonvolatile memory device.
  • the storage controller executes a command provided by a host, sends a completion entry to the host upon executing the command, and issues an interrupt corresponding to the completion entry to the host.
  • the storage controller issues the interrupt to the host in response to at least one of a first interrupt generation condition, a second interrupt generation condition, and a third interrupt generation condition being satisfied.
  • the first interrupt generation condition is satisfied when a difference between a tail pointer and a head pointer of a completion queue of the host in which the completion entry is stored is equal to a first mismatch value.
  • the second interrupt generation condition is satisfied when the difference between the tail pointer and the head pointer is at least equal to an aggregation threshold.
  • the third interrupt generation condition is satisfied when an amount of time that has elapsed since a previous interrupt was issued exceeds a reference time.
  • an interrupt issuing method of a solid state drive includes writing a completion entry at a completion queue of a host, determining whether to issue an interrupt corresponding to the completion queue based on a number of completion entries accumulated in the completion queue or an amount of time that has elapsed since a previous interrupt was issued, and sending the interrupt to the host based on a result of the determination.
  • SSD solid state drive
  • an interrupt issuing method of a solid state drive includes writing a completion entry at a completion queue of a host, determining whether to issue an interrupt corresponding to the completion queue based on at least one of a first interrupt generation condition indicating whether a difference between a tail pointer and a head pointer of the completion queue is equal to a first mismatch value, a second interrupt generation condition indicating whether the difference between the tail pointer and the head pointer is at least equal to an aggregation threshold, and a third interrupt generation condition indicating whether an amount of time that has elapsed since a previous interrupt was issued exceeds a reference time, and sending the interrupt to the host based on a result of the determination.
  • a first interrupt generation condition indicating whether a difference between a tail pointer and a head pointer of the completion queue is equal to a first mismatch value
  • a second interrupt generation condition indicating whether the difference between the tail pointer and the head pointer is at least equal to an aggregation threshold
  • a third interrupt generation condition indicating whether an
  • FIG. 1 is a block diagram illustrating a user device according to an exemplary embodiment of the inventive concept.
  • FIG. 2 is a block diagram illustrating a queue management operation of a host according to an exemplary embodiment of the inventive concept.
  • FIG. 3 is a block diagram illustrating a storage controller illustrated in FIG. 1 according to an exemplary embodiment of the inventive concept.
  • FIG. 4 is a diagram illustrating an example of a method in which the storage controller of FIG. 3 generates an interrupt for a host, according to an exemplary embodiment of the inventive concept.
  • FIG. 5 is a timing diagram illustrating an operating method of a storage device according to an exemplary embodiment of the inventive concept.
  • FIG. 6 is a flow chart illustrating an operating method of a storage controller according to an exemplary embodiment of the inventive concept.
  • FIG. 7 is a diagram illustrating a call process procedure of a host and a storage device according to an interrupt generation method of FIG. 5 , according to an exemplary embodiment of the inventive concept.
  • FIG. 8 is a timing diagram illustrating an operating method of a storage device according to an exemplary embodiment of the inventive concept.
  • FIG. 9 is a flow chart illustrating an interrupt generation method of the storage controller according to the exemplary embodiment described with reference to FIG. 8 .
  • FIG. 10 is a diagram illustrating a call process procedure of a host and a storage device according to an interrupt generation method of FIG. 9 , according to an exemplary embodiment of the inventive concept.
  • FIG. 11 is a timing diagram illustrating an exemplary embodiment of an interrupt generation method.
  • FIG. 12 is a flow chart illustrating an interrupt generation method of the storage controller for performing the exemplary embodiment described with reference to FIG. 11 .
  • FIG. 13 is a diagram illustrating a call process procedure of a host and a storage device according to an interrupt generation method of FIG. 11 , according to an exemplary embodiment of the inventive concept.
  • FIG. 14 is a timing diagram illustrating an interrupt generation method according to an exemplary embodiment of the inventive concept.
  • FIG. 15 is a timing diagram illustrating an interrupt generation method according to an exemplary embodiment of the inventive concept.
  • FIG. 16 is a block diagram illustrating a nonvolatile memory described with reference to FIG. 1 , according to an exemplary embodiment of the inventive concept.
  • FIG. 17 is a circuit diagram illustrating a first memory block of memory blocks included in a memory cell array of FIG. 16 according to an exemplary embodiment of the inventive concept.
  • FIG. 18 is a block diagram illustrating a memory card system including a nonvolatile memory system according to an exemplary embodiment of the inventive concept.
  • FIG. 19 is a block diagram illustrating a solid state drive including a nonvolatile memory system according to an exemplary embodiment of the inventive concept.
  • FIG. 20 is a block diagram illustrating a user system including a nonvolatile memory system according to an exemplary embodiment of the inventive concept.
  • SSD solid state drive
  • flash memory device a solid state drive (SSD) using a flash memory device
  • SSD solid state drive
  • exemplary embodiments of the inventive concept are not limited thereto.
  • FIG. 1 is a block diagram illustrating a user device according to an exemplary embodiment of the inventive concept.
  • a user device 10 may include a host 100 and a storage device 200 .
  • the host 100 may provide a command CMD to the storage device 200 .
  • the storage device 200 may write a completion entry at a completion queue CQ of the host 100 as the result of executing a command, and may issue an interrupt.
  • the storage device 200 may issue less interrupts than the number of events occurring that correspond to completion entries being written. This will be described in further detail below.
  • the host 100 may read or write data from or to the storage device 200 .
  • the host 100 may write data to the storage device 200 and may generate a command CMD used to read data stored in the storage device 200 .
  • the host 100 may output a command CMD to the storage device 200 and may receive a completion entry indicating whether a corresponding command is executed, and an associated interrupt, from the storage device 200 .
  • the host 100 may execute an interrupt process for completing a thread or a task associated with a corresponding command in response to the interrupt.
  • the host 100 may include a processing unit 110 , a host memory 120 , and an interface circuit 130 .
  • a variety of software used to drive the host 100 including, for example, an application program, a file system, a device driver, etc., may be loaded onto and stored in the host memory 120 .
  • the processing unit 110 may execute a variety of software (e.g., an application program, an operating system, a device driver, etc.) stored in the host memory 120 .
  • the processing unit 110 may execute an operating system (OS), application programs, etc.
  • OS operating system
  • the processing unit 110 may be, for example, a homogeneous multi-core processor or a heterogeneous multi-core processor.
  • An application program or data to be processed by the processing unit 110 may be loaded on the host memory 120 .
  • An input/output scheduler 122 for managing a queue for a command to be transferred to the storage device 200 may be loaded on the host memory 120 .
  • the input/output scheduler 122 may include, for example, a submission queue 123 and a completion queue 125 .
  • the submission queue 123 may be, for example, a queue that corresponds to commands to be sent to the storage device 200 .
  • the completion queue 125 may be, for example, a wait string of completion entries written by the storage device 200 , and may indicate whether a command requested by the host 100 is completed.
  • the submission queue 123 may be written or supplied by the host 100 and may be read by the storage device 200 .
  • a tail pointer TP of the submission queue 123 may be advanced by the host 100 , and a position of a new tail pointer TP may be sent to the storage device 200 .
  • the storage device 200 may advance a head pointer HP of the submission queue by providing a completion entry.
  • the completion queue 125 may be written by the storage device 200 and may be stored in the host 100 .
  • a tail pointer TP of the completion queue 125 may be advanced through a write operation of the storage device 200 .
  • the host 100 may advance a head pointer HP of the completion queue 125 in response to an interrupt, and a position of a new head pointer HP may be transferred to the storage device 200 .
  • a position of the head pointer HP may be indicated by the host 100 to the storage device 200 by writing it at a doorbell register of the storage device 200 .
  • the interface circuit 130 may provide a physical connection between the host 100 and the storage device 200 .
  • the interface circuit 130 may convert, for example, a command, an address, data, etc., which corresponds to various access requests issued from the host 100 , to a format that is suitable for interfacing with the storage device 200 .
  • the interface circuit 130 may include at least one of protocols such as, for example, Universal Serial Bus (USB), Small Computer System Interface (SCSI), Peripheral Component Interconnect Express (PCI Express), Advanced Technology Attachment (ATA), parallel ATA (PTA), serial ATA (SATA), and serial attached SCSI (SAS).
  • USB Universal Serial Bus
  • SCSI Small Computer System Interface
  • PCI Express Peripheral Component Interconnect Express
  • ATA Advanced Technology Attachment
  • PTA parallel ATA
  • SATA serial ATA
  • SAS serial attached SCSI
  • the interface circuit 130 is not limited thereto.
  • the storage device 200 may access a nonvolatile memory device (e.g., nonvolatile memory devices 230 , 240 . . . 250 ) in response to a command CMD from the host 100 , and may perform various requested operations.
  • the storage device 200 may generate an interrupt signal with reference to a doorbell register about a completion queue CQ provided from the host 100 .
  • the storage device 200 may generate an interrupt only at a time when a first mismatch between a tail pointer TP and a head pointer HP of the completion queue CQ occurs.
  • the storage device 200 may generate an interrupt vector corresponding to a plurality of completion signals when the number of entries accumulated at the completion queue CQ exceeds a threshold TH.
  • the storage device 200 may generate an interrupt vector corresponding to a plurality of completion signals if a certain amount of time elapses from a point in time when a first mismatch between a tail pointer TP and a head pointer HP of the completion queue CQ occurs.
  • the storage device 200 may include, for example, a storage controller 210 , a buffer memory 220 , and at least one nonvolatile memory device (e.g., nonvolatile memory devices 230 , 240 . . . 250 ).
  • the storage controller 210 may provide interfacing between the host 100 and the storage device 200 . According to exemplary embodiments of the inventive concept, the storage controller 210 may perform interrupt generation with reference to head pointer HP doorbell information of the completion queue CQ from the host 100 . For example, in an exemplary embodiment, the storage controller 210 may perform a lazy interrupt generation operation for generating an interrupt at a point in time when a first mismatch between a tail pointer and a head pointer of the completion queue CQ occurs. In an exemplary embodiment, the storage controller 210 may generate a relatively small number of interrupts when the number of completion entries accumulated with the lazy interrupt generation operation exceeds a threshold, or in response to a certain amount of time elapsing from a point in time when an interrupt is previously generated. A detailed operation of the storage controller 210 will be described later.
  • the storage device 200 may reduce the number of events that generate an interrupt, thereby reducing consumed resources and improving the performance of the host 100 by reducing overhead.
  • FIG. 2 is a block diagram illustrating a queue management operation of a host according to an exemplary embodiment of the inventive concept.
  • software of the host 100 which is loaded on the host memory 120 and is driven by the processing unit 110 may include, for example, application programs 121 and a kernel 122 of an operating system (OS).
  • the kernel 122 may include, for example, an input/output scheduler 126 and a device driver 128 .
  • a file system may be included in the kernel 122 of the operating system.
  • the application programs 121 may be driven as a basic service or may be software of an upper layer driven by a user.
  • a plurality of application programs App 0 to App 3 may be simultaneously driven to provide various services.
  • the application programs App 0 to App 3 to be executed may be loaded on the host memory 120 and may be executed by the processing unit 110 .
  • an application program e.g., a video player
  • the executed application program may issue a read request or a write request to the storage device to play the requested video file.
  • a command for a write request to the storage device 200 may be written at the submission queue 123 , and a tail pointer TP of the submission queue 123 may be updated.
  • the host 100 may output a tail doorbell to the storage device 200 , indicating to the storage device 200 that a new command is recorded at the submission queue 123 .
  • the storage device 200 may fetch a corresponding command from the submission queue 123 and may execute the fetched command.
  • the storage device 200 may write a completion entry at the completion queue 125 to indicate that a command most recently fetched from the host 100 is completed. At this time, a tail pointer TP of the completion queue 125 increases as the completion entry is written. Next, if an interrupt corresponding to a corresponding completion entry is received from the storage device 200 , the host 100 may perform an internal operation for completing the procedure for processing a command written at the submission queue 123 .
  • the device driver 128 may be, for example, a control module for controlling the storage device 200 at an OS level. If a memory access is requested by a user or from the application programs 121 , the device driver 128 may be called.
  • the device driver 128 may be implemented using, for example, a software module of the kernel for controlling the storage device 200 .
  • a command When a command is generated by an application program, a plurality of commands may be written at the submission queue 123 , and a completion entry corresponding to commands written in the submission queue 123 may be written in the completion queue 125 .
  • the host 100 may process completion entries written in the completion queue 125 based on interrupts. In a case in which the processing of completion entries accumulated in the completion queue 125 is delayed, an interrupt may frequently occur, which may cause overhead at the host 100 .
  • the storage device 200 may generate interrupts in a manner that reduces the number of events for which an interrupt is generated, as described further below, reducing overhead of the system.
  • FIG. 3 is a block diagram illustrating the storage controller 210 illustrated in FIG. 1 according to an exemplary embodiment of the inventive concept.
  • the storage controller 210 may include, for example, a central processing unit (CPU) 211 , a host interface 212 , a buffer manager 216 , and a flash interface 217 .
  • CPU central processing unit
  • the CPU 211 may provide a variety of information used to perform a read/write operation regarding the nonvolatile memory device(s) 230 , 240 . . . 250 to registers of the host interface 212 and the flash interface 217 .
  • the CPU 211 may operate based on firmware which is provided for various control operations of the storage controller 210 .
  • the CPU 211 may execute a flash translation layer (FTL) for garbage collection for managing the nonvolatile memory device(s) 230 , 240 . . . 250 , address managing, wear leveling, etc.
  • FTL flash translation layer
  • the host interface 212 may communicate with the host 100 .
  • the host interface 212 may include a first doorbell register 213 for writing a tail pointer doorbell of the submission queue 123 of the host 100 .
  • the host interface 212 may further include a second doorbell register 214 at which the host 100 writes that a head pointer HP of the completion queue 125 is updated and an update position.
  • the host interface 212 may further include an interrupt table 215 for managing interrupts to be generated according to a status of the second doorbell register 214 .
  • the host interface 212 may provide a physical connection between the host 100 and the storage device 200 .
  • the host interface 212 may interface with the storage device 200 in compliance with the bus format of the host 100 .
  • the bus format of the host 100 may include at least one of, for example, a universal serial bus (USB), a small computer system interface (SCSI), a PCI express, ATA, a parallel ATA (PTA), a serial ATA (SATA), or a serial attached SCSI (SAS).
  • USB universal serial bus
  • SCSI small computer system interface
  • PCI express PCI express
  • ATA ATA
  • PTA parallel ATA
  • SATA serial ATA
  • SAS serial attached SCSI
  • an NVMe protocol installed on the host 100 which exchanges data using a PCI express interface may be applied to the host interface 212 .
  • the buffer manager 216 may control read and write operations of the buffer memory 220 .
  • the buffer manager 216 may temporarily store write data or read data in the buffer memory 220 .
  • the buffer manager 216 may classify a memory area of the buffer memory by a stream unit under control of the CPU 211 .
  • the flash interface 217 may exchange data with the flash memory device (e.g., nonvolatile memory devices 230 , 240 . . . 250 ).
  • the flash interface 217 may write data from the buffer memory 220 at the flash memory device (e.g., nonvolatile memory devices 230 , 240 . . . 250 ) through memory channels CH 1 to CHn.
  • Read data which is read out from the flash memory device (e.g., nonvolatile memory devices 230 , 240 . . . 250 ), is provided through a memory channel and may be collected by the flash interface 217 .
  • the collected data may be stored in the buffer memory 220 .
  • the storage controller 210 may fetch a command written at the submission queue 123 of the host 100 in response to doorbell information written at the first doorbell register 213 by the host 100 . If the execution of the fetched command CMD is completed, the storage controller 210 may write a completion entry, indicating that the execution of a corresponding command is completed, at the completion queue 125 of the host 100 . In addition, the storage controller 210 may generate an interrupt for a corresponding completion entry with reference to a difference between a tail pointer TP and a head pointer HP of the completion queue 125 managed by the host 100 .
  • the storage controller 210 may generate an interrupt only when a first mismatch value between a tail pointer TP and a head pointer HP of the completion queue 125 occurs.
  • the storage device 210 may generate an interrupt at a time when the difference between the tail pointer TP and the head pointer HP of the completion queue CQ exceeds a threshold.
  • the storage device 210 may generate an interrupt for accumulated completion entries after a time elapses from a point in time when a first mismatch between the tail pointer TP and the head pointer HP of the completion queue 125 occurs.
  • FIG. 4 is a diagram illustrating an example of a method in which the storage controller 210 of FIG. 3 generates an interrupt for a host, according to an exemplary embodiment of the inventive concept.
  • a method for generating an interrupt corresponding to a plurality of completion queues 215 a and 215 b managed at the host 100 is illustrated in FIG. 4 .
  • the host 100 previously writes a command set at the submission queue (SQ) 123 .
  • SQ submission queue
  • the storage controller 210 may write a completion entry CQ 1 _ 1 at a first completion queue 215 a ( ⁇ circle around ( 1 ) ⁇ ). After executing another fetched command, the storage controller 210 may write a completion entry CQ 2 _ 1 at a second completion queue 215 b ( ⁇ circle around ( 2 ) ⁇ ). Next, the storage controller 210 may detect a difference between a head pointer and a tail pointer of a completion queue updated at the second doorbell register 214 .
  • the storage controller 210 may generate an interrupt Int 0 corresponding to the two completion entries CQ 1 _ 1 and CQ 2 _ 1 ( ⁇ circle around ( 4 ) ⁇ ). Accordingly, a single interrupt may allow the host 100 to process two completion entries CQ 1 _ 1 and CQ 2 _ 1 ( ⁇ circle around ( 5 ) ⁇ ).
  • the host 100 may update the second doorbell register 214 to inform, update, or release the head pointers for the completion queues 215 a and 215 b ( ⁇ circle around ( 6 ) ⁇ ).
  • an interrupt regarding a plurality of completion queues is provided using one interrupt vector.
  • exemplary embodiments are not limited thereto.
  • exemplary embodiments may utilize three or more completion queues.
  • FIG. 5 is a timing diagram illustrating an operating method of the storage device 200 according to an exemplary embodiment of the inventive concept.
  • the storage controller 210 writes a completion entry at the completion queue 125 of the host 100 .
  • An interrupt is generated at a point in time of a first mismatch between a tail pointer and a head pointer of a completion queue. This exemplary scenario will be described in more detail below.
  • the storage controller 210 when completing the execution of the command fetched from the host 100 , the storage controller 210 writes a completion entry C 0 at the completion queue 125 of the host 100 .
  • the tail pointer TP of the completion queue 125 increases to (N+1).
  • the completion queue 125 is not processed by the host 100 , and a head pointer HP of the completion queue 125 does not increase. For this reason, the head pointer HP is N at this time.
  • a point in time T 0 is determined to be a first mismatch point in time (e.g., a first point in time at which the value of the tail pointer TP and the value of the head pointer HP do not match).
  • the difference in values between the tail pointer TP and the head pointer HP that occurs at the first mismatch point in time may be referred to herein as a first mismatch value.
  • the storage controller 210 outputs an interrupt IR 0 to the host 100 .
  • the interrupt may be, for example, a pin-base signal or may be transferred in a message signaled interrupt (MSI) manner or an MSI-X manner.
  • MSI message signaled interrupt
  • the storage controller 210 When the execution of one fetched command is completed at time T 1 , the storage controller 210 writes a completion entry C 1 at the completion queue 125 of the host 100 .
  • the completion entry C 1 When the completion entry C 1 is written, the tail pointer TP of the completion queue 125 increases to (N+2). However, the completion queue 125 is not processed by the host 100 , and the head pointer HP of the completion queue 125 does not increase. For this reason, the head pointer HP is still N at this time. Accordingly, when a new completion entry C 1 is written at time T 1 , the difference between the tail pointer TP and the head pointer HP of the completion queue 125 is 2.
  • An interrupt is not generated because the difference between the tail pointer TP and the head pointer HP is not equal to the first mismatch value (e.g., is not equal to 1), and in this exemplary embodiment, interrupts are generated only when the difference between the tail pointer TP and the head pointer HP is equal to the first mismatch value (e.g., equal to 1 in this exemplary scenario).
  • the storage controller 210 When the execution of one fetched command is completed at time T 2 , the storage controller 210 writes a completion entry C 2 at the completion queue 125 of the host 100 .
  • the completion entry C 2 When the completion entry C 2 is written, the tail pointer TP of the completion queue 125 increases to (N+3). However, the completion queue 125 is not processed by the host 100 , and the head pointer HP of the completion queue 125 does not increase. Accordingly, when the new completion entry C 2 is written at time T 2 , the difference between the tail pointer TP and the head pointer HP of the completion queue 125 is 3. An interrupt is not generated because the difference between the tail pointer TP and the head pointer HP is not equal to the first mismatch value (e.g., is not equal to 1).
  • the storage controller 210 When the execution of one fetched command is completed at time T 3 , the storage controller 210 writes a completion entry C 3 at the completion queue 125 of the host 100 .
  • the completion entry C 3 When the completion entry C 3 is written, the tail pointer TP of the completion queue 125 increases to (N+4).
  • the head pointer HP of the completion queue 125 is maintained at N, and the difference between the tail pointer TP and the head pointer HP is 4.
  • An interrupt is not generated because the difference between the tail pointer TP and the head pointer HP is not equal to the mismatch value (e.g., is not equal to 1).
  • the tail pointer TP of the completion queue 125 increases to (N+5), and the completion queue 125 is processed by the host 100 . Accordingly, the head pointer HP increases to N+4, and the difference between the tail pointer TP and the head pointer HP is reset to 0 before time T 4 .
  • the storage controller 210 When the execution of one fetched command is completed at time T 4 , the storage controller 210 writes a completion entry C 4 at the completion queue 125 of the host 100 .
  • the completion entry C 4 When the completion entry C 4 is written, the tail pointer TP of the completion queue 125 increases to (N+5).
  • the head pointer HP of the completion queue 125 is maintained at (N+4). Accordingly, when the new completion entry C 4 is written at time T 4 , the difference between the tail pointer TP and the head pointer HP of the completion queue 125 is equal to the first mismatch value (e.g., is equal to 1). In this case, since the difference between the tail pointer TP and the head pointer HP corresponds to the first mismatch value, the storage controller 210 issues an interrupt IR 1 .
  • the generation of the interrupt may be controlled under the same condition.
  • an interrupt is generated only when the difference between the tail pointer TP and the head pointer HP corresponds to the first mismatch value, thereby reducing a decrease in the performance of the host 100 due to interrupt generation.
  • FIG. 6 is a flow chart illustrating an operating method of the storage controller 210 according to an exemplary embodiment of the inventive concept.
  • the storage device 210 generates an interrupt only at time at which the difference between the tail pointer TP and the head pointer HP of the completion queue CQ is equal to a first mismatch value.
  • the storage controller 210 detects the difference (TP ⁇ HP) between the tail pointer TP and the head pointer HP with reference to a head pointer doorbell of a completion queue transferred from the host 100 .
  • the tail pointer may be previously written by the storage controller 210 at the host 100 . Accordingly, a position of the tail pointer TP may be information which the storage controller 210 has recognized.
  • the storage controller 210 which writes the completion queue 125 , may only depend on doorbell information provided by the host 100 to obtain a position of the head pointer HP of the completion queue 125 .
  • the storage controller 210 may detect the difference between the tail pointer TP and the head pointer HP with reference to a position of the head pointer HP provided by the host 100 which consumes the completion queue 125 .
  • the storage device 210 detects whether the difference between the tail pointer TP and the head pointer HP of the completion queue 125 is 0. If the difference between the tail pointer TP and the head pointer HP of the completion queue 125 is 0, the storage controller 210 does not generate an interrupt, and the procedure returns to operation S 110 . If the difference between the tail pointer TP and the head pointer HP of the completion queue 125 is not 0, the procedure proceeds to operation S 130 .
  • the storage device 210 detects whether the difference between the tail pointer TP and the head pointer HP of the completion queue 125 is 1. If the difference between the tail pointer TP and the head pointer HP of the completion queue 125 is not 1, the storage controller 210 does not generate an interrupt and the procedure returns to operation S 110 . If the difference between the tail pointer TP and the head pointer HP of the completion queue 125 is 1, the procedure proceeds to operation S 140 .
  • a difference between the tail pointer TP and the head pointer HP of the completion queue 125 is not 1 may mean that the number of completion queues not processed is 2 or more.
  • the storage device 210 outputs an interrupt to the host 100 .
  • the interrupt may be, for example, a pin-base signal or may be transferred in a message signaled interrupt (MSI) manner or an MSI-X manner.
  • MSI message signaled interrupt
  • an interrupt is issued to the host 100 only when the difference between the tail pointer TP and the head pointer HP of the completion queue 125 is 1 (e.g., an interrupt is generated only when the difference between the tail pointer TP and the head pointer HP is equal to the first mismatch value).
  • exemplary embodiments of the inventive concept are not limited to the mismatch value being equal to 1.
  • an interrupt may be generated only when the difference between the tail pointer TP and the head pointer HP of the completion queue 125 is equal to a different mismatch value (e.g., 2, 3, etc.), or an interrupt may be generated only at when an aggregation count is equal to an aggregation threshold, as described further below.
  • the above-described interrupt generation method may reduce overhead of the host 100 due to the processing of accumulated interrupts (e.g., less interrupts may be utilized).
  • FIG. 7 is a diagram illustrating a call process procedure of a host and a storage device according to the interrupt generation method of FIG. 5 .
  • the procedure begins as the storage device 200 writes a completion entry at the completion queue 125 after processing a command fetched from the host 100 .
  • the storage device 200 completes the execution of a fetched command and indicates this state by writing a completion entry at the completion queue 125 of the host 100 .
  • a tail pointer TP of the completion queue 125 which is implemented with a ring buffer of the host 100 , increases.
  • the host 100 informs the storage device 100 of the most recent head pointer HP of the completion queue 125 .
  • the procedure for providing the most recent head pointer HP of the completion queue 125 may be omitted.
  • the most recent head pointer HP of the completion queue 125 is provided before a completion entry is written by the storage device 200 .
  • the storage device 200 detects the difference between the tail pointer TP and the head pointer HP of the completion queue 125 with reference to information of the tail pointer TP and the head pointer HP, and an interrupt is generated only when the difference between the tail pointer TP and the head pointer HP is 1 (e.g., is equal to the first mismatch value in the exemplary scenario of FIG. 5 ).
  • FIG. 8 is a timing diagram illustrating an operating method of the storage device 200 according to an exemplary embodiment of the inventive concept.
  • the storage controller 210 writes completion entries C 0 , C 1 , C 2 , etc. at the completion queue 125 of the host 100 .
  • an interrupt is generated only when the accumulated difference between the tail pointer TP and the head pointer HP of the completion queue 125 reaches an aggregation threshold.
  • an aggregation threshold is set, and interrupts are generated only when the difference between the tail pointer TP and the head pointer HP of the completion queue 125 is equal to the aggregation threshold.
  • an interval at which a completion entry is written may vary according to a status or performance of the storage device 200 , the type of a fetched command, etc., as described in further detail below.
  • FIG. 8 shows an aggregation count, which is described below as being equal to (TH ⁇ (TP ⁇ HP)) with reference to FIG. 9 .
  • the point in time T 0 is determined to be a first mismatch point in time.
  • the storage controller 210 waits without generating an interrupt at that time.
  • the storage controller 210 is set such that an interrupt is generated only at a point in time when the difference between the tail pointer TP and the head pointer HP of the completion queue 125 is equal to the aggregation threshold value (e.g., equal to 4). This point in time also correspond to the aggregation count being equal to 0.
  • the difference between the tail pointer TP and the head pointer HP is set to 1, and thus, the aggregation count is 4.
  • the storage controller 210 When the execution of one fetched command is completed at time T 1 , the storage controller 210 writes a completion entry C 1 at the completion queue 125 of the host 100 .
  • the completion entry C 1 When the completion entry C 1 is written, the tail pointer TP of the completion queue 125 increases. Since it is detected that the difference between the tail pointer TP and the head pointer HP of the completion queue 125 is 1 at time T 1 , the point in time T 1 is determined to be equal to the first mismatch value (e.g., equal to 1). However, in this exemplary embodiment, the storage controller 210 waits without generating an interrupt even at that time.
  • the storage controller 210 is set such that an interrupt is generated only at a point in time when the difference between the tail pointer TP and the head pointer HP of the completion queue 125 is equal to the aggregation threshold value (e.g., is equal to 4). This point in time also corresponds to the aggregation count being equal to 0. Afterwards, since a head pointer doorbell of the completion queue 125 from the host 100 is written, the difference between the tail pointer TP and the head pointer HP is set to 0, and thus, the aggregation count is 4.
  • the aggregation threshold value e.g., is equal to 4.
  • the storage controller 210 When the execution of one fetched command is completed at time T 2 , the storage controller 210 writes a completion entry C 2 at the completion queue 125 of the host 100 . When the completion entry C 2 is written, the tail pointer TP of the completion queue 125 increases. At time T 2 , it is detected that the difference between the tail pointer TP and the head pointer HP of the completion queue 125 is 1, and an aggregation count of 3 is detected. However, in an exemplary embodiment, the storage controller 210 waits without generating an interrupt even at that time.
  • the storage controller 210 When the execution of one fetched command is completed, at time T 3 , the storage controller 210 writes a completion entry C 3 at the completion queue 125 of the host 100 .
  • the completion entry C 3 When the completion entry C 3 is written, it is detected that the difference between the tail pointer TP and the head pointer HP of the completion queue 125 is 2, and an aggregation count of 2 is detected. Accordingly, the storage controller 210 waits without generating an interrupt even at that time.
  • the storage controller 210 When the execution of one fetched command is completed, at time T 4 , the storage controller 210 writes a completion entry C 4 at the completion queue 125 of the host 100 .
  • the completion entry C 4 When the completion entry C 4 is written, it is detected that the difference between the tail pointer TP and the head pointer HP of the completion queue 125 is 3, and an aggregation count of 1 is detected. Accordingly, the storage controller 210 waits without generating an interrupt even at that time.
  • the storage controller 210 When the execution of one fetched command is completed, at time T 5 , the storage controller 210 writes a completion entry C 5 at the completion queue 125 of the host 100 .
  • the completion entry C 5 When the completion entry C 5 is written, it is detected that the difference between the tail pointer TP and the head pointer HP of the completion queue 125 is equal to 4 (e.g., is equal to the aggregation threshold), and an aggregation count of 0 is detected. Since the difference between the tail pointer TP and the head pointer HP is equal to the aggregation threshold, and since the aggregation count regarding the tail pointer TP and the head pointer HP reaches 0, the storage controller 210 generates an interrupt IR 0 corresponding to a plurality of completion entries accumulated at the host 100 .
  • the storage device 210 generates an interrupt only when the difference between a tail pointer TP and a head pointer HP of the completion queue CQ reaches an aggregation threshold. That is, an interrupt is generated only at a specific aggregation count (e.g., an aggregation count equal to 0). Accordingly, in exemplary embodiments of the inventive concept, a decrease in the performance of the host due to interrupt aggregation may be reduced.
  • FIG. 9 is a flow chart illustrating an interrupt generation method of the storage controller 210 according to the exemplary embodiment of the inventive concept described with reference to FIG. 8 .
  • the storage controller 210 issues an interrupt based on the number completion entries accumulated at the completion queue 125 .
  • the storage controller 210 detects the difference (TP ⁇ HP) between the tail pointer TP and the head pointer HP with reference to a head pointer doorbell of a completion queue 125 transferred from the host 100 .
  • the storage controller 210 may calculate the difference (TP ⁇ HP) between the tail pointer TP and the head pointer HP of the completion queue 125 with reference to doorbell information which the host 100 provides.
  • the storage controller 210 determines the number of entries accumulated at the completion queue 125 .
  • the storage controller 210 may determine whether the difference between the tail pointer TP and the head pointer HP reaches an aggregation threshold.
  • an aggregation count may be utilized as a parameter for determining whether the number of accumulated entries reaches an aggregation count. That is, the aggregation count is a parameter indicating whether the number of entries accumulated at the completion queue 125 reaches an aggregation count.
  • the aggregation count may correspond to a value obtained by subtracting a difference (TP ⁇ HP) between the tail pointer TP and the head pointer HP from the threshold TH. That is, the aggregation count may be calculated by (TH ⁇ (TP ⁇ HP)).
  • the manner of determining whether the number of entries accumulated at the completion queue 125 reaches an aggregation count is not limited thereto.
  • the storage controller 210 determines whether the aggregation count is 0. Determining that the aggregation count is 0 refers to the number of entries accumulated at the completion queue 125 reaching the threshold TH. When the aggregation count is not 0, the procedure returns to operation S 210 . When the aggregation count is 0, the procedure proceeds to operation S 240 .
  • an interrupt vector may be transferred with a value corresponding to a plurality of completion entries.
  • the interrupt may be, for example, a pin-base signal, or may be transferred in a message signaled interrupt (MSI) manner or an MSI-X manner.
  • MSI message signaled interrupt
  • whether to generate an interrupt is determined based on whether the difference between the tail pointer TP and the head pointer HP of the completion queue 125 reaches the threshold TH. That is, in the exemplary embodiment described above, an interrupt is generated only when the difference between the tail pointer TP and the head pointer HP of the completion queue 125 reaches the threshold TH. As a result, according to exemplary embodiments of the inventive concept, the number of interrupts generated and provided to the host 100 may be reduced.
  • FIG. 10 is a diagram illustrating a call process procedure of a host and a storage device according to the interrupt generation method of FIG. 9 .
  • the procedure begins as the storage device 200 writes a completion entry at the completion queue 125 after processing a command fetched from the host 100 .
  • the storage device 200 completes the execution of a fetched command and indicates this state by writing a completion entry at the completion queue 125 of the host 100 .
  • a tail pointer TP of the completion queue 125 increases.
  • the host 100 informs the storage device 100 of the most recent head pointer HP of the completion queue 125 .
  • the procedure for providing the most recent head pointer HP of the completion queue 125 may be omitted.
  • the most recent head pointer HP of the completion queue 125 is provided before a completion entry is written by the storage device 200 .
  • the storage controller 210 calculates an aggregation count of the completion queue 125 with reference to head pointer information of the completion queue 125 , which is provided by the host 100 . That is, it may be determined whether the number of entries not released at the completion queue 125 reaches the threshold TH. In an exemplary embodiment, the aggregation count may be used as a parameter for such a determination. For example, the storage controller 210 may determine the aggregation count is 0, which indicates that the number of accumulated completion entries reaches the threshold TH. When the aggregation count is not 0, the storage controller 210 does not generate an interrupt. In contrast, when the aggregation count is 0, the storage controller 210 issues an interrupt vector associated with a plurality of completion entries accumulated.
  • FIG. 11 is a timing diagram illustrating an exemplary embodiment of an interrupt generation method.
  • the storage controller 210 after executing a command fetched from the host 100 , the storage controller 210 writes completion entries C 0 , C 1 , C 2 , etc. at the completion queue 125 of the host 100 .
  • the storage device 210 issues an interrupt when either a first mismatch between a tail pointer TP and a head pointer HP of the completion queue 125 occurs, as described with reference to FIGS. 5 to 8 , or at a point in time when the number of completion entries accumulated at the completion queue reaches the threshold TH, as described with reference to FIGS. 8 to 10 .
  • the storage controller 210 When the execution of the command fetched from the host 100 is completed, at time T 0 , the storage controller 210 writes a completion entry C 0 at the completion queue 125 of the host 100 .
  • interrupts IR 0 and IR 1 may be issued according to either an aggregation count condition or a condition corresponding to a first mismatch between pointers.
  • the storage controller 210 When the execution of the command fetched from the host 100 is completed, at time T 3 , the storage controller 210 writes a completion entry C 3 at the completion queue 125 of the host 100 .
  • the storage controller 210 determines whether to issue an interrupt corresponding to the completion entry C 3 . For example, whether aggregation counts reach the threshold TH may be respectively determined. Since the difference between the tail pointer TP and the head pointer HP is 2, it is determined that a first mismatch between pointers does not occur. In addition, a value of the aggregation count is calculated to be 2. Accordingly, it is determined that a first mismatch between pointers and an aggregation count condition are not satisfied. For this reason, the storage controller 210 waits without generating an interrupt corresponding to the completion entry C 3 .
  • the storage controller 210 When the execution of the command fetched from the host 100 is completed, at time T 5 , the storage controller 210 writes a completion entry C 5 at the completion queue 125 of the host 100 .
  • the storage controller 210 determines whether to issue an interrupt corresponding to the completion entry C 5 .
  • the storage controller 210 may respectively determine whether a first mismatch between the tail pointer TP and the head pointer HP occurs, and whether aggregation counts reach the threshold TH. Since the difference between the tail pointer TP and the head pointer HP is 4, it does not correspond to a first mismatch condition. However, a value of the aggregation count is calculated to be 0. Accordingly, the storage controller 210 issues an interrupt IR 3 based on the aggregation count condition.
  • FIG. 12 is a flow chart illustrating an interrupt generation method of the storage controller 210 for performing the exemplary embodiment of the inventive concept described with reference to FIG. 11 .
  • the storage controller 210 issues an interrupt based on the number of completion entries accumulated at the completion queue 125 and based on a first mismatch between pointers (e.g., an interrupt is generated when either of these conditions occur).
  • the storage controller 210 detects a difference (TP ⁇ HP) between the tail pointer TP and the head pointer HP with reference to a head pointer doorbell of the completion queue 125 transferred from the host 100 .
  • the storage controller 210 calculates the difference (TP ⁇ HP) between the tail pointer TP and the head pointer HP of the completion queue 125 with reference to doorbell information, which is provided by the host 100 .
  • the storage controller 210 calculates the number of entries accumulated at the completion queue 125 . For example, in an exemplary embodiment, the storage controller 210 may determine whether the difference between the tail pointer TP and the head pointer HP reaches the threshold. In an exemplary embodiment, the storage controller 210 calculates an aggregation count, which is a value obtained by subtracting the difference (TP ⁇ HP) between the tail pointer TP and the head pointer HP from the threshold TH.
  • the storage controller 210 determines whether the aggregation count is 0. It is determined that the aggregation count is 0 when the number of entries accumulated at the completion queue 125 reaches the threshold TH. When the aggregation count is not 0, the procedure returns to operation S 310 . When the aggregation count is 0, the procedure proceeds to operation S 350 .
  • an interrupt vector may be transferred with a value corresponding to one completion entry or a plurality of completion entries.
  • whether to generate an interrupt is determined based on whether a first mismatch between pointers of the completion queue 125 occurs and whether the number of entries accumulated reaches a threshold (e.g., it is determined to generate an interrupt when either of these conditions occur).
  • FIG. 13 is a diagram illustrating a call process procedure of a host and a storage device according to the interrupt generation method of FIG. 11 .
  • the procedure begins as the storage device 200 writes a completion entry at the completion queue 125 after processing a command fetched from the host 100 .
  • the storage device 200 completes the execution of a fetched command and indicates this state by writing a completion entry at the completion queue 125 of the host 100 .
  • a tail pointer TP of the completion queue 125 of the host 100 increases.
  • the host 100 informs the storage device 100 of the most recent head pointer HP of the completion queue 125 .
  • the procedure for providing the most recent head pointer HP of the completion queue 125 may be omitted.
  • the most recent head pointer HP of the completion queue 125 is provided before a completion entry is written by the storage device 200 .
  • the storage controller 210 detects a difference (TP ⁇ HP) between the tail pointer TP and the head pointer 1 -IP of the completion queue 125 with reference to head pointer information of the completion queue 125 transferred from the host 100 .
  • the storage controller 210 calculates an aggregation count, which is a value obtained by subtracting the difference (TP ⁇ HP) between the tail pointer TP and the head pointer HP from the threshold TH.
  • the difference (TP ⁇ HP) between pointers is 1, the storage controller 210 issues an interrupt regardless of an aggregation count value.
  • the difference (TP ⁇ HP) between pointers is not 1, it is determined whether the aggregation count reaches the threshold TH.
  • the storage controller 210 issues an interrupt, and when the difference (TP ⁇ HP) between pointers is not 0, the storage controller 210 does not issue an interrupt.
  • FIG. 14 is a timing diagram illustrating an interrupt generation method according to an exemplary embodiment of the inventive concept.
  • the storage controller 210 writes completion entries C 0 , C 1 , C 2 , etc. at the completion queue 125 of the host 100 .
  • the storage device 210 generates an interrupt when a first mismatch between a tail pointer TP and a head pointer HP of the completion queue 125 occurs (see FIGS. 5 to 7 ), or when a reference elapsed time Tout elapses after the issuing of a previous interrupt.
  • an interval when a completion entry is written may vary according to, for example, a status or performance of the storage device 200 , a type of a fetched command, etc.
  • the reference elapsed time Tout may be determined in light of a status of performance of the host 100 or a status or performance of the storage device 200 .
  • the storage controller 210 When the execution of the command fetched from the host 100 is completed, at time T 0 , the storage controller 210 writes a completion entry C 0 at the completion queue 125 of the host 100 .
  • the storage controller 210 determines whether to issue an interrupt corresponding to the completion entry C 0 based on criteria of exemplary embodiments of the inventive concept, as described above. Since it is detected that the difference between the tail pointer TP and the head pointer HP of the completion queue 125 is 1 at time T 0 , the point in time T 0 is determined to be a first mismatch point in time. Accordingly, an interrupt IR 0 is issued regardless of an elapsed time.
  • a completion entry C 1 is written in the completion queue 125 of the host 100 , and the storage controller 210 monitors the completion queue 125 to determine whether a first mismatch between pointers of the completion entry 125 occurs, and it is determined whether the reference elapsed time Tout elapses after issuing the interrupt. Since it is detected that the difference between the tail pointer TP and the head pointer HP of the completion queue 125 is 1, the detection point in time is determined to be a first mismatch point in time (e.g., the difference is equal to the first mismatch value). In addition, a first mismatch point in time is determined to be a point in time when a time ⁇ T 1 elapses after the interrupt IR 0 is issued.
  • the storage controller 210 monitors the completion queue 125 to determine whether a first mismatch between pointers of the completion entry occurs, and it is determined whether the reference elapsed time Tout elapses.
  • the difference between the tail pointer TP and the head pointer HP is 2. That is, the difference between pointers does not satisfy an interrupt issuing condition.
  • the interrupt issuing condition is not satisfied. Accordingly, the issuing of the interrupt is postponed at that time.
  • a point in time T 5 corresponds to a time ⁇ T 3 (which is longer than Tout) elapsing after the interrupt IR 2 is issued. Accordingly, the storage controller 210 issues an interrupt IR 3 .
  • a determination of whether to issue an interrupt is made based on the amount of time elapsing after an interrupt is issued, and whether the difference between pointers of the completion queue 125 corresponds to a first mismatch (e.g., an interrupt is generated when either of these interrupt generation conditions are satisfied).
  • FIG. 15 is a timing diagram illustrating an interrupt generation method according to an exemplary embodiment of the inventive concept.
  • the storage controller 210 issues an interrupt based on at least one of determining whether a first mismatch between pointers of the completion queue 125 occurs (see FIGS. 5 to 7 ), an aggregation count (see FIGS. 8 to 10 ), and a time elapsing after the issuing of an interrupt (see FIG. 14 ).
  • the time elapsing after the issuing of an interrupt is Tout.
  • the storage controller 210 writes a completion entry C 0 at the completion queue 125 .
  • the storage controller 210 determines whether to issue an interrupt corresponding to the completion entry C 0 based on criteria of exemplary embodiments of the inventive concept described herein. Since it is detected that the difference between the tail pointer TP and the head pointer HP of the completion queue 125 is 1 at time T 0 , the point in time T 0 is determined to be a first mismatch point in time. Accordingly, an interrupt IR 0 is issued at that time regardless of an elapsed time or an aggregation count. At times T 1 and T 2 , interrupts IR 1 and IR 2 are respectively issued for the same reason as at time T 0 .
  • the point in time T 1 is a first mismatch point in time because an elapsed time ⁇ T 1 is shorter than Tout, and a value corresponding to the difference between the tail pointer TP and the head pointer HP transitions from 0 to 1.
  • the point in time T 2 is the first mismatch point in time because an elapsed time ⁇ T 2 is shorter than Tout, and a value corresponding to the difference between the tail pointer TP and the head pointer HP transitions from 0 to 1.
  • a point in time T 3 does not satisfy an elapsed time condition because a time elapsing after the issuing of the interrupt IR 2 is shorter than Tout. Further, the point in time T 3 does not satisfy an interrupt generation condition because the aggregation count is 2. Accordingly, at time T 3 , the storage controller 210 does not issue an interrupt.
  • the storage controller 210 issues an interrupt IR 3 at time T 4 .
  • an interrupt IR 4 is issued.
  • an interrupt IR 5 is issued because the difference between pointers satisfies a first mismatch condition.
  • an interrupt IR 6 is issued because the difference between pointers satisfies the first mismatch condition of the three interrupt generation conditions.
  • an interrupt is issued based on the following interrupt generation conditions: whether a difference between pointers of the completion queue 125 corresponds to a first mismatch (see FIGS. 5 to 8 ), an aggregation threshold/aggregation count (see FIGS. 8-10 ), and a time elapsing after an interrupt is issued (see FIG. 14 ).
  • interrupts are issued in response to at least one of these three interrupt generation conditions occurring.
  • additional interrupt generation conditions may be included.
  • an interrupt may be issued only when at least two or more certain interrupt conditions are satisfied, or when all possible interrupt conditions are satisfied.
  • FIG. 16 is a block diagram illustrating a nonvolatile memory described with reference to FIG. 1 according to an exemplary embodiment of the inventive concept.
  • a nonvolatile memory e.g., nonvolatile memory 230 , 240 . . . 250
  • a nonvolatile memory device 230 , 240 . . . 250 may include a memory cell array 231 , an address decoder 232 , a control logic and voltage generating circuit 235 , a page buffer 233 , and an input/output (I/O) circuit 234 .
  • I/O input/output
  • the memory cell array 231 may include a plurality of memory blocks. Each of the memory blocks may include a plurality of cell strings, and each of the cell strings may include a plurality of memory cells. The memory cells may be connected with a plurality of word lines WL. Each memory cell may be, for example, a single level cell (SLC) storing one bit or a multi-level cell (MLC) storing at least two bits.
  • SLC single level cell
  • MLC multi-level cell
  • the address decoder 232 may be connected with the memory cell array 231 through the word lines WL, string selection lines SSL, and ground selection lines GSL.
  • the address decoder 232 may receive and decode a physical address ADD from an external device (e.g., the processing unit 110 ) and may drive the word lines based on the decoding result.
  • the address decoder 232 may decode a physical address ADD received from the external device, may select at least one of the word lines based on the decoded physical address ADD, and may drive the selected word line.
  • the control logic and voltage generating circuit 235 may control the address decoder 232 , the page buffer 233 , and the input/output circuit 234 in response to a storage command CMD and a control signal CTRL from the external device.
  • the control logic and voltage generating circuit 235 may control other components in response to the signals CMD and CTRL such that data is stored in the memory cell array 231 , or such that data stored in the memory cell array 231 is transmitted to the external device.
  • the page buffer 233 may be connected to the memory cell array 231 through bit lines BL. Under control of the control logic and voltage generating circuit 235 , the page buffer 233 may control the bit lines BL such that data provided from the input/output circuit 234 is stored in the memory cell array 231 . Under control of the control logic and voltage generating circuit 235 , the page buffer 233 may read data stored in the memory cell array 231 and may provide the read data to the input/output circuit 234 . For example, the page buffer 233 may be provided with data from the input/output circuit 234 by the page or may read data from the memory cell array 231 by the page.
  • the input/output circuit 234 may receive data from the external device and may transfer the received data to the page buffer 233 .
  • the input/output circuit 234 may receive data from the page buffer 233 and may transmit the received data to the external device.
  • the input/output circuit 234 may exchange data with the external device in synchronization with the control signal CTRL.
  • the control logic and voltage generating circuit 235 may generate various voltages used by the nonvolatile memory 230 to operate. For example, the control logic and voltage generating circuit 235 may generate a plurality of program voltages, a plurality of pass voltages, a plurality of verification voltages, a plurality of selection read voltages, a plurality of non-selection read voltages, a plurality of erase voltages, etc. The control logic and voltage generating circuit 235 may provide the generated voltages to the address decoder 232 or to a substrate of the memory cell array 231 .
  • FIG. 17 is a circuit diagram illustrating a first memory block of memory blocks included in a memory cell array of FIG. 16 according to an exemplary embodiment of the inventive concept.
  • a first memory block BLK 1 having a three-dimensional structure according to an exemplary embodiment will be described with reference to FIG. 17 .
  • exemplary embodiments of the inventive concept are not limited thereto.
  • other types of memory blocks respectively included in the nonvolatile memory device 230 , 240 . . . 250 may have a similar structure to that of the first memory block BLK 1 .
  • the first memory block BLK 1 may include a plurality of cell strings CS 11 , CS 12 , CS 21 , and CS 22 .
  • the cell strings CS 11 , CS 12 , CS 21 , and CS 22 may be arranged along a row direction, and a column direction and may form rows and columns.
  • the cell strings CS 1 and CS 12 may be connected to string selection lines SSL 1 a and SSL 1 b to form a first row.
  • the cell strings CS 21 and CS 22 may be connected to string selection lines SSL 2 a and SSL 2 b to form a second row.
  • the cell strings CS 11 and CS 21 may be connected to a first bit line BL 1 to form a first column.
  • the cell strings CS 12 and CS 22 may be connected to a second bit line BL 2 to form a second column.
  • Each of the cell strings CS 11 , CS 12 , CS 21 , and CS 22 may include a plurality of cell transistors.
  • Each of the cell strings CS 11 , CS 12 , CS 21 , and CS 22 may include string selection transistors SSTa and SSTb, a plurality of memory cells MC 1 to MC 8 , ground selection transistors GSTa and GSTb, and dummy memory cells DMC 1 and DMC 2 .
  • each of the memory cells included in the cell strings CS 11 , CS 12 , CS 21 , and CS 22 may be, for example, a charge trap flash (CTF) memory cell.
  • CTF charge trap flash
  • the memory cells MC 1 to MC 8 may be serially connected and may be stacked in a height direction, which is a direction substantially perpendicular to a plane defined by a row direction and a column direction.
  • the string selection transistors SSTa and SSTb may be serially connected and may be disposed between the memory cells MC 1 to MC 8 and a bit line BL.
  • the ground selection transistors GSTa and GSTb may be serially connected and may be disposed between the memory cells MC 1 to MC 8 and a common source line CSL.
  • the first dummy memory cell DMC 1 may be disposed between the memory cells MC 1 to MC 8 and the ground selection transistors GSTa and GSTb.
  • the second dummy memory cell DMC 2 may be disposed between the memory cells MC 1 to MC 8 and the string selection transistors SSTa and SSTb.
  • ground selection transistors GSTa and GSTb of the cell strings CS 11 , CS 12 , CS 21 , and CS 22 may be connected in common to a ground selection line GSL.
  • ground selection transistors in the same row may be connected to the same ground selection line, and ground selection transistors in different rows may be connected to different ground selection lines.
  • the first ground selection transistors GSTa of the cell strings CS 11 and CS 12 in the first row may be connected to the first ground selection line
  • the first ground selection transistors GSTa of the cell strings CS 21 and CS 22 in the second row may be connected to the second ground selection line.
  • ground selection transistors at substantially the same height from a substrate may be connected to the same ground selection line, and ground selection transistors at different heights therefrom may be connected to different ground selection lines.
  • the first ground selection transistors GSTa of the cell strings CS 11 , CS 12 , CS 21 , and CS 22 may be connected to the first ground selection line
  • the second ground selection transistors GSTb thereof may be connected to the second ground selection line.
  • Memory cells placed at substantially the same height from the substrate may be connected in common to the same word line, and memory cells placed at different heights therefrom may be connected to different word lines.
  • memory cells MC 1 to MC 8 of the cell strings CS 11 , CS 12 , CS 21 , and CS 22 may be connected in common to first to eighth word lines WL 1 to WL 8 .
  • String selection transistors belonging to the same row from among the first string selection transistors SSTa placed at substantially the same height may be connected to the same string selection line, and string selection transistors belonging to different rows may be connected to different string selection lines.
  • the first string selection transistors SSTa of the cell strings CS 11 and CS 12 in the first row may be connected in common to the string selection line SSL 1 a
  • the first string selection transistors SSTa of the cell strings CS 21 and CS 22 in the second row may be connected in common to the string selection line SSL 1 a.
  • String selection transistors belonging to the same row from among the second string selection transistors SSTb at substantially the same height may be connected to the same string selection line, and string selection transistors belonging to different rows may be connected to different string selection lines.
  • the second string selection transistors SSTb of the cell strings CS 11 and CS 12 in the first row may be connected in common to the string selection line SSL b
  • the second string selection transistors SSTb of the cell strings CS 21 and CS 22 in the second row may be connected in common to the string selection line SSL 2 b.
  • String selection transistors of cell strings in the same row may be connected in common to the same string selection line.
  • the first and second string selection transistors SSTa and SSTb of the cell strings CS 11 and CS 12 in the first row may be connected in common to the same string selection line.
  • the first and second string selection transistors SSTa and SSTb of the cell strings CS 21 and CS 22 in the second row may be connected in common to the same string selection line.
  • dummy memory cells at substantially the same height may be connected with the same dummy word line, and dummy memory cells at different heights may be connected with different dummy word lines.
  • the first dummy memory cells DMC 1 may be connected to a first dummy word line DWL 1
  • the second dummy memory cells DMC 2 may be connected to a second dummy word line DWL 2 .
  • read and write operations may be performed by the row.
  • one row of the memory block BLK 1 may be selected by the string selection lines SSL 1 a , SSL 1 b , SSL 2 a , and SSL 2 b.
  • the cell strings CS 11 and CS 12 in the first row may be respectively connected to the bit lines BL 1 and BL 2 when a turn-on voltage is supplied to the string selection lines SSL 1 a and SSL 1 b and a turn-off voltage is supplied to the string selection lines SSL 2 a and SSL 2 b .
  • the cell strings CS 21 and CS 22 in the second row may be respectively connected to the bit lines BL 1 and BL 2 when the turn-on voltage is supplied to the string selection lines SSL 2 a and SSL 2 b and the turn-off voltage is supplied to the string selection lines SSL 1 a and SSL 1 b .
  • As a word line is driven memory cells placed at substantially the same height from among memory cells in cell strings connected to the driven word line may be selected. Read and write operations may be performed with respect to the selected memory cells. The selected memory cells may form a physical page.
  • memory cells may be erased by the memory block or by the sub-block.
  • all memory cells MC in the memory block BLK 1 may be simultaneously erased according to an erase request.
  • a portion of memory cells MC in the memory block BLK 1 may be simultaneously erased according to an erase request, and the others thereof may be erase-inhibited.
  • a low voltage e.g., a ground voltage
  • the first memory block BLK 1 illustrated in FIG. 17 is exemplary.
  • the number of cell strings may increase or decrease, and the number of rows of cell strings and the number of columns of cell strings may increase or decrease according to the number of cell strings.
  • the number of cell strings (GST, MC, DMC, SST, etc.) may increase or decrease, and a height of the first memory block BLK 1 may increase or decrease according to the number of cell strings (GST, MC, DMC, SST, etc.).
  • the number of lines (GSL, WL, DWL, SSL, etc.) connected with cell transistors may increase or decrease according to the number of cell strings (GST, MC, DMC, SST, etc.).
  • FIG. 18 is a block diagram illustrating a memory card system including a nonvolatile memory system according to an exemplary embodiment of the inventive concept.
  • a memory card system 1000 may include a memory controller 1100 , a nonvolatile memory 1200 , and a connector 1300 .
  • the memory controller 1100 may be connected to the nonvolatile memory 1200 .
  • the memory controller 1100 may be configured to access the nonvolatile memory 1200 .
  • the memory controller 1100 may be adapted to control an overall operation of the nonvolatile memory 1200 including, but not limited to, a read operation, a write operation, an erase operation, and a background operation.
  • the background operation may include, but is not limited to, wear-leveling management, garbage collection, etc.
  • the memory controller 1100 may generate an interrupt based on a method described above with reference to FIGS. 1 to 15 .
  • the memory controller 1100 may provide an interface between the nonvolatile memory 1200 and a host.
  • the memory controller 1100 may be configured to drive firmware for controlling the nonvolatile memory 1200 .
  • the memory controller 1100 may include components such as, but not limited to, a RAM, a processing unit, a host interface, a memory interface, and an error correction unit.
  • the memory controller 1100 may communicate with an external device through the connector 1300 .
  • the memory controller 1100 may communicate with an external device based on a specific communication protocol.
  • the memory controller 1100 may communicate with the external device through at least one of various communication protocols such as, but not limited to, universal serial bus (USB), multimedia card (MMC), eMMC (embedded MMC), peripheral component interconnection (PCI), PCI-express (PCI-E), advanced technology attachment (ATA), a serial-ATA, parallel-ATA, small computer small interface (SCSI), enhanced small disk interface (ESDI), integrated drive electronics (IDE), Firewire, universal flash storage (UFS), nonvolatile memory express (NVMe), etc.
  • a write command defined by the above-described standards may include, for example, size information of write data.
  • the nonvolatile memory 1200 may be implemented with a variety of nonvolatile memory devices such as, but not limited to, an electrically erasable and programmable ROM (EEPROM), a NAND flash memory, a NOR flash memory, a phase-change RAM (PRAM), a resistive RAM (ReRAM), a ferroelectric RAM (FRAM), a spin-torque magnetic RAM (STT-MRAM), etc.
  • EEPROM electrically erasable and programmable ROM
  • NAND flash memory a NAND flash memory
  • NOR flash memory a phase-change RAM (PRAM), a resistive RAM (ReRAM), a ferroelectric RAM (FRAM), a spin-torque magnetic RAM (STT-MRAM), etc.
  • PRAM phase-change RAM
  • ReRAM resistive RAM
  • FRAM ferroelectric RAM
  • STT-MRAM spin-torque magnetic RAM
  • the memory controller 1100 and the nonvolatile memory 1200 may be integrated in a single semiconductor device.
  • the memory controller 1100 and the nonvolatile memory 1200 may be integrated in a single semiconductor device to form a solid state drive (SSD).
  • SSD solid state drive
  • the memory controller 1100 and the nonvolatile memory 1200 may be integrated in a single semiconductor device to form a memory card.
  • the controller 1100 and the nonvolatile memory 1200 may be integrated in a single semiconductor device to form a memory card such as, but not limited to, a PC card (a personal computer memory card international association (PCMCIA) card), a compact flash card (CF), a smart media card (SM, SMC), a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), and a universal flash storage (UFS).
  • PCMCIA personal computer memory card international association
  • CF compact flash card
  • SM smart media card
  • MMC multimedia card
  • RS-MMC RS-MMC
  • MMCmicro multimedia card
  • SD miniSD, microSD, SDHC
  • UFS universal flash storage
  • FIG. 19 is a block diagram illustrating a solid state drive including a nonvolatile memory system according to an exemplary embodiment of the inventive concept.
  • a solid state drive (SSD)) system 2000 may include a host 2100 and an SSD 2200 .
  • the SSD 2200 may exchange signals with the host 2100 through a host interface 2001 and may be supplied with power through a power connector 2002 .
  • the SSD 2200 may include, for example, an SSD controller 2210 , a plurality of flash memories 2221 to 222 n connected to the SSD controller 2210 via channels CH 1 to CHn, an auxiliary power supply 2230 , and a buffer memory 2240 .
  • the SSD controller 2210 may control the flash memories 2221 to 222 n in response to a signal from the host 2100 .
  • the SSD controller 2210 may generate an interrupt based on a method described above with reference to FIGS. 1 to 15 .
  • the auxiliary power supply 2230 may be connected to the host 2100 via the power connector 2002 .
  • the auxiliary power supply 2230 may be charged by power from the host 2100 .
  • the auxiliary power supply 2230 may power the SSD system 2000 .
  • the auxiliary power supply 2230 may be placed inside or outside the SSD 2200 .
  • the auxiliary power supply 2230 may be disposed on a main board to supply auxiliary power to the SSD 2200 .
  • the buffer memory 2240 may act as a buffer memory of the SSD 2200 .
  • the buffer memory 2240 may temporarily store data received from the host 2100 or from the flash memories 2221 to 222 n , and may temporarily store metadata (e.g., mapping tables) of the flash memories 2221 to 222 n .
  • metadata e.g., mapping tables
  • the buffer memory 2240 may include volatile memories such as, for example, a dynamic random-access memory (DRAM), a synchronous DRAM (SDRAM), a double data rate SDRAM (DDR SDRAM), a low power double data rate SDRAM (LPDDR SDRAM), a static random-access memory (SRAM), etc., or nonvolatile memories such as, for example, a ferroelectric RAM (FRAM), a resistive random-access memory (ReRAM), a spin-transfer torque magnetic random-access memory (STT-MRAM), a parameter random access memory (PRAM), etc.
  • DRAM dynamic random-access memory
  • SDRAM synchronous DRAM
  • DDR SDRAM double data rate SDRAM
  • LPDDR SDRAM low power double data rate SDRAM
  • SRAM static random-access memory
  • nonvolatile memories such as, for example, a ferroelectric RAM (FRAM), a resistive random-access memory (ReRAM), a spin-transfer torque magnetic random-access memory (STT-MRAM), a parameter random access
  • FIG. 20 is a block diagram illustrating a user system including a nonvolatile memory system according to an exemplary embodiment of the inventive concept.
  • a user system 3000 may include, for example, an application processor 3100 , a memory module 3200 , a network module 3300 , a storage module 3400 , and a user interface 3500 .
  • the application processor 3100 may drive components, an operating system, etc., of the user system 3000 .
  • the application processor 3100 may include controllers for controlling components of the user system 3000 such as, for example, graphics engines, a variety of interfaces, etc.
  • the application processor 3100 may be a system-on-chip (SoC).
  • SoC system-on-chip
  • the memory module 3200 may operate as, for example, a main memory, a working memory, a buffer memory, or a cache memory of the user system 3000 .
  • the memory module 3200 may be implemented with a volatile random access memory such as, for example, DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR DRAM, LPDDR2 DRAM, or LPDDR3 DRAM, or a nonvolatile random access memory such as, for example, PRAM, MRAM, RRAM, or FRAM.
  • the network module 3300 may communicate with external devices.
  • the network module 3300 may support wireless communications, such as code division multiple access (CDMA), global system for mobile communication (GSM), wideband CDMA (WCDMA), CDMA-2000, time division multiple access (TDMA), long term evolution (LTE), Wimax, WLAN, UWB, Bluetooth, WI-DI, etc.
  • CDMA code division multiple access
  • GSM global system for mobile communication
  • WCDMA wideband CDMA
  • TDMA time division multiple access
  • LTE long term evolution
  • Wimax Wimax
  • WLAN UWB
  • Bluetooth WI-DI
  • WI-DI WI-DI
  • the storage module 3400 may store data.
  • the storage module 3400 may store data received from the application processor 3100 .
  • the storage module 3400 may provide the application processor 3100 with data stored therein.
  • the storage module 3400 may be implemented with a semiconductor memory device such as PRAM, MRAM, RRAM, NAND flash memory, NOR flash memory, or a three-dimensional NAND flash memory.
  • a three dimensional (3D) memory array is provided.
  • the 3D memory array is monolithically formed in one or more physical levels of arrays of memory cells having an active area disposed above a silicon substrate and circuitry associated with the operation of those memory cells, whether such associated circuitry is above or within such substrate.
  • the term “monolithic” means that layers of each level of the array are directly deposited on the layers of each underlying level of the array.
  • the 3D memory array includes vertical NAND strings that are vertically oriented such that at least one memory cell is located over another memory cell.
  • the at least one memory cell may comprise a charge trap layer.
  • the storage module 3400 may generate an interrupt based on a method described with reference to FIGS. 1 to 15 .
  • the storage module 3400 may communicate with the application processor 3100 based on a given interface.
  • the storage module 3400 may adjust a time taken to perform garbage collection based on a write command from the application processor 3100 .
  • the user interface 3500 may include interfaces which input data or a command in the application processor 3100 or output data to an external device.
  • the user interface 3500 may include user input interfaces such as a keyboard, a keypad, buttons, a touch panel, a touch screen, a touch pad, a touch ball, a camera, a microphone, a gyroscope sensor, a vibration sensor, etc.
  • the user interface 3500 may further include user output interfaces such as a liquid crystal display (LCD), an organic light-emitting diode (OLED) display device, an active matrix OLED (AMOLED) display device, a light-emitting diode (LED), a speaker, a motor, etc.
  • LCD liquid crystal display
  • OLED organic light-emitting diode
  • AMOLED active matrix OLED
  • LED light-emitting diode
  • speaker a motor, etc.
  • a nonvolatile memory device, a card controller, and a memory card according to exemplary embodiments of the inventive concept may be packaged according to any of a variety of different packaging technologies.
  • packaging technologies include, but are not limited to, package on package (PoP), ball grid arrays (BGAs), chip scale packages (CSPs), plastic leaded chip carrier (PLCC), plastic dual in-line package (PDIP), die in waffle pack, die in wafer form, chip on board (COB), ceramic dual in-line package (CERDIP), plastic metric quad flat pack (MQFP), small outline (SOIC), shrink small outline package (SSOP), thin small outline (TSOP), thin quad flatpack (TQFP), system in package (SIP), multi-chip package (MCP), wafer-level fabricated package (WFP), and wafer-level processed stack package (WSP).
  • PoP package on package
  • BGAs ball grid arrays
  • CSPs chip scale packages
  • PLCC plastic leaded chip carrier
  • PDIP plastic dual in-line package
  • the number of events that generate an interrupt may be reduced, resulting in improved performance of a storage device (e.g., an SSD) due to decreased accumulation of interrupts.
  • a storage device e.g., an SSD

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US11561914B2 (en) 2023-01-24
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