US20150333231A1 - Method for manufacturing semiconductor light emitting apparatus and semiconductor light emitting apparatus - Google Patents
Method for manufacturing semiconductor light emitting apparatus and semiconductor light emitting apparatus Download PDFInfo
- Publication number
- US20150333231A1 US20150333231A1 US14/809,751 US201514809751A US2015333231A1 US 20150333231 A1 US20150333231 A1 US 20150333231A1 US 201514809751 A US201514809751 A US 201514809751A US 2015333231 A1 US2015333231 A1 US 2015333231A1
- Authority
- US
- United States
- Prior art keywords
- light emitting
- semiconductor light
- film
- side electrode
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 378
- 238000004519 manufacturing process Methods 0.000 title abstract description 76
- 238000000034 method Methods 0.000 title abstract description 68
- 230000002093 peripheral effect Effects 0.000 claims description 5
- 239000010410 layer Substances 0.000 description 258
- 239000000463 material Substances 0.000 description 71
- 229910052751 metal Inorganic materials 0.000 description 22
- 239000002184 metal Substances 0.000 description 22
- 229910000679 solder Inorganic materials 0.000 description 21
- 229910002601 GaN Inorganic materials 0.000 description 20
- 230000008569 process Effects 0.000 description 20
- 238000000605 extraction Methods 0.000 description 18
- 239000000758 substrate Substances 0.000 description 18
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 16
- 238000013461 design Methods 0.000 description 15
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 12
- 239000011347 resin Substances 0.000 description 12
- 229920005989 resin Polymers 0.000 description 12
- 229910052709 silver Inorganic materials 0.000 description 12
- 239000004332 silver Substances 0.000 description 12
- 239000003989 dielectric material Substances 0.000 description 10
- 230000002349 favourable effect Effects 0.000 description 10
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Substances [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 10
- 230000000694 effects Effects 0.000 description 9
- 239000011777 magnesium Substances 0.000 description 9
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 9
- 239000002356 single layer Substances 0.000 description 9
- 229910052681 coesite Inorganic materials 0.000 description 8
- 229910052906 cristobalite Inorganic materials 0.000 description 8
- 239000013078 crystal Substances 0.000 description 8
- 230000007547 defect Effects 0.000 description 8
- 239000010931 gold Substances 0.000 description 8
- 239000000377 silicon dioxide Substances 0.000 description 8
- 229910052682 stishovite Inorganic materials 0.000 description 8
- 229910052905 tridymite Inorganic materials 0.000 description 8
- 238000007740 vapor deposition Methods 0.000 description 8
- 230000000052 comparative effect Effects 0.000 description 7
- 230000006870 function Effects 0.000 description 7
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 6
- 230000006866 deterioration Effects 0.000 description 6
- 239000012299 nitrogen atmosphere Substances 0.000 description 6
- 229910052594 sapphire Inorganic materials 0.000 description 6
- 239000010980 sapphire Substances 0.000 description 6
- 238000005245 sintering Methods 0.000 description 6
- 239000010936 titanium Substances 0.000 description 6
- 229910001316 Ag alloy Inorganic materials 0.000 description 5
- 108010043121 Green Fluorescent Proteins Proteins 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910009372 YVO4 Inorganic materials 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 4
- 238000005253 cladding Methods 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 4
- 230000006872 improvement Effects 0.000 description 4
- 239000000203 mixture Substances 0.000 description 4
- 239000010955 niobium Substances 0.000 description 4
- 150000004767 nitrides Chemical class 0.000 description 4
- 239000010948 rhodium Substances 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- DDFHBQSCUXNBSA-UHFFFAOYSA-N 5-(5-carboxythiophen-2-yl)thiophene-2-carboxylic acid Chemical compound S1C(C(=O)O)=CC=C1C1=CC=C(C(O)=O)S1 DDFHBQSCUXNBSA-UHFFFAOYSA-N 0.000 description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 229910052799 carbon Inorganic materials 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 238000002230 thermal chemical vapour deposition Methods 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- 230000004075 alteration Effects 0.000 description 2
- 239000007767 bonding agent Substances 0.000 description 2
- 238000004364 calculation method Methods 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000003776 cleavage reaction Methods 0.000 description 2
- 229910017052 cobalt Inorganic materials 0.000 description 2
- 239000010941 cobalt Substances 0.000 description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 2
- 239000003086 colorant Substances 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 229910003460 diamond Inorganic materials 0.000 description 2
- 239000010432 diamond Substances 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 239000010419 fine particle Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 229910052741 iridium Inorganic materials 0.000 description 2
- GKOZUEZYRPOHIO-UHFFFAOYSA-N iridium atom Chemical compound [Ir] GKOZUEZYRPOHIO-UHFFFAOYSA-N 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 229910052758 niobium Inorganic materials 0.000 description 2
- GUCVJGMIXFAOAE-UHFFFAOYSA-N niobium atom Chemical compound [Nb] GUCVJGMIXFAOAE-UHFFFAOYSA-N 0.000 description 2
- 229910052762 osmium Inorganic materials 0.000 description 2
- SYQBFIAQOQZEGI-UHFFFAOYSA-N osmium atom Chemical compound [Os] SYQBFIAQOQZEGI-UHFFFAOYSA-N 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 230000002265 prevention Effects 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 229910052702 rhenium Inorganic materials 0.000 description 2
- WUAPFZMCVAUBPE-UHFFFAOYSA-N rhenium atom Chemical compound [Re] WUAPFZMCVAUBPE-UHFFFAOYSA-N 0.000 description 2
- 229910052703 rhodium Inorganic materials 0.000 description 2
- MHOVAHRLVXNVSD-UHFFFAOYSA-N rhodium atom Chemical compound [Rh] MHOVAHRLVXNVSD-UHFFFAOYSA-N 0.000 description 2
- 230000007017 scission Effects 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 229910052720 vanadium Inorganic materials 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- 229910052684 Cerium Inorganic materials 0.000 description 1
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- FYYHWMGAXLPEAU-UHFFFAOYSA-N Magnesium Chemical compound [Mg] FYYHWMGAXLPEAU-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 1
- 239000005084 Strontium aluminate Substances 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000005275 alloying Methods 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- GWXLDORMOJMVQZ-UHFFFAOYSA-N cerium Chemical compound [Ce] GWXLDORMOJMVQZ-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000002860 competitive effect Effects 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000005284 excitation Effects 0.000 description 1
- -1 gallium nitride compound Chemical class 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 229910021478 group 5 element Inorganic materials 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000031700 light absorption Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 229910052749 magnesium Inorganic materials 0.000 description 1
- 229910001092 metal group alloy Inorganic materials 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 229910003465 moissanite Inorganic materials 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 229910052707 ruthenium Inorganic materials 0.000 description 1
- VSZWPYCFIRKVQL-UHFFFAOYSA-N selanylidenegallium;selenium Chemical compound [Se].[Se]=[Ga].[Se]=[Ga] VSZWPYCFIRKVQL-UHFFFAOYSA-N 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 230000035939 shock Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
- 230000007480 spreading Effects 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- JBQYATWDVHIOAR-UHFFFAOYSA-N tellanylidenegermanium Chemical compound [Te]=[Ge] JBQYATWDVHIOAR-UHFFFAOYSA-N 0.000 description 1
- 238000012719 thermal polymerization Methods 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- LEONUFNNVUYDNQ-UHFFFAOYSA-N vanadium atom Chemical compound [V] LEONUFNNVUYDNQ-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
- H01L33/46—Reflective coating, e.g. dielectric Bragg reflector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/10—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a light reflecting structure, e.g. semiconductor Bragg reflector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/483—Containers
- H01L33/486—Containers adapted for surface mounting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/58—Optical field-shaping elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05124—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05139—Silver [Ag] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05567—Disposition the external layer being at least partially embedded in the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05573—Single external layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05639—Silver [Ag] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05644—Gold [Au] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05655—Nickel [Ni] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/05666—Titanium [Ti] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/05669—Platinum [Pt] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0605—Shape
- H01L2224/06051—Bonding areas having different shapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/06102—Disposition the bonding areas being at different heights
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
- H01L2224/1701—Structure
- H01L2224/1703—Bump connectors having different sizes, e.g. different diameters, heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/3201—Structure
- H01L2224/32012—Structure relative to the bonding area, e.g. bond pad
- H01L2224/32013—Structure relative to the bonding area, e.g. bond pad the layer connector being larger than the bonding area, e.g. bond pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0025—Processes relating to coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0033—Processes relating to semiconductor body packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0033—Processes relating to semiconductor body packages
- H01L2933/0058—Processes relating to semiconductor body packages relating to optical field-shaping elements
Definitions
- This invention relates to a method for manufacturing a semiconductor light emitting apparatus and a semiconductor light emitting apparatus.
- light extraction efficiency can be improved by improving the reflectance and increasing the surface area of the reflecting region of an electrode formation surface.
- the reflectance of regions in which electrodes are not formed is low, resulting in a lower light extraction efficiency. Therefore, light extraction efficiencies are being improved by increasing the surface area of the reflecting region by ingenuity such as shortening the distance between the p-side electrode and an n-side electrode.
- JP-A 2007-324585 discusses mounting technology using metal solder for flip-chip mounted semiconductor light emitting devices.
- a method for manufacturing a semiconductor light emitting apparatus including: causing a semiconductor light emitting device and a mounting member to face each other, the semiconductor light emitting device including: a stacked structure unit including a first semiconductor layer, a second semiconductor layer, and a light emitting layer provided between the first semiconductor layer and the second semiconductor layer; a first electrode provided on a major surface of the stacked structure unit to connect to the first semiconductor layer; a second electrode provided on the major surface of the stacked structure unit to connect to the second semiconductor layer; and a dielectric stacked film provided on the first semiconductor layer and the second semiconductor layer of the major surface not covered by the first electrode and the second electrode, formed of stacked dielectric films having different refractive indexes, and including a protruding portion erected on at least a portion of a rim of at least one of the first and second electrodes, the mounting member including a connection member connected to at least one of the first and second electrodes, and causing the connection member to contact and join to
- a semiconductor light emitting apparatus including: a semiconductor light emitting device; and a mounting member, the semiconductor light emitting device including: a stacked structure unit including a first semiconductor layer, a second semiconductor layer, and a light emitting layer provided between the first semiconductor layer and the second semiconductor layer; a first electrode provided on a major surface of the stacked structure unit to connect to the first semiconductor layer; a second electrode provided on the major surface of the stacked structure unit to connect to the second semiconductor layer; and a dielectric stacked film provided on the first semiconductor layer and the second semiconductor layer of the major surface not covered by the first electrode and the second electrode, formed of stacked dielectric films having different refractive indexes, and including a protruding portion erected on a rim of at least one of the first and second electrodes, and the mounting member being provided to face the major surface of the semiconductor light emitting device and including a connection member, the connection member welded to the at least one of the first electrode and the second electrode and covered by a
- FIGS. 1A and 1B are sequential schematic cross-sectional views illustrating manufacturing processes of a semiconductor light emitting apparatus according to a first embodiment of the invention
- FIGS. 2A and 2B are schematic views illustrating the configuration of a semiconductor light emitting device applicable to the manufacturing processes of the semiconductor light emitting apparatus according to the first embodiment of the invention
- FIG. 3 is a schematic cross-sectional view illustrating the configuration of the semiconductor light emitting apparatus manufactured by the manufacturing processes of the semiconductor light emitting apparatus according to the first embodiment of the invention
- FIG. 4 is a flowchart illustrating the manufacturing processes of the semiconductor light emitting apparatus according to the first embodiment of the t invention
- FIGS. 5A to 5C are sequential schematic cross-sectional views illustrating manufacturing processes of the semiconductor light emitting device applicable to the method for manufacturing the semiconductor light emitting apparatus according to the first embodiment of the invention
- FIGS. 6A to 6C are sequential schematic cross-sectional views continuing from FIG. 5C ;
- FIGS. 7A and 7B are graphs illustrating characteristics of the semiconductor light emitting device for which the method for manufacturing the semiconductor light emitting apparatus according to the first embodiment of the invention is applicable;
- FIG. 8 is a graph illustrating the characteristic of the semiconductor light emitting device for which the method for manufacturing the semiconductor light emitting apparatus according to the first embodiment of the invention is applicable;
- FIGS. 9A and 9B are schematic cross-sectional views illustrating the structure of a semiconductor light emitting device of a comparative example
- FIG. 10 is a schematic cross-sectional view illustrating the configuration of another semiconductor light emitting apparatus manufactured by the manufacturing processes of the semiconductor light emitting apparatus according to the first embodiment of the invention.
- FIG. 11 is a schematic view illustrating the configuration of another semiconductor light emitting device applicable to the manufacturing processes of the semiconductor light emitting apparatus according to the first embodiment of the invention.
- FIGS. 12A to 12C are sequential schematic cross-sectional views illustrating manufacturing processes of another semiconductor light emitting device applicable to the method for manufacturing the semiconductor light emitting apparatus according to the first embodiment of the invention
- FIGS. 13A to 13C are sequential schematic cross-sectional views continuing from FIG. 12C ;
- FIG. 14 is a schematic view illustrating the configuration of another semiconductor light emitting device applicable to the manufacturing processes of the semiconductor light emitting apparatus according to the first embodiment of the invention.
- FIG. 15 is a schematic view illustrating the configuration of another semiconductor light emitting device applicable to the manufacturing processes of the semiconductor light emitting apparatus according to the first embodiment of the invention.
- FIG. 16 is a flowchart illustrating the manufacturing processes of a semiconductor light emitting apparatus according to a second embodiment of the invention.
- FIG. 17 is a flowchart illustrating the manufacturing processes of a semiconductor light emitting apparatus according to a third embodiment of the invention.
- FIG. 18 is a flowchart illustrating the manufacturing processes of a semiconductor light emitting apparatus according to a fourth embodiment of the invention.
- FIG. 19 is a flowchart illustrating the manufacturing processes of a semiconductor light emitting apparatus according to a fifth embodiment of the invention.
- FIG. 20 is a schematic cross-sectional view illustrating the structure of another semiconductor light emitting apparatus manufactured by the method for manufacturing the semiconductor light emitting apparatus according to the embodiments of the invention.
- FIGS. 1A and 1B are sequential schematic cross-sectional views illustrating manufacturing processes of a semiconductor light emitting apparatus according to a first embodiment of the invention.
- FIGS. 2A and 2B are schematic views illustrating the configuration of a semiconductor light emitting device applicable to the manufacturing processes of the semiconductor light emitting apparatus according to the first embodiment of the invention.
- FIG. 2B is a plan view
- FIG. 2A is a cross-sectional view along line A-A′ of FIG. 2B .
- FIG. 3 is a schematic cross-sectional view illustrating the configuration of the semiconductor light emitting apparatus manufactured by the manufacturing processes of the semiconductor light emitting apparatus according to the first embodiment of the invention.
- FIG. 4 is a flowchart illustrating the manufacturing processes of the semiconductor light emitting apparatus according to the first embodiment of the invention.
- an n-type semiconductor layer (first semiconductor layer) 1 , a light emitting layer 3 , and a p-type semiconductor layer (second semiconductor layer) 2 are stacked in this order to form a stacked structure unit 1 s on a substrate 10 made of, for example, sapphire.
- a p-side electrode (second electrode) 4 , an n-side electrode (first electrode) 7 , and a dielectric stacked film 11 are provided on the same major surface 1 a of the stacked structure unit 1 s.
- the p-side electrode 4 is provided on the p-type semiconductor layer 2 .
- the p-side electrode 4 may include a second metal film (second p-side electrode film) 4 b (not illustrated) forming a high-efficiency reflecting film and a first metal film (first p-side electrode film) 4 a (not illustrated) made of metal having not necessarily highly efficient reflecting characteristics.
- a portion of the p-type semiconductor layer 2 and the light emitting layer 3 is removed by, for example, etching.
- the n-side electrode 7 is provided on the exposed n-type semiconductor layer 1 .
- the n-side electrode 7 occupies one corner of the square semiconductor light emitting device 101 in the specific example illustrated in FIG. 2B , the configuration of the n-side electrode 7 is not limited thereto.
- the dielectric stacked film 11 is provided on the n-type semiconductor layer 1 and the p-type semiconductor layer 2 of the major surface 1 a not covered by the n-side electrode 7 and the p-side electrode 4 .
- the dielectric stacked film 11 includes stacked dielectric films having different refractive indexes. As described below, the dielectric stacked film 11 functions as a guide during the assembly when manufacturing a semiconductor light emitting apparatus using the semiconductor light emitting device 101 in addition to the function of reflecting light emitted by the light emitting layer 3 .
- the dielectric stacked film 11 recited above is provided on at least a portion of a rim of at least one of the n-side electrode 7 and the p-side electrode 4 .
- the dielectric stacked film 11 may be provided to completely enclose the rim of at least one of the n-side electrode 7 and the p-side electrode, or the dielectric stacked film 11 may be provided on a portion of the rim of at least one of the n-side electrode 7 and the p-side electrode 4 .
- a portion of the dielectric stacked film 11 may be provided on at least a portion of the n-side electrode 7 and the p-side electrode 4 .
- the dielectric stacked film 11 is provided in the semiconductor light emitting device 101 . Therefore, a difference in levels from the dielectric stacked film 11 to the n-side electrode 7 and the p-side electrode 4 is provided. Restated, the dielectric stacked film 11 in the semiconductor light emitting device 101 includes protruding portions 11 b protruding further than the n-side electrode 7 and the p-side electrode 4 .
- the protruding portions 11 b are erected on at least a portion of the rim of at least one of the n-side electrode 7 and the p-side electrode 4 .
- Recesses 11 c are defined by the protruding portions 11 b between the protruding portions 11 b.
- FIG. 3 illustrates the semiconductor light emitting device 101 vertically inverted from the illustration of FIG. 2A .
- a semiconductor light emitting apparatus 201 manufactured by the method for manufacturing the semiconductor light emitting apparatus according to this embodiment includes the semiconductor light emitting device 101 recited above and a mounting member 13 on which the semiconductor light emitting device 101 may be mounted.
- the mounting member 13 includes, for example, a submount, mounting substrate, etc., on which the semiconductor light emitting device may be mounted.
- connection members 14 are conductive and may include a material which can be welded to metal.
- a material which is conductive is a solid at room temperature, and changes to a liquid state at a high temperature, e.g., solder, may be used.
- connection members 14 include an n-side connection member 14 a which connects to the n-side electrode 7 of the semiconductor light emitting device 101 and a p-side connection member 14 b which connects to the p-side electrode 4 of the semiconductor light emitting device 101 .
- the connection members 14 (the n-side connection member 14 a and the p-side connection member 14 b ) may be provided on not-illustrated electrodes provided on the mounting member 13 .
- the n-side connection member 14 a and the p-side connection member 14 b protrude further than the major surface of the mounting member 13 .
- the semiconductor light emitting device 101 and the mounting member 13 can be fixed while electrically connecting the not-illustrated electrodes provided on the mounting member 13 to the electrodes (the n-side electrode 7 and the p-side electrode 4 ) of the semiconductor light emitting device 101 .
- the semiconductor light emitting device 101 and the mounting member 13 are caused to face each other, and the connection members 14 are caused to contact and join to the n-side electrode 7 and the p-side electrode 4 using the protruding portions 11 b of the dielectric stacked film 11 as guides as illustrated in FIGS. 1A and 1B .
- the protruding portions 11 b are provided on at least a portion of the rim of at least one of the n-side electrode 7 and the p-side electrode 7 . Accordingly, in the manufacturing method recited above, the connection members 14 are caused to contact and join to the n-side electrode 7 and the p-side electrode 4 (i.e., the at least one of the same) having the protruding portions 11 b recited above provided thereon using the protruding portions 11 b as guides.
- the semiconductor light emitting device 101 is held by a vacuum chuck using a collet, etc., moved above the mounting member 13 , and positioned substantially aligned with the mounting member 13 .
- the mounting member 13 and the semiconductor light emitting device 101 are caused to contact each other in the substantially aligned state.
- step S 110 the semiconductor light emitting device 101 and the mounting member 13 are brought into contact such that the recess 11 c and the connection member 14 are in a substantially aligned state as illustrated in FIG. 4 (step S 110 ).
- the dielectric stacked film 11 provided in the semiconductor light emitting device 101 protrudes further than the n-side electrode 7 and the p-side electrode 4 , and the protruding portion 11 b of each of the n-side electrode 7 and the p-side electrode 4 forms an n-side guide portion 12 a and a p-side guide portion 12 b , respectively.
- the n-side guide portion 12 a and the p-side guide portion 12 b are caused to contact and mutually align with the n-side connection member 14 a and the p-side connection member 14 b of the mounting member 13 .
- the n-side connection member 14 a and the p-side connection member 14 b are inserted and fit into interiors of the n-side guide portion 12 a and the p-side guide portion 12 b.
- planar configurations of the n-side connection member 14 a and the p-side connection member 14 b are smaller than the configurations of the recesses of the n-side guide portion 12 a and the p-side guide portion 12 b to enter into the interiors of the n-side guide portion 12 a and the p-side guide portion 12 b , respectively.
- connection members 14 in the plane parallel to the major surface 1 a are smaller than the configurations of the recesses 11 c in the plane parallel to the major surface 1 a.
- the heights of the n-side connection member 14 a and the p-side connection member 14 b are set higher than the differences in levels of the n-side guide portion 12 a and the p-side guide portion 12 b (the difference in levels between the n-side guide portion 12 a and the n-side electrode 7 and the difference in levels between the p-side guide portion 12 b and the p-side electrode 4 ), respectively.
- the heights of the connection members 14 are higher than the heights (the difference in levels between the n-side guide portion 12 a and the n-side electrode 7 and the difference in levels between the p-side guide portion 12 b and the p-side electrode 4 ) of the protruding portions 11 b.
- vibrations may be applied to the semiconductor light emitting device 101 via, for example, a collet; the semiconductor light emitting device 101 moves around instantaneously in a range of several tens of microns; the n-side connection member 14 a and the p-side connection member 14 b are inserted and fit into the interiors of the n-side guide portion 12 a and the p-side guide portion 12 b ; and the semiconductor light emitting device 101 may be fixed in this position. It is sufficient that the vibrations recited above are applied to at least one of the semiconductor light emitting device 101 and the mounting member 13 . Although there is no particular limitation in regard to the frequency of the vibrations recited above, ultrasonic vibrations of at least 20 kHz are desirable.
- connection members 14 are inserted into the recesses 11 c surrounded by the protruding portions 11 b , and the connection members 14 are brought into contact with the at least one of the n-side electrode 7 and the p-side electrode 7 as illustrated in FIG. 4 (step S 120 ).
- connection member 14 Thereafter, for example, the temperature is increased to at least the melting point of the connection member 14 , and the connection members 14 are welded to the p-side electrode 4 and the n-side electrode 7 , respectively.
- connection members 14 are welded to the at least one of the n-side electrode 7 and the p-side electrode 4 after the fitting (step S 130 ).
- the semiconductor light emitting apparatus 201 by performing high-precision and high-speed assembly of the semiconductor light emitting device 101 having a high light extraction efficiency and the mounting member 13 .
- Such a manufacturing method improves the precision and increases the light extraction efficiency of the semiconductor light emitting apparatus 201 .
- connection members 14 melt due to the heat and are welded to at least one of the n-side electrode 7 and the p-side electrode 4 .
- Step S 130 recited above may be implemented according to the properties of the connection members 14 and the electrical characteristics and/or reliability required for the semiconductor light emitting apparatus.
- step S 130 recited above may be omitted in the case where the connection member 14 is electrically connected to at least one of the n-side electrode 7 and the p-side electrode 4 with the practically required contact resistance and reliability after the fitting in step S 120 recited above.
- step S 130 may be omitted in the case where, for example, the semiconductor light emitting device 101 and the mounting member 13 are housed in an interior of another holder, etc., and the connection member 14 is electrically connected to at least one of the n-side electrode 7 and the p-side electrode 4 by a force from the holder with the practically required contact resistance and reliability after step S 120 .
- the possible range of the alignment of the semiconductor light emitting device 101 can be adjusted by the force from the collet to press (or bring into contact) the semiconductor light emitting device 101 , the frequency and/or strength of the vibrations, optimization of the material qualities of the collet itself to amplify the vibration amplitude, etc.
- the surface area of the n-side electrode 7 can be made smaller than those of conventional structures. Thereby, the surface area of the p-side electrode 4 can be increased, the light emitting region and the reflecting region can be increased, and the light output can be increased.
- the positioning guides (the n-side guide portion 12 a and the p-side guide portion 12 b ) corresponding to the electrodes (the n-side electrode 4 and the p-side electrode 7 ) can be formed with high precision on the substrate 10 forming the semiconductor light emitting device 101 . Therefore, the design degrees of freedom of the electrodes can be improved, the light extraction efficiency can be increased, and improvement of the light output can be expected.
- connection members (the solder) 14 can be prevented from contacting the semiconductor layers, and the occurrence of stress and voids between the connection members (the solder) 14 and the semiconductor layers can be prevented.
- the dielectric stacked film 11 of the semiconductor light emitting device 101 by using the dielectric stacked film 11 of the semiconductor light emitting device 101 , the majority of the major surface of the semiconductor layers where the electrodes are formed can have a reflective structure. Also, by using the dielectric stacked film 11 as a positioning guide, mounting with high alignment precision is easily possible. Thereby, the degrees of freedom of the electrode design increase; improvement of the light extraction efficiency due to the increase of the reflecting region and cost reductions due to high-speed mounting can be expected; and a light source can be provided having little shifting of the light emission points in the semiconductor light emitting apparatus.
- the semiconductor light emitting device 101 applicable to the method for manufacturing the semiconductor light emitting apparatus of this embodiment will now be described in detail.
- the semiconductor light emitting device 101 includes, for example, a nitride semiconductor formed on the substrate 10 made of sapphire.
- metal organic chemical vapor deposition may be used to form, on the substrate 10 having a surface made of a sapphire c-plane, a sequentially stacked structure including a high carbon-concentration first AlN buffer layer (having a carbon concentration of 3 ⁇ 10 18 cm ⁇ 3 to 5 ⁇ 10 20 cm ⁇ 3 ) with a thickness of 3 nm to 20 nm, a high-purity second AlN buffer layer (having a carbon concentration of 1 ⁇ 10 16 cm ⁇ 3 to 3 ⁇ 10 18 cm ⁇ 3 ) with a thickness of 2 ⁇ m, a non-doped GaN buffer layer with a thickness of 3 ⁇ m, a Si-doped n-type GaN contact layer (having a Si concentration of 1 ⁇ 10 18 cm ⁇ 3 to 5 ⁇ 10 18 cm ⁇ 3 ) with a thickness of 4 ⁇ m, a Si-doped n-type Al 0.10 Ga 0.90 N cladding layer (having a Si concentration of 1 ⁇
- the n-type semiconductor layer 1 illustrated in FIG. 2A may include the high carbon-concentration first AlN buffer layer, the high-purity second AlN buffer layer, the non-doped GaN buffer layer, the Si-doped n-type GaN contact layer, and the Si-doped n-type Al 0.10 Ga 0.90 N cladding layer recited above.
- the light emitting layer 3 illustrated in FIG. 2A may include the final Al 0.11 Ga 0.89 N barrier layer of the multiple quantum well and the light emitting layer having the multiple quantum well structure formed of three alternately stacked periods of the Si-doped n-type Al 0.11 Ga 0.89 N barrier layer and the GaInN light emitting layer (having a wavelength of 380 nm) recited above.
- the p-type semiconductor layer 2 illustrated in FIG. 2A may include the Mg-doped p-type Al 0.28 Ga 0.72 N cladding layer, the Mg-doped p-type GaN contact layer, and the high-purity Mg-doped p-type GaN contact layer recited above.
- Increasing the Mg concentration of the Mg-doped p-type GaN contact layer to about 1 ⁇ 10 20 cm ⁇ 3 improves the ohmic contact characteristics with the p-side electrode.
- a semiconductor light emitting diode differs from a semiconductor laser diode in that there is a risk of deterioration of characteristics due to Mg diffusion due to the short distance between the contact layer and the light emitting layer 4 . Therefore, by utilizing the increased contact surface area between the p-side electrode 4 and the contact layer and the lower current density during operation, the Mg concentration can be kept at about 1 ⁇ 10 19 cm ⁇ 3 without greatly harming the electrical characteristics. Thereby, Mg diffusion can be prevented, and light emission characteristics can be improved.
- the high carbon-concentration first AlN buffer layer acts to relieve effects of crystal types different from the substrate and particularly reduce screw dislocations.
- the surface of the high-purity second AlN buffer layer flattens at the atomic level. Although defects of the non-doped GaN buffer layer grown thereon can be thereby reduced, to this end, it is favorable that the film thickness of the high-purity second AlN buffer layer is thicker than 1 ⁇ m. To prevent warp due to strain, it is desirable that the thickness of the high-purity second AlN buffer layer is not greater than 4 ⁇ m.
- the high-purity second AlN buffer layer is not limited to AlN, Al x Ga 1-x N (0.8 ⁇ x ⁇ 1) may be used, and the warp of the wafer can be compensated.
- the non-doped GaN buffer layer performs the role of reducing defects by performing three-dimensional island growth on the high-purity second AlN buffer layer. It is necessary for the average film thickness of the non-doped GaN buffer layer to be not less than 2 ⁇ m to allow flattening of the growth surface. A total film thickness of the non-doped GaN buffer layer of 4 to 10 ⁇ m is appropriate from the aspect of reproducibility and reduction of warp.
- buffer layers defects can be reduced to about one-tenth of those in conventional low-temperature growth AlN buffer layers.
- Such technology enables high-concentration Si doping of the n-type GaN contact layer and the manufacture of highly efficient semiconductor light emitting devices emitting light even in the ultraviolet band. Absorption of light in the buffer layers also can be suppressed by reducing the crystal defects of the buffer layers.
- the p-side electrode 4 of the semiconductor light emitting device 101 includes a first metal film (first p-side electrode film) 4 a made of metal having not necessarily high-efficiency reflecting characteristics and a second metal film (second p-side electrode film) 4 b forming a high-efficiency reflecting film provided between the first metal film (the first p-side electrode film) 4 a and the p-type semiconductor layer 2 .
- FIGS. 5A to 5C are sequential schematic cross-sectional views illustrating manufacturing processes of the semiconductor light emitting device applicable to the method for manufacturing the semiconductor light emitting apparatus according to the first embodiment of the invention.
- FIGS. 6A to 6C are sequential schematic cross-sectional views continuing from FIG. 5C .
- dry etching using a mask is performed on a region of a portion of the p-type semiconductor layer 2 to remove the p-type semiconductor layer 2 and the light emitting layer 3 until the n-type contact layer is exposed at the surface.
- the difference in levels between the p-type semiconductor layer 2 and the n-type semiconductor layer 1 can be patterned into a tapered configuration having any angle by optimizing the mask configuration and the dry etching conditions. Restated, a tapered portion it can be provided on the semiconductor layers.
- taper angle ⁇ (°).
- the smaller the taper angle ⁇ the more the inclination of the tapered portion it forms a moderate inclined face; and a taper angle ⁇ of 90 degrees has a side face in which the stepped region of the n-type semiconductor layer 1 and the p-type semiconductor layer 2 has a stairstep configuration.
- the n-side electrode 7 having ohmic characteristics is then formed as illustrated in FIG. 5B .
- a not-illustrated patterned lift-off resist is formed on the exposed n-type contact layer, a vacuum vapor deposition apparatus is used to form, for example; a Ti/Al/Ni/Au film having a film thickness of 500 nm as the n-side electrode 7 for the ohmic contact region; and after lift-off, sintering is performed at 550° C. in a nitrogen atmosphere.
- the p-side electrode 4 is formed by forming a not-illustrated patterned lift-off resist on the p-type contact layer; using a vacuum vapor deposition apparatus to form, for example, a Ag film with a film thickness of 200 nm as the second p-side electrode film 4 b ; and after lift-off, performing sintering at 350° C. in a nitrogen atmosphere.
- a not-illustrated patterned lift-off resist is formed on the semiconductor layers, and a Pt/Au film, for example, having a film thickness of 500 nm is formed as the first p-side electrode film 4 a on the region in which the Ag film was formed. Thereby, the p-side electrode 4 is formed.
- a vacuum vapor deposition apparatus is used to form, for example, five pairs combining a SiO 2 film and a TiO 2 film for a total of ten layers on the semiconductor layers.
- a not-illustrated patterned resist is formed thereupon and ammonium fluoride processing is performed to remove the dielectrics recited above to expose the p-side electrode 4 and the n-side electrode 7 to form the dielectric stacked film 11 .
- the dielectrics recited above may be removed by a dry etching process by using a patterned resist as a mask.
- the dielectric stacked film 11 protrudes further than the n-side electrode 7 and the p-side electrode 4 , and the protruding portions 11 b provided on at least a portion of the rims of each of the n-side electrode 7 and the p-side electrode 4 form the n-side guide portion 12 a and the p-side guide portion 12 b.
- individual light emitting devices are formed by cleavage or cutting by a diamond blade, etc.
- the semiconductor light emitting device 101 illustrated in FIGS. 2A and 2B is formed.
- the semiconductor light emitting device 101 is mounted on the mounting member 13 to fabricate the semiconductor light emitting apparatus 201 .
- the semiconductor light emitting device 101 will now be described further.
- the dielectric stacked film 11 may be formed using, for example, five pairs combining the stacked films of the first dielectric layer (e.g., SiO 2 ) and the second dielectric layer (e.g., TiO 2 ) as dielectrics having at least two types with different refractive indexes, that is, a stacked film made of a total of, for example, ten layers of dielectric layers.
- the first dielectric layer e.g., SiO 2
- the second dielectric layer e.g., TiO 2
- the film thicknesses of each of the first dielectric layer and the second dielectric layer may be set to a thickness of ⁇ /(4n), where n is the refractive index of each of the first dielectric layer and the second dielectric layer and ⁇ is the light emission wavelength of the light emitting layer 3 .
- the dielectric stacked film 11 includes multiple first dielectric layers having a first refractive index alternately stacked with multiple second dielectric layers having a second refractive index different from the first refractive index, the thickness of each of the first dielectric layers being substantially ⁇ /(4n 1 ) and the thickness of each of the second dielectric layers being substantially ⁇ /(4n 2 ), where n 1 is the first refractive index, n 2 is the second refractive index, and ⁇ is the light emission wavelength of the light emitting layer 3 .
- a higher refractive index ratio of the combined dielectrics and a greater number of combined layers (pairs) having different refractive indexes result in a higher reflectance and a wider margin with respect to film thickness and/or wavelength.
- FIGS. 7A and 7B are graphs illustrating characteristics of the semiconductor light emitting device to which the method for manufacturing the semiconductor light emitting apparatus according to the first embodiment of the invention is applicable.
- FIGS. 7A and 7B illustrate simulation results of the reflectance of light emitted by GaN and perpendicularly incident on the dielectric stacked film 11 .
- FIG. 7A illustrates the dependency of the reflectance on the refractive index ratio.
- FIG. 7B illustrates the dependency of the reflectance on the number of pairs.
- the refractive index ratio of the dielectrics of the dielectric stacked film 11 combining two types is plotted on the horizontal axis of FIG. 7A .
- the number of pairs of the dielectrics of the dielectric stacked film 11 combining two types is plotted on the horizontal axis of FIG. 7B .
- the reflectance is plotted on the vertical axes of FIGS. 7A and 7B .
- values of the reflectance near 100% can be obtained by appropriately selecting the conditions.
- Selecting design conditions from such properties can provide a dielectric stacked film 11 that functions as a reflecting film having better performance than a metal reflecting film. By utilizing such a dielectric stacked film 11 , improvement of the light extraction efficiency can be expected.
- the design reflectance of the dielectric stacked film 11 of the semiconductor light emitting device 101 of this specific example is 99.7%.
- the emitted light incident on the semiconductor layer cross sections disposed on either side of the light emitting layer 3 is affected by the film thickness in the direction normal to the dielectric stacked film 11 formed on the semiconductor layer cross sections. Therefore, unless the taper angle is 0°, the light is affected in a direction shifted such that the dielectric stacked film 11 is thinner than the design film thickness. The smaller the taper angle, the more the dielectric stacked film of the semiconductor layer cross sections functions as designed.
- FIG. 8 is a graph illustrating the characteristic of the semiconductor light emitting device to which the method for manufacturing the semiconductor light emitting apparatus according to the first embodiment of the invention is applicable.
- FIG. 8 illustrates the calculation results of the relationship between the taper angle and the reflectance of the dielectric stacked film 11 .
- the taper angle is plotted on the horizontal axis
- the reflectance of the dielectric stacked film 11 is plotted on the vertical axis.
- FIG. 8 illustrates the calculation results using the design conditions described above in regard to the semiconductor light emitting device 101 .
- the film thickness of the dielectric stacked film 11 is too thin when the taper angle ⁇ is larger than 40 degrees. Therefore, the high reflecting characteristics are not obtained as designed.
- the margin for high reflecting characteristics with respect to the taper angle is wider for a larger refractive index ratio of the two types of stacked dielectrics.
- the tapered portion 1 t can prevent separation of the dielectric stacked film 11 due to the different levels of the semiconductor layer cross sections disposed on either side of the light emitting layer 3 .
- the tapered portion it functions as a region that changes the angle of emitted light repeatedly reflected inside the semiconductor layers without being extracted. Therefore, the extraction efficiency is improved.
- the taper angle ⁇ of the tapered portion it may be appropriately established based on the device surface area and light emission characteristics of the semiconductor light emitting device, the patterning precision, and the like.
- the dielectric stacked film 11 may include an oxide, nitride, oxynitride, or the like including at least one of silicon (Si), aluminum (Al), zirconium (Zr), titanium (Ti), niobium (Nb), tantalum (Ta), magnesium (Mg), hafnium (Hf), cerium (Ce), zinc (Zn), or the like. It is favorable that the total film thickness of the stacked dielectric films is not less than 50 nm to ensure insulative properties and not more than 1,000 nm to suppress cracks in the dielectric films.
- the film thickness of the dielectric stacked film 11 is 1,000 nm to 10,000 nm.
- the first layer of the dielectric stacked film 11 on the semiconductor layer side is a material having a linear coefficient of thermal expansion near to those of the semiconductor layers.
- the semiconductor layers are GaN
- stacking dielectrics under tensile stress and compressive stress promotes stress-relieving effects.
- the dielectric stacked film 11 forming the positioning guides is provided around the connection members 14 and therefore can prevent excessive spreading of the connection members (the solder) during the heating of the mounting process.
- the design degrees of freedom of the surface area, film thickness, etc., of the connection members (the solder) 14 increase; the degrees of freedom of the wettability with respect to the electrodes increase; and rapid mounting is possible.
- the semiconductor light emitting device to which the method for manufacturing the semiconductor light emitting apparatus of this embodiment is applicable is made of at least the semiconductor layers including the n-type semiconductor layer, the p-type semiconductor layer, and the light emitting layer disposed therebetween.
- the materials of the semiconductor layers are not particularly limited, a gallium nitride compound semiconductor such as, for example, Al x Ga 1-x-y In y N (x ⁇ 0, y ⁇ 0, and x+y ⁇ 1) may be used.
- the methods for forming such semiconductor layers are not particularly limited, technology such as, for example, metal organic chemical vapor deposition, molecular beam epitaxy, and the like may be used.
- the substrate material of the semiconductor light emitting device to which the method for manufacturing the semiconductor light emitting apparatus of this embodiment is applicable is not particularly limited, general substrates such as sapphire, SiC, GaN, GaAs, and Si may be used. The substrate may ultimately be removed.
- the p-side electrode 4 may be formed of the second p-side electrode film 4 b including at least silver or silver alloy and the first p-side electrode film 4 a made of metal not including at least silver or silver alloy.
- the material of the second p-side electrode film 4 b may be a single layer of silver, or may be an alloy layer including metal other than silver and aluminum.
- the risk of insulation defects and breakdown voltage defects due to migration from the silver or the silver alloy decreases as the distance between the second p-side electrode film 4 b and the n-side electrode 7 increases.
- the light extraction efficiency increases as the p-side electrode 4 facing the n-side electrode 7 proximal to the center of the device is formed up to the end of the p-type contact layer as much as the process conditions such as lithography precision permit.
- the surface area and configuration of the second p-side electrode film 4 b and the distance between the second p-side electrode film 4 b and the n-side electrode 7 may be appropriately decided considering such effects.
- the first p-side electrode film 4 a is formed of metal not including silver and electrically contacts the second p-side electrode film 4 b .
- the material of the first p-side electrode film 4 a is not particularly limited and may include a single-layer or multi-layer metal film, a metal alloy layer, a single-layer or multi-layer conductive oxide film, or a combination thereof.
- the film thickness of the first p-side electrode film 4 a is not particularly limited, and may be selected, for example, between 100 nm to 1,000 nm.
- the material of the n-side electrode 7 is not particularly limited.
- a conductive single-layer or multi-layer film providing an ohmic electrode for an n-type semiconductor may be used.
- the film thickness of the n-side electrode 7 is not particularly limited, and may be between 5 nm and 1,000 nm.
- pads may be provided on the p-side electrode 4 and the n-side electrode 7 .
- the film thickness of the pads is not particularly limited, and may be, for example, between 1,000 nm and 10,000 nm. Forming the pads can improve wettability during welding with the connection members (e.g., the solder) 14 and reduce the risk of excessive alloying reactions between the electrodes and the connection members (e.g., the solder) 14 .
- Using a crystal on a monocrystalline AlN buffer layer can reduce crystal defects to realize high luminous efficiency even in wavelength bands shorter than 400 nm where efficiency normally declines.
- the buffer layer itself forms a light absorbing body. Therefore, the light extraction efficiency of the light emitting device declines undesirably.
- the buffer layers do not easily form light absorbing bodies, and crystal defects can be drastically reduced. Thereby, the light absorbing bodies in the crystal can be drastically reduced. In such a case, it is possible for the emitted light to repeatedly be reflected many times inside the crystal, resulting in better effects from increasing the reflecting region of the electrode formation surface. Due to such effects, improvement of the light emission intensity can be expected.
- FIGS. 9A and 9B are schematic cross-sectional views illustrating the structure of a semiconductor light emitting device of a comparative example.
- the dielectric stacked film 11 is not provided in a semiconductor light emitting device 90 of the comparative example illustrated in FIGS. 9A and 9B .
- SiO 2 of 400 nm for example, is formed as a not-illustrated single layer dielectric film instead of the dielectric stacked film 11 . Therefore, no differences in levels to the n-side electrode 7 and to the p-side electrode 4 are provided, and no protruding portions forming guide portions are provided.
- the electrodes of the semiconductor light emitting device 90 having such a configuration are formed as follows.
- n-side electrode 7 a patterned lift-off resist is formed on the exposed n-type contact layer; a vacuum vapor deposition apparatus is used to form the n-side electrode 7 having a film thickness of 500 nm made of, for example, Ti/Al/Ni/Au as an ohmic contact region; and sintering is performed at 550° C. in a nitrogen atmosphere.
- a patterned lift-off resist is formed on the semiconductor layers; a vacuum vapor deposition apparatus is used to form a Ag film having a film thickness of 200 nm as the second p-side electrode film 4 b on the p-type contact layer; and after lift-off, sintering is performed at 350° C. in a nitrogen atmosphere.
- a similarly patterned lift-off resist is formed on the semiconductor layers, and a Pt/Au film having a film thickness of 500 nm of the first p-side electrode film 4 a is formed to cover the region in which the Ag film of the second p-side electrode film 4 b is formed.
- individual light emitting devices are formed by cleavage or cutting by a diamond blade, etc.
- the semiconductor light emitting device 90 of the comparative example is fabricated.
- a process that mounts the semiconductor light emitting device 90 on the mounting member 13 uses a collet or the like to move the semiconductor light emitting device 90 above the mounting member 13 .
- the semiconductor light emitting device 90 is pressed onto the mounting member 13 .
- the temperature of the mounting member is increased to at least the melting point of the connection members (the solder) 14 , and the connection members (the solder) 14 are welded to the p-side electrode 4 and the n-side electrode 7 , respectively.
- the relative positions of the semiconductor light emitting device 90 and the mounting member 13 are determined by the alignment precision of, for example, a motor that moves the collet. Therefore, the mounting precision is poor. Also, in the case where the speed of moving the device is increased to increase the takt time, the mounting precision gets worse further. To accommodate the poor mounting precision, it is necessary to improve the alignment margin by making the electrodes of the semiconductor light emitting device 90 mutually distal, enlarging the surface area of the n-side electrode 7 , etc. As a result, the degrees of freedom of the electrode design decrease, and it is not always possible to select the optimal electrode structure in regard to the light extraction efficiency and the light output.
- the dielectric stacked film 11 is utilized as a positioning guide to easily provide a high mounting precision. Therefore, the degrees of freedom of the electrode design increase. Simultaneously, the dielectric stacked film 11 can be used as a high-efficiency reflecting film. Due to such effects, the light extraction efficiency and the light output can be improved.
- the method for manufacturing the semiconductor light emitting apparatus can perform high-precision and high-speed assembly of a semiconductor light emitting apparatus having high light extraction efficiency.
- FIG. 10 is a schematic cross-sectional view illustrating the configuration of another semiconductor light emitting apparatus manufactured by the manufacturing processes of the semiconductor light emitting apparatus according to the first embodiment of the invention.
- connection members 14 cover a portion of the dielectric stacked film 11 .
- the semiconductor light emitting apparatus 202 includes the semiconductor light emitting device 101 including the stacked structure unit 1 s including the n-type semiconductor layer (first semiconductor layer) 1 , the p-type semiconductor layer (second semiconductor layer) 2 , and the light emitting layer 3 provided between the first semiconductor layer and the second semiconductor layer, the n-side electrode (first electrode) 7 provided on the major surface 1 a of the stacked structure unit is to connect to the first semiconductor layer, the p-side electrode (second electrode) 4 provided on the major surface 1 a of the stacked structure unit 1 s to connect to the second semiconductor layer 2 , and the dielectric stacked film 11 provided on the first semiconductor layer and the second semiconductor layer of the major surface 1 a not covered by the first electrode and the second electrode, formed of multiple stacked dielectric films having different refractive indexes, and including the protruding portion 11 b erected on at least a portion of a rim of at least one of the first and second electrodes; and the mounting member 13 provided to face the
- connection member 14 (e.g., solder), as shown in FIG. 10 , covers a portion of the protruding portion 11 b of the dielectric stacked film 11 and thereby prevents, for example, moisture and the like from entering from the interface between the dielectric stacked film 11 and the connection member 14 , reaching the n-side electrode 7 and/or the p-side electrode 4 , and causing deterioration of the electrodes.
- the welding step S 130 of the method for manufacturing the semiconductor light emitting apparatus according to this embodiment illustrated in FIG. 4 includes covering a portion of the protruding portion 11 b of the dielectric stacked film 11 with the connection member 14 .
- connection member 14 fixes the semiconductor light emitting device 101 and the mounting member 13 using a pattern having high precision to prevent electrical shorts between the n-side electrode 7 and the p-side electrode 4 .
- the semiconductor light emitting device 101 and the mounting member 13 are assembled by using the protruding portion 11 b formed of the dielectric stacked film 11 as a guide, that is, fitting the connection member 14 into the recess 11 c defined by the protruding portion 11 b .
- the assembly precision is thereby increased. Therefore, the precision of the configuration of the connection member 14 is high after assembling and fixing the semiconductor light emitting device 101 and the mounting member 13 . Thereby, the connection member 14 can cover a portion of the dielectric stacked film 11 with high precision.
- the low assembly precision of the comparative example in which the dielectric stacked film 11 is not provided results in electrical shorts between the n-side electrode 7 and the p-side electrode 4 in the case of an excessive amount of the connection member 14 .
- deterioration of the electrodes cannot be prevented.
- connection member 14 flows and is disposed on portions on the dielectric stacked film 11 other than the regions to be covered, unfortunately resulting in electrical shorts between the n-side electrode 7 and the p-side electrode 4 .
- the connection member 14 cannot cover the prescribed region of the dielectric stacked film 11 , and the effect of preventing the deterioration of the electrodes described above cannot be obtained.
- connection member 14 cannot be sufficiently filled into the interior of the recess 11 c defined by the dielectric stacked film 11 , a gap occurs, the deterioration of the electrodes cannot be prevented, and the reliability is poor.
- the dielectric stacked film 11 is used as a positioning guide during assembly. Therefore, the precision is high, and the connection member 14 can cover a portion of the dielectric stacked film 11 from above to provide the prescribed configuration and good precision. Thereby, a semiconductor light emitting apparatus having high reliability can be realized.
- the connection member 14 covers a portion of the dielectric stacked film 11 from above with the prescribed configuration and good precision. Therefore, the reliability is high.
- FIG. 11 is a schematic view illustrating the configuration of another semiconductor light emitting device applicable to the manufacturing processes of the semiconductor light emitting apparatus according to the first embodiment of the invention.
- FIGS. 12A to 12C are sequential schematic cross-sectional views illustrating manufacturing processes of another semiconductor light emitting device applicable to the method for manufacturing the semiconductor light emitting apparatus according to the first embodiment of the invention.
- FIGS. 13A to 13C are sequential schematic cross-sectional views continuing from FIG. 12C .
- a dielectric film 11 a is provided between the dielectric stacked film 11 and the n-type semiconductor layer 1 and between the dielectric stacked film 11 and the p-type semiconductor layer 2 .
- the dielectric film 11 a has a better ability than the dielectric stacked film 11 to cover differences in levels. Thereby, even in the case where the semiconductor layer cross sections disposed on either side of the light emitting layer 3 are perpendicular (have a taper angle ⁇ of 90°), the cross section thereof can be covered well by the dielectric film 11 a . Otherwise, the semiconductor light emitting device 102 is similar to the semiconductor light emitting device 101 described above, and a description is omitted.
- the p-side electrode 4 includes the first p-side electrode film 4 a and the second p-side electrode film 4 b provided between the first p-side electrode film 4 a and the p-type semiconductor layer 2 .
- Such a semiconductor light emitting device 102 is fabricated as follows.
- dry etching using a mask is performed on a region of a portion of the p-type semiconductor layer 2 to remove the p-type semiconductor layer 2 and the light emitting layer 3 until the n-type contact layer is exposed at the surface.
- SiO 2 forming the dielectric film 11 a having a film thickness of 200 nm is formed on the semiconductor layers using a thermal CVD apparatus.
- a film having a good ability to cover steps can be formed, the ability to cover perpendicular cross sections is good, and the dielectric film 11 a can be formed.
- the n-side electrode 7 having ohmic characteristics is formed. Namely, a not-illustrated patterned lift-off resist is formed on the semiconductor layers and a portion of the SiO 2 film on the exposed n-type contact layer is removed by ammonium fluoride processing. The SiO 2 film is removed and a vacuum vapor deposition apparatus is used to form the n-side electrode 7 made of, for example, a Ti/Al/Ni/Au film having a film thickness of 500 nm as an ohmic contact region on the exposed n-type contact layer, and sintering is performed at 550° C. in a nitrogen atmosphere.
- a not-illustrated patterned lift-off resist is formed on the semiconductor layers and a portion of the SiO 2 film on the p-type contact layer is removed by ammonium fluoride processing.
- a patterned lift-off resist is then formed on the p-type contact layer; a vacuum vapor deposition apparatus is used to form a Ag film, for example, with a film thickness of 200 nm as the second p-side electrode film 4 b ; and after lift-off, sintering is performed at 350° C. in a nitrogen atmosphere.
- a patterned lift-off resist is formed on the semiconductor layers, a Pt/Au film, for example, is formed with a film thickness of 500 nm as the first p-side electrode film 4 a in the region in which the Ag film is formed, and the p-side electrode 4 is formed.
- a not-illustrated patterned lift-off resist is formed on the semiconductor layers, a vacuum vapor deposition apparatus is used to form, for example, five pairs combining a SiO 2 film and a TiO 2 film for a total of ten layers on the semiconductor layers, and the dielectric stacked film 11 is formed by lift-off.
- the film thicknesses are ⁇ /(4n), where n is the refractive index of each film and A is the light emission wavelength of the light emitting layer 3 .
- the p-side guide portion 12 b for the p-side electrode 4 and the p-side guide portion 12 a for the n-side electrode 7 can be formed to be used during mounting.
- the dielectric film 11 a formed by, for example, thermal CVD has a better ability than the dielectric stacked film 11 to cover differences in levels and therefore can be formed to cover even steep differences in levels of the semiconductor layer cross sections disposed on either side of the light emitting layer 3 . Therefore, it is unnecessary to pattern the differences in levels of the semiconductor layer cross sections disposed on either side of the light emitting layer 3 into a tapered configuration, and simpler and fewer semiconductor layer patterning processes can be used.
- Forming the dielectric film 11 a results in almost no effects on the reflectance of the dielectric stacked film 11 and the dielectric film 11 a .
- Using multiple stacked pairs of dielectrics having different refractive indexes for the dielectric stacked film 11 can provide a sufficiently high design reflectance.
- the design reflectance of the region in which the dielectric film 11 a and the dielectric stacked film 11 are stacked together is 99.5%.
- FIG. 14 is a schematic view illustrating the configuration of another semiconductor light emitting device applicable to the manufacturing processes of the semiconductor light emitting apparatus according to the first embodiment of the invention.
- the p-side electrode 4 includes the first p-side electrode film 4 a and the second p-side electrode film 4 b provided between the first p-side electrode film 4 a and the p-type semiconductor layer 2 , and further includes a third p-side electrode film 4 c provided between the first p-side electrode film 4 a and the second p-side electrode film 4 b .
- the semiconductor light emitting device 103 is similar to the semiconductor light emitting device 101 described above, and a description is omitted.
- the third p-side electrode film 4 c functions to prevent the materials included in the first p-side electrode film 4 a , the solder of the connection member 14 during mounting, and the like from diffusing into the second p-side electrode film 4 b , and prevent the materials included in the first p-side electrode film 4 a and/or the connection members 14 from reacting with the materials included in the second p-side electrode film 4 b .
- the third p-side electrode film 4 c electrically connects to the first p-side electrode film 4 a and the second p-side electrode film 4 b.
- the third p-side electrode film 4 c may include a material that does not react with silver or does not actively diffuse into silver.
- Materials which may be used as the third p-side electrode film 4 c include single-layer films or stacked films of a high melting-point metal usable as the diffusion prevention layer such as, for example, vanadium (V), chrome (Cr), iron (Fe), cobalt (Co), nickel (Ni), niobium (Nb), molybdenum (Mo), ruthenium (Ru), rhodium (Rh), tantalum (Ta), tungsten (W), rhenium (Re), osmium (Os), iridium (Ir), and platinum (Pt).
- a high melting-point metal usable as the diffusion prevention layer
- a high melting-point metal usable as the diffusion prevention layer such as, for example, vanadium (V), chrome (Cr), iron (Fe), cobalt (Co), nickel (Ni), niobium (Nb), molybdenum (Mo), ruthenium (Ru), rhodium (Rh), tantalum (
- More favorable metals that have a high work function and easily provide ohmic contact with the p-GaN contact layer to prevent problems even in the case where some diffusion into the second p-side electrode film 4 b occurs include iron (Fe), cobalt (Co), nickel (Ni), rhodium (Rh), tungsten (W), rhenium (Re), osmium (Os), iridium (Ir), and platinum (Pt).
- the film thickness thereof is in the range of 5 nm to 200 nm to maintain the film state.
- the film thickness for a stacked film is not particularly limited, and may be, for example, between 10 nm and 10,000 nm.
- the third p-side electrode film 4 c as a diffusion prevention layer, mounting is possible at higher temperatures. Therefore, the mounting rate can be increased to improve cost competitiveness.
- the dielectric film 11 a described in regard to the semiconductor light emitting device 102 may be provided in the semiconductor light emitting device 103 .
- FIG. 15 is a schematic view illustrating the configuration of another semiconductor light emitting device applicable to the manufacturing processes of the semiconductor light emitting apparatus according to the first embodiment of the invention.
- conductive guide films 12 m are provided on the p-side electrode 4 and the n-side electrode 7 not covered by the dielectric stacked film 11 , the upper face (on the side of the dielectric stacked film 11 opposite the semiconductor layers) of the dielectric stacked film 11 of the peripheral portions of the p-side electrode 4 and the n-side electrode 7 , and on the side faces of the dielectric stacked film 11 .
- the semiconductor light emitting device 104 is similar to the semiconductor light emitting device 101 described above, and a description is omitted.
- the n-side guide portion 12 a is formed of the dielectric stacked film 11 and the conductive guide film 12 m at the peripheral portion of the n-side electrode 7 .
- the p-side guide portion 12 b is formed of the dielectric stacked film 11 and the conductive guide film 12 m at the peripheral portion of the p-side electrode 4 .
- the conductive guide films 12 m provided on the side faces of the dielectric stacked film 11 define the recesses 11 c
- the connection members 14 fit into the recesses 11 c to assemble the semiconductor light emitting device 104 and the mounting member 13 .
- connection members 14 can be brought into contact and joined with the at least one of the n-side electrode 7 and the p-side electrode 4 using the protruding portions 11 b of the dielectric stacked film 11 as guides.
- the conductive guide films 12 m may be formed by, for example, forming a patterned lift-off resist on the semiconductor layers after forming the dielectric stacked film 11 and forming, for example, a Ti/Pt/Au film with a film thickness of 500 nm as the conductive guide films 12 m.
- the conductive guide films 12 m in the n-side guide portion 12 a and the p-side guide portion 12 b to cover a portion of the upper face and the side faces of the dielectric stacked film 11 , damage of the guide portions due to shocks during contact of the connection members 14 (e.g., the solder) with the n-side guide portion 12 a and the p-side guide portion 12 b or applied vibrations can be prevented during mounting.
- the connection members 14 e.g., the solder
- the wettability against the solder is improved by providing the conductive guide films 12 m as the effective bonding surface area with the solder is increased. Thereby, easiness of mounting process is improved and the mounting speed can be further improved, then a cost competitive edge can be further improved.
- the cross section of the dielectric stacked film 11 has a tapered configuration for easy formation of the conductive guide films 12 m on the side faces of the dielectric stacked film 11 .
- the dielectric stacked film 11 forming the n-side guide portion 12 a and the p-side guide portion 12 b By protecting the dielectric stacked film 11 forming the n-side guide portion 12 a and the p-side guide portion 12 b by the conductive guide films 12 m , vibrations under more vigorous conditions can be used, and the semiconductor light emitting device 104 can be moved in a wider range. Therefore, the mounting rate can be increased more to further improve cost competitiveness.
- FIG. 16 is a flowchart illustrating the manufacturing processes of a semiconductor light emitting apparatus according to a second embodiment of the invention.
- the method for manufacturing the semiconductor light emitting apparatus according to the second embodiment of the invention further includes the following processes prior to step S 110 illustrated in FIG. 4 .
- the first semiconductor layer (the n-type semiconductor layer 1 ), the light emitting layer 3 , and the second semiconductor layer (the p-type semiconductor layer 2 ) are stacked on the substrate 10 (step S 210 ).
- step S 220 a portion of the second semiconductor layer and the light emitting layer is removed to expose the first semiconductor layer.
- the first electrode (the n-side electrode 7 ) is then formed on the exposed first semiconductor layer (step S 230 ).
- the second electrode (the p-side electrode 4 ) is then formed on the second semiconductor layer (step S 240 ).
- step S 250 Multiple types of dielectric films having different refractive indexes are alternately stacked on the exposed first semiconductor layer and the second semiconductor layer not covered by the first electrode and the second electrode to form the dielectric stacked film 11 .
- step S 210 to step S 250 may be used in step S 210 to step S 250 recited above.
- the dielectric stacked film 11 forming the guide portions is formed; the semiconductor light emitting device and the mounting member 13 can be assembled utilizing the guide portions; high-precision and high-speed assembly is possible; and a semiconductor light emitting apparatus having high light extraction efficiency can be provided.
- Steps S 210 to S 250 recited above are interchangeable within the extent of technical feasibility and may be implemented simultaneously.
- steps S 230 and S 240 which form the n-side electrode 7 and the p-side electrode 4 are interchangeable and may be implemented simultaneously.
- FIG. 17 is a flowchart illustrating the manufacturing processes of a semiconductor light emitting apparatus according to a third embodiment of the invention.
- the method for manufacturing the semiconductor light emitting apparatus according to the third embodiment of the invention further includes the following processes prior to step S 110 illustrated in FIG. 4 .
- the first semiconductor layer (the n-type semiconductor layer 1 ), the light emitting layer 3 , and the second semiconductor layer (the p-type semiconductor layer 2 ) are stacked on the substrate 10 (step S 310 ).
- step S 320 a portion of the second semiconductor layer and a portion of the light emitting layer are removed to expose the first semiconductor layer.
- Dielectric films having different refractive indexes are then alternately stacked on a portion of the exposed first semiconductor layer and a portion of the second semiconductor layer to form the dielectric stacked film 11 (step S 330 ).
- the first electrode (the n-side electrode 7 ) is then formed on the first semiconductor layer not covered by the dielectric stacked film 11 (step S 340 ).
- the second electrode (the p-side electrode 4 ) is then formed on the second semiconductor layer not covered by the dielectric stacked film 11 (step S 350 ).
- step S 310 may be modified and used in step S 350 recited above.
- FIG. 18 is a flowchart illustrating the manufacturing processes of a semiconductor light emitting apparatus according to a fourth embodiment of the invention.
- the dielectric film 11 a described above is provided in the method for manufacturing the semiconductor light emitting apparatus according to the fourth embodiment of the invention after exposing the first semiconductor layer and prior to forming the dielectric stacked film 11 .
- the dielectric film 11 a having a better ability than the dielectric stacked film 11 to cover the first semiconductor layer and the second semiconductor layer, is formed on a portion of the uncovered first semiconductor layer and a portion of the second semiconductor layer (step S 225 ) between the process that exposes the first semiconductor layer (step S 220 ) and the process that forms the dielectric stacked film (step S 250 ).
- step S 225 is implemented between the process that exposes the first semiconductor layer (step S 220 ) and the process that forms the first electrode (step S 230 ).
- step S 230 is interchangeable, and the processes can be implemented simultaneously.
- step S 210 to step S 250 may be used in step S 210 to step S 250 recited above.
- FIG. 19 is a flowchart illustrating the manufacturing processes of a semiconductor light emitting apparatus according to a fifth embodiment of the invention.
- the dielectric film 11 a described above is provided by the method for manufacturing the semiconductor light emitting apparatus according to the fifth embodiment of the invention after exposing the first semiconductor layer and prior to forming the dielectric stacked film 11 .
- the dielectric film 11 a having a better ability than the dielectric stacked film 11 to cover the first semiconductor layer and the second semiconductor layer, is formed on a portion of the exposed first semiconductor layer and a portion of the second semiconductor layer (step S 325 ) between the process that exposes the first semiconductor layer (step S 320 ) and the process that forms the dielectric stacked film (step S 330 ).
- step S 330 to step S 350 recited above is interchangeable, and the processes may be implemented simultaneously.
- the dielectric stacked film 11 including the protruding portions 11 b forming the guide portions are formed; the semiconductor light emitting device and the mounting member 13 can be assembled utilizing the guide portions; high-precision and high-speed assembly is possible; and a semiconductor light emitting apparatus having high light extraction efficiency can be provided.
- the process that exposes the first semiconductor layer may include forming the tapered portion it on the stacked structure unit 1 s to incline with respect to the layer surface of the stacked structure unit 1 s .
- the covering of the dielectric stacked film 11 formed thereon improves, the reflecting abilities of the dielectric stacked film 11 can be improved by the difference in levels, and a semiconductor light emitting apparatus having high light extraction efficiency can be provided.
- the methods for manufacturing the semiconductor light emitting apparatus further include a process that forms the connection member 14 on a mounting substrate, the connection member 14 having a configuration in the plane parallel to the surface of the mounting substrate smaller than a configuration of the at least one of the n-side electrode 7 and the p-side electrode 4 surrounded by the protruding portion 11 b .
- the connection member 14 of the prescribed configuration can be formed, and the semiconductor light emitting device and the mounting member 13 can be assembled with high precision.
- the height of the connection member 14 is higher than the height of the protruding portion 11 b.
- FIG. 20 is a schematic cross-sectional view illustrating the structure of another semiconductor light emitting apparatus manufactured by the method for manufacturing the semiconductor light emitting apparatus according to the embodiments of the invention.
- a semiconductor light emitting apparatus 301 of this specific example is a white LED combining any of the semiconductor light emitting devices according to the embodiments recited above and a fluorescent material. That is, the semiconductor light emitting apparatus 301 according to this embodiment includes any of the semiconductor light emitting devices recited above and a fluorescent material layer irradiated by light emitted by the semiconductor light emitting device.
- reflecting films 23 are provided on inner faces of a container 22 made of ceramic and the like.
- the reflecting films 23 are provided separately on an inner side face and a bottom face of the container 22 .
- the reflecting film 23 is made of, for example, aluminum and the like.
- the semiconductor light emitting device 101 is disposed on the reflecting film 23 provided on the bottom portion of the container 22 via a submount 24 .
- the submount 24 is the mounting member 13 .
- connection members 14 e.g., solder
- Bonding by a bonding agent, solder, etc. may be used to fix the semiconductor light emitting device 101 , the submount 24 , and the reflecting film 23 .
- Patterned electrodes are formed on the surface of the submount 24 on the semiconductor light emitting device side to insulate the p-side electrode 4 and the n-side electrode 7 of the semiconductor light emitting device 101 .
- Each of the electrodes is connected to a not-illustrated electrode provided on the container 22 by bonding wires 26 . The connection is made to the portion between the reflecting film 23 of the inner side face and the reflecting film 23 of the bottom face.
- a first fluorescent material layer 211 including a red fluorescent material is provided to cover the semiconductor light emitting device 101 and the bonding wire 26 .
- a second fluorescent material layer 212 including a blue, green, or yellow fluorescent material is formed on the first fluorescent material layer 211 .
- a lid 27 made of silicon resin is provided on the fluorescent material layer.
- the first fluorescent material layer 211 includes a resin and the red fluorescent material dispersed in the resin.
- the red fluorescent material may include, for example, an activating substance of trivalent Eu (Eu 3+ ) in a main material such as Y 2 O 3 , YVO 4 , or Y 2 (P, V)O 4 .
- Y 2 O 3 :Eu 3+ , YVO 4 :Eu 3+ , and the like may be used as the red fluorescent material.
- the molar concentration of Eu 3+ may be 1% to 10%.
- LaOS, Y 2 (P, V)O 4 , and the like may be used as the main material of the red fluorescent material in addition to Y 2 O 3 and YVO 4 .
- Mn 4+ and the like may be used in addition to Eu 3+ .
- absorption at 380 nm increases by adding a small amount of Bi with trivalent Eu to the YVO 4 base material. Therefore, the luminous efficiency increases even more.
- a silicon resin and the like, for example, may be used as the resin.
- the second fluorescent material layer 212 includes a resin and at least one of a blue fluorescent material, a green fluorescent material, and a yellow fluorescent material dispersed in the resin.
- a fluorescent material combining a blue fluorescent material and a green fluorescent material, a fluorescent material combining a blue fluorescent material and a yellow fluorescent material, or a fluorescent material combining a blue fluorescent material, a green fluorescent material, and a yellow fluorescent material may be used.
- Y 2 SiO 5 :Ce 3+ , Tb 3+ having centers of light emission of trivalent Tb may be used as the green fluorescent material.
- energy is transmitted from Ce ions to Tb ions to improve the excitation efficiency.
- Sr 4 Al 14 O 25 :Eu 2+ and the like, for example, may be used as the green fluorescent material.
- Y 3 Al 5 :Ce 3+ and the like may be used as the yellow fluorescent material.
- a silicon resin and the like, for example, may be used as the resin.
- trivalent Tb has a sharp light emission around 550 nm at which visibility is at a maximum and thereby markedly improves the luminous efficiency when combined with the sharp red light emission of trivalent Eu.
- ultraviolet light of 380 nm emitted by the semiconductor light emitting device 101 is radiated to the substrate 10 side of the semiconductor light emitting device 101 and efficiently excites the fluorescent materials recited above included in the fluorescent material layers by utilizing reflections of the reflecting films 23 .
- the fluorescent material recited above having centers of light emission of trivalent Eu and the like included in the first fluorescent material layer 211 converts light into light having a narrow wavelength distribution around 620 nm to efficiently produce red visible light.
- the blue, green, and yellow fluorescent materials included in the second fluorescent material layer 212 are efficiently excited and efficiently produce blue, green, and yellow visible light.
- a metal film forming the reflecting film 23 is formed on the inner face of the container 22 by, for example, sputtering.
- the metal film is patterned, and the reflecting film 23 is left on each of the inner side face and the bottom face of the container 22 .
- the methods described in regard to the first embodiment are used to fix the semiconductor light emitting device 101 on the submount 24 (the mounting member 13 ).
- the submount 24 is disposed and fixed on the reflecting film 23 on the bottom face of the container 22 . Bonding using a bonding agent, solder, etc., may be used for the fixation.
- each of a not-illustrated n-side electrode and p-side electrode on the submount 24 is connected to a not-illustrated electrode provided on the container 22 by bonding wires 26 .
- the first fluorescent material layer 211 including the red fluorescent material is then formed to cover the semiconductor light emitting device 101 and the bonding wires 26 .
- the second fluorescent material layer 212 including the blue, the green, or the yellow fluorescent material is formed on the first fluorescent material layer 211 .
- the method for forming each of the fluorescent material layers may drop resin/source material mixture solutions having the fluorescent materials dispersed therein and perform heat treatment to cure the resin by thermal polymerization. It is possible to cause the fine particles of the fluorescent materials to distribute unevenly in the lower layers of the first and second fluorescent material layers 211 and 212 to appropriately control the luminous efficacy of each of the fluorescent materials by allowing the resin/source material mixture solutions including the fluorescent materials to lie for a while after dropping and prior to curing to allow the fine particles of the fluorescent materials to settle. Subsequently, the lid 27 is provided on the fluorescent material layer, and the semiconductor light emitting apparatus 301 according to this embodiment, that is, the white LED, is fabricated.
- nitride semiconductor includes all compositions of semiconductors of the chemical formula B x In y Al z Ga 1-x-y-z N (0 ⁇ x ⁇ 1, 0 ⁇ y ⁇ 1, 0 ⁇ z ⁇ 1, x+y+z ⁇ 1) for which each of the composition ratios x, y, and z are changed within the ranges.
- Nonride semiconductor further includes group V elements other than N (nitrogen) in the chemical formula recited above and any of various dopants added to control the conductivity type, etc.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Led Devices (AREA)
- Led Device Packages (AREA)
Abstract
A method for manufacturing a semiconductor light emitting apparatus includes causing a semiconductor light emitting device and a mounting member to face each other. The semiconductor light emitting device includes a stacked structure unit including a first semiconductor layer, a second semiconductor layer, and a light emitting layer provided between the first semiconductor layer and the second semiconductor layer, a first electrode provided on a major surface of the stacked structure unit to connect to the first semiconductor layer, a second electrode provided on the major surface of the stacked structure unit to connect to the second semiconductor layer, and a dielectric stacked film provided on the first semiconductor layer and the second semiconductor layer of the major surface not covered by the first electrode and the second electrode, formed of stacked dielectric films having different refractive indexes, and including a protruding portion erected on at least a portion of a rim of at least one of the first and second electrodes. The mounting member includes a connection member connected to at least one of the first and second electrodes. The method further includes causing the connection member to contact and join to the at least one of the first and second electrodes using the protruding portion as a guide.
Description
- This application is a division of and claims priority under 35 U.S.C. §120 from U.S. Ser. No. 14/506,201 filed Oct. 3, 2014, which is a division of U.S. Ser. No. 13/679,109 filed Nov. 16, 2012 (now U.S. Pat. No. 8,890,193 issued Nov. 18, 2014), which is a division of U.S. Ser. No. 12/549,048 filed Aug. 27, 2009 (now U.S. Pat. No. 8,338,844 issued Dec. 25, 2012), and claims the benefit of priority under 35 U.S.C. §119 from Japanese Patent Application No. 2008-220144 filed Aug. 28, 2008, the entire contents of each of which are incorporated herein by reference.
- 1. Field of the Invention
- This invention relates to a method for manufacturing a semiconductor light emitting apparatus and a semiconductor light emitting apparatus.
- 2. Background Art
- In a flip-chip semiconductor light emitting device using a light emitting layer to produce light and emit the light from a substrate side, light extraction efficiency can be improved by improving the reflectance and increasing the surface area of the reflecting region of an electrode formation surface.
- For example, in the case where a p-side electrode is used to provide both ohmic characteristics and high-efficiency reflecting characteristics, the reflectance of regions in which electrodes are not formed is low, resulting in a lower light extraction efficiency. Therefore, light extraction efficiencies are being improved by increasing the surface area of the reflecting region by ingenuity such as shortening the distance between the p-side electrode and an n-side electrode.
- High mounting precision is necessary during flip-chip mounting of the semiconductor light emitting device in the case where electrode design emphasizes such light extraction efficiency.
- On the other hand, mass production of light emitting diodes using semiconductor light emitting devices is necessary to increase cost competitiveness. Therefore, the time to mount a single device normally must not be more than 0.5 seconds, and the mounting precision is extremely low.
- JP-A 2007-324585 (Kokai) discusses mounting technology using metal solder for flip-chip mounted semiconductor light emitting devices.
- According to an aspect of the invention, there is provided a method for manufacturing a semiconductor light emitting apparatus, including: causing a semiconductor light emitting device and a mounting member to face each other, the semiconductor light emitting device including: a stacked structure unit including a first semiconductor layer, a second semiconductor layer, and a light emitting layer provided between the first semiconductor layer and the second semiconductor layer; a first electrode provided on a major surface of the stacked structure unit to connect to the first semiconductor layer; a second electrode provided on the major surface of the stacked structure unit to connect to the second semiconductor layer; and a dielectric stacked film provided on the first semiconductor layer and the second semiconductor layer of the major surface not covered by the first electrode and the second electrode, formed of stacked dielectric films having different refractive indexes, and including a protruding portion erected on at least a portion of a rim of at least one of the first and second electrodes, the mounting member including a connection member connected to at least one of the first and second electrodes, and causing the connection member to contact and join to the at least one of the first and second electrodes using the protruding portion as a guide.
- According to another aspect of the invention, there is provided a semiconductor light emitting apparatus, including: a semiconductor light emitting device; and a mounting member, the semiconductor light emitting device including: a stacked structure unit including a first semiconductor layer, a second semiconductor layer, and a light emitting layer provided between the first semiconductor layer and the second semiconductor layer; a first electrode provided on a major surface of the stacked structure unit to connect to the first semiconductor layer; a second electrode provided on the major surface of the stacked structure unit to connect to the second semiconductor layer; and a dielectric stacked film provided on the first semiconductor layer and the second semiconductor layer of the major surface not covered by the first electrode and the second electrode, formed of stacked dielectric films having different refractive indexes, and including a protruding portion erected on a rim of at least one of the first and second electrodes, and the mounting member being provided to face the major surface of the semiconductor light emitting device and including a connection member, the connection member welded to the at least one of the first electrode and the second electrode and covered by a portion of the protruding portion.
-
FIGS. 1A and 1B are sequential schematic cross-sectional views illustrating manufacturing processes of a semiconductor light emitting apparatus according to a first embodiment of the invention; -
FIGS. 2A and 2B are schematic views illustrating the configuration of a semiconductor light emitting device applicable to the manufacturing processes of the semiconductor light emitting apparatus according to the first embodiment of the invention; -
FIG. 3 is a schematic cross-sectional view illustrating the configuration of the semiconductor light emitting apparatus manufactured by the manufacturing processes of the semiconductor light emitting apparatus according to the first embodiment of the invention; -
FIG. 4 is a flowchart illustrating the manufacturing processes of the semiconductor light emitting apparatus according to the first embodiment of the t invention; -
FIGS. 5A to 5C are sequential schematic cross-sectional views illustrating manufacturing processes of the semiconductor light emitting device applicable to the method for manufacturing the semiconductor light emitting apparatus according to the first embodiment of the invention; -
FIGS. 6A to 6C are sequential schematic cross-sectional views continuing fromFIG. 5C ; -
FIGS. 7A and 7B are graphs illustrating characteristics of the semiconductor light emitting device for which the method for manufacturing the semiconductor light emitting apparatus according to the first embodiment of the invention is applicable; -
FIG. 8 is a graph illustrating the characteristic of the semiconductor light emitting device for which the method for manufacturing the semiconductor light emitting apparatus according to the first embodiment of the invention is applicable; -
FIGS. 9A and 9B are schematic cross-sectional views illustrating the structure of a semiconductor light emitting device of a comparative example; -
FIG. 10 is a schematic cross-sectional view illustrating the configuration of another semiconductor light emitting apparatus manufactured by the manufacturing processes of the semiconductor light emitting apparatus according to the first embodiment of the invention; -
FIG. 11 is a schematic view illustrating the configuration of another semiconductor light emitting device applicable to the manufacturing processes of the semiconductor light emitting apparatus according to the first embodiment of the invention; -
FIGS. 12A to 12C are sequential schematic cross-sectional views illustrating manufacturing processes of another semiconductor light emitting device applicable to the method for manufacturing the semiconductor light emitting apparatus according to the first embodiment of the invention; -
FIGS. 13A to 13C are sequential schematic cross-sectional views continuing fromFIG. 12C ; -
FIG. 14 is a schematic view illustrating the configuration of another semiconductor light emitting device applicable to the manufacturing processes of the semiconductor light emitting apparatus according to the first embodiment of the invention; -
FIG. 15 is a schematic view illustrating the configuration of another semiconductor light emitting device applicable to the manufacturing processes of the semiconductor light emitting apparatus according to the first embodiment of the invention; -
FIG. 16 is a flowchart illustrating the manufacturing processes of a semiconductor light emitting apparatus according to a second embodiment of the invention; -
FIG. 17 is a flowchart illustrating the manufacturing processes of a semiconductor light emitting apparatus according to a third embodiment of the invention; -
FIG. 18 is a flowchart illustrating the manufacturing processes of a semiconductor light emitting apparatus according to a fourth embodiment of the invention; -
FIG. 19 is a flowchart illustrating the manufacturing processes of a semiconductor light emitting apparatus according to a fifth embodiment of the invention; and -
FIG. 20 is a schematic cross-sectional view illustrating the structure of another semiconductor light emitting apparatus manufactured by the method for manufacturing the semiconductor light emitting apparatus according to the embodiments of the invention. - Embodiments of the invention will now be described with reference to the drawings.
- The drawings are schematic or conceptual; and the relationships between the thickness and width of portions, the proportional coefficients of sizes among portions, etc., are not necessarily the same as the actual values thereof. Further, the dimensions and proportional coefficients may be illustrated differently among drawings, even for identical portions.
- In the specification and drawings, components similar to those described or illustrated in a drawing thereinabove are marked with like reference numerals, and a detailed description is omitted as appropriate.
-
FIGS. 1A and 1B are sequential schematic cross-sectional views illustrating manufacturing processes of a semiconductor light emitting apparatus according to a first embodiment of the invention. -
FIGS. 2A and 2B are schematic views illustrating the configuration of a semiconductor light emitting device applicable to the manufacturing processes of the semiconductor light emitting apparatus according to the first embodiment of the invention. - Namely,
FIG. 2B is a plan view, andFIG. 2A is a cross-sectional view along line A-A′ ofFIG. 2B . -
FIG. 3 is a schematic cross-sectional view illustrating the configuration of the semiconductor light emitting apparatus manufactured by the manufacturing processes of the semiconductor light emitting apparatus according to the first embodiment of the invention. -
FIG. 4 is a flowchart illustrating the manufacturing processes of the semiconductor light emitting apparatus according to the first embodiment of the invention. - First, the configuration of a semiconductor
light emitting device 101 for which the semiconductor light emitting apparatus of this embodiment is applicable will be described with reference toFIGS. 2A and 2B . - In the semiconductor
light emitting device 101 according to the first embodiment of the invention illustrated inFIG. 2A , an n-type semiconductor layer (first semiconductor layer) 1, alight emitting layer 3, and a p-type semiconductor layer (second semiconductor layer) 2 are stacked in this order to form astacked structure unit 1 s on asubstrate 10 made of, for example, sapphire. - A p-side electrode (second electrode) 4, an n-side electrode (first electrode) 7, and a dielectric stacked
film 11 are provided on the samemajor surface 1 a of the stackedstructure unit 1 s. - That is, the p-
side electrode 4 is provided on the p-type semiconductor layer 2. As described below, the p-side electrode 4 may include a second metal film (second p-side electrode film) 4 b (not illustrated) forming a high-efficiency reflecting film and a first metal film (first p-side electrode film) 4 a (not illustrated) made of metal having not necessarily highly efficient reflecting characteristics. - A portion of the p-
type semiconductor layer 2 and thelight emitting layer 3 is removed by, for example, etching. The n-side electrode 7 is provided on the exposed n-type semiconductor layer 1. - Although the n-
side electrode 7 occupies one corner of the square semiconductorlight emitting device 101 in the specific example illustrated inFIG. 2B , the configuration of the n-side electrode 7 is not limited thereto. - The dielectric stacked
film 11 is provided on the n-type semiconductor layer 1 and the p-type semiconductor layer 2 of themajor surface 1 a not covered by the n-side electrode 7 and the p-side electrode 4. The dielectric stackedfilm 11 includes stacked dielectric films having different refractive indexes. As described below, the dielectric stackedfilm 11 functions as a guide during the assembly when manufacturing a semiconductor light emitting apparatus using the semiconductorlight emitting device 101 in addition to the function of reflecting light emitted by thelight emitting layer 3. - It is sufficient that the dielectric stacked
film 11 recited above is provided on at least a portion of a rim of at least one of the n-side electrode 7 and the p-side electrode 4. In other words, the dielectric stackedfilm 11 may be provided to completely enclose the rim of at least one of the n-side electrode 7 and the p-side electrode, or the dielectric stackedfilm 11 may be provided on a portion of the rim of at least one of the n-side electrode 7 and the p-side electrode 4. - A portion of the dielectric stacked
film 11 may be provided on at least a portion of the n-side electrode 7 and the p-side electrode 4. - The dielectric stacked
film 11 is provided in the semiconductorlight emitting device 101. Therefore, a difference in levels from the dielectric stackedfilm 11 to the n-side electrode 7 and the p-side electrode 4 is provided. Restated, the dielectric stackedfilm 11 in the semiconductorlight emitting device 101 includes protrudingportions 11 b protruding further than the n-side electrode 7 and the p-side electrode 4. - The protruding
portions 11 b are erected on at least a portion of the rim of at least one of the n-side electrode 7 and the p-side electrode 4. -
Recesses 11 c are defined by the protrudingportions 11 b between the protrudingportions 11 b. - A semiconductor light emitting apparatus including such a semiconductor
light emitting device 101 will now be described with reference toFIG. 3 .FIG. 3 illustrates the semiconductorlight emitting device 101 vertically inverted from the illustration ofFIG. 2A . - As illustrated in
FIG. 3 , a semiconductorlight emitting apparatus 201 manufactured by the method for manufacturing the semiconductor light emitting apparatus according to this embodiment includes the semiconductorlight emitting device 101 recited above and a mountingmember 13 on which the semiconductorlight emitting device 101 may be mounted. The mountingmember 13 includes, for example, a submount, mounting substrate, etc., on which the semiconductor light emitting device may be mounted. - The mounting
member 13 and the semiconductorlight emitting device 101 are joined byconnection members 14 connected to the electrodes (the n-side electrode 7 and the p-side electrode 4) of the semiconductorlight emitting device 101. Theconnection members 14 are conductive and may include a material which can be welded to metal. For example, a material which is conductive, is a solid at room temperature, and changes to a liquid state at a high temperature, e.g., solder, may be used. - The
connection members 14 include an n-side connection member 14 a which connects to the n-side electrode 7 of the semiconductorlight emitting device 101 and a p-side connection member 14 b which connects to the p-side electrode 4 of the semiconductorlight emitting device 101. The connection members 14 (the n-side connection member 14 a and the p-side connection member 14 b) may be provided on not-illustrated electrodes provided on the mountingmember 13. The n-side connection member 14 a and the p-side connection member 14 b protrude further than the major surface of the mountingmember 13. - Thereby, the semiconductor
light emitting device 101 and the mountingmember 13 can be fixed while electrically connecting the not-illustrated electrodes provided on the mountingmember 13 to the electrodes (the n-side electrode 7 and the p-side electrode 4) of the semiconductorlight emitting device 101. - In the method for manufacturing the semiconductor light emitting apparatus according to this embodiment that manufactures a semiconductor
light emitting apparatus 201 including such a configuration, the semiconductorlight emitting device 101 and the mountingmember 13 are caused to face each other, and theconnection members 14 are caused to contact and join to the n-side electrode 7 and the p-side electrode 4 using the protrudingportions 11 b of the dielectric stackedfilm 11 as guides as illustrated inFIGS. 1A and 1B . - The protruding
portions 11 b are provided on at least a portion of the rim of at least one of the n-side electrode 7 and the p-side electrode 7. Accordingly, in the manufacturing method recited above, theconnection members 14 are caused to contact and join to the n-side electrode 7 and the p-side electrode 4 (i.e., the at least one of the same) having the protrudingportions 11 b recited above provided thereon using the protrudingportions 11 b as guides. - The above description will now be described in greater detail.
- First, as illustrated in
FIG. 1A , for example, the semiconductorlight emitting device 101 is held by a vacuum chuck using a collet, etc., moved above the mountingmember 13, and positioned substantially aligned with the mountingmember 13. - The mounting
member 13 and the semiconductorlight emitting device 101 are caused to contact each other in the substantially aligned state. - In other words, the semiconductor
light emitting device 101 and the mountingmember 13 are brought into contact such that therecess 11 c and theconnection member 14 are in a substantially aligned state as illustrated inFIG. 4 (step S110). - At this time, the dielectric stacked
film 11 provided in the semiconductorlight emitting device 101 protrudes further than the n-side electrode 7 and the p-side electrode 4, and the protrudingportion 11 b of each of the n-side electrode 7 and the p-side electrode 4 forms an n-side guide portion 12 a and a p-side guide portion 12 b, respectively. In this design, the n-side guide portion 12 a and the p-side guide portion 12 b are caused to contact and mutually align with the n-side connection member 14 a and the p-side connection member 14 b of the mountingmember 13. The n-side connection member 14 a and the p-side connection member 14 b are inserted and fit into interiors of the n-side guide portion 12 a and the p-side guide portion 12 b. - In other words, the planar configurations of the n-
side connection member 14 a and the p-side connection member 14 b are smaller than the configurations of the recesses of the n-side guide portion 12 a and the p-side guide portion 12 b to enter into the interiors of the n-side guide portion 12 a and the p-side guide portion 12 b, respectively. - In other words, the configurations of the
connection members 14 in the plane parallel to themajor surface 1 a are smaller than the configurations of therecesses 11 c in the plane parallel to themajor surface 1 a. - The heights of the n-
side connection member 14 a and the p-side connection member 14 b are set higher than the differences in levels of the n-side guide portion 12 a and the p-side guide portion 12 b (the difference in levels between the n-side guide portion 12 a and the n-side electrode 7 and the difference in levels between the p-side guide portion 12 b and the p-side electrode 4), respectively. In other words, the heights of theconnection members 14 are higher than the heights (the difference in levels between the n-side guide portion 12 a and the n-side electrode 7 and the difference in levels between the p-side guide portion 12 b and the p-side electrode 4) of the protrudingportions 11 b. - As illustrated in
FIG. 1B , vibrations (e.g., ultrasonic vibrations) may be applied to the semiconductorlight emitting device 101 via, for example, a collet; the semiconductorlight emitting device 101 moves around instantaneously in a range of several tens of microns; the n-side connection member 14 a and the p-side connection member 14 b are inserted and fit into the interiors of the n-side guide portion 12 a and the p-side guide portion 12 b; and the semiconductorlight emitting device 101 may be fixed in this position. It is sufficient that the vibrations recited above are applied to at least one of the semiconductorlight emitting device 101 and the mountingmember 13. Although there is no particular limitation in regard to the frequency of the vibrations recited above, ultrasonic vibrations of at least 20 kHz are desirable. - In other words, vibrations are applied to at least one of the semiconductor
light emitting device 101 and the mountingmember 13 in a contacting state, theconnection members 14 are inserted into therecesses 11 c surrounded by the protrudingportions 11 b, and theconnection members 14 are brought into contact with the at least one of the n-side electrode 7 and the p-side electrode 7 as illustrated inFIG. 4 (step S120). - Thereafter, for example, the temperature is increased to at least the melting point of the
connection member 14, and theconnection members 14 are welded to the p-side electrode 4 and the n-side electrode 7, respectively. - In other words, the
connection members 14 are welded to the at least one of the n-side electrode 7 and the p-side electrode 4 after the fitting (step S130). - Thereby, it is possible to manufacture the semiconductor
light emitting apparatus 201 by performing high-precision and high-speed assembly of the semiconductorlight emitting device 101 having a high light extraction efficiency and the mountingmember 13. Such a manufacturing method improves the precision and increases the light extraction efficiency of the semiconductorlight emitting apparatus 201. - The heating in step S130 recited above may be performed according to the properties of the
connection members 14. For example, in the case where theconnection members 14 are solder, theconnection members 14 melt due to the heat and are welded to at least one of the n-side electrode 7 and the p-side electrode 4. - Step S130 recited above may be implemented according to the properties of the
connection members 14 and the electrical characteristics and/or reliability required for the semiconductor light emitting apparatus. - In other words, step S130 recited above may be omitted in the case where the
connection member 14 is electrically connected to at least one of the n-side electrode 7 and the p-side electrode 4 with the practically required contact resistance and reliability after the fitting in step S120 recited above. Alternatively, step S130 may be omitted in the case where, for example, the semiconductorlight emitting device 101 and the mountingmember 13 are housed in an interior of another holder, etc., and theconnection member 14 is electrically connected to at least one of the n-side electrode 7 and the p-side electrode 4 by a force from the holder with the practically required contact resistance and reliability after step S120. - In the method for manufacturing the semiconductor light emitting apparatus according to this embodiment, the possible range of the alignment of the semiconductor
light emitting device 101 can be adjusted by the force from the collet to press (or bring into contact) the semiconductorlight emitting device 101, the frequency and/or strength of the vibrations, optimization of the material qualities of the collet itself to amplify the vibration amplitude, etc. - According to the method for manufacturing the semiconductor light emitting apparatus according to this embodiment, it is unnecessary to use gold bumps and the like formed by a ball bonder, and alignment is possible with high precision. Therefore, the surface area of the n-
side electrode 7 can be made smaller than those of conventional structures. Thereby, the surface area of the p-side electrode 4 can be increased, the light emitting region and the reflecting region can be increased, and the light output can be increased. - The positioning guides (the n-
side guide portion 12 a and the p-side guide portion 12 b) corresponding to the electrodes (the n-side electrode 4 and the p-side electrode 7) can be formed with high precision on thesubstrate 10 forming the semiconductorlight emitting device 101. Therefore, the design degrees of freedom of the electrodes can be improved, the light extraction efficiency can be increased, and improvement of the light output can be expected. - Further, by forming the dielectric stacked
film 11 to cover the ends of the p-side electrode 4 and the n-side electrode 7, the connection members (the solder) 14 can be prevented from contacting the semiconductor layers, and the occurrence of stress and voids between the connection members (the solder) 14 and the semiconductor layers can be prevented. - Thus, by using the dielectric stacked
film 11 of the semiconductorlight emitting device 101, the majority of the major surface of the semiconductor layers where the electrodes are formed can have a reflective structure. Also, by using the dielectric stackedfilm 11 as a positioning guide, mounting with high alignment precision is easily possible. Thereby, the degrees of freedom of the electrode design increase; improvement of the light extraction efficiency due to the increase of the reflecting region and cost reductions due to high-speed mounting can be expected; and a light source can be provided having little shifting of the light emission points in the semiconductor light emitting apparatus. - The semiconductor
light emitting device 101 applicable to the method for manufacturing the semiconductor light emitting apparatus of this embodiment will now be described in detail. - First, a specific example of the stacked structure of the semiconductor layer formed on the
substrate 10 will be described. - The semiconductor
light emitting device 101 according to this embodiment includes, for example, a nitride semiconductor formed on thesubstrate 10 made of sapphire. - Namely, for example, metal organic chemical vapor deposition may be used to form, on the substrate 10 having a surface made of a sapphire c-plane, a sequentially stacked structure including a high carbon-concentration first AlN buffer layer (having a carbon concentration of 3×1018 cm−3 to 5×1020 cm−3) with a thickness of 3 nm to 20 nm, a high-purity second AlN buffer layer (having a carbon concentration of 1×1016 cm−3 to 3×1018 cm−3) with a thickness of 2 μm, a non-doped GaN buffer layer with a thickness of 3 μm, a Si-doped n-type GaN contact layer (having a Si concentration of 1×1018 cm−3 to 5×1018 cm−3) with a thickness of 4 μm, a Si-doped n-type Al0.10Ga0.90N cladding layer (having a Si concentration of 1×1018 cm−3) with a thickness 0.02 μm, a light emitting layer having a multiple quantum well structure of three alternately stacked periods of a Si-doped n-type Al0.11Ga0.89N barrier layer (having a Si concentration of 1.1 to 1.5×1019 cm−3) and a GaInN light emitting layer (having a wavelength of 380 nm) with a thickness 0.075 μm, a final Al0.11Ga0.89N barrier layer of a multiple quantum well (having a Si concentration of 1.1 to 1.5×1019 cm−3) with a thickness 0.01 μm, a Si-doped n-type Al0.11Ga0.89N layer (having a Si concentration of 0.8 to 1.0×1019 cm−3) with a thickness of 0.01 μm, a non-doped Al0.11Ga0.89N spacer layer with a thickness of 0.02 μm, a Mg-doped p-type Al0.28Ga0.72N cladding layer (having a Mg concentration of 1×1019 cm−3) with a thickness of 0.02 μm, a Mg-doped p-type GaN contact layer (having a Mg concentration of 1×1019 cm−3) with a thickness of 0.1 μm, and a high-concentration Mg-doped p-type GaN contact layer (having a Mg concentration of 2×1020 cm−3) with a thickness of 0.02 μm.
- Here, the n-
type semiconductor layer 1 illustrated inFIG. 2A may include the high carbon-concentration first AlN buffer layer, the high-purity second AlN buffer layer, the non-doped GaN buffer layer, the Si-doped n-type GaN contact layer, and the Si-doped n-type Al0.10Ga0.90N cladding layer recited above. - The
light emitting layer 3 illustrated inFIG. 2A may include the final Al0.11Ga0.89N barrier layer of the multiple quantum well and the light emitting layer having the multiple quantum well structure formed of three alternately stacked periods of the Si-doped n-type Al0.11Ga0.89N barrier layer and the GaInN light emitting layer (having a wavelength of 380 nm) recited above. - The p-
type semiconductor layer 2 illustrated inFIG. 2A may include the Mg-doped p-type Al0.28Ga0.72N cladding layer, the Mg-doped p-type GaN contact layer, and the high-purity Mg-doped p-type GaN contact layer recited above. - Increasing the Mg concentration of the Mg-doped p-type GaN contact layer to about 1×1020 cm−3 improves the ohmic contact characteristics with the p-side electrode. However, a semiconductor light emitting diode differs from a semiconductor laser diode in that there is a risk of deterioration of characteristics due to Mg diffusion due to the short distance between the contact layer and the
light emitting layer 4. Therefore, by utilizing the increased contact surface area between the p-side electrode 4 and the contact layer and the lower current density during operation, the Mg concentration can be kept at about 1×1019 cm−3 without greatly harming the electrical characteristics. Thereby, Mg diffusion can be prevented, and light emission characteristics can be improved. - The high carbon-concentration first AlN buffer layer acts to relieve effects of crystal types different from the substrate and particularly reduce screw dislocations.
- The surface of the high-purity second AlN buffer layer flattens at the atomic level. Although defects of the non-doped GaN buffer layer grown thereon can be thereby reduced, to this end, it is favorable that the film thickness of the high-purity second AlN buffer layer is thicker than 1 μm. To prevent warp due to strain, it is desirable that the thickness of the high-purity second AlN buffer layer is not greater than 4 μm. The high-purity second AlN buffer layer is not limited to AlN, AlxGa1-xN (0.8≦x≦1) may be used, and the warp of the wafer can be compensated.
- The non-doped GaN buffer layer performs the role of reducing defects by performing three-dimensional island growth on the high-purity second AlN buffer layer. It is necessary for the average film thickness of the non-doped GaN buffer layer to be not less than 2 μm to allow flattening of the growth surface. A total film thickness of the non-doped GaN buffer layer of 4 to 10 μm is appropriate from the aspect of reproducibility and reduction of warp.
- By utilizing such buffer layers, defects can be reduced to about one-tenth of those in conventional low-temperature growth AlN buffer layers. Such technology enables high-concentration Si doping of the n-type GaN contact layer and the manufacture of highly efficient semiconductor light emitting devices emitting light even in the ultraviolet band. Absorption of light in the buffer layers also can be suppressed by reducing the crystal defects of the buffer layers.
- The formation of the electrodes on the semiconductor layers of the semiconductor
light emitting device 101 will now be described. - The following description assumes the case where the p-
side electrode 4 of the semiconductorlight emitting device 101 includes a first metal film (first p-side electrode film) 4 a made of metal having not necessarily high-efficiency reflecting characteristics and a second metal film (second p-side electrode film) 4 b forming a high-efficiency reflecting film provided between the first metal film (the first p-side electrode film) 4 a and the p-type semiconductor layer 2. -
FIGS. 5A to 5C are sequential schematic cross-sectional views illustrating manufacturing processes of the semiconductor light emitting device applicable to the method for manufacturing the semiconductor light emitting apparatus according to the first embodiment of the invention. -
FIGS. 6A to 6C are sequential schematic cross-sectional views continuing fromFIG. 5C . - First, as illustrated in
FIG. 5A , dry etching using a mask is performed on a region of a portion of the p-type semiconductor layer 2 to remove the p-type semiconductor layer 2 and thelight emitting layer 3 until the n-type contact layer is exposed at the surface. At this time, the difference in levels between the p-type semiconductor layer 2 and the n-type semiconductor layer 1 can be patterned into a tapered configuration having any angle by optimizing the mask configuration and the dry etching conditions. Restated, a tapered portion it can be provided on the semiconductor layers. Here, the angle between the layer surfaces of the semiconductor layers and the inclined face of the tapered portion it is referred to as “taper angle θ (°).” That is, the smaller the taper angle θ, the more the inclination of the tapered portion it forms a moderate inclined face; and a taper angle θ of 90 degrees has a side face in which the stepped region of the n-type semiconductor layer 1 and the p-type semiconductor layer 2 has a stairstep configuration. - The n-
side electrode 7 having ohmic characteristics is then formed as illustrated inFIG. 5B . Namely, a not-illustrated patterned lift-off resist is formed on the exposed n-type contact layer, a vacuum vapor deposition apparatus is used to form, for example; a Ti/Al/Ni/Au film having a film thickness of 500 nm as the n-side electrode 7 for the ohmic contact region; and after lift-off, sintering is performed at 550° C. in a nitrogen atmosphere. - Continuing as illustrated in
FIG. 5C , the p-side electrode 4 is formed by forming a not-illustrated patterned lift-off resist on the p-type contact layer; using a vacuum vapor deposition apparatus to form, for example, a Ag film with a film thickness of 200 nm as the second p-side electrode film 4 b; and after lift-off, performing sintering at 350° C. in a nitrogen atmosphere. - Then, as illustrated in
FIG. 6A , a not-illustrated patterned lift-off resist is formed on the semiconductor layers, and a Pt/Au film, for example, having a film thickness of 500 nm is formed as the first p-side electrode film 4 a on the region in which the Ag film was formed. Thereby, the p-side electrode 4 is formed. - Continuing as illustrated in
FIG. 6B , a vacuum vapor deposition apparatus is used to form, for example, five pairs combining a SiO2 film and a TiO2 film for a total of ten layers on the semiconductor layers. - Then, as illustrated in
FIG. 6C , a not-illustrated patterned resist is formed thereupon and ammonium fluoride processing is performed to remove the dielectrics recited above to expose the p-side electrode 4 and the n-side electrode 7 to form the dielectric stackedfilm 11. The dielectrics recited above may be removed by a dry etching process by using a patterned resist as a mask. - Thus, by forming the dielectric stacked
film 11, the dielectric stackedfilm 11 protrudes further than the n-side electrode 7 and the p-side electrode 4, and the protrudingportions 11 b provided on at least a portion of the rims of each of the n-side electrode 7 and the p-side electrode 4 form the n-side guide portion 12 a and the p-side guide portion 12 b. - Continuing, individual light emitting devices are formed by cleavage or cutting by a diamond blade, etc. Thus, the semiconductor
light emitting device 101 illustrated inFIGS. 2A and 2B is formed. - Thereafter, as described in regard to
FIGS. 1A and 1B , the semiconductorlight emitting device 101 is mounted on the mountingmember 13 to fabricate the semiconductorlight emitting apparatus 201. - The semiconductor
light emitting device 101 will now be described further. - As described above, the dielectric stacked
film 11 may be formed using, for example, five pairs combining the stacked films of the first dielectric layer (e.g., SiO2) and the second dielectric layer (e.g., TiO2) as dielectrics having at least two types with different refractive indexes, that is, a stacked film made of a total of, for example, ten layers of dielectric layers. - In such a case, the film thicknesses of each of the first dielectric layer and the second dielectric layer may be set to a thickness of λ/(4n), where n is the refractive index of each of the first dielectric layer and the second dielectric layer and λ is the light emission wavelength of the
light emitting layer 3. - In other words, the dielectric stacked
film 11 includes multiple first dielectric layers having a first refractive index alternately stacked with multiple second dielectric layers having a second refractive index different from the first refractive index, the thickness of each of the first dielectric layers being substantially λ/(4n1) and the thickness of each of the second dielectric layers being substantially λ/(4n2), where n1 is the first refractive index, n2 is the second refractive index, and λ is the light emission wavelength of thelight emitting layer 3. - In the dielectric stacked
film 11, a higher refractive index ratio of the combined dielectrics and a greater number of combined layers (pairs) having different refractive indexes result in a higher reflectance and a wider margin with respect to film thickness and/or wavelength. -
FIGS. 7A and 7B are graphs illustrating characteristics of the semiconductor light emitting device to which the method for manufacturing the semiconductor light emitting apparatus according to the first embodiment of the invention is applicable. - Namely,
FIGS. 7A and 7B illustrate simulation results of the reflectance of light emitted by GaN and perpendicularly incident on the dielectric stackedfilm 11.FIG. 7A illustrates the dependency of the reflectance on the refractive index ratio.FIG. 7B illustrates the dependency of the reflectance on the number of pairs. The refractive index ratio of the dielectrics of the dielectric stackedfilm 11 combining two types is plotted on the horizontal axis ofFIG. 7A . The number of pairs of the dielectrics of the dielectric stackedfilm 11 combining two types is plotted on the horizontal axis ofFIG. 7B . The reflectance is plotted on the vertical axes ofFIGS. 7A and 7B . - In these simulations, parameters are changed using the properties of the materials of the dielectric stacked
film 11 of the semiconductorlight emitting device 101 described above. - For both the refractive index ratio and the number of pairs illustrated in
FIGS. 7A and 7B , values of the reflectance near 100% can be obtained by appropriately selecting the conditions. - For example, as illustrated in
FIG. 7A , it is desirable to use a refractive index ratio of not less than 1.4 to obtain a reflectance of 95% or higher. - As illustrated in
FIG. 7B , it is desirable to use a number of pairs of not less than 3 to obtain a reflectance of 95% or higher. - The more the angle of the light from the GaN incident on the dielectric stacked
film 11 inclines from the perpendicular, the more the reflectance increases. Total reflection is obtained at a threshold angle. - Selecting design conditions from such properties can provide a dielectric stacked
film 11 that functions as a reflecting film having better performance than a metal reflecting film. By utilizing such a dielectric stackedfilm 11, improvement of the light extraction efficiency can be expected. The design reflectance of the dielectric stackedfilm 11 of the semiconductorlight emitting device 101 of this specific example is 99.7%. - The emitted light incident on the semiconductor layer cross sections disposed on either side of the
light emitting layer 3 is affected by the film thickness in the direction normal to the dielectric stackedfilm 11 formed on the semiconductor layer cross sections. Therefore, unless the taper angle is 0°, the light is affected in a direction shifted such that the dielectric stackedfilm 11 is thinner than the design film thickness. The smaller the taper angle, the more the dielectric stacked film of the semiconductor layer cross sections functions as designed. -
FIG. 8 is a graph illustrating the characteristic of the semiconductor light emitting device to which the method for manufacturing the semiconductor light emitting apparatus according to the first embodiment of the invention is applicable. - Namely,
FIG. 8 illustrates the calculation results of the relationship between the taper angle and the reflectance of the dielectric stackedfilm 11. The taper angle is plotted on the horizontal axis, and the reflectance of the dielectric stackedfilm 11 is plotted on the vertical axis.FIG. 8 illustrates the calculation results using the design conditions described above in regard to the semiconductorlight emitting device 101. - As illustrated in
FIG. 8 , although high reflecting characteristics are obtained in the case where the taper angle θ is about 40 degrees or smaller, the film thickness of the dielectric stackedfilm 11 is too thin when the taper angle θ is larger than 40 degrees. Therefore, the high reflecting characteristics are not obtained as designed. - The margin for high reflecting characteristics with respect to the taper angle is wider for a larger refractive index ratio of the two types of stacked dielectrics.
- Providing the tapered
portion 1 t can prevent separation of the dielectric stackedfilm 11 due to the different levels of the semiconductor layer cross sections disposed on either side of thelight emitting layer 3. The tapered portion it functions as a region that changes the angle of emitted light repeatedly reflected inside the semiconductor layers without being extracted. Therefore, the extraction efficiency is improved. - The taper angle θ of the tapered portion it may be appropriately established based on the device surface area and light emission characteristics of the semiconductor light emitting device, the patterning precision, and the like.
- The dielectric stacked
film 11 may include an oxide, nitride, oxynitride, or the like including at least one of silicon (Si), aluminum (Al), zirconium (Zr), titanium (Ti), niobium (Nb), tantalum (Ta), magnesium (Mg), hafnium (Hf), cerium (Ce), zinc (Zn), or the like. It is favorable that the total film thickness of the stacked dielectric films is not less than 50 nm to ensure insulative properties and not more than 1,000 nm to suppress cracks in the dielectric films. - Increasing the film thickness of the dielectric stacked
film 11 as much as possible improves the performance as a positioning guide. Therefore, it is more favorable that the film thickness of the dielectric stackedfilm 11 is 1,000 nm to 10,000 nm. - To reduce stress between different types of materials due to heat released during device operation, it is favorable that the first layer of the dielectric stacked
film 11 on the semiconductor layer side is a material having a linear coefficient of thermal expansion near to those of the semiconductor layers. For example, in the case where the semiconductor layers are GaN, it is favorable to use, for example, SiN as the first layer of the dielectric stackedfilm 11 on the semiconductor layer side. - Even when the total film thickness of the dielectric stacked
film 11 is increased, stacking different types of dielectrics can relieve the stress in the interior. Therefore, compared to a single layer, damage such as cracks do not occur easily; stress on the semiconductor layers can also be relieved; and therefore the performance as the positioning guide improves and the reliability also improves. - In particular, stacking dielectrics under tensile stress and compressive stress promotes stress-relieving effects.
- The dielectric stacked
film 11 forming the positioning guides is provided around theconnection members 14 and therefore can prevent excessive spreading of the connection members (the solder) during the heating of the mounting process. Thereby, the design degrees of freedom of the surface area, film thickness, etc., of the connection members (the solder) 14 increase; the degrees of freedom of the wettability with respect to the electrodes increase; and rapid mounting is possible. - The semiconductor light emitting device to which the method for manufacturing the semiconductor light emitting apparatus of this embodiment is applicable is made of at least the semiconductor layers including the n-type semiconductor layer, the p-type semiconductor layer, and the light emitting layer disposed therebetween. Although the materials of the semiconductor layers are not particularly limited, a gallium nitride compound semiconductor such as, for example, AlxGa1-x-yInyN (x≧0, y≧0, and x+y≦1) may be used. Although the methods for forming such semiconductor layers are not particularly limited, technology such as, for example, metal organic chemical vapor deposition, molecular beam epitaxy, and the like may be used.
- Although the substrate material of the semiconductor light emitting device to which the method for manufacturing the semiconductor light emitting apparatus of this embodiment is applicable is not particularly limited, general substrates such as sapphire, SiC, GaN, GaAs, and Si may be used. The substrate may ultimately be removed.
- As described above, the p-
side electrode 4 may be formed of the second p-side electrode film 4 b including at least silver or silver alloy and the first p-side electrode film 4 a made of metal not including at least silver or silver alloy. The material of the second p-side electrode film 4 b may be a single layer of silver, or may be an alloy layer including metal other than silver and aluminum. - Although there is a trend for the reflection efficiencies of normal metal single-layer films in the visible light band to decline as the wavelengths become shorter in the ultraviolet band of 400 nm and below, silver has high reflecting efficiency characteristics for light in the ultraviolet band of 370 nm to 400 nm. Therefore, in the case of a semiconductor light emitting device emitting ultraviolet light including a second p-
side electrode film 4 b of silver or silver alloy, it is desirable that the component ratio of silver of the second p-side electrode film 4 b on the semiconductor interface side is high. It is favorable that the film thickness of the second p-side electrode film 4 b is not less than 100 nm to ensure the light reflection efficiency. - In the case where silver or silver alloy is used in the second p-
side electrode film 4 b, the risk of insulation defects and breakdown voltage defects due to migration from the silver or the silver alloy decreases as the distance between the second p-side electrode film 4 b and the n-side electrode 7 increases. The light extraction efficiency increases as the p-side electrode 4 facing the n-side electrode 7 proximal to the center of the device is formed up to the end of the p-type contact layer as much as the process conditions such as lithography precision permit. When considering the current path from the second p-side electrode film 4 b to the n-side electrode 7, there is a trend for the current to concentrate in the region having the shortest distance between the second p-side electrode film 4 b and the n-side electrode 7. Therefore, it is favorable to design the region having the shortest distance between the second p-side electrode film 4 b and the n-side electrode 7 facing each other to be as long as possible to relieve the electric field concentration. - When viewed as a plane, the longer the length of the region where the second p-
side electrode film 4 b and the n-side electrode 7 face each other, the longer the current path from the second p-side electrode film 4 b to the n-side electrode 7. Therefore, the electric field concentration is relieved and deterioration of the second p-side electrode film 4 b is suppressed. The surface area and configuration of the second p-side electrode film 4 b and the distance between the second p-side electrode film 4 b and the n-side electrode 7 may be appropriately decided considering such effects. - The first p-
side electrode film 4 a is formed of metal not including silver and electrically contacts the second p-side electrode film 4 b. The material of the first p-side electrode film 4 a is not particularly limited and may include a single-layer or multi-layer metal film, a metal alloy layer, a single-layer or multi-layer conductive oxide film, or a combination thereof. The film thickness of the first p-side electrode film 4 a is not particularly limited, and may be selected, for example, between 100 nm to 1,000 nm. - The material of the n-
side electrode 7 is not particularly limited. A conductive single-layer or multi-layer film providing an ohmic electrode for an n-type semiconductor may be used. The film thickness of the n-side electrode 7 is not particularly limited, and may be between 5 nm and 1,000 nm. - Other pads may be provided on the p-
side electrode 4 and the n-side electrode 7. The film thickness of the pads is not particularly limited, and may be, for example, between 1,000 nm and 10,000 nm. Forming the pads can improve wettability during welding with the connection members (e.g., the solder) 14 and reduce the risk of excessive alloying reactions between the electrodes and the connection members (e.g., the solder) 14. - Using a crystal on a monocrystalline AlN buffer layer can reduce crystal defects to realize high luminous efficiency even in wavelength bands shorter than 400 nm where efficiency normally declines.
- In the case where an amorphous or polycrystalline AlN layer is provided to relieve differences in crystal types on the sapphire substrate, the buffer layer itself forms a light absorbing body. Therefore, the light extraction efficiency of the light emitting device declines undesirably. Conversely, by forming the n-
type semiconductor layer 1, thelight emitting layer 3, and the p-type semiconductor layer 2 on the substrate made of sapphire via the high carbon concentration monocrystalline AlN buffer layer and the high-purity monocrystalline AlN buffer layer, the buffer layers do not easily form light absorbing bodies, and crystal defects can be drastically reduced. Thereby, the light absorbing bodies in the crystal can be drastically reduced. In such a case, it is possible for the emitted light to repeatedly be reflected many times inside the crystal, resulting in better effects from increasing the reflecting region of the electrode formation surface. Due to such effects, improvement of the light emission intensity can be expected. -
FIGS. 9A and 9B are schematic cross-sectional views illustrating the structure of a semiconductor light emitting device of a comparative example. - The dielectric stacked
film 11 is not provided in a semiconductorlight emitting device 90 of the comparative example illustrated inFIGS. 9A and 9B . In other words, SiO2 of 400 nm, for example, is formed as a not-illustrated single layer dielectric film instead of the dielectric stackedfilm 11. Therefore, no differences in levels to the n-side electrode 7 and to the p-side electrode 4 are provided, and no protruding portions forming guide portions are provided. - The electrodes of the semiconductor
light emitting device 90 having such a configuration are formed as follows. - First, to form the n-
side electrode 7, a patterned lift-off resist is formed on the exposed n-type contact layer; a vacuum vapor deposition apparatus is used to form the n-side electrode 7 having a film thickness of 500 nm made of, for example, Ti/Al/Ni/Au as an ohmic contact region; and sintering is performed at 550° C. in a nitrogen atmosphere. - To form the p-
side electrode 4, a patterned lift-off resist is formed on the semiconductor layers; a vacuum vapor deposition apparatus is used to form a Ag film having a film thickness of 200 nm as the second p-side electrode film 4 b on the p-type contact layer; and after lift-off, sintering is performed at 350° C. in a nitrogen atmosphere. A similarly patterned lift-off resist is formed on the semiconductor layers, and a Pt/Au film having a film thickness of 500 nm of the first p-side electrode film 4 a is formed to cover the region in which the Ag film of the second p-side electrode film 4 b is formed. - Continuing, individual light emitting devices are formed by cleavage or cutting by a diamond blade, etc. Thus, the semiconductor
light emitting device 90 of the comparative example is fabricated. - The method for mounting the semiconductor
light emitting device 90 having such a configuration on the mountingmember 13 is described below. - First, a process that mounts the semiconductor
light emitting device 90 on the mountingmember 13 uses a collet or the like to move the semiconductorlight emitting device 90 above the mountingmember 13. After aligning the connection members (the solder) 14 on the mountingmember 13 with the electrodes, the semiconductorlight emitting device 90 is pressed onto the mountingmember 13. Then, the temperature of the mounting member is increased to at least the melting point of the connection members (the solder) 14, and the connection members (the solder) 14 are welded to the p-side electrode 4 and the n-side electrode 7, respectively. - In this comparative example, the relative positions of the semiconductor
light emitting device 90 and the mountingmember 13 are determined by the alignment precision of, for example, a motor that moves the collet. Therefore, the mounting precision is poor. Also, in the case where the speed of moving the device is increased to increase the takt time, the mounting precision gets worse further. To accommodate the poor mounting precision, it is necessary to improve the alignment margin by making the electrodes of the semiconductorlight emitting device 90 mutually distal, enlarging the surface area of the n-side electrode 7, etc. As a result, the degrees of freedom of the electrode design decrease, and it is not always possible to select the optimal electrode structure in regard to the light extraction efficiency and the light output. - Conversely, according to this embodiment, the dielectric stacked
film 11 is utilized as a positioning guide to easily provide a high mounting precision. Therefore, the degrees of freedom of the electrode design increase. Simultaneously, the dielectric stackedfilm 11 can be used as a high-efficiency reflecting film. Due to such effects, the light extraction efficiency and the light output can be improved. - Thus, the method for manufacturing the semiconductor light emitting apparatus according to this embodiment can perform high-precision and high-speed assembly of a semiconductor light emitting apparatus having high light extraction efficiency.
-
FIG. 10 is a schematic cross-sectional view illustrating the configuration of another semiconductor light emitting apparatus manufactured by the manufacturing processes of the semiconductor light emitting apparatus according to the first embodiment of the invention. - In a semiconductor
light emitting apparatus 202 illustrated inFIG. 10 , the connection members 14 (the n-side connection member 14 a and the p-side connection member 14 b) cover a portion of the dielectric stackedfilm 11. - In other words, the semiconductor light emitting apparatus 202 according to this embodiment includes the semiconductor light emitting device 101 including the stacked structure unit 1 s including the n-type semiconductor layer (first semiconductor layer) 1, the p-type semiconductor layer (second semiconductor layer) 2, and the light emitting layer 3 provided between the first semiconductor layer and the second semiconductor layer, the n-side electrode (first electrode) 7 provided on the major surface 1 a of the stacked structure unit is to connect to the first semiconductor layer, the p-side electrode (second electrode) 4 provided on the major surface 1 a of the stacked structure unit 1 s to connect to the second semiconductor layer 2, and the dielectric stacked film 11 provided on the first semiconductor layer and the second semiconductor layer of the major surface 1 a not covered by the first electrode and the second electrode, formed of multiple stacked dielectric films having different refractive indexes, and including the protruding portion 11 b erected on at least a portion of a rim of at least one of the first and second electrodes; and the mounting member 13 provided to face the major surface 1 a of the semiconductor light emitting device 101 and including the connection member 14, the connection member 14 welded to the at least one of the first electrode and the second electrode and covering a portion of the protruding portion 11 b.
- Thus, the connection member 14 (e.g., solder), as shown in
FIG. 10 , covers a portion of the protrudingportion 11 b of the dielectric stackedfilm 11 and thereby prevents, for example, moisture and the like from entering from the interface between the dielectric stackedfilm 11 and theconnection member 14, reaching the n-side electrode 7 and/or the p-side electrode 4, and causing deterioration of the electrodes. - To manufacture the semiconductor
light emitting apparatus 202, the welding step S130 of the method for manufacturing the semiconductor light emitting apparatus according to this embodiment illustrated inFIG. 4 includes covering a portion of the protrudingportion 11 b of the dielectric stackedfilm 11 with theconnection member 14. - At this time, it is necessary that the
connection member 14 fixes the semiconductorlight emitting device 101 and the mountingmember 13 using a pattern having high precision to prevent electrical shorts between the n-side electrode 7 and the p-side electrode 4. - As in the method for manufacturing the semiconductor light emitting apparatus according to this embodiment, the semiconductor
light emitting device 101 and the mountingmember 13 are assembled by using the protrudingportion 11 b formed of the dielectric stackedfilm 11 as a guide, that is, fitting theconnection member 14 into therecess 11 c defined by the protrudingportion 11 b. The assembly precision is thereby increased. Therefore, the precision of the configuration of theconnection member 14 is high after assembling and fixing the semiconductorlight emitting device 101 and the mountingmember 13. Thereby, theconnection member 14 can cover a portion of the dielectric stackedfilm 11 with high precision. - In other words, the low assembly precision of the comparative example in which the dielectric stacked
film 11 is not provided unfortunately results in electrical shorts between the n-side electrode 7 and the p-side electrode 4 in the case of an excessive amount of theconnection member 14. In the case of a scant amount of theconnection member 14, deterioration of the electrodes cannot be prevented. - Further, in the manufacturing method of the comparative example in which the dielectric stacked
film 11 is provided but not used as a guide during assembly, the assembly precision is low. Therefore, in the case of an excessive amount of theconnection member 14, theconnection member 14 flows and is disposed on portions on the dielectric stackedfilm 11 other than the regions to be covered, unfortunately resulting in electrical shorts between the n-side electrode 7 and the p-side electrode 4. On the other hand, in the case of a scant amount of theconnection member 14, theconnection member 14 cannot cover the prescribed region of the dielectric stackedfilm 11, and the effect of preventing the deterioration of the electrodes described above cannot be obtained. Furthermore, in the case where the precision is low and the amount of theconnection member 14 is small, theconnection member 14 cannot be sufficiently filled into the interior of therecess 11 c defined by the dielectric stackedfilm 11, a gap occurs, the deterioration of the electrodes cannot be prevented, and the reliability is poor. - Conversely, according to the method for manufacturing the semiconductor light emitting apparatus according to this embodiment as described above, the dielectric stacked
film 11 is used as a positioning guide during assembly. Therefore, the precision is high, and theconnection member 14 can cover a portion of the dielectric stackedfilm 11 from above to provide the prescribed configuration and good precision. Thereby, a semiconductor light emitting apparatus having high reliability can be realized. In the semiconductorlight emitting apparatus 202 according to this embodiment, theconnection member 14 covers a portion of the dielectric stackedfilm 11 from above with the prescribed configuration and good precision. Therefore, the reliability is high. -
FIG. 11 is a schematic view illustrating the configuration of another semiconductor light emitting device applicable to the manufacturing processes of the semiconductor light emitting apparatus according to the first embodiment of the invention. -
FIGS. 12A to 12C are sequential schematic cross-sectional views illustrating manufacturing processes of another semiconductor light emitting device applicable to the method for manufacturing the semiconductor light emitting apparatus according to the first embodiment of the invention. -
FIGS. 13A to 13C are sequential schematic cross-sectional views continuing fromFIG. 12C . - In another semiconductor
light emitting device 102 applicable to the method for manufacturing the semiconductor light emitting apparatus according to this embodiment illustrated inFIG. 11 , adielectric film 11 a is provided between the dielectric stackedfilm 11 and the n-type semiconductor layer 1 and between the dielectric stackedfilm 11 and the p-type semiconductor layer 2. Thedielectric film 11 a has a better ability than the dielectric stackedfilm 11 to cover differences in levels. Thereby, even in the case where the semiconductor layer cross sections disposed on either side of thelight emitting layer 3 are perpendicular (have a taper angle θ of 90°), the cross section thereof can be covered well by thedielectric film 11 a. Otherwise, the semiconductorlight emitting device 102 is similar to the semiconductorlight emitting device 101 described above, and a description is omitted. - Although details are omitted in
FIG. 11 , the p-side electrode 4 includes the first p-side electrode film 4 a and the second p-side electrode film 4 b provided between the first p-side electrode film 4 a and the p-type semiconductor layer 2. - Such a semiconductor
light emitting device 102 is fabricated as follows. - First, as illustrated in
FIG. 12A , dry etching using a mask is performed on a region of a portion of the p-type semiconductor layer 2 to remove the p-type semiconductor layer 2 and thelight emitting layer 3 until the n-type contact layer is exposed at the surface. - Then, as illustrated in
FIG. 12B , SiO2 forming thedielectric film 11 a having a film thickness of 200 nm is formed on the semiconductor layers using a thermal CVD apparatus. By using the thermal CVD apparatus, a film having a good ability to cover steps can be formed, the ability to cover perpendicular cross sections is good, and thedielectric film 11 a can be formed. - Continuing as illustrated in
FIG. 12C , the n-side electrode 7 having ohmic characteristics is formed. Namely, a not-illustrated patterned lift-off resist is formed on the semiconductor layers and a portion of the SiO2 film on the exposed n-type contact layer is removed by ammonium fluoride processing. The SiO2 film is removed and a vacuum vapor deposition apparatus is used to form the n-side electrode 7 made of, for example, a Ti/Al/Ni/Au film having a film thickness of 500 nm as an ohmic contact region on the exposed n-type contact layer, and sintering is performed at 550° C. in a nitrogen atmosphere. - Then, to form the p-
side electrode 4 illustrated inFIG. 13A , a not-illustrated patterned lift-off resist is formed on the semiconductor layers and a portion of the SiO2 film on the p-type contact layer is removed by ammonium fluoride processing. A patterned lift-off resist is then formed on the p-type contact layer; a vacuum vapor deposition apparatus is used to form a Ag film, for example, with a film thickness of 200 nm as the second p-side electrode film 4 b; and after lift-off, sintering is performed at 350° C. in a nitrogen atmosphere. - Then, as illustrated in
FIG. 13B , a patterned lift-off resist is formed on the semiconductor layers, a Pt/Au film, for example, is formed with a film thickness of 500 nm as the first p-side electrode film 4 a in the region in which the Ag film is formed, and the p-side electrode 4 is formed. - Continuing, a not-illustrated patterned lift-off resist is formed on the semiconductor layers, a vacuum vapor deposition apparatus is used to form, for example, five pairs combining a SiO2 film and a TiO2 film for a total of ten layers on the semiconductor layers, and the dielectric stacked
film 11 is formed by lift-off. Each of the film thicknesses are λ/(4n), where n is the refractive index of each film and A is the light emission wavelength of thelight emitting layer 3. - Thus, by forming the dielectric stacked
film 11, the p-side guide portion 12 b for the p-side electrode 4 and the p-side guide portion 12 a for the n-side electrode 7 can be formed to be used during mounting. - Thus, in the semiconductor
light emitting device 102, thedielectric film 11 a formed by, for example, thermal CVD has a better ability than the dielectric stackedfilm 11 to cover differences in levels and therefore can be formed to cover even steep differences in levels of the semiconductor layer cross sections disposed on either side of thelight emitting layer 3. Therefore, it is unnecessary to pattern the differences in levels of the semiconductor layer cross sections disposed on either side of thelight emitting layer 3 into a tapered configuration, and simpler and fewer semiconductor layer patterning processes can be used. - Further, by protecting the p-type contact layer and the n-type contact layer from above by the
dielectric film 11 a prior to forming the n-side electrode 7 and the p-side electrode 4, contamination adhering at the interface between the electrodes and the semiconductor layers during the electrode formation steps can be drastically reduced. Therefore, the reliability, yield, electrical characteristics, and light emission characteristics can be improved. - Forming the
dielectric film 11 a results in almost no effects on the reflectance of the dielectric stackedfilm 11 and thedielectric film 11 a. Using multiple stacked pairs of dielectrics having different refractive indexes for the dielectric stackedfilm 11 can provide a sufficiently high design reflectance. In the semiconductorlight emitting device 102 of this specific example, the design reflectance of the region in which thedielectric film 11 a and the dielectric stackedfilm 11 are stacked together is 99.5%. -
FIG. 14 is a schematic view illustrating the configuration of another semiconductor light emitting device applicable to the manufacturing processes of the semiconductor light emitting apparatus according to the first embodiment of the invention. - In another semiconductor
light emitting device 103 applicable to the method for manufacturing the semiconductor light emitting apparatus according to this embodiment illustrated inFIG. 14 , the p-side electrode 4 includes the first p-side electrode film 4 a and the second p-side electrode film 4 b provided between the first p-side electrode film 4 a and the p-type semiconductor layer 2, and further includes a third p-side electrode film 4 c provided between the first p-side electrode film 4 a and the second p-side electrode film 4 b. Otherwise, the semiconductorlight emitting device 103 is similar to the semiconductorlight emitting device 101 described above, and a description is omitted. - The third p-
side electrode film 4 c functions to prevent the materials included in the first p-side electrode film 4 a, the solder of theconnection member 14 during mounting, and the like from diffusing into the second p-side electrode film 4 b, and prevent the materials included in the first p-side electrode film 4 a and/or theconnection members 14 from reacting with the materials included in the second p-side electrode film 4 b. The third p-side electrode film 4 c electrically connects to the first p-side electrode film 4 a and the second p-side electrode film 4 b. - The third p-
side electrode film 4 c may include a material that does not react with silver or does not actively diffuse into silver. - Materials which may be used as the third p-
side electrode film 4 c include single-layer films or stacked films of a high melting-point metal usable as the diffusion prevention layer such as, for example, vanadium (V), chrome (Cr), iron (Fe), cobalt (Co), nickel (Ni), niobium (Nb), molybdenum (Mo), ruthenium (Ru), rhodium (Rh), tantalum (Ta), tungsten (W), rhenium (Re), osmium (Os), iridium (Ir), and platinum (Pt). - More favorable metals that have a high work function and easily provide ohmic contact with the p-GaN contact layer to prevent problems even in the case where some diffusion into the second p-
side electrode film 4 b occurs include iron (Fe), cobalt (Co), nickel (Ni), rhodium (Rh), tungsten (W), rhenium (Re), osmium (Os), iridium (Ir), and platinum (Pt). - In the case where the third p-
side electrode film 4 c is a single-layer film, it is favorable that the film thickness thereof is in the range of 5 nm to 200 nm to maintain the film state. The film thickness for a stacked film is not particularly limited, and may be, for example, between 10 nm and 10,000 nm. - By providing the third p-
side electrode film 4 c as a diffusion prevention layer, mounting is possible at higher temperatures. Therefore, the mounting rate can be increased to improve cost competitiveness. - The
dielectric film 11 a described in regard to the semiconductorlight emitting device 102 may be provided in the semiconductorlight emitting device 103. -
FIG. 15 is a schematic view illustrating the configuration of another semiconductor light emitting device applicable to the manufacturing processes of the semiconductor light emitting apparatus according to the first embodiment of the invention. - In another semiconductor
light emitting device 104 applicable to the method for manufacturing the semiconductor light emitting apparatus according to this embodiment illustrated inFIG. 15 ,conductive guide films 12 m are provided on the p-side electrode 4 and the n-side electrode 7 not covered by the dielectric stackedfilm 11, the upper face (on the side of the dielectric stackedfilm 11 opposite the semiconductor layers) of the dielectric stackedfilm 11 of the peripheral portions of the p-side electrode 4 and the n-side electrode 7, and on the side faces of the dielectric stackedfilm 11. Otherwise, the semiconductorlight emitting device 104 is similar to the semiconductorlight emitting device 101 described above, and a description is omitted. - The n-
side guide portion 12 a is formed of the dielectric stackedfilm 11 and theconductive guide film 12 m at the peripheral portion of the n-side electrode 7. The p-side guide portion 12 b is formed of the dielectric stackedfilm 11 and theconductive guide film 12 m at the peripheral portion of the p-side electrode 4. In other words, theconductive guide films 12 m provided on the side faces of the dielectric stackedfilm 11 define therecesses 11 c, and theconnection members 14 fit into therecesses 11 c to assemble the semiconductorlight emitting device 104 and the mountingmember 13. - Thus, even in the case where the
conductive guide films 12 m are provided on portions of the protruding portions of the dielectric stackedfilm 11, theconnection members 14 can be brought into contact and joined with the at least one of the n-side electrode 7 and the p-side electrode 4 using the protrudingportions 11 b of the dielectric stackedfilm 11 as guides. - The
conductive guide films 12 m may be formed by, for example, forming a patterned lift-off resist on the semiconductor layers after forming the dielectric stackedfilm 11 and forming, for example, a Ti/Pt/Au film with a film thickness of 500 nm as theconductive guide films 12 m. - By providing the
conductive guide films 12 m in the n-side guide portion 12 a and the p-side guide portion 12 b to cover a portion of the upper face and the side faces of the dielectric stackedfilm 11, damage of the guide portions due to shocks during contact of the connection members 14 (e.g., the solder) with the n-side guide portion 12 a and the p-side guide portion 12 b or applied vibrations can be prevented during mounting. In the case of using solder for theconnection member 14, the wettability against the solder is improved by providing theconductive guide films 12 m as the effective bonding surface area with the solder is increased. Thereby, easiness of mounting process is improved and the mounting speed can be further improved, then a cost competitive edge can be further improved. - It is favorable that the cross section of the dielectric stacked
film 11 has a tapered configuration for easy formation of theconductive guide films 12 m on the side faces of the dielectric stackedfilm 11. - By protecting the dielectric stacked
film 11 forming the n-side guide portion 12 a and the p-side guide portion 12 b by theconductive guide films 12 m, vibrations under more vigorous conditions can be used, and the semiconductorlight emitting device 104 can be moved in a wider range. Therefore, the mounting rate can be increased more to further improve cost competitiveness. -
FIG. 16 is a flowchart illustrating the manufacturing processes of a semiconductor light emitting apparatus according to a second embodiment of the invention. - As illustrated in
FIG. 16 , the method for manufacturing the semiconductor light emitting apparatus according to the second embodiment of the invention further includes the following processes prior to step S110 illustrated inFIG. 4 . - Namely, first, the first semiconductor layer (the n-type semiconductor layer 1), the
light emitting layer 3, and the second semiconductor layer (the p-type semiconductor layer 2) are stacked on the substrate 10 (step S210). - Then, a portion of the second semiconductor layer and the light emitting layer is removed to expose the first semiconductor layer (step S220).
- The first electrode (the n-side electrode 7) is then formed on the exposed first semiconductor layer (step S230).
- The second electrode (the p-side electrode 4) is then formed on the second semiconductor layer (step S240).
- Multiple types of dielectric films having different refractive indexes are alternately stacked on the exposed first semiconductor layer and the second semiconductor layer not covered by the first electrode and the second electrode to form the dielectric stacked film 11 (step S250).
- The methods described in regard to
FIGS. 5A to 6C , for example, may be used in step S210 to step S250 recited above. - Thus, according to the method for manufacturing the semiconductor light emitting apparatus according to this embodiment, the dielectric stacked
film 11 forming the guide portions is formed; the semiconductor light emitting device and the mountingmember 13 can be assembled utilizing the guide portions; high-precision and high-speed assembly is possible; and a semiconductor light emitting apparatus having high light extraction efficiency can be provided. - Steps S210 to S250 recited above are interchangeable within the extent of technical feasibility and may be implemented simultaneously. For example, steps S230 and S240 which form the n-
side electrode 7 and the p-side electrode 4 are interchangeable and may be implemented simultaneously. -
FIG. 17 is a flowchart illustrating the manufacturing processes of a semiconductor light emitting apparatus according to a third embodiment of the invention. - As illustrated in
FIG. 17 , the method for manufacturing the semiconductor light emitting apparatus according to the third embodiment of the invention further includes the following processes prior to step S110 illustrated inFIG. 4 . - Namely, the first semiconductor layer (the n-type semiconductor layer 1), the
light emitting layer 3, and the second semiconductor layer (the p-type semiconductor layer 2) are stacked on the substrate 10 (step S310). - Then, a portion of the second semiconductor layer and a portion of the light emitting layer are removed to expose the first semiconductor layer (step S320).
- Dielectric films having different refractive indexes are then alternately stacked on a portion of the exposed first semiconductor layer and a portion of the second semiconductor layer to form the dielectric stacked film 11 (step S330).
- The first electrode (the n-side electrode 7) is then formed on the first semiconductor layer not covered by the dielectric stacked film 11 (step S340).
- The second electrode (the p-side electrode 4) is then formed on the second semiconductor layer not covered by the dielectric stacked film 11 (step S350).
- The methods described in regard to
FIGS. 5A to 6C , for example, may be modified and used in step S310 to step S350 recited above. -
FIG. 18 is a flowchart illustrating the manufacturing processes of a semiconductor light emitting apparatus according to a fourth embodiment of the invention. - As illustrated in
FIG. 18 , thedielectric film 11 a described above is provided in the method for manufacturing the semiconductor light emitting apparatus according to the fourth embodiment of the invention after exposing the first semiconductor layer and prior to forming the dielectric stackedfilm 11. - Namely, as illustrated in
FIG. 18 , thedielectric film 11 a, having a better ability than the dielectric stackedfilm 11 to cover the first semiconductor layer and the second semiconductor layer, is formed on a portion of the uncovered first semiconductor layer and a portion of the second semiconductor layer (step S225) between the process that exposes the first semiconductor layer (step S220) and the process that forms the dielectric stacked film (step S250). - In this specific example, step S225 is implemented between the process that exposes the first semiconductor layer (step S220) and the process that forms the first electrode (step S230). In such a case, the order of step S230 to step S250 is interchangeable, and the processes can be implemented simultaneously.
- The methods described in regard to
FIG. 12A toFIG. 13C , for example, may be used in step S210 to step S250 recited above. -
FIG. 19 is a flowchart illustrating the manufacturing processes of a semiconductor light emitting apparatus according to a fifth embodiment of the invention. - As illustrated in
FIG. 19 , thedielectric film 11 a described above is provided by the method for manufacturing the semiconductor light emitting apparatus according to the fifth embodiment of the invention after exposing the first semiconductor layer and prior to forming the dielectric stackedfilm 11. - Namely, as illustrated in
FIG. 19 , thedielectric film 11 a, having a better ability than the dielectric stackedfilm 11 to cover the first semiconductor layer and the second semiconductor layer, is formed on a portion of the exposed first semiconductor layer and a portion of the second semiconductor layer (step S325) between the process that exposes the first semiconductor layer (step S320) and the process that forms the dielectric stacked film (step S330). - The order of step S330 to step S350 recited above is interchangeable, and the processes may be implemented simultaneously.
- In the methods for manufacturing the semiconductor light emitting apparatus according to the third to fifth embodiments recited above, the dielectric stacked
film 11 including the protrudingportions 11 b forming the guide portions are formed; the semiconductor light emitting device and the mountingmember 13 can be assembled utilizing the guide portions; high-precision and high-speed assembly is possible; and a semiconductor light emitting apparatus having high light extraction efficiency can be provided. - In the method for manufacturing the semiconductor light emitting apparatus according to the second to fifth embodiments recited above, the process that exposes the first semiconductor layer (step S220 or step S320) may include forming the tapered portion it on the stacked
structure unit 1 s to incline with respect to the layer surface of the stackedstructure unit 1 s. Thereby, the covering of the dielectric stackedfilm 11 formed thereon improves, the reflecting abilities of the dielectric stackedfilm 11 can be improved by the difference in levels, and a semiconductor light emitting apparatus having high light extraction efficiency can be provided. - The methods for manufacturing the semiconductor light emitting apparatus according to the first to fifth embodiments further include a process that forms the
connection member 14 on a mounting substrate, theconnection member 14 having a configuration in the plane parallel to the surface of the mounting substrate smaller than a configuration of the at least one of the n-side electrode 7 and the p-side electrode 4 surrounded by the protrudingportion 11 b. Thereby, theconnection member 14 of the prescribed configuration can be formed, and the semiconductor light emitting device and the mountingmember 13 can be assembled with high precision. At this time, the height of theconnection member 14 is higher than the height of the protrudingportion 11 b. -
FIG. 20 is a schematic cross-sectional view illustrating the structure of another semiconductor light emitting apparatus manufactured by the method for manufacturing the semiconductor light emitting apparatus according to the embodiments of the invention. - A semiconductor
light emitting apparatus 301 of this specific example is a white LED combining any of the semiconductor light emitting devices according to the embodiments recited above and a fluorescent material. That is, the semiconductorlight emitting apparatus 301 according to this embodiment includes any of the semiconductor light emitting devices recited above and a fluorescent material layer irradiated by light emitted by the semiconductor light emitting device. - The following description assumes the semiconductor
light emitting device 101 recited above combined with a fluorescent material. - In the semiconductor
light emitting apparatus 301 according to this embodiment illustrated inFIG. 20 , reflectingfilms 23 are provided on inner faces of acontainer 22 made of ceramic and the like. The reflectingfilms 23 are provided separately on an inner side face and a bottom face of thecontainer 22. The reflectingfilm 23 is made of, for example, aluminum and the like. The semiconductorlight emitting device 101 is disposed on the reflectingfilm 23 provided on the bottom portion of thecontainer 22 via asubmount 24. Thesubmount 24 is the mountingmember 13. - As described above, the semiconductor
light emitting device 101 and the submount 24 (the mounting member 13) are connected and fixed by the connection members 14 (e.g., solder). - Bonding by a bonding agent, solder, etc., may be used to fix the semiconductor
light emitting device 101, thesubmount 24, and the reflectingfilm 23. - Patterned electrodes are formed on the surface of the
submount 24 on the semiconductor light emitting device side to insulate the p-side electrode 4 and the n-side electrode 7 of the semiconductorlight emitting device 101. Each of the electrodes is connected to a not-illustrated electrode provided on thecontainer 22 bybonding wires 26. The connection is made to the portion between the reflectingfilm 23 of the inner side face and the reflectingfilm 23 of the bottom face. - A first
fluorescent material layer 211 including a red fluorescent material is provided to cover the semiconductorlight emitting device 101 and thebonding wire 26. A secondfluorescent material layer 212 including a blue, green, or yellow fluorescent material is formed on the firstfluorescent material layer 211. Alid 27 made of silicon resin is provided on the fluorescent material layer. - The first
fluorescent material layer 211 includes a resin and the red fluorescent material dispersed in the resin. - The red fluorescent material may include, for example, an activating substance of trivalent Eu (Eu3+) in a main material such as Y2O3, YVO4, or Y2(P, V)O4. In other words, Y2O3:Eu3+, YVO4:Eu3+, and the like may be used as the red fluorescent material. The molar concentration of Eu3+ may be 1% to 10%. LaOS, Y2(P, V)O4, and the like may be used as the main material of the red fluorescent material in addition to Y2O3 and YVO4. Mn4+ and the like may be used in addition to Eu3+. In particular, absorption at 380 nm increases by adding a small amount of Bi with trivalent Eu to the YVO4 base material. Therefore, the luminous efficiency increases even more. A silicon resin and the like, for example, may be used as the resin.
- The second
fluorescent material layer 212 includes a resin and at least one of a blue fluorescent material, a green fluorescent material, and a yellow fluorescent material dispersed in the resin. For example, a fluorescent material combining a blue fluorescent material and a green fluorescent material, a fluorescent material combining a blue fluorescent material and a yellow fluorescent material, or a fluorescent material combining a blue fluorescent material, a green fluorescent material, and a yellow fluorescent material may be used. - (Sr, Ca)10(PO4)6Cl2:Eu2+, BaMg2Al16O27:Eu2+, and the like, for example, may be used as the blue fluorescent material.
- Y2SiO5:Ce3+, Tb3+ having centers of light emission of trivalent Tb, for example, may be used as the green fluorescent material. In such a case, energy is transmitted from Ce ions to Tb ions to improve the excitation efficiency. Sr4Al14O25:Eu2+ and the like, for example, may be used as the green fluorescent material.
- Y3Al5:Ce3+ and the like, for example, may be used as the yellow fluorescent material.
- A silicon resin and the like, for example, may be used as the resin.
- In particular, trivalent Tb has a sharp light emission around 550 nm at which visibility is at a maximum and thereby markedly improves the luminous efficiency when combined with the sharp red light emission of trivalent Eu.
- According to the semiconductor
light emitting apparatus 301 according to this embodiment, ultraviolet light of 380 nm emitted by the semiconductorlight emitting device 101 is radiated to thesubstrate 10 side of the semiconductorlight emitting device 101 and efficiently excites the fluorescent materials recited above included in the fluorescent material layers by utilizing reflections of the reflectingfilms 23. - For example, the fluorescent material recited above having centers of light emission of trivalent Eu and the like included in the first
fluorescent material layer 211 converts light into light having a narrow wavelength distribution around 620 nm to efficiently produce red visible light. - The blue, green, and yellow fluorescent materials included in the second
fluorescent material layer 212 are efficiently excited and efficiently produce blue, green, and yellow visible light. - Mixing such colors produces white light and light of other various colors with high efficiency and good color rendition.
- The method for manufacturing the semiconductor
light emitting apparatus 301 according to this embodiment will now be described. - The methods described above may be used in the processes that fabricate the semiconductor
light emitting device 101. Therefore, the processes after completion of the semiconductorlight emitting device 101 will now be described. - First, a metal film forming the reflecting
film 23 is formed on the inner face of thecontainer 22 by, for example, sputtering. The metal film is patterned, and the reflectingfilm 23 is left on each of the inner side face and the bottom face of thecontainer 22. - Then, the methods described in regard to the first embodiment are used to fix the semiconductor
light emitting device 101 on the submount 24 (the mounting member 13). Thesubmount 24 is disposed and fixed on the reflectingfilm 23 on the bottom face of thecontainer 22. Bonding using a bonding agent, solder, etc., may be used for the fixation. - Continuing, each of a not-illustrated n-side electrode and p-side electrode on the
submount 24 is connected to a not-illustrated electrode provided on thecontainer 22 bybonding wires 26. - The first
fluorescent material layer 211 including the red fluorescent material is then formed to cover the semiconductorlight emitting device 101 and thebonding wires 26. The secondfluorescent material layer 212 including the blue, the green, or the yellow fluorescent material is formed on the firstfluorescent material layer 211. - The method for forming each of the fluorescent material layers may drop resin/source material mixture solutions having the fluorescent materials dispersed therein and perform heat treatment to cure the resin by thermal polymerization. It is possible to cause the fine particles of the fluorescent materials to distribute unevenly in the lower layers of the first and second fluorescent material layers 211 and 212 to appropriately control the luminous efficacy of each of the fluorescent materials by allowing the resin/source material mixture solutions including the fluorescent materials to lie for a while after dropping and prior to curing to allow the fine particles of the fluorescent materials to settle. Subsequently, the
lid 27 is provided on the fluorescent material layer, and the semiconductorlight emitting apparatus 301 according to this embodiment, that is, the white LED, is fabricated. - In the specification, “nitride semiconductor” includes all compositions of semiconductors of the chemical formula BxInyAlzGa1-x-y-zN (0≦x≦1, 0≦y≦1, 0≦z≦1, x+y+z≦1) for which each of the composition ratios x, y, and z are changed within the ranges. “Nitride semiconductor” further includes group V elements other than N (nitrogen) in the chemical formula recited above and any of various dopants added to control the conductivity type, etc.
- Hereinabove, exemplary embodiments of the invention are described with reference to specific examples. However, the invention is not limited to these specific examples. For example, one skilled in the art may appropriately select configurations, sizes, material qualities, arrangements, etc., of components of semiconductor multi-layer films, metal films, dielectric films, etc., of semiconductor light emitting devices or manufacturing methods from known art and similarly practice the invention. Such practice is included in the scope of the invention to the extent that similar effects thereto are obtained.
- Further, any two or more components of the specific examples may be combined within the extent of technical feasibility; and are included in the scope of the invention to the extent that the purport of the invention is included.
- Moreover, all methods for manufacturing semiconductor light emitting apparatuses and semiconductor light emitting apparatuses obtainable by an appropriate design modification by one skilled in the art based on methods for manufacturing the semiconductor light emitting apparatuses and the semiconductor light emitting apparatuses described above as exemplary embodiments of the invention also are within the scope of the invention to the extent that the purport of the invention is included.
- Furthermore, various modifications and alterations within the spirit of the invention will be readily apparent to those skilled in the art. All such modifications and alterations should therefore be seen as within the scope of the invention.
Claims (1)
1. A semiconductor light emitting apparatus comprising:
a semiconductor light emitting device including:
a stacked structure unit including a first semiconductor layer, a second semiconductor layer, and a light emitting layer provided between the first semiconductor layer and the second semiconductor layer;
a first electrode provided on a major surface of the stacked structure unit to connect to the first semiconductor layer;
a second electrode provided on the major surface of the stacked structure unit to connect to the second semiconductor layer;
a dielectric stacked film provided on the first semiconductor layer and the second semiconductor layer of the major surface not covered by the first electrode and the second electrode, formed of stacked dielectric films; and
a conductive guide film provided on at least one of a first position on the first electrode not covered by the dielectric stacked film, a second position on the second electrode not covered by the dielectric stacked film, a third position on a first upper face of the dielectric stacked film on a peripheral portion of the first electrode, a fourth position on a second upper face of the dielectric stacked film on a peripheral portion of the second electrode, and a fifth position on a side faces of the dielectric stacked film.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/809,751 US20150333231A1 (en) | 2008-08-28 | 2015-07-27 | Method for manufacturing semiconductor light emitting apparatus and semiconductor light emitting apparatus |
Applications Claiming Priority (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008-220144 | 2008-08-28 | ||
JP2008220144A JP5426124B2 (en) | 2008-08-28 | 2008-08-28 | Semiconductor light emitting device manufacturing method and semiconductor light emitting device |
US12/549,048 US8338844B2 (en) | 2008-08-28 | 2009-08-27 | Semiconductor light emitting apparatus having stacked reflective dielectric films |
US13/679,109 US8890193B2 (en) | 2008-08-28 | 2012-11-16 | Semiconductor light emitting apparatus having stacked reflective dielectric films |
US14/506,201 US9130106B2 (en) | 2008-08-28 | 2014-10-03 | Method for manufacturing semiconductor light emitting apparatus by mounting semiconductor light emitting device having stacked dielectric films having different refractive indexes on mounting member |
US14/809,751 US20150333231A1 (en) | 2008-08-28 | 2015-07-27 | Method for manufacturing semiconductor light emitting apparatus and semiconductor light emitting apparatus |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US14/506,201 Division US9130106B2 (en) | 2008-08-28 | 2014-10-03 | Method for manufacturing semiconductor light emitting apparatus by mounting semiconductor light emitting device having stacked dielectric films having different refractive indexes on mounting member |
Publications (1)
Publication Number | Publication Date |
---|---|
US20150333231A1 true US20150333231A1 (en) | 2015-11-19 |
Family
ID=41723985
Family Applications (4)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/549,048 Active 2030-06-22 US8338844B2 (en) | 2008-08-28 | 2009-08-27 | Semiconductor light emitting apparatus having stacked reflective dielectric films |
US13/679,109 Active US8890193B2 (en) | 2008-08-28 | 2012-11-16 | Semiconductor light emitting apparatus having stacked reflective dielectric films |
US14/506,201 Active US9130106B2 (en) | 2008-08-28 | 2014-10-03 | Method for manufacturing semiconductor light emitting apparatus by mounting semiconductor light emitting device having stacked dielectric films having different refractive indexes on mounting member |
US14/809,751 Abandoned US20150333231A1 (en) | 2008-08-28 | 2015-07-27 | Method for manufacturing semiconductor light emitting apparatus and semiconductor light emitting apparatus |
Family Applications Before (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/549,048 Active 2030-06-22 US8338844B2 (en) | 2008-08-28 | 2009-08-27 | Semiconductor light emitting apparatus having stacked reflective dielectric films |
US13/679,109 Active US8890193B2 (en) | 2008-08-28 | 2012-11-16 | Semiconductor light emitting apparatus having stacked reflective dielectric films |
US14/506,201 Active US9130106B2 (en) | 2008-08-28 | 2014-10-03 | Method for manufacturing semiconductor light emitting apparatus by mounting semiconductor light emitting device having stacked dielectric films having different refractive indexes on mounting member |
Country Status (2)
Country | Link |
---|---|
US (4) | US8338844B2 (en) |
JP (1) | JP5426124B2 (en) |
Families Citing this family (47)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7915629B2 (en) | 2008-12-08 | 2011-03-29 | Cree, Inc. | Composite high reflectivity layer |
US9461201B2 (en) | 2007-11-14 | 2016-10-04 | Cree, Inc. | Light emitting diode dielectric mirror |
US8368100B2 (en) * | 2007-11-14 | 2013-02-05 | Cree, Inc. | Semiconductor light emitting diodes having reflective structures and methods of fabricating same |
JP5426124B2 (en) | 2008-08-28 | 2014-02-26 | 株式会社東芝 | Semiconductor light emitting device manufacturing method and semiconductor light emitting device |
US8529102B2 (en) * | 2009-04-06 | 2013-09-10 | Cree, Inc. | Reflector system for lighting device |
KR101065402B1 (en) * | 2009-08-13 | 2011-09-16 | 삼성모바일디스플레이주식회사 | Organic light emitting diode display |
WO2011027418A1 (en) * | 2009-09-01 | 2011-03-10 | 株式会社 東芝 | Semiconductor light emitting element and semiconductor light emitting device |
US9362459B2 (en) | 2009-09-02 | 2016-06-07 | United States Department Of Energy | High reflectivity mirrors and method for making same |
US9435493B2 (en) * | 2009-10-27 | 2016-09-06 | Cree, Inc. | Hybrid reflector system for lighting device |
US9012938B2 (en) | 2010-04-09 | 2015-04-21 | Cree, Inc. | High reflective substrate of light emitting devices with improved light output |
US9105824B2 (en) | 2010-04-09 | 2015-08-11 | Cree, Inc. | High reflective board or substrate for LEDs |
JP5390472B2 (en) * | 2010-06-03 | 2014-01-15 | 株式会社東芝 | Semiconductor light emitting device and manufacturing method thereof |
US8471282B2 (en) * | 2010-06-07 | 2013-06-25 | Koninklijke Philips Electronics N.V. | Passivation for a semiconductor light emitting device |
JP5759790B2 (en) * | 2010-06-07 | 2015-08-05 | 株式会社東芝 | Manufacturing method of semiconductor light emitting device |
JP4875185B2 (en) * | 2010-06-07 | 2012-02-15 | 株式会社東芝 | Optical semiconductor device |
US8764224B2 (en) | 2010-08-12 | 2014-07-01 | Cree, Inc. | Luminaire with distributed LED sources |
JP4872014B1 (en) * | 2010-08-31 | 2012-02-08 | Jx日鉱日石金属株式会社 | Laminated structure and manufacturing method thereof |
US9070851B2 (en) | 2010-09-24 | 2015-06-30 | Seoul Semiconductor Co., Ltd. | Wafer-level light emitting diode package and method of fabricating the same |
KR101746004B1 (en) * | 2010-10-29 | 2017-06-27 | 엘지이노텍 주식회사 | Light emitting device |
JP4940363B1 (en) * | 2011-02-28 | 2012-05-30 | 株式会社東芝 | Semiconductor light emitting device and semiconductor light emitting device |
US8680556B2 (en) | 2011-03-24 | 2014-03-25 | Cree, Inc. | Composite high reflectivity layer |
US10243121B2 (en) | 2011-06-24 | 2019-03-26 | Cree, Inc. | High voltage monolithic LED chip with improved reliability |
US8686429B2 (en) | 2011-06-24 | 2014-04-01 | Cree, Inc. | LED structure with enhanced mirror reflectivity |
US9728676B2 (en) | 2011-06-24 | 2017-08-08 | Cree, Inc. | High voltage monolithic LED chip |
CN102856458B (en) * | 2011-06-28 | 2015-05-06 | 夏普株式会社 | Photosemiconductor element and method for manufacturing photosemiconductor element |
JP5394461B2 (en) * | 2011-06-28 | 2014-01-22 | シャープ株式会社 | Method for manufacturing optical semiconductor element |
KR101939333B1 (en) * | 2011-10-07 | 2019-01-16 | 서울바이오시스 주식회사 | Light emitting diode package |
JP6038698B2 (en) * | 2013-03-22 | 2016-12-07 | 日本碍子株式会社 | Ceramic member and member for semiconductor manufacturing equipment |
EP3043395B1 (en) * | 2013-09-05 | 2018-11-07 | Panasonic Intellectual Property Management Co., Ltd. | Light-emitting device |
JP5712368B2 (en) * | 2013-09-05 | 2015-05-07 | パナソニックIpマネジメント株式会社 | Light emitting device |
TW201511347A (en) * | 2013-09-10 | 2015-03-16 | Lingsen Precision Ind Ltd | LED package structure and manufacturing method thereof |
US9954144B2 (en) * | 2014-01-10 | 2018-04-24 | Cree, Inc. | Wafer level contact pad solder bumping for surface mount devices with non-planar recessed contacting surfaces |
JP6334945B2 (en) * | 2014-02-17 | 2018-05-30 | スタンレー電気株式会社 | Semiconductor light emitting device, semiconductor light emitting element, and method for manufacturing semiconductor light emitting device |
CN104681684A (en) * | 2014-12-30 | 2015-06-03 | 深圳市华星光电技术有限公司 | Light emitting device and light emitting device package |
US10658546B2 (en) | 2015-01-21 | 2020-05-19 | Cree, Inc. | High efficiency LEDs and methods of manufacturing |
US10062820B2 (en) * | 2015-05-15 | 2018-08-28 | Panasonic Intellectual Property Management Co., Ltd. | Interposer |
KR102373677B1 (en) | 2015-08-24 | 2022-03-14 | 쑤저우 레킨 세미컨덕터 컴퍼니 리미티드 | Light emittng device |
CN205944139U (en) | 2016-03-30 | 2017-02-08 | 首尔伟傲世有限公司 | Ultraviolet ray light -emitting diode spare and contain this emitting diode module |
TWI778010B (en) * | 2017-01-26 | 2022-09-21 | 晶元光電股份有限公司 | Light-emitting device |
JP7233859B2 (en) * | 2017-06-20 | 2023-03-07 | 旭化成エレクトロニクス株式会社 | infrared light emitting diode |
KR102607596B1 (en) * | 2018-05-11 | 2023-11-29 | 삼성전자주식회사 | Semiconductor light emitting device and semiconductor light emitting device package using the same |
DE102018118824A1 (en) * | 2018-08-02 | 2020-02-06 | Osram Opto Semiconductors Gmbh | SEMICONDUCTOR COMPONENT WITH A STRESS COMPENSATION LAYER AND METHOD FOR PRODUCING A SEMICONDUCTOR COMPONENT |
JP6806218B2 (en) * | 2018-10-31 | 2021-01-06 | 日亜化学工業株式会社 | Light emitting device, light emitting module, light emitting device and manufacturing method of light emitting module |
CN109768141A (en) * | 2018-12-24 | 2019-05-17 | 华灿光电(浙江)有限公司 | A kind of light emitting diode flip-chip, its epitaxial wafer and preparation method |
US11387392B2 (en) * | 2018-12-25 | 2022-07-12 | Nichia Corporation | Light-emitting device and display device |
US11764328B2 (en) * | 2019-08-13 | 2023-09-19 | Epistar Corporation | Light-emitting diode package having bump formed in wriggle shape |
TWI726685B (en) * | 2020-04-16 | 2021-05-01 | 錼創顯示科技股份有限公司 | Micro light-emitting device display apparatus |
Family Cites Families (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3557033B2 (en) * | 1995-03-24 | 2004-08-25 | 三洋電機株式会社 | Semiconductor light emitting device and method of manufacturing the same |
JPH10247747A (en) * | 1997-03-05 | 1998-09-14 | Toshiba Corp | Semiconductor light emitting device and manufacture thereof |
JP4411695B2 (en) | 1999-07-28 | 2010-02-10 | 日亜化学工業株式会社 | Nitride semiconductor light emitting device |
JP2001085749A (en) * | 1999-09-16 | 2001-03-30 | Nichia Chem Ind Ltd | Mounting method of nitride semiconductor light-emitting element |
JP4897133B2 (en) * | 1999-12-09 | 2012-03-14 | ソニー株式会社 | Semiconductor light emitting device, method for manufacturing the same, and mounting substrate |
US6630689B2 (en) * | 2001-05-09 | 2003-10-07 | Lumileds Lighting, U.S. Llc | Semiconductor LED flip-chip with high reflectivity dielectric coating on the mesa |
KR100799857B1 (en) * | 2003-10-27 | 2008-01-31 | 삼성전기주식회사 | Electrode structure and semiconductor light-emitting device provided with the same |
JP4580633B2 (en) * | 2003-11-14 | 2010-11-17 | スタンレー電気株式会社 | Semiconductor device and manufacturing method thereof |
CN100459189C (en) * | 2003-11-19 | 2009-02-04 | 日亚化学工业株式会社 | Semiconductor element and manufacturing method for the same |
JP2005158904A (en) * | 2003-11-21 | 2005-06-16 | Toyoda Gosei Co Ltd | Iii-v nitride semiconductor element and light emitting device |
EP2023411A1 (en) * | 2006-05-01 | 2009-02-11 | Mitsubishi Chemical Corporation | Integrated semiconductor light-emitting device and its manufacturing method |
JP2007324585A (en) * | 2006-05-02 | 2007-12-13 | Mitsubishi Chemicals Corp | Semiconductor light-emitting element |
EP2023412A1 (en) * | 2006-05-02 | 2009-02-11 | Mitsubishi Chemical Corporation | Semiconductor light-emitting device |
US7652374B2 (en) * | 2006-07-31 | 2010-01-26 | Chi Wah Kok | Substrate and process for semiconductor flip chip package |
JP2008071910A (en) * | 2006-09-13 | 2008-03-27 | Mitsubishi Cable Ind Ltd | Nitride semiconductor light emitting diode element and its manufacturing method |
US7791096B2 (en) * | 2007-06-08 | 2010-09-07 | Koninklijke Philips Electronics N.V. | Mount for a semiconductor light emitting device |
JP5139005B2 (en) * | 2007-08-22 | 2013-02-06 | 株式会社東芝 | Semiconductor light emitting device and semiconductor light emitting device |
US8115222B2 (en) * | 2008-01-16 | 2012-02-14 | Rohm Co., Ltd. | Semiconductor light emitting device and fabrication method for the semiconductor light emitting device |
JP5305790B2 (en) * | 2008-08-28 | 2013-10-02 | 株式会社東芝 | Semiconductor light emitting device |
JP5426124B2 (en) * | 2008-08-28 | 2014-02-26 | 株式会社東芝 | Semiconductor light emitting device manufacturing method and semiconductor light emitting device |
-
2008
- 2008-08-28 JP JP2008220144A patent/JP5426124B2/en active Active
-
2009
- 2009-08-27 US US12/549,048 patent/US8338844B2/en active Active
-
2012
- 2012-11-16 US US13/679,109 patent/US8890193B2/en active Active
-
2014
- 2014-10-03 US US14/506,201 patent/US9130106B2/en active Active
-
2015
- 2015-07-27 US US14/809,751 patent/US20150333231A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
US20130146914A1 (en) | 2013-06-13 |
US20150056729A1 (en) | 2015-02-26 |
JP2010056323A (en) | 2010-03-11 |
JP5426124B2 (en) | 2014-02-26 |
US8890193B2 (en) | 2014-11-18 |
US8338844B2 (en) | 2012-12-25 |
US9130106B2 (en) | 2015-09-08 |
US20100051995A1 (en) | 2010-03-04 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9130106B2 (en) | Method for manufacturing semiconductor light emitting apparatus by mounting semiconductor light emitting device having stacked dielectric films having different refractive indexes on mounting member | |
US8513687B2 (en) | Semiconductor light emitting device and semiconductor light emitting apparatus | |
US9093614B2 (en) | Semiconductor light emitting element and semiconductor light emitting device | |
US7615794B2 (en) | Semiconductor light emitting device and semiconductor light emitting apparatus | |
JP5305790B2 (en) | Semiconductor light emitting device | |
US20130299847A1 (en) | Semiconductor light emitting device and method for manufacturing same | |
JP5052636B2 (en) | Semiconductor light emitting device | |
US7902565B2 (en) | Semiconductor light emitting device and method for manufacturing same | |
JP5334601B2 (en) | Semiconductor light emitting diode element and semiconductor light emitting device | |
EP2023412A1 (en) | Semiconductor light-emitting device | |
US20140353705A1 (en) | Semiconductor light emitting element, method of manufacturing semiconductor light emitting element, semiconductor light emitting device and substrate | |
WO2006082687A1 (en) | GaN LIGHT EMITTING DIODE AND LIGHT EMITTING DEVICE | |
KR20090085594A (en) | Light emitting device using gan led chip | |
JP5514283B2 (en) | Semiconductor light emitting device and semiconductor light emitting device | |
JP5608762B2 (en) | Semiconductor light emitting device | |
KR20150114110A (en) | Semiconductor light emitting device | |
JPH09162488A (en) | Semiconductor laser device for large output | |
JP5851001B2 (en) | Semiconductor light emitting device | |
JP5433798B2 (en) | Semiconductor light emitting device and semiconductor light emitting device | |
JP5886899B2 (en) | Semiconductor light emitting device and semiconductor light emitting device | |
US20220416508A1 (en) | Semiconductor laser element |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |