US20150102488A1 - Printed circuit board using solder coating ball - Google Patents

Printed circuit board using solder coating ball Download PDF

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Publication number
US20150102488A1
US20150102488A1 US14/575,915 US201414575915A US2015102488A1 US 20150102488 A1 US20150102488 A1 US 20150102488A1 US 201414575915 A US201414575915 A US 201414575915A US 2015102488 A1 US2015102488 A1 US 2015102488A1
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United States
Prior art keywords
solder
pattern
substrate
circuit board
printed circuit
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Abandoned
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US14/575,915
Inventor
Jin Won Choi
Yon Ho You
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Samsung Electro Mechanics Co Ltd
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Samsung Electro Mechanics Co Ltd
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Priority to US14/575,915 priority Critical patent/US20150102488A1/en
Assigned to SAMSUNG ELECTRO-MECHANICS CO.,LTD. reassignment SAMSUNG ELECTRO-MECHANICS CO.,LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHOI, JIN WON, YOU, YON HO
Publication of US20150102488A1 publication Critical patent/US20150102488A1/en
Abandoned legal-status Critical Current

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    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
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    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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Definitions

  • the present invention relates to a printed circuit board using a solder coating-ball.
  • Methods forming the solder bump as described above may be divided into a scheme forming the solder bump by printing a solder paste on the substrate and then reflowing the solder paste, a scheme forming the solder ball by mounting a fine solder ball on the substrate, and a method forming the solder bump by injecting a melted solder into the substrate directly or using a mask.
  • the solder bump formed on the substrate as described above is melted so as to connect to a copper (Cu) pad or a solder bump formed on a chip, thereby coupling between metals.
  • the methods forming the above-mentioned solder bump may include a ball placing scheme in which the same size openings having the same size are formed on the mask and then the solder ball is squeegeed using a squeegee, such that the solder ball is mounted on input/output pad of the substrate through the mask openings, or a scheme in which a vacuum hole having the same pattern as a substrate pattern is formed at a jig and then the solder ball is picked-up at vacuum so as to be mounted on the substrate, as described in Korea Patent Laid-Open Publication No. 2008-0014143(laid-open published on Feb. 13, 2008).
  • the packaging method using the bump made of copper (Cu) using the above-mentioned plating and lithography technologies has a problem in that an interface between the solder and an electroless Cu is separated from each other due to low interface stability, such that processing stability is degraded.
  • a plating thickness deviation occurring at the time of plating copper (Cu) leads to a height deviation between the solder and the copper (Cu) bump, such that connection reliability in the packaged chip is deteriorated.
  • the present invention has been made in an effort to provide a printed circuit board improving connection reliability using a solder coating ball so as to solve the problems as mentioned above.
  • a printed circuit board manufacturing method including: (A) forming a plurality of pads and another circuit pattern on a substrate; (B) forming a second dry film pattern including opening exposing the pad; (C) mounting a solder coating ball in the opening of the second dry film pattern; (D) performing a reflow process on the solder coating ball in order to allow the solder coating ball to have a modified pattern; (E) delaminating the second dry film pattern; and (F) forming a solder pattern including the modified pattern of the solder coating ball in a solder to mount a chip on the substrate using the solder pattern.
  • Step (A) may include: (A-1) forming a first dry film pattern having openings corresponding to the pad and another circuit pattern; (A-2) filling the first dry film pattern with copper; (A-3) delaminating the first dry film pattern; and (A-4) forming a solder resist (SR) pattern enclosing a region of the pad and burying another circuit pattern.
  • Step (A-2) may be performed by any one of a chemical vapor deposition (CVD) method, a physical vapor deposition (PVD) method, a subtractive method, an additive method using an electroless copper plating or electrolytic copper plating, a semi-additive process (SAP), and a modified semi-additive process (MSAP).
  • CVD chemical vapor deposition
  • PVD physical vapor deposition
  • SAP semi-additive process
  • MSAP modified semi-additive process
  • Step (B) may include: (B-1) laminating a dry film in an uncured state on the substrate including the pad and another circuit pattern using a laminate; and (B-2) performing a patterning process on the laminated dry film.
  • the solder coating ball may be formed of a metal ball made of a conductive metal material and a solder coating film formed on an outer surface of the metal ball, wherein the solder coating film is melted and accumulated according to the reflow process to be adhered to the pad.
  • the solder coating film may be provided by plating an outer surface of the metal ball with the solder by an electroplating method.
  • a printed circuit board including: a plurality of pads formed on a substrate; a solder resist (SR) pattern enclosing a region of the pad and burying another circuit pattern; and a solder pattern including a metal pattern therein using a solder and formed on an upper surface of each of the pads.
  • SR solder resist
  • the solder pattern may include a metal pattern made of a conductive metal material in the solder.
  • a chip may be formed at the same height from an upper surface of the substrate.
  • the printed circuit board may further include a post bump between the chip and the solder pattern.
  • the solder pattern is formed to have a flat upper surface.
  • a printed circuit board manufacturing method including: (A) forming a plurality of pads and another circuit pattern on a substrate; (B) forming a second dry film pattern including an opening exposing the pad; (C) mounting a solder coating ball in the opening of the second dry film pattern; (D) performing a reflow process on the solder coating ball in order to allow the solder coating ball to have a modified pattern; (E) forming a solder pattern by filling and press-fitting the opening with a solder; and (F) delaminating the second dry film pattern.
  • step (E) the solder may be filled and press-fitted into the opening using a solder injector.
  • the solder injector may include: a storing part storing the solder supplied from an outside; a discharging hole connected to the storing part in the form of a pipe to discharge the solder; a heating part enclosing and heating the discharging hole; and a press-fitting part allowing a melted solder discharged from the discharging hole to flow a surface of the press-fitting part to be injected, wherein the solder is filled and press-fitted into the openings using the press-fitting part.
  • the storing part may be connected to a pressurization pump or a piston to discharge the solder into the discharging hole.
  • the press-fitting part may be formed of an elastic material to squeeze along with an upper surface of the second dry film provided with the openings.
  • step (G) the chip may be mounted on the substrate by correspondingly adhering a post bump of the chip to the solder pattern.
  • FIG. 1 is a cross-sectional view showing a package using a printed circuit board according to a preferred embodiment of the present invention
  • FIGS. 2A to 2F are cross-sectional views sequentially showing the process of a printed circuit board manufacturing method of a package according to a preferred embodiment of the present invention
  • FIG. 3 is a cross-sectional view showing a package using a printed circuit board according to another preferred embodiment of the present invention.
  • FIGS. 4A to 4G are cross-sectional views sequentially showing the process of a printed circuit board manufacturing method of a package according to another preferred embodiment of the present invention.
  • FIG. 1 is a cross-sectional view showing a package using a printed circuit board according to a preferred embodiment of the present invention.
  • a package using a printed circuit board includes a plurality of pads 110 formed on a substrate 100 , solder resist patterns (SR patterns) 120 enclosing the pad 110 and burying another circuit pattern on the substrate 100 , solder patterns 210 formed to include a solder on each of the pads 110 , and a chip 200 connected to the pad 110 on the substrate 100 through the solder pattern 210 to be mounted thereon.
  • SR patterns solder resist patterns
  • the SR pattern 120 encloses a pad 110 region in which the chip 200 is mounted on the substrate 100 using the solder resist and buries a plurality of circuits formed in a region except for the pad 110 region.
  • the solder pattern 210 is implemented as a form in which a conductive metal pattern 141 ′ is included in the solder and is formed between the pad 110 on the substrate 100 and the chip 200 to electrically connect therebetween.
  • the conductive metal pattern 141 ′ which is formed to support the form of the solder pattern 210 , is formed, for example, of a pattern in which a ball shape made of conductive metal materials such as copper, gold, silver, aluminum, or the like, is modified in a reflow process.
  • each of the solder patterns 210 as described above has the same volume and is formed between the pad 110 and the chip 200 , the chip 200 is packaged while having the same mounted height T from an upper surface of the substrate 100 .
  • the chip 200 is packaged while having the same mounted height (T) from the upper surface of the substrate 100 , thereby making it possible to improve connection reliability between the chip 200 and the pad 110 .
  • FIGS. 2A to 2F are cross-sectional views sequentially showing the process of a printed circuit board manufacturing method of a package according to a preferred embodiment of the present invention.
  • a plurality of pads 110 and SR patterns 120 burying other circuit patterns are first formed on a substrate 100 , as shown in FIG. 2A .
  • a first dry film pattern having openings corresponding to the pad 110 and another circuit pattern is formed.
  • the first dry film pattern may be filled with copper by methods, for example, a chemical vapor deposition (CVD) method, a physical vapor deposition (PVD) method, a subtractive method, an additive method using an electroless copper plating or electrolytic copper plating, a semi-additive process (SAP), and a modified semi-additive process (MSAP).
  • CVD chemical vapor deposition
  • PVD physical vapor deposition
  • SAP semi-additive process
  • MSAP modified semi-additive process
  • the first dry film pattern is filled with the copper and then the dry film pattern is delaminated, such that the plurality of pads 110 and another circuit pattern are formed, as shown in FIG. 2A .
  • the SR pattern 120 burying another circuit pattern formed in the region except for the pad 110 region using the solder resist is formed.
  • a second dry film pattern 130 exposing each of the pads 110 is formed, as shown in FIG. 2B .
  • the second dry film pattern first laminates a dry film in an uncured state on the substrate 100 on which the plurality of pads 110 and the SR pattern 120 are formed, using a laminate.
  • the dry film laminated on the substrate 100 is subjected to a patterning process including a lithography process, an etching process, and the like, such that a second dry film pattern 130 having openings exposing each of the pads 110 may be formed.
  • each of the openings exposing the pad 110 is mounted with a solder coating ball 140 having the same diameter, as shown in FIG. 2C .
  • the solder coating ball 140 is formed of a metal ball 141 made of a conductive metal material and a solder coating film 142 formed on the outside of the metal ball 141 .
  • the metal ball 141 is made of a conductive metal material, for example, copper, gold, silver, aluminum, or the like, and the solder coating film 142 is formed by plating the metal ball 141 as described above with the solder by a method such as electroplating, or the like.
  • solder coating ball 140 After the solder coating ball 140 is mounted, a reflow process is performed on the solder coating ball 140 , such that the metal ball 141 of the solder coating ball 140 is modified to have the conductive metal pattern 141 ′, as shown in FIG. 2D .
  • the solder coating film 142 formed on an outer surface of the metal ball 141 is melted and accumulated on a lower portion of the metal pattern 141 ′ to thereby be adhered to the pad 110 .
  • the chip 200 is mounted on the metal pattern 141 ′ having the same height t from the upper surface of the substrate 100 using the solder, as shown in FIG. 2F .
  • solder pattern 210 that the conductive metal pattern 141 ′ is included in the solder is formed and the plurality of solder patterns 210 as described above are formed between the pad 110 on the substrate 100 and the chip 200 to electrically connect therebetween.
  • the solder pattern 210 as described above has the same volume and is formed between the pad 110 and the chip 200 , the chip 200 is packaged while having the same mounted height T from the upper surface of the substrate 100 .
  • the solder pattern 210 is easily formed using the solder coating ball 140 , thereby making it possible to reduce the manufacturing cost.
  • the chip 200 is packaged while having the same mounted height (T) from the upper surface of the substrate 100 , thereby making it possible to improve the connection reliability between the chip 200 and the pad 110 .
  • FIG. 3 is a cross-sectional view showing a package using the printed circuit board according to another preferred embodiment of the present invention.
  • a package using the printed circuit board includes a plurality of pads 310 formed on a substrate 300 , a solder resist (SR) pattern layer 320 enclosing each of the pads 310 and a solder region thereon and burying another circuit pattern on the substrate 300 , solder patterns 350 including a conductive metal pattern 341 ′ on an upper surface of the SR pattern layer 320 and connected to a post bump 410 , and a chip 400 connected to the pad 310 on the substrate 300 through the solder pattern 350 and the post bump 410 to be mounted thereon.
  • SR solder resist
  • the SR pattern 320 encloses a region including each of the pads 310 and a solder of a top portion of the pad 310 on the substrate 300 using a solder resist and buries a plurality of circuits formed in another region.
  • the solder pattern 350 in which a conductive metal pattern 341 ′ is included in the solder electrically connects between the post bump 410 of the chip 400 and the pad 310 , while having a form in which the conductive metal pattern 341 ′ connected to the solder of the top portion of the pad 310 is included in an upper solder.
  • the conductive metal pattern 341 ′ which is formed to support the form of the solder pattern 350 , is formed of a pattern in which a ball shape made of metal materials, for example, copper, gold, silver, aluminum, or the like, is modified in a reflow process.
  • each of the solder patterns 350 as described above has the same volume and is connected to the post bump 410 , the chip 400 is packaged while having the same mounted height T from an upper surface of the SR pattern layer 320 .
  • the chip 400 is packaged while having the same mounted height (T) from the upper surface of the SR pattern layer 320 , thereby making it possible to improve connection reliability between the chip 400 and the pad 310 .
  • FIGS. 4A to 4G are cross-sectional views sequentially showing the process of a printed circuit board manufacturing method of a package according to another preferred embodiment of the present invention.
  • the SR pattern layer 320 exposing upper surfaces of a plurality of pads 310 and burying other circuit patterns is formed on a substrate 300 , as shown in FIG. 4A .
  • a first dry film pattern having openings corresponding to the pad 310 and another circuit pattern is formed on an upper surface of the substrate 300 .
  • the first dry film pattern may be filled with copper by methods, for example, a chemical vapor deposition (CVD) method, a physical vapor deposition (PVD) method, a subtractive method, a additive method using an electroless copper plating or electrolytic copper plating, a semi-additive process (SAP), and a modified semi-additive process (MSAP).
  • CVD chemical vapor deposition
  • PVD physical vapor deposition
  • SAP semi-additive process
  • MSAP modified semi-additive process
  • the first dry film pattern is filled with the copper and then is delaminated, such that the plurality of pads 310 and another circuit pattern are formed on the substrate 300 , as shown in FIG. 4A .
  • the SR pattern layer 320 exposing the upper surface of the pad 310 and burying another circuit pattern may be formed by applying a solder resist to the substrate 300 including the plurality of pads 310 and another circuit pattern as described above and performing a patterning process including a lithography process and an etching processes on the applied solder resist.
  • a second dry film pattern 330 exposing each of the upper surfaces of the pad 310 is formed on an upper surface of the SR pattern layer 320 , as shown in FIG. 4B .
  • a dry film in an uncured state is first laminated on the SR pattern 320 using a laminate.
  • the laminated dry film is subjected to a patterning process including a lithography process, an etching process, a cleaning process, and the like, such that the second dry film pattern 330 having openings exposing the upper surface of each of the pads 310 may be formed.
  • each of the openings exposing the upper surface of the pad 310 is mounted with a solder coating ball 340 having the same diameter, as shown in FIG. 4C .
  • the solder coating ball 340 is formed of a metal ball 341 made of a conductive metal material and a solder coating film 342 formed on the outside of the metal ball 341 .
  • the metal ball 341 is made of the conductive metal material, for example, copper, gold, silver, aluminum, or the like, and the solder coating film 342 is formed by plating the metal ball 341 with the solder by a method such as electroplating, or the like.
  • solder coating ball 340 After the solder coating ball 340 is mounted, a reflow process is performed on the solder coating ball 340 , such that the metal ball 340 of the solder coating ball 341 is modified to have the conductive metal pattern 341 ′, as shown in FIG. 4D .
  • the solder coating film 342 formed on an outer surface of the metal ball 341 is melted and accumulated on a lower portion of the metal pattern 341 ′ as the solder to thereby be adhered to the pad 310 .
  • solder is injected into the openings of the second dry film pattern 330 each provided with the metal pattern 341 ′ using a solder injector 500 .
  • solder pattern 350 in which the metal pattern 341 ′ is buried by the solder may be formed.
  • the solder injector 500 includes a storing part 510 storing the solder supplied from the outside, a discharging hole 511 connected to the storing part 510 in the form of a pipe to discharge the solder, a heating part 512 enclosing and heating the discharging hole 511 , and a press-fitting part 520 allowing a melted solder discharged from the discharging hole 511 to flow a surface to be injected.
  • the storing part 510 stores the solder supplied from the outside and includes a pressurization pump or a piston, thereby discharging the solder into the discharging hole 511 .
  • the storing part 510 is supplied with the solder in the form of a solder paste and stores a flux or the like in addition to the solder, thereby discharging them into the discharging hole 511 .
  • the heating part 512 is formed of a heat wire or a heater enclosing a circumference of the discharging hole 511 , and heats and melts the solder discharged along with the discharging hole 511 .
  • the press-fitting part 520 is a part contacting and squeegeeing the upper surface of the second dry film pattern 330 and the melted solder discharged from an end of the discharging hole 511 flows down along with a surface of the press-fitting part 520 .
  • the press-fitting part 520 is formed of an elastic material, such that the melted solder discharged from the end of the discharging hole 511 flows to be filled and press-fitted in the openings of the second dry film pattern 330 .
  • the solder pattern 350 in which the metal pattern 341 ′ is buried may be formed to have a flat upper surface.
  • solder pattern 350 is cured and then the second dry film pattern 330 is delaminated, the solder pattern 350 having the same height t from the upper surface of the substrate 300 is formed as shown in FIG. 4F .
  • the solder pattern 350 is connected to a post bump 410 , such that a chip 400 is mounted so as to be electrically connected to the pad 310 on the substrate 300 .
  • the chip 400 may also be mounted to be electrically connected to the pad 310 on the substrate 300 only using the solder pattern 350 , without the post bump 410 .
  • the chip 400 is packaged while having the same mounted height from the upper surface of the SR pattern layer 320 , thereby making it possible to improve connection reliability between the chip 400 and the pad 310 .
  • the chip is packaged while having the same mounted height (T) from the upper surface of the substrate, thereby making it possible to improve the connection reliability between the chip and the pad.
  • the solder pattern is easily formed using the solder coating ball, thereby making it possible to reduce the manufacturing cost.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

Disclosed herein a printed circuit board comprising: a plurality of pads formed on a substrate; a solder resist (SR) pattern enclosing a region of the pad and burying another circuit pattern; and a solder pattern including a metal pattern therein using a solder and formed on an upper surface of each of the pads.

Description

    CROSS REFERENCE TO RELATED APPLICATION
  • This application claims the benefit of Korean Patent Application No. 10-2012-0085823, filed on Aug. 6, 2012, entitled “Packaging Method Using Solder Coating-Ball and Package Manufactured Thereby”, which is hereby incorporated by reference in its entirety into this application.
    • BACKGROUND OF THE INVENTION
  • 1. Technical Field
  • The present invention relates to a printed circuit board using a solder coating-ball.
  • 2. Description of the Related Art
  • According to the prior art, a flip chip scheme in which a solder bump is formed on a printed circuit board (PCB) and then, a device is mounted thereon to thereby package them has been increasingly used.
  • In particular, in the case of a central processing unit (CPU) and a graphic operation device operating large capacity data at a high speed, a change from a scheme connecting between a substrate and a device using a gold (Au) wire according to the prior art to the flip chip scheme in which the substrate and the device are connected by the solder bump so as to improve connection resistance has been rapidly increased.
  • Methods forming the solder bump as described above may be divided into a scheme forming the solder bump by printing a solder paste on the substrate and then reflowing the solder paste, a scheme forming the solder ball by mounting a fine solder ball on the substrate, and a method forming the solder bump by injecting a melted solder into the substrate directly or using a mask. The solder bump formed on the substrate as described above is melted so as to connect to a copper (Cu) pad or a solder bump formed on a chip, thereby coupling between metals.
  • The methods forming the above-mentioned solder bump may include a ball placing scheme in which the same size openings having the same size are formed on the mask and then the solder ball is squeegeed using a squeegee, such that the solder ball is mounted on input/output pad of the substrate through the mask openings, or a scheme in which a vacuum hole having the same pattern as a substrate pattern is formed at a jig and then the solder ball is picked-up at vacuum so as to be mounted on the substrate, as described in Korea Patent Laid-Open Publication No. 2008-0014143(laid-open published on Feb. 13, 2008).
  • However, as a pitch of the input/output pad of the substrate gradually becomes fine, a technology forming the solder bump on the input/output pad of the substrate using the solder ball or a paste according to the prior art has been gradually changed to a scheme forming the bump made of copper (Cu) using a plating and lithography technologies.
  • The packaging method using the bump made of copper (Cu) using the above-mentioned plating and lithography technologies has a problem in that an interface between the solder and an electroless Cu is separated from each other due to low interface stability, such that processing stability is degraded.
  • In addition, a plating thickness deviation occurring at the time of plating copper (Cu) leads to a height deviation between the solder and the copper (Cu) bump, such that connection reliability in the packaged chip is deteriorated.
    • SUMMARY OF THE INVENTION
  • The present invention has been made in an effort to provide a printed circuit board improving connection reliability using a solder coating ball so as to solve the problems as mentioned above.
  • According to a preferred embodiment of the present invention, there is provided a printed circuit board manufacturing method including: (A) forming a plurality of pads and another circuit pattern on a substrate; (B) forming a second dry film pattern including opening exposing the pad; (C) mounting a solder coating ball in the opening of the second dry film pattern; (D) performing a reflow process on the solder coating ball in order to allow the solder coating ball to have a modified pattern; (E) delaminating the second dry film pattern; and (F) forming a solder pattern including the modified pattern of the solder coating ball in a solder to mount a chip on the substrate using the solder pattern.
  • Step (A) may include: (A-1) forming a first dry film pattern having openings corresponding to the pad and another circuit pattern; (A-2) filling the first dry film pattern with copper; (A-3) delaminating the first dry film pattern; and (A-4) forming a solder resist (SR) pattern enclosing a region of the pad and burying another circuit pattern.
  • Step (A-2) may be performed by any one of a chemical vapor deposition (CVD) method, a physical vapor deposition (PVD) method, a subtractive method, an additive method using an electroless copper plating or electrolytic copper plating, a semi-additive process (SAP), and a modified semi-additive process (MSAP).
  • Step (B) may include: (B-1) laminating a dry film in an uncured state on the substrate including the pad and another circuit pattern using a laminate; and (B-2) performing a patterning process on the laminated dry film.
  • In step (D), the solder coating ball may be formed of a metal ball made of a conductive metal material and a solder coating film formed on an outer surface of the metal ball, wherein the solder coating film is melted and accumulated according to the reflow process to be adhered to the pad.
  • The solder coating film may be provided by plating an outer surface of the metal ball with the solder by an electroplating method.
  • According to another preferred embodiment of the present invention, there is provided a printed circuit board including: a plurality of pads formed on a substrate; a solder resist (SR) pattern enclosing a region of the pad and burying another circuit pattern; and a solder pattern including a metal pattern therein using a solder and formed on an upper surface of each of the pads.
  • The solder pattern may include a metal pattern made of a conductive metal material in the solder.
  • A chip may be formed at the same height from an upper surface of the substrate.
  • The printed circuit board may further include a post bump between the chip and the solder pattern.
  • The solder pattern is formed to have a flat upper surface.
  • The respective cross sections of upper and lower surfaces of the solder pattern are substantially same.
  • According to another preferred embodiment of the present invention, there is provided a printed circuit board manufacturing method including: (A) forming a plurality of pads and another circuit pattern on a substrate; (B) forming a second dry film pattern including an opening exposing the pad; (C) mounting a solder coating ball in the opening of the second dry film pattern; (D) performing a reflow process on the solder coating ball in order to allow the solder coating ball to have a modified pattern; (E) forming a solder pattern by filling and press-fitting the opening with a solder; and (F) delaminating the second dry film pattern.
  • In step (E), the solder may be filled and press-fitted into the opening using a solder injector.
  • The solder injector may include: a storing part storing the solder supplied from an outside; a discharging hole connected to the storing part in the form of a pipe to discharge the solder; a heating part enclosing and heating the discharging hole; and a press-fitting part allowing a melted solder discharged from the discharging hole to flow a surface of the press-fitting part to be injected, wherein the solder is filled and press-fitted into the openings using the press-fitting part.
  • The storing part may be connected to a pressurization pump or a piston to discharge the solder into the discharging hole.
  • The press-fitting part may be formed of an elastic material to squeeze along with an upper surface of the second dry film provided with the openings.
  • In step (G), the chip may be mounted on the substrate by correspondingly adhering a post bump of the chip to the solder pattern.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The above and other objects, features and advantages of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:
  • FIG. 1 is a cross-sectional view showing a package using a printed circuit board according to a preferred embodiment of the present invention;
  • FIGS. 2A to 2F are cross-sectional views sequentially showing the process of a printed circuit board manufacturing method of a package according to a preferred embodiment of the present invention;
  • FIG. 3 is a cross-sectional view showing a package using a printed circuit board according to another preferred embodiment of the present invention; and
  • FIGS. 4A to 4G are cross-sectional views sequentially showing the process of a printed circuit board manufacturing method of a package according to another preferred embodiment of the present invention.
    •  DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • The objects, features and advantages of the present invention will be more clearly understood from the following detailed description of the preferred embodiments taken in conjunction with the accompanying drawings. Throughout the accompanying drawings, the same reference numerals are used to designate the same or similar components, and redundant descriptions thereof are omitted. Further, in the following description, the terms “first”, “second”, “one side”, “the other side” and the like are used to differentiate a certain component from other components, but the configuration of such components should not be construed to be limited by the terms. Further, in the description of the present invention, when it is determined that the detailed description of the related art would obscure the gist of the present invention, the description thereof will be omitted.
  • Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings. FIG. 1 is a cross-sectional view showing a package using a printed circuit board according to a preferred embodiment of the present invention.
  • A package using a printed circuit board according to a preferred embodiment of the present invention includes a plurality of pads 110 formed on a substrate 100, solder resist patterns (SR patterns) 120 enclosing the pad 110 and burying another circuit pattern on the substrate 100, solder patterns 210 formed to include a solder on each of the pads 110, and a chip 200 connected to the pad 110 on the substrate 100 through the solder pattern 210 to be mounted thereon.
  • The SR pattern 120 encloses a pad 110 region in which the chip 200 is mounted on the substrate 100 using the solder resist and buries a plurality of circuits formed in a region except for the pad 110 region.
  • The solder pattern 210 is implemented as a form in which a conductive metal pattern 141′ is included in the solder and is formed between the pad 110 on the substrate 100 and the chip 200 to electrically connect therebetween.
  • Specifically, the conductive metal pattern 141′, which is formed to support the form of the solder pattern 210, is formed, for example, of a pattern in which a ball shape made of conductive metal materials such as copper, gold, silver, aluminum, or the like, is modified in a reflow process.
  • Since each of the solder patterns 210 as described above has the same volume and is formed between the pad 110 and the chip 200, the chip 200 is packaged while having the same mounted height T from an upper surface of the substrate 100.
  • Therefore, according to the package using the printed circuit board according to the preferred embodiment of the present invention, the chip 200 is packaged while having the same mounted height (T) from the upper surface of the substrate 100, thereby making it possible to improve connection reliability between the chip 200 and the pad 110.
  • Hereinafter, a printed circuit board manufacturing method of a package according to a preferred embodiment of the present invention will be described with reference to FIGS. 2A to 2F. FIGS. 2A to 2F are cross-sectional views sequentially showing the process of a printed circuit board manufacturing method of a package according to a preferred embodiment of the present invention.
  • With the printed circuit board manufacturing method of the package according to the preferred embodiment of the present invention, a plurality of pads 110 and SR patterns 120 burying other circuit patterns are first formed on a substrate 100, as shown in FIG. 2A.
  • Specifically, in order to form the plurality of pads 110 and another circuit patterns on the substrate 110, a first dry film pattern having openings corresponding to the pad 110 and another circuit pattern is formed.
  • Next, the first dry film pattern may be filled with copper by methods, for example, a chemical vapor deposition (CVD) method, a physical vapor deposition (PVD) method, a subtractive method, an additive method using an electroless copper plating or electrolytic copper plating, a semi-additive process (SAP), and a modified semi-additive process (MSAP).
  • As such, the first dry film pattern is filled with the copper and then the dry film pattern is delaminated, such that the plurality of pads 110 and another circuit pattern are formed, as shown in FIG. 2A.
  • Subsequently, the SR pattern 120 burying another circuit pattern formed in the region except for the pad 110 region using the solder resist is formed.
  • After the plurality of pads 110 and the SR pattern 120 burying another circuit pattern are formed on the substrate 100, a second dry film pattern 130 exposing each of the pads 110 is formed, as shown in FIG. 2B.
  • Specifically, the second dry film pattern first laminates a dry film in an uncured state on the substrate 100 on which the plurality of pads 110 and the SR pattern 120 are formed, using a laminate.
  • Next, the dry film laminated on the substrate 100 is subjected to a patterning process including a lithography process, an etching process, and the like, such that a second dry film pattern 130 having openings exposing each of the pads 110 may be formed.
  • For the second dry film pattern 130 as described above, each of the openings exposing the pad 110 is mounted with a solder coating ball 140 having the same diameter, as shown in FIG. 2C.
  • Here, the solder coating ball 140 is formed of a metal ball 141 made of a conductive metal material and a solder coating film 142 formed on the outside of the metal ball 141. The metal ball 141 is made of a conductive metal material, for example, copper, gold, silver, aluminum, or the like, and the solder coating film 142 is formed by plating the metal ball 141 as described above with the solder by a method such as electroplating, or the like.
  • After the solder coating ball 140 is mounted, a reflow process is performed on the solder coating ball 140, such that the metal ball 141 of the solder coating ball 140 is modified to have the conductive metal pattern 141′, as shown in FIG. 2D.
  • In this case, the solder coating film 142 formed on an outer surface of the metal ball 141 is melted and accumulated on a lower portion of the metal pattern 141′ to thereby be adhered to the pad 110.
  • Next, when the second dry film pattern 130 is delaminated, a structure having the same height t from the upper surface of the substrate 100 to the metal pattern 141′ is formed as shown in FIG. 2E.
  • Next, the chip 200 is mounted on the metal pattern 141′ having the same height t from the upper surface of the substrate 100 using the solder, as shown in FIG. 2F.
  • Therefore, a solder pattern 210 that the conductive metal pattern 141′ is included in the solder is formed and the plurality of solder patterns 210 as described above are formed between the pad 110 on the substrate 100 and the chip 200 to electrically connect therebetween.
  • Since the solder pattern 210 as described above has the same volume and is formed between the pad 110 and the chip 200, the chip 200 is packaged while having the same mounted height T from the upper surface of the substrate 100.
  • Therefore, according to the printed circuit board manufacturing method of the package according to the preferred embodiment of the present invention, the solder pattern 210 is easily formed using the solder coating ball 140, thereby making it possible to reduce the manufacturing cost.
  • In addition, according to the printed circuit board manufacturing method of the package according to the preferred embodiments of the present invention, the chip 200 is packaged while having the same mounted height (T) from the upper surface of the substrate 100, thereby making it possible to improve the connection reliability between the chip 200 and the pad 110.
  • Hereinafter, a package using the printed circuit board according to another embodiment of the present invention will be described with reference to FIG. 3. FIG. 3 is a cross-sectional view showing a package using the printed circuit board according to another preferred embodiment of the present invention.
  • As shown in FIG. 3, a package using the printed circuit board according to another preferred embodiment of the present invention includes a plurality of pads 310 formed on a substrate 300, a solder resist (SR) pattern layer 320 enclosing each of the pads 310 and a solder region thereon and burying another circuit pattern on the substrate 300, solder patterns 350 including a conductive metal pattern 341′ on an upper surface of the SR pattern layer 320 and connected to a post bump 410, and a chip 400 connected to the pad 310 on the substrate 300 through the solder pattern 350 and the post bump 410 to be mounted thereon.
  • The SR pattern 320 encloses a region including each of the pads 310 and a solder of a top portion of the pad 310 on the substrate 300 using a solder resist and buries a plurality of circuits formed in another region.
  • The solder pattern 350 in which a conductive metal pattern 341′ is included in the solder, electrically connects between the post bump 410 of the chip 400 and the pad 310, while having a form in which the conductive metal pattern 341′ connected to the solder of the top portion of the pad 310 is included in an upper solder.
  • Specifically, the conductive metal pattern 341′, which is formed to support the form of the solder pattern 350, is formed of a pattern in which a ball shape made of metal materials, for example, copper, gold, silver, aluminum, or the like, is modified in a reflow process.
  • Since each of the solder patterns 350 as described above has the same volume and is connected to the post bump 410, the chip 400 is packaged while having the same mounted height T from an upper surface of the SR pattern layer 320.
  • Therefore, according to the package using the printed circuit board according to another preferred embodiment of the present invention, the chip 400 is packaged while having the same mounted height (T) from the upper surface of the SR pattern layer 320, thereby making it possible to improve connection reliability between the chip 400 and the pad 310.
  • Hereinafter, a printed circuit board manufacturing method of a package according to another preferred embodiment of the present invention will be described with reference to FIGS. 4A to 4G. FIGS. 4A to 4G are cross-sectional views sequentially showing the process of a printed circuit board manufacturing method of a package according to another preferred embodiment of the present invention.
  • With the printed circuit board manufacturing method of the package according to another preferred embodiment of the present invention, the SR pattern layer 320 exposing upper surfaces of a plurality of pads 310 and burying other circuit patterns is formed on a substrate 300, as shown in FIG. 4A.
  • Specifically, in order to form the plurality of pads 310 and another circuit patterns on the substrate 310, a first dry film pattern having openings corresponding to the pad 310 and another circuit pattern is formed on an upper surface of the substrate 300.
  • Next, the first dry film pattern may be filled with copper by methods, for example, a chemical vapor deposition (CVD) method, a physical vapor deposition (PVD) method, a subtractive method, a additive method using an electroless copper plating or electrolytic copper plating, a semi-additive process (SAP), and a modified semi-additive process (MSAP).
  • As such, the first dry film pattern is filled with the copper and then is delaminated, such that the plurality of pads 310 and another circuit pattern are formed on the substrate 300, as shown in FIG. 4A.
  • The SR pattern layer 320 exposing the upper surface of the pad 310 and burying another circuit pattern may be formed by applying a solder resist to the substrate 300 including the plurality of pads 310 and another circuit pattern as described above and performing a patterning process including a lithography process and an etching processes on the applied solder resist.
  • After the SR pattern layer 320 is formed, a second dry film pattern 330 exposing each of the upper surfaces of the pad 310 is formed on an upper surface of the SR pattern layer 320, as shown in FIG. 4B.
  • Specifically, for the second dry film pattern, a dry film in an uncured state is first laminated on the SR pattern 320 using a laminate.
  • Next, the laminated dry film is subjected to a patterning process including a lithography process, an etching process, a cleaning process, and the like, such that the second dry film pattern 330 having openings exposing the upper surface of each of the pads 310 may be formed.
  • For the second dry film pattern 330 as described above, each of the openings exposing the upper surface of the pad 310 is mounted with a solder coating ball 340 having the same diameter, as shown in FIG. 4C.
  • The solder coating ball 340 is formed of a metal ball 341 made of a conductive metal material and a solder coating film 342 formed on the outside of the metal ball 341. The metal ball 341 is made of the conductive metal material, for example, copper, gold, silver, aluminum, or the like, and the solder coating film 342 is formed by plating the metal ball 341 with the solder by a method such as electroplating, or the like.
  • After the solder coating ball 340 is mounted, a reflow process is performed on the solder coating ball 340, such that the metal ball 340 of the solder coating ball 341 is modified to have the conductive metal pattern 341′, as shown in FIG. 4D.
  • In this case, the solder coating film 342 formed on an outer surface of the metal ball 341 is melted and accumulated on a lower portion of the metal pattern 341′ as the solder to thereby be adhered to the pad 310.
  • Next, the solder is injected into the openings of the second dry film pattern 330 each provided with the metal pattern 341′ using a solder injector 500.
  • As such, as the solder is injected into the openings using the solder injector 500, a solder pattern 350 in which the metal pattern 341′ is buried by the solder may be formed.
  • Here, the solder injector 500 includes a storing part 510 storing the solder supplied from the outside, a discharging hole 511 connected to the storing part 510 in the form of a pipe to discharge the solder, a heating part 512 enclosing and heating the discharging hole 511, and a press-fitting part 520 allowing a melted solder discharged from the discharging hole 511 to flow a surface to be injected.
  • The storing part 510 stores the solder supplied from the outside and includes a pressurization pump or a piston, thereby discharging the solder into the discharging hole 511. Here, the storing part 510 is supplied with the solder in the form of a solder paste and stores a flux or the like in addition to the solder, thereby discharging them into the discharging hole 511.
  • The heating part 512 is formed of a heat wire or a heater enclosing a circumference of the discharging hole 511, and heats and melts the solder discharged along with the discharging hole 511.
  • The press-fitting part 520 is a part contacting and squeegeeing the upper surface of the second dry film pattern 330 and the melted solder discharged from an end of the discharging hole 511 flows down along with a surface of the press-fitting part 520. The press-fitting part 520 is formed of an elastic material, such that the melted solder discharged from the end of the discharging hole 511 flows to be filled and press-fitted in the openings of the second dry film pattern 330.
  • Due to the press-fitting part 520, the solder pattern 350 in which the metal pattern 341′ is buried may be formed to have a flat upper surface.
  • Also, the respective cross sections of upper and lower surfaces of the solder pattern are substantially same.
  • Next, when the solder pattern 350 is cured and then the second dry film pattern 330 is delaminated, the solder pattern 350 having the same height t from the upper surface of the substrate 300 is formed as shown in FIG. 4F.
  • The solder pattern 350 is connected to a post bump 410, such that a chip 400 is mounted so as to be electrically connected to the pad 310 on the substrate 300. Of course, the chip 400 may also be mounted to be electrically connected to the pad 310 on the substrate 300 only using the solder pattern 350, without the post bump 410.
  • Therefore, the chip 400 is packaged while having the same mounted height from the upper surface of the SR pattern layer 320, thereby making it possible to improve connection reliability between the chip 400 and the pad 310.
  • According to the package using the printed circuit board according to the preferred embodiment of the present invention, the chip is packaged while having the same mounted height (T) from the upper surface of the substrate, thereby making it possible to improve the connection reliability between the chip and the pad.
  • According to the printed circuit board manufacturing method according to another preferred embodiment of the present invention, the solder pattern is easily formed using the solder coating ball, thereby making it possible to reduce the manufacturing cost.
  • Although the embodiments of the present invention have been disclosed for illustrative purposes, it will be appreciated that the present invention is not limited thereto, and those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention.
  • Accordingly, any and all modifications, variations or equivalent arrangements should be considered to be within the scope of the invention, and the detailed scope of the invention will be disclosed by the accompanying claims.

Claims (6)

What is claimed is:
1. A printed circuit board comprising:
a plurality of pads formed on a substrate;
a solder resist (SR) pattern enclosing a region of the pad and burying another circuit pattern; and
a solder pattern including a metal pattern therein using a solder and formed on an upper surface of each of the pads.
2. The printed circuit board as set forth in claim 1, wherein the solder pattern includes a metal pattern made of a conductive metal material in the solder.
3. The package as set forth in claim 1, wherein a chip is formed at the same height from an upper surface of the substrate.
4. The package as set forth in claim 1, further comprising a post bump between a chip and the solder pattern.
5. The printed circuit board as set forth in claim 1, wherein the solder pattern is formed to have a flat upper surface.
6. The printed circuit board as set forth in claim 1, wherein the respective cross sections of upper and lower surfaces of the solder pattern are substantially same.
US14/575,915 2012-08-06 2014-12-18 Printed circuit board using solder coating ball Abandoned US20150102488A1 (en)

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Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20140019173A (en) * 2012-08-06 2014-02-14 삼성전기주식회사 Packaging method using solder coating-ball and package thereby
KR102214512B1 (en) * 2014-07-04 2021-02-09 삼성전자 주식회사 Printed circuit board and semiconductor package using the same

Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080105355A1 (en) * 2003-12-31 2008-05-08 Microfabrica Inc. Probe Arrays and Method for Making
US7459345B2 (en) * 2004-10-20 2008-12-02 Mutual-Pak Technology Co., Ltd. Packaging method for an electronic element
US20100059881A1 (en) * 2008-09-05 2010-03-11 Samsung Electro-Mechanics Co., Ltd. Semiconductor package and method of manufacturing the same
US20100252926A1 (en) * 2007-09-04 2010-10-07 Kyocera Corporation Semiconductor Element, Method for Manufacturing the Same, and Mounting Structure Having the Semiconductor Element Mounted Thereon
US20100313416A1 (en) * 2008-02-29 2010-12-16 Sumitomo Bakelite Co., Ltd Method for providing solder connection, electronic equipment and method for manufacturing same
US20110074020A1 (en) * 2009-09-30 2011-03-31 Fujitsu Limited Semiconductor device and method for mounting semiconductor device
US20110285012A1 (en) * 2010-05-20 2011-11-24 Taiwan Semiconductor Manufacturing Company, Ltd. Substrate Contact Opening
US20120098130A1 (en) * 2010-10-26 2012-04-26 Xilinx, Inc. Lead-free structures in a semiconductor device
US20120252168A1 (en) * 2011-04-01 2012-10-04 International Business Machines Corporation Copper Post Solder Bumps on Substrate
US8686300B2 (en) * 2008-12-24 2014-04-01 Ibiden Co., Ltd. Printed wiring board and method for manufacturing the same
US20140312498A1 (en) * 2013-04-17 2014-10-23 Renesas Electronics Corporation Semiconductor device and method of manufacturing same
US8952531B2 (en) * 2012-08-06 2015-02-10 Samsung Electro-Mechanics Co., Ltd. Packaging method using solder coating ball and package having solder pattern including metal pattern

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040012097A1 (en) * 2002-07-17 2004-01-22 Chien-Wei Chang Structure and method for fine pitch flip chip substrate
WO2005088706A1 (en) * 2004-02-11 2005-09-22 Infineon Technologies Ag Semiconductor package with perforated substrate
US20090065936A1 (en) * 2005-03-16 2009-03-12 Jenny Wai Lian Ong Substrate, electronic component, electronic configuration and methods of producing the same
TWI413471B (en) 2006-01-27 2013-10-21 Ibiden Co Ltd Method and device for mounting solder ball
JP5259095B2 (en) * 2006-06-19 2013-08-07 新光電気工業株式会社 Semiconductor device
US7952207B2 (en) * 2007-12-05 2011-05-31 International Business Machines Corporation Flip-chip assembly with organic chip carrier having mushroom-plated solder resist opening
US8581403B2 (en) * 2008-01-30 2013-11-12 Nec Corporation Electronic component mounting structure, electronic component mounting method, and electronic component mounting board
US9345148B2 (en) * 2008-03-25 2016-05-17 Stats Chippac, Ltd. Semiconductor device and method of forming flipchip interconnection structure with bump on partial pad
KR101019151B1 (en) * 2008-06-02 2011-03-04 삼성전기주식회사 Printed Circuit Board and Manufacturing Method Thereof
JP5113114B2 (en) * 2009-04-06 2013-01-09 新光電気工業株式会社 Wiring board manufacturing method and wiring board
JP5481724B2 (en) * 2009-12-24 2014-04-23 新光電気工業株式会社 Semiconductor device embedded substrate
JP2012009586A (en) * 2010-06-24 2012-01-12 Shinko Electric Ind Co Ltd Wiring board, semiconductor device and wiring board manufacturing method
TWI506738B (en) * 2011-06-09 2015-11-01 Unimicron Technology Corp Semiconductor package and fabrication method thereof
TWI447864B (en) * 2011-06-09 2014-08-01 Unimicron Technology Corp Package substrate and fabrication method thereof

Patent Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080105355A1 (en) * 2003-12-31 2008-05-08 Microfabrica Inc. Probe Arrays and Method for Making
US7459345B2 (en) * 2004-10-20 2008-12-02 Mutual-Pak Technology Co., Ltd. Packaging method for an electronic element
US20100252926A1 (en) * 2007-09-04 2010-10-07 Kyocera Corporation Semiconductor Element, Method for Manufacturing the Same, and Mounting Structure Having the Semiconductor Element Mounted Thereon
US20100313416A1 (en) * 2008-02-29 2010-12-16 Sumitomo Bakelite Co., Ltd Method for providing solder connection, electronic equipment and method for manufacturing same
US20100059881A1 (en) * 2008-09-05 2010-03-11 Samsung Electro-Mechanics Co., Ltd. Semiconductor package and method of manufacturing the same
US8686300B2 (en) * 2008-12-24 2014-04-01 Ibiden Co., Ltd. Printed wiring board and method for manufacturing the same
US20110074020A1 (en) * 2009-09-30 2011-03-31 Fujitsu Limited Semiconductor device and method for mounting semiconductor device
US20110285012A1 (en) * 2010-05-20 2011-11-24 Taiwan Semiconductor Manufacturing Company, Ltd. Substrate Contact Opening
US20120098130A1 (en) * 2010-10-26 2012-04-26 Xilinx, Inc. Lead-free structures in a semiconductor device
US20120252168A1 (en) * 2011-04-01 2012-10-04 International Business Machines Corporation Copper Post Solder Bumps on Substrate
US8952531B2 (en) * 2012-08-06 2015-02-10 Samsung Electro-Mechanics Co., Ltd. Packaging method using solder coating ball and package having solder pattern including metal pattern
US20140312498A1 (en) * 2013-04-17 2014-10-23 Renesas Electronics Corporation Semiconductor device and method of manufacturing same

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US20140035130A1 (en) 2014-02-06
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