US20140217591A1

US20140217591A1 - Multi-layer barrier layer for interconnect structure

Info

Publication number: US20140217591A1
Application number: US14/247,375
Authority: US
Inventors: Vivian W. Ryan; Xunyuan Zhang; Paul R. Besser
Original assignee: GlobalFoundries Inc
Current assignee: GlobalFoundries Inc
Priority date: 2012-07-20
Filing date: 2014-04-08
Publication date: 2014-08-07
Also published as: US8728931B2; US20140021613A1

Abstract

A semiconductor device includes a dielectric layer positioned above a substrate of the semiconductor device and a recess defined in the dielectric layer. An adhesion barrier layer is positioned on and in direct contact with at least the sidewalls of the recess, a barrier layer interface being defined where the adhesion barrier layer directly contacts the dielectric layer. A stress-reducing barrier layer is positioned adjacent to the adhesion barrier layer, wherein the stress-reducing barrier layer is adapted to reduce a stress level across the barrier layer interface from a first stress level to a second stress level that is less than the first stress level. At least one layer of a conductive fill material is positioned over the stress-reducing barrier layer, the at least one layer of the conductive fill material substantially filling the recess.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

This is a divisional of co-pending application Ser. No. 13/553,977, filed Jul. 20, 2012.

STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

Not applicable

BACKGROUND

The disclosed subject matter relates generally to the field of semiconductor device manufacturing, and more particularly, to a multi-layer barrier layer for an interconnect structure.
A conventional integrated circuit device, such as a microprocessor, is typically comprised of many thousands of semiconductor devices, e.g., transistors, formed above the surface of a semi-conductive substrate. For the integrated circuit device to function, the transistors must be electrically connected to one another through conductive interconnect structures. The back end of line (BEOL) is the second portion of integrated circuit fabrication where the individual devices (transistors, capacitors, resistors, etc.) get interconnected with wiring on device. BEOL generally begins when the first layer of metal is deposited on the wafer. It includes contacts, insulating layers (dielectrics), metal levels, and bonding sites for chip-to-package connections. Many modern integrated circuit devices are very densely packed, i.e., there is very little space between the transistors formed above the substrate. Thus, these conductive interconnect structures must be made in multiple layers to conserve plot space on the semiconductor substrate.
The conductive interconnect structures are typically accomplished through the formation of a plurality of conductive lines and conductive plugs, commonly referred to as contacts or vias, formed in alternative layers of dielectric materials formed on the device. As is readily apparent to those skilled in the art, the conductive plugs are means by which various layers of conductive lines, and/or semiconductor devices, may be electrically coupled to one another. The conductive lines that connect the various interconnect structures are commonly formed in trenches defined in the dielectric layers.
A contact is generally used to define an interconnect structure (e.g., using polysilicon or metal) to an underlying polysilicon layer (e.g., source/drain or gate region of a transistor), while a via denotes a metal to metal interconnect structure. In either case, a contact opening is formed in an insulating layer overlaying the conductive member. A second conductive layer is then formed over the contact opening and electrical communication is established with the conductive member.
One technique for reducing the size of the features formed on the semiconductor device involves the use of copper for the lines and interconnections in conjunction with new dielectric materials having lower dielectric constants than previously achievable with common dielectric material choices. Standard dielectric materials such as silicon dioxide, TEOS, and F-TEOS have dielectric constants greater than 3. The new dielectric materials, commonly referred to as low-k dielectrics, have dielectric constants less than 3, and thus, allow greater device densities, due to their more efficient isolation capabilities. One such low-k dielectric is sold under the name of Black Diamond, by Applied Materials, Inc.
Typical interconnect features include a metal stack including three materials, a barrier layer, a seed layer, and bulk fill. The barrier layer serves to inhibit migration or diffusion of copper into the dielectric and also to inhibit oxygen diffusion from the dielectric into the interconnect feature. The seed layer provides favorable surface to nucleate isolets for copper grain growth, improves wettability of copper over the topography to minimize agglomeration, protects the barrier material from attack in the copper plating bath, and provides a dopant material for diffusion into the copper to mitigate electromigration (EM) and stress migration (SM).
In a narrow BEOL pitch, the barrier and seed layers must be relatively thin to accommodate the geometry while leaving enough room for the bulk copper fill. Due to continuous scaling to smaller dimensions, it becomes more difficult to create barrier and seed layers that are capable of performing their functions.
This section of this document is intended to introduce various aspects of art that may be related to various aspects of the disclosed subject matter described and/or claimed below. This section provides background information to facilitate a better understanding of the various aspects of the disclosed subject matter. It should be understood that the statements in this section of this document are to be read in this light, and not as admissions of prior art. The disclosed subject matter is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.

BRIEF SUMMARY OF EMBODIMENTS

The following presents a simplified summary of only some aspects of embodiments of the disclosed subject matter in order to provide a basic understanding of some aspects of the disclosed subject matter. This summary is not an exhaustive overview of the disclosed subject matter. It is not intended to identify key or critical elements of the disclosed subject matter or to delineate the scope of the disclosed subject matter. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is discussed later.
One aspect of the disclosed subject matter is seen in a semiconductor device that includes a dielectric layer positioned above a substrate of the semiconductor device, a recess defined in the dielectric layer, and an adhesion barrier layer that is positioned on and in direct contact with at least the sidewalls of the recess, a barrier layer interface being defined where the adhesion barrier layer directly contacts the dielectric layer. Additionally, the disclosed semiconductor device includes a stress-reducing barrier layer that is positioned adjacent to the adhesion barrier layer, wherein the stress-reducing barrier layer is adapted to reduce a stress level across the barrier layer interface from a first stress level to a second stress level that is less than the first stress level. Furthermore, the semiconductor device also includes at least one layer of a conductive fill material that is positioned over the stress-reducing barrier layer, the at least one layer of the conductive fill material substantially filling the recess.
Another aspect of the disclosed subject matter is seen in a semiconductor device that includes a dielectric layer positioned above a substrate of the semiconductor device, a recess defined in said dielectric layer, and a first barrier layer positioned on and in direct contact with at least the sidewalls of the recess, a barrier layer interface being defined where the first barrier layer directly contacts the dielectric layer. Furthermore, the disclosed semiconductor device also includes, among other things, a second barrier layer positioned adjacent to said first barrier layer, wherein the second barrier layer is adapted to reduce a stress level across the barrier layer interface from a first stress level to a second stress level that is less than the first stress level, the second barrier layer including tantalum and a first transition metal other than tantalum. The illustrative semiconductor device further includes a wetting layer positioned adjacent to the second barrier layer, the wetting layer including an alloy of the first transition metal and a second transition metal other than tantalum. Moreover, the semiconductor device includes at least one layer of conductive material filling the recess, wherein the wetting layer is positioned between the second barrier layer and the at least one layer of conductive material.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

The disclosed subject matter will hereafter be described with reference to the accompanying drawings, wherein like reference numerals denote like elements, and:

FIGS. 1 is a cross section view of a partially completed interconnect structure;

FIG. 2 is a cross-section view of the structure of FIG. 1 illustrating the formation of a barrier layer;

FIG. 3 is a cross-section view of the structure of FIG. 2 illustrating the formation of a transition metal layer at corners of the interconnect structure;

FIG. 4 is a cross-section view of the structure of FIG. 3 illustrating the formation of a ruthenium layer;

FIG. 5 is a cross-section view of the structure of FIG. 4 illustrating a copper fill process;

FIG. 6 is a cross-section view of the structure of FIG. 5 illustrating a copper anneal process to form alloy regions at the corners; and

FIG. 7 is a cross-section view of the structure of FIG. 6 illustrating a polishing process to remove excess copper and recess the copper at the corners.

While the disclosed subject matter is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific embodiments is not intended to limit the disclosed subject matter to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the disclosed subject matter as defined by the appended claims.

DETAILED DESCRIPTION

One or more specific embodiments of the disclosed subject matter will be described below. It is specifically intended that the disclosed subject matter not be limited to the embodiments and illustrations contained herein, but include modified forms of those embodiments including portions of the embodiments and combinations of elements of different embodiments as come within the scope of the following claims. It should be appreciated that in the development of any such actual implementation, as in any engineering or design project, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business related constraints, which may vary from one implementation to another. Moreover, it should be appreciated that such a development effort might be complex and time consuming, but would nevertheless be a routine undertaking of design, fabrication, and manufacture for those of ordinary skill having the benefit of this disclosure. Nothing in this application is considered critical or essential to the disclosed subject matter unless explicitly indicated as being “critical” or “essential.”
The disclosed subject matter will now be described with reference to the attached figures. Various structures, systems and devices are schematically depicted in the drawings for purposes of explanation only and so as to not obscure the disclosed subject matter with details that are well known to those skilled in the art. Nevertheless, the attached drawings are included to describe and explain illustrative examples of the disclosed subject matter. The words and phrases used herein should be understood and interpreted to have a meaning consistent with the understanding of those words and phrases by those skilled in the relevant art. No special definition of a term or phrase, i.e., a definition that is different from the ordinary and customary meaning as understood by those skilled in the art, is intended to be implied by consistent usage of the term or phrase herein. To the extent that a term or phrase is intended to have a special meaning, i.e., a meaning other than that understood by skilled artisans, such a special definition will be expressly set forth in the specification in a definitional manner that directly and unequivocally provides the special definition for the term or phrase.
Referring now to the drawings wherein like reference numbers correspond to similar components throughout the several views and, specifically, referring to FIGS. 1, the disclosed subject matter shall be described in the context of a method for fabricating an interconnect structure. FIG. 1 is a cross-section view of a partially completed interconnect structure 10. A dielectric layer 20 has been provided on a substrate 25. The dielectric layer may represent an interlayer dielectric layer disposed between a device layer or metallization layer and another metallization layer. In one embodiment, the dielectric layer 20 may have a low dielectric coefficient, commonly referred to as a low-k dielectric. One such suitable low-k dielectric material is Black Diamond, offered by Applied Materials, Inc. A hard mask layer 30 is formed to provide a template for etching a recess 40. In the illustrated embodiment, the recess 40 is a trench in which an interconnect line feature is being formed, however, the methods described herein may also be applied to other types of interconnects, such as via structures or dual damascene trench and via structures, where an underlying metal region is being contacted by the interconnect feature. Hence, the recess 40 may be a trench, a via opening, or a combined trench and via opening.
As illustrated in FIG. 2, a barrier layer stack 50 is formed to line the recess 40. The barrier layer stack 50 includes an adhesion barrier layer 60 and a stress-reducing barrier layer 70. The adhesion barrier layer 60 provides good adhesion between the dielectric layer 20 and the metal interconnect structure 10. Exemplary adhesion barrier materials include tantalum (Ta) or tantalum nitride (TaN), which may be formed by physical vapor deposition (PVD) or atomic layer deposition (ALD) processes known in the art. An exemplary material for the stress-reducing barrier layer 70 includes an alloy of tantalum and a transition metal (TaMx), which may be formed using a PVD process. Exemplary transition metals could include any element in the d-block of the periodic table, which includes groups 3 to 12 on the periodic table. In the illustrated embodiment, titanium (Ti) is used to form the alloy with tantalum (Ta) in the stress-reducing barrier layer 70. The use of a TaMx alloy reduces the overall resistance of the barrier layer stack 50, and also reduces the likelihood of pipe diffusion for copper.
The TaMx alloy in the stress-reducing barrier layer 70 reduces stress in the interconnect structure 10 by reducing the delta stress. Delta stress is the absolute value of stress in the metal film stack (Cu fill plus any barrier) minus stress in the low-k dielectric layer 20. The use of the adhesion barrier layer 60 provides the opportunity to modulate the delta stress. The stress-reducing barrier layer 70 is engineered to reduce the stress present in the adhesion barrier layer 60 across the interface with the dielectric layer 20, thereby also reducing the net delta stress. Hence, stress level present across the interface between the adhesion barrier layer 60 and the dielectric layer 20 is changed by the stress-reducing barrier layer 70 to provide a reduced stress level across the interface between the adhesion barrier layer 60 and the dielectric layer 20. The stress may be tensile or compressive, depending on the particular application, geometry, and materials. The stress reduction reduces stress between the layers 60, 70 and also the stress at critical interfaces of the interconnect structure 10, such as the interfaces at corner regions. Thus, the stress-reducing barrier layer 70 serves to reduce the stress differential across the interconnect/dielectric interface. The percentages of tantalum and transition metal, Mx, in the stress-reducing barrier layer 70 may be about 60-93% and 7-40%, respectively.
As illustrated in FIG. 3, a seed layer stack 80 is formed over the barrier layer stack 50 to line the recess 40. The seed layer stack 80 includes an undoped seed layer 90 and a doped seed layer 100. In the illustrated embodiment, the seed layer 90 is undoped copper, and the doped seed layer 100 may be a copper alloy such as copper-manganese (CuMn). Other alloy metals for the doped seed layer 100 include aluminum, gold, calcium, zinc, cadmium, silver, tin, etc.
In FIG. 4, a bulk copper fill is performed using an electroplating process or a PVD copper process with reflow to form copper fill layer 110. After the fill process, an anneal process is performed to realign the grain boundaries and increase the grain size of the copper layer 110. During the anneal process, the dopant in the doped seed layer 100 diffuses into the copper fill layer 110 to improve its EM and SM resistance. The dopant tends to migrate to the upper surface 120 of the copper fill layer 110. Some dopant may also diffuse into the undoped seed layer 90, however, the undoped seed layer 90 acts as a buffer to limit dopant diffusion into dislocations present in the barrier layer stack 50. An exemplary anneal process may be conducted at 100-400° C. for 30-60 min.
Subsequently, a chemical mechanical polishing (CMP) process is performed to remove excess copper fill material 110. During the polishing process the horizontal portions of the seed layer stack 80, the barrier layer stack 50, and the hard mask layer 30 are removed, resulting in the structure shown in FIG. 5.
Referring to FIG. 6, an embodiment is illustrated where the barrier layer stack 50 also includes a wetting layer 130. In the illustrated embodiment, the material of the wetting layer 130 is ruthenium (Ru), but other transition metals having relatively high wettabilities for copper that may be used are osmium, rhodium, palladium, platinum, iridium, niobium, and cobalt. The wetting layer 130 acts as a seed enhancement layer to improve the copper seed coverage, thereby enhancing the copper fill. The wetting layer 130 allows direct copper plating of the seed layer stack 80.
As illustrated in FIG. 7, during the anneal process performed after the copper fill layer 110 has been formed, transition metal from the stress-reducing barrier layer 70 diffuses into the wetting layer 130, creating an alloy layer 140 (e.g., RuTi). The alloy serves to change the characteristics of the wetting layer 130 to improve its efficacy as a barrier layer for mitigating EM and SM. This change increases the overall effectiveness of the barrier layer stack 50, while also providing an advantage during the copper fill process.
The use of the multiple layer barrier layer stack 50 and the seed layer stack 80 as described herein provides process advantages and reliability advantages (i.e., EM and SM resistance). The stress gradient across the interconnect/dielectric interface is reduced in both the barrier layer stack 50 and the seed layer stack 80.
The particular embodiments disclosed above are illustrative only, as the disclosed subject matter may be modified and practiced in different but equivalent manners apparent to those skilled in the art having the benefit of the teachings herein. Furthermore, no limitations are intended to the details of construction or design herein shown, other than as described in the claims below. It is therefore evident that the particular embodiments disclosed above may be altered or modified and all such variations are considered within the scope and spirit of the disclosed subject matter. Accordingly, the protection sought herein is as set forth in the claims below.

Claims

1.-21. (canceled)

22. A semiconductor device, comprising:

a dielectric layer positioned above a substrate of said semiconductor device;

a recess defined in said dielectric layer;

an adhesion barrier layer positioned on and in direct contact with at least sidewalls of said recess, a barrier layer interface being defined where said adhesion barrier layer directly contacts said dielectric layer;

a stress-reducing barrier layer positioned adjacent to said adhesion barrier layer, wherein said stress-reducing barrier layer is adapted to reduce a stress level across said barrier layer interface from a first stress level to a second stress level that is less than said first stress level; and

at least one layer of a conductive fill material positioned over said stress-reducing barrier layer, said at least one layer of said conductive fill material substantially filling said recess.

23. The semiconductor device of claim 22, wherein said stress-reducing barrier layer comprises an alloy of tantalum and a first transition metal other than tantalum.

24. The semiconductor device of claim 23, wherein said first transition metal comprises titanium.

25. The semiconductor device of claim 23, further comprising a wetting layer positioned between said stress-reducing barrier layer and said at least one layer of said conductive fill material, said wetting layer comprising an alloy of said first transition metal and a second transition metal other than tantalum.

26. The semiconductor device of claim 25, wherein said first transition metal comprises titanium and said second transition metal comprises ruthenium.

27. The semiconductor device of claim 22, wherein said at least said one layer of said conductive fill material comprises copper.

28. The semiconductor device of claim 22, wherein said at least one layer of said conductive fill material comprises first and second seed layers positioned adjacent to said stress-reducing barrier layer.

29. The semiconductor device of claim 28, wherein said first seed layer is positioned between said second seed layer and said stress-reducing barrier layer and said second seed layer is a doped seed layer comprising a dopant that is not present in said first seed layer.

30. The semiconductor device of claim 29, wherein said dopant comprises manganese.

31. The semiconductor device of claim 22, wherein said adhesion barrier layer comprises tantalum.

32. The semiconductor device of claim 22, wherein said recess comprises at least one of a trench and a via opening.

33. A semiconductor device, comprising:

a dielectric layer positioned above a substrate of said semiconductor device;

a recess defined in said dielectric layer;

a first barrier layer positioned on and in direct contact with at least sidewalls of said recess, a barrier layer interface being defined where said first barrier layer directly contacts said dielectric layer;

a second barrier layer positioned adjacent to said first barrier layer, wherein said second barrier layer is adapted to reduce a stress level across said barrier layer interface from a first stress level to a second stress level that is less than said first stress level, said second barrier layer comprising tantalum and a first transition metal other than tantalum;

a wetting layer positioned adjacent to said second barrier layer, said wetting layer comprising an alloy of said first transition metal and a second transition metal other than tantalum; and

at least one layer of conductive material filling said recess, wherein said wetting layer is positioned between said second barrier layer and said at least one layer of conductive material.

34. The semiconductor device of claim 33, wherein said first transition metal comprises titanium.

35. The semiconductor device of claim 33, wherein said second transition metal comprises ruthenium.

36. The semiconductor device of claim 33, wherein said at least one layer of conductive material comprises copper.

37. The semiconductor device of claim 33, wherein said at least one layer of conductive material comprises a doped seed layer and a layer of bulk fill material positioned on and in direct contact with said doped seed layer, said doped seed layer comprising manganese and said layer of bulk fill material comprising copper.