US20130292838A1 - Package-on-package interconnect stiffener - Google Patents
Package-on-package interconnect stiffener Download PDFInfo
- Publication number
- US20130292838A1 US20130292838A1 US13/939,146 US201313939146A US2013292838A1 US 20130292838 A1 US20130292838 A1 US 20130292838A1 US 201313939146 A US201313939146 A US 201313939146A US 2013292838 A1 US2013292838 A1 US 2013292838A1
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- Prior art keywords
- package
- die
- stiffener
- semiconductor
- contact pads
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- 239000003351 stiffener Substances 0.000 title claims abstract description 118
- 239000004065 semiconductor Substances 0.000 claims abstract description 86
- 239000000758 substrate Substances 0.000 claims description 29
- 239000011806 microball Substances 0.000 claims description 18
- 239000000463 material Substances 0.000 claims description 14
- 238000000034 method Methods 0.000 claims description 10
- 239000000853 adhesive Substances 0.000 claims description 5
- 230000001070 adhesive effect Effects 0.000 claims description 5
- 230000009477 glass transition Effects 0.000 claims description 2
- 229910000679 solder Inorganic materials 0.000 description 9
- 239000012792 core layer Substances 0.000 description 7
- 239000010931 gold Substances 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 239000010410 layer Substances 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000011805 ball Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000012536 packaging technology Methods 0.000 description 2
- JYEUMXHLPRZUAT-UHFFFAOYSA-N 1,2,3-triazine Chemical compound C1=CN=NN=C1 JYEUMXHLPRZUAT-UHFFFAOYSA-N 0.000 description 1
- XQUPVDVFXZDTLT-UHFFFAOYSA-N 1-[4-[[4-(2,5-dioxopyrrol-1-yl)phenyl]methyl]phenyl]pyrrole-2,5-dione Chemical compound O=C1C=CC(=O)N1C(C=C1)=CC=C1CC1=CC=C(N2C(C=CC2=O)=O)C=C1 XQUPVDVFXZDTLT-UHFFFAOYSA-N 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 230000000712 assembly Effects 0.000 description 1
- 238000000429 assembly Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 230000008602 contraction Effects 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229920003192 poly(bis maleimide) Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 238000004886 process control Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/562—Protection against mechanical damage
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- H01L23/00—Details of semiconductor or other solid state devices
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H—ELECTRICITY
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- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
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- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
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- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
- H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
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- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
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- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
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Definitions
- Embodiments of the invention relate to semiconductor packaging technology. More particularly, embodiments of the invention relate to a package-on-package interconnect stiffener.
- PoP Package-on-package
- FIG. 1 is a cross-sectional view of a known package-on-package (PoP) assembly.
- Bottom device package 150 may be a core chip such as a microprocessor unit and includes die 170 , substrate 160 , inter-package contact pads 155 on the top side of bottom package 150 , micro balls 180 attached to inter-package contact pads 155 , and second level interconnect pads 190 attachable to a motherboard (not shown).
- Top device package 100 is stacked onto bottom package 150 to form an electrical connection therebetween.
- Top device package 100 may be a peripheral chip such as a memory or cache unit, and may include die 120 interconnected to substrate 110 via wire bond 130 and encapsulated by molding 125 .
- the bottom side of top device package 100 includes micro balls 140 reflowed and electrically connected to micro balls 180 on the top side of bottom device package 150 .
- micro balls 140 of top device package 100 is limited by the pitch of micro balls 180 of bottom device package 150 .
- a change in the ball pitch of top device package 100 necessitates a change in the ball pitch of the bottom device package 150 and vice versa.
- CTE coefficient of thermal expansion
- top device package 100 and bottom device package 150 Another problem typically associated with PoP packaging is the coefficient of thermal expansion (CTE) mismatch between top device package 100 and bottom device package 150 .
- the CTE mismatch is due to the fact that top device package 100 and bottom device package 150 are made from different materials and undergo different rates of thermal expansion in an elevated temperature range.
- the different rates of expansion and contraction result in warpage of the PoP assembly.
- Warpage of the PoP assembly presents process challenges in the package stacking process step and quality of joint formation between top device package 100 and bottom device package 150 . Intrinsic stresses accumulated in the solder joints between the packages may risk quality and reliability failures during the use of the device.
- FIG. 1 is a cross-sectional view of a known package-on-package (PoP) assembly.
- PoP package-on-package
- FIG. 2 is a cross-sectional view of a package-on-package (PoP) assembly having an interconnect stiffener according to an embodiment.
- PoP package-on-package
- FIG. 3 is an exploded perspective view of a PoP assembly having an interconnect stiffener according to an embodiment.
- FIG. 4 is an exploded perspective view of a top device package and a bottom device package having an interconnect stiffener attached to the top side of the bottom device package according to an embodiment.
- FIG. 5 is a perspective view of an assembled PoP assembly having a top device package and a bottom device package attached to an interconnect stiffener according to an embodiment.
- FIG. 6 is a cross-sectional view of a PoP interconnect stiffener according to an embodiment.
- FIG. 7 is a cross-sectional view of a PoP interconnect stiffener according to another embodiment.
- FIG. 8 is a flowchart of a method of fabricating a PoP assembly having an interconnect stiffener according to an embodiment.
- Embodiments of the invention relate to a package-on-package (PoP) assembly comprising a top device package and a bottom device package interconnected by way of an electrically interconnected planar stiffener.
- PoP package-on-package
- Embodiments include a planar stiffener having contact pads on the bottom side attached to a bottom device package, and contact pads on the top side of the stiffener to receive a top device package.
- Embodiments of the invention include a first semiconductor package having a plurality of inter-package contact pads and a plurality of second level interconnect (SLI) pads; a second semiconductor package having a plurality of SLI pads on the bottom side of the package; and a planar stiffener having a first plurality of planar contact pads on the top side of the stiffener electrically connected to the SLI pads of the second package, and a second plurality of planar contact pads electrically connected to the inter-package contact pads of the first package.
- Embodiments of the invention provide reliable electrical interconnection and warpage control between the top device package and the bottom device package.
- FIG. 2 is a cross-sectional view of a package-on-package (PoP) assembly having an interconnect stiffener according to an embodiment.
- the PoP assembly is attachable to a motherboard (not shown) via second level interconnect pads 190 disposed on the bottom side of bottom device package 150 .
- the PoP assembly includes bottom device package 150 interconnected to planar interconnect stiffener 200 .
- Bottom device package 150 may be any semiconductor package depending on the application.
- bottom device package 150 may be a semiconductor logic package, an application processor, or a memory package with an integrated circuit in die 170 .
- Planar stiffener 200 includes a plurality of planar contact pads 210 disposed on the top side of stiffener 200 .
- Planar contact pads 210 are configured to be electrically connected to top device package 100 , for example, by way of micro balls 140 .
- Top device package 100 may be a memory package or cache unit or any other device package suited for connection with the type of device of bottom device package 150 .
- Planar stiffener 200 also includes a plurality of planar contact pads 240 disposed on the bottom side of stiffener 200 . In the PoP assembly, planar contact pads 240 are electrically connected to bottom device package 150 , for example, by way of micro balls 180 .
- FIG. 3 is an exploded perspective view of a PoP assembly having an interconnect stiffener according to an embodiment.
- Planar interconnect stiffener 200 includes substrate 220 defining a through recess 330 adapted to house die 170 of bottom device package 150 .
- Stiffener 200 also includes small through openings through which planar contact pads 210 and 240 are formed.
- Planar contact pads 210 and 240 formed on substrate 220 each includes a solder-wettable surface finish so that during reflow, the solder materials of micro balls 140 and 180 can melt, wet and form permanent conductive connection between stiffener 200 and the top and bottom packages 100 , 150 .
- Electroless Nickel/Immersion Gold ENIG
- ENIG+Electroless Gold ENIG+EG
- NiPdAu Nickel-Palladium-Gold
- FIG. 4 is an exploded perspective view of a top device package and a bottom device package having an interconnect stiffener attached to the top side of the bottom device package according to an embodiment.
- Stiffener 220 is attached to bottom device package 150 via respective contact pads 155 and 240 .
- Planar contact pads 240 disposed on the bottom side of stiffener 220 are connected to inter-package contact pads 155 of bottom device package 150 by way of conductive micro balls 180 .
- Stiffener 220 may be attached to bottom device package 150 before attaching top device package 100 to the top side of stiffener 220 .
- the layout of planar contact pads 240 on the bottom side of stiffener 220 may match the layout of inter-package contact pads 155 of bottom device package 150 . However, the layout of planar contact pads 240 on the bottom side of stiffener 220 is not precluded to be different from the layout of planar contact pads 210 on the top side of stiffener 220 .
- FIG. 5 is a perspective view of an assembled PoP assembly having a top device package and a bottom device package attached to an interconnect stiffener according to an embodiment.
- Top device package 100 is connected to stiffener 220 via interconnects such as micro balls 140 disposed on planar contact pads 210 on the top side of stiffener 220 .
- FIG. 5 shows an embodiment of assembled PoP with the width and length dimensions of top device package 100 substantially the same with the respective dimensions of stiffener 220 . However, stiffener 220 is not precluded to have other dimensions relative to top device package 100 and bottom device package 150 .
- FIG. 6 is a cross-sectional view of a PoP interconnect stiffener according to an embodiment.
- Stiffener 200 includes substrate 220 to provide structural support and upon which contact pads 210 , 240 are fabricated.
- Stiffener 200 includes solder resist layer 620 disposed on the top surface and bottom surface of core layer 630 .
- core layer 630 is a cored substrate fabricated from known polymeric materials such as bismaleimide triazine (BT), polyimide, and liquid crystalline (LC) polymer.
- BT bismaleimide triazine
- LC liquid crystalline
- Substrate 220 may include a coefficient of thermal expansion (CTE) of approximately between 15 and 25 ppm.
- CTE coefficient of thermal expansion
- Substrate 220 may also include a flexural modulus of approximately between 15 and 30 GPa.
- the properties of stiffener 200 will be designed to provide acceptable end-of-line warpage of the assembly of top device package 100 and stiffener 200 and/or the reliability of the interconnections between top device package 100 and stiffener 200 .
- Stiffener 200 also includes conductive traces 600 fabricated in substrate 220 to electrically interconnect planar contact pads 210 on the top side of stiffener 220 with planar contact pads 240 on the bottom side of stiffener 220 .
- FIG. 6 illustrates a via-in-pad design in which plug material 610 is disposed between core layer 630 and between planar contact pads 210 , 240 .
- Plug material 610 forms part of the material for substrate 220 to provide structural rigidity and foundation to contact pads 210 and 240 and is made from known materials such as silica filled epoxy composite or commercially available solder resist materials.
- Stiffener 220 may also include routing features accommodating various circuitry designs of top device package 100 .
- Stiffener 200 may include adhesive 640 laminated on solder resist layer 620 on the bottom side of stiffener 200 to adhere stiffener 200 to the top surface of bottom device package 150 .
- Adhesive 640 may be any type of known adhesive having a low glass transition temperature (T g ), for example between 90 and 180° C., such that adhesive 640 is cured below the typical solder reflow temperature range of 220-260° C.
- FIG. 7 is a cross-sectional view of a PoP interconnect stiffener according to another embodiment.
- FIG. 7 embodies a via-off-pad design in which core layer 630 extends in planar contact pads 210 and 240 regions, and plug material 610 is disposed between solder resist layers 520 and in substrate 220 .
- Other designs of substrate 220 are not in precluded in other embodiments of the invention.
- FIG. 8 is a flowchart of a method of fabricating a PoP assembly having an interconnect stiffener according to an embodiment.
- Bottom device package 150 having inter-package contact pads 155 on the top side of the package and second level interconnect (SLI) pads 190 on the bottom side of the package is provided.
- Bottom device package 150 may be in the form of individual package or multiple packages connected in a panel form.
- micro balls 180 are placed on inter-package contact pads 155 of bottom device package 150 and reflowed to form solder interconnection.
- planar stiffener 200 is fabricated from core layer 630 material. Stiffener 200 may be formed in a panel form from which individual stiffener 200 units may be obtained after singulation.
- Known process to fabricate package substrate may be used to form stiffener 200 and the key process steps may include: drilling through-holes in core layer 630 ; plating the sidewalls of through-holes; disposing plug material 610 in the through-holes; forming electrically conductive planar contact pads 210 and 240 ; forming a solder-wettable finish on planar contact pads 210 and 240 ; and forming recess 330 in stiffener 200 .
- planar stiffener 200 is mounted on the top side of bottom device package 150 .
- Planar contact pads 240 on the bottom side of stiffener 200 are aligned and attached to micro balls 180 connected to inter-package contact pads 155 of bottom device package 150 .
- the assembly of stiffener 200 and bottom device package 150 are reflowed to form permanent interconnection.
- die 170 is attached to bottom device package 150 attached to stiffener 200 .
- the assembly of bottom device package 150 and stiffener 200 (in panel form) may then be singulated to yield individual assemblies of bottom device package 150 with stiffener 200 attached thereto.
- Top device package 100 may subsequently be attached to planar contact pads 210 on the top side of stiffener 200 to form a package-on-package assembly.
- Embodiments of the invention provide a device package electrically interconnected with an interconnect stiffener upon which another device package can be mounted and electrically connected to form a package-on-package assembly.
- the stiffener in the package-on-package assembly provides the necessary stiffness to the assembly for improved warpage control and the platform on which a top device package can be attached with greater process control.
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Abstract
Embodiments of the invention relate to a package-on-package (PoP) assembly comprising a top device package and a bottom device package interconnected by way of an electrically interconnected planar stiffener. Embodiments of the invention include a first semiconductor package having a plurality of inter-package contact pads and a plurality of second level interconnect (SLI) pads; a second semiconductor package having a plurality of SLI pads on the bottom side of the package; and a planar stiffener having a first plurality of planar contact pads on the top side of the stiffener electrically connected to the SLI pads of the second package, and a second plurality of planar contact pads electrically connected to the inter-package contact pads of the first package.
Description
- This is a Continuation application of Ser. No. 12/384,984 filed Apr. 10, 2009, which is presently pending.
- Embodiments of the invention relate to semiconductor packaging technology. More particularly, embodiments of the invention relate to a package-on-package interconnect stiffener.
- Mobile devices such as mobile phones, mobile internet devices (MIDs) and laptops, are designed with smaller form factor and slimmer profile for improved aesthetic and functional appeals. The size of and real estate occupied by semiconductor packages in the devices need to be scaled down accordingly. Package-on-package (PoP) packaging technology is employed to stack a semiconductor package on top of another semiconductor package to remove the x and y dimensions constraints in the layout of semiconductor packages on a motherboard.
- PoP technology presents various problems, particularly with respect to the original equipment manufacturer (OEM) process. One of the problems is the limitation of cold surface to cold surface solder reflow process.
FIG. 1 is a cross-sectional view of a known package-on-package (PoP) assembly.Bottom device package 150 may be a core chip such as a microprocessor unit and includes die 170,substrate 160,inter-package contact pads 155 on the top side ofbottom package 150,micro balls 180 attached tointer-package contact pads 155, and secondlevel interconnect pads 190 attachable to a motherboard (not shown).Top device package 100 is stacked ontobottom package 150 to form an electrical connection therebetween.Top device package 100 may be a peripheral chip such as a memory or cache unit, and may include die 120 interconnected tosubstrate 110 viawire bond 130 and encapsulated by molding 125. The bottom side oftop device package 100 includesmicro balls 140 reflowed and electrically connected tomicro balls 180 on the top side ofbottom device package 150. During the OEM process, accurate placement and reflow oftop device package 100 onbottom device package 150 are typically limited and difficult to control due to the curved surfaces ofmicro balls micro balls 140 oftop device package 100 is limited by the pitch ofmicro balls 180 ofbottom device package 150. A change in the ball pitch oftop device package 100 necessitates a change in the ball pitch of thebottom device package 150 and vice versa. - Another problem typically associated with PoP packaging is the coefficient of thermal expansion (CTE) mismatch between
top device package 100 andbottom device package 150. The CTE mismatch is due to the fact thattop device package 100 andbottom device package 150 are made from different materials and undergo different rates of thermal expansion in an elevated temperature range. The different rates of expansion and contraction result in warpage of the PoP assembly. Warpage of the PoP assembly presents process challenges in the package stacking process step and quality of joint formation betweentop device package 100 andbottom device package 150. Intrinsic stresses accumulated in the solder joints between the packages may risk quality and reliability failures during the use of the device. - Embodiments of the invention are illustrated by way of example and not limited in the figures of the accompanying drawings, in which like references indicate similar elements.
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FIG. 1 is a cross-sectional view of a known package-on-package (PoP) assembly. -
FIG. 2 is a cross-sectional view of a package-on-package (PoP) assembly having an interconnect stiffener according to an embodiment. -
FIG. 3 is an exploded perspective view of a PoP assembly having an interconnect stiffener according to an embodiment. -
FIG. 4 is an exploded perspective view of a top device package and a bottom device package having an interconnect stiffener attached to the top side of the bottom device package according to an embodiment. -
FIG. 5 is a perspective view of an assembled PoP assembly having a top device package and a bottom device package attached to an interconnect stiffener according to an embodiment. -
FIG. 6 is a cross-sectional view of a PoP interconnect stiffener according to an embodiment. -
FIG. 7 is a cross-sectional view of a PoP interconnect stiffener according to another embodiment. -
FIG. 8 is a flowchart of a method of fabricating a PoP assembly having an interconnect stiffener according to an embodiment. - Embodiments of the invention relate to a package-on-package (PoP) assembly comprising a top device package and a bottom device package interconnected by way of an electrically interconnected planar stiffener. Embodiments include a planar stiffener having contact pads on the bottom side attached to a bottom device package, and contact pads on the top side of the stiffener to receive a top device package. Embodiments of the invention include a first semiconductor package having a plurality of inter-package contact pads and a plurality of second level interconnect (SLI) pads; a second semiconductor package having a plurality of SLI pads on the bottom side of the package; and a planar stiffener having a first plurality of planar contact pads on the top side of the stiffener electrically connected to the SLI pads of the second package, and a second plurality of planar contact pads electrically connected to the inter-package contact pads of the first package. Embodiments of the invention provide reliable electrical interconnection and warpage control between the top device package and the bottom device package.
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FIG. 2 is a cross-sectional view of a package-on-package (PoP) assembly having an interconnect stiffener according to an embodiment. The PoP assembly is attachable to a motherboard (not shown) via secondlevel interconnect pads 190 disposed on the bottom side ofbottom device package 150. The PoP assembly includesbottom device package 150 interconnected toplanar interconnect stiffener 200.Bottom device package 150 may be any semiconductor package depending on the application. For example,bottom device package 150 may be a semiconductor logic package, an application processor, or a memory package with an integrated circuit in die 170.Planar stiffener 200 includes a plurality ofplanar contact pads 210 disposed on the top side ofstiffener 200.Planar contact pads 210 are configured to be electrically connected totop device package 100, for example, by way ofmicro balls 140.Top device package 100 may be a memory package or cache unit or any other device package suited for connection with the type of device ofbottom device package 150.Planar stiffener 200 also includes a plurality ofplanar contact pads 240 disposed on the bottom side ofstiffener 200. In the PoP assembly,planar contact pads 240 are electrically connected tobottom device package 150, for example, by way ofmicro balls 180. -
FIG. 3 is an exploded perspective view of a PoP assembly having an interconnect stiffener according to an embodiment.Planar interconnect stiffener 200 includessubstrate 220 defining athrough recess 330 adapted to house die 170 ofbottom device package 150. Stiffener 200 also includes small through openings through whichplanar contact pads Planar contact pads substrate 220 each includes a solder-wettable surface finish so that during reflow, the solder materials ofmicro balls stiffener 200 and the top andbottom packages planar contact pads -
FIG. 4 is an exploded perspective view of a top device package and a bottom device package having an interconnect stiffener attached to the top side of the bottom device package according to an embodiment.Stiffener 220 is attached tobottom device package 150 viarespective contact pads Planar contact pads 240 disposed on the bottom side ofstiffener 220 are connected tointer-package contact pads 155 ofbottom device package 150 by way ofconductive micro balls 180.Stiffener 220 may be attached tobottom device package 150 before attachingtop device package 100 to the top side ofstiffener 220. The layout ofplanar contact pads 240 on the bottom side ofstiffener 220 may match the layout ofinter-package contact pads 155 ofbottom device package 150. However, the layout ofplanar contact pads 240 on the bottom side ofstiffener 220 is not precluded to be different from the layout ofplanar contact pads 210 on the top side ofstiffener 220. -
FIG. 5 is a perspective view of an assembled PoP assembly having a top device package and a bottom device package attached to an interconnect stiffener according to an embodiment.Top device package 100 is connected tostiffener 220 via interconnects such asmicro balls 140 disposed onplanar contact pads 210 on the top side ofstiffener 220.FIG. 5 shows an embodiment of assembled PoP with the width and length dimensions oftop device package 100 substantially the same with the respective dimensions ofstiffener 220. However,stiffener 220 is not precluded to have other dimensions relative totop device package 100 andbottom device package 150. -
FIG. 6 is a cross-sectional view of a PoP interconnect stiffener according to an embodiment.Stiffener 200 includessubstrate 220 to provide structural support and upon whichcontact pads Stiffener 200 includes solder resistlayer 620 disposed on the top surface and bottom surface ofcore layer 630. For an embodiment,core layer 630 is a cored substrate fabricated from known polymeric materials such as bismaleimide triazine (BT), polyimide, and liquid crystalline (LC) polymer. However, other materials suitable forcore layer 630 are not precluded in other embodiments of the invention.Substrate 220 may include a coefficient of thermal expansion (CTE) of approximately between 15 and 25 ppm.Substrate 220 may also include a flexural modulus of approximately between 15 and 30 GPa. The properties ofstiffener 200 will be designed to provide acceptable end-of-line warpage of the assembly oftop device package 100 andstiffener 200 and/or the reliability of the interconnections betweentop device package 100 andstiffener 200. -
Stiffener 200 also includesconductive traces 600 fabricated insubstrate 220 to electrically interconnectplanar contact pads 210 on the top side ofstiffener 220 withplanar contact pads 240 on the bottom side ofstiffener 220.FIG. 6 illustrates a via-in-pad design in which plugmaterial 610 is disposed betweencore layer 630 and betweenplanar contact pads Plug material 610 forms part of the material forsubstrate 220 to provide structural rigidity and foundation to contactpads Stiffener 220 may also include routing features accommodating various circuitry designs oftop device package 100. Hence, the circuitry laid insubstrate 160 ofbottom device package 150 needs not be redesigned every time whentop device package 100 of different circuitry layout is paired withbottom device package 150.Stiffener 200 may include adhesive 640 laminated on solder resistlayer 620 on the bottom side ofstiffener 200 to adherestiffener 200 to the top surface ofbottom device package 150. Adhesive 640 may be any type of known adhesive having a low glass transition temperature (Tg), for example between 90 and 180° C., such that adhesive 640 is cured below the typical solder reflow temperature range of 220-260° C. -
FIG. 7 is a cross-sectional view of a PoP interconnect stiffener according to another embodiment.FIG. 7 embodies a via-off-pad design in whichcore layer 630 extends inplanar contact pads material 610 is disposed between solder resist layers 520 and insubstrate 220. Other designs ofsubstrate 220 are not in precluded in other embodiments of the invention. -
FIG. 8 is a flowchart of a method of fabricating a PoP assembly having an interconnect stiffener according to an embodiment.Bottom device package 150 havinginter-package contact pads 155 on the top side of the package and second level interconnect (SLI)pads 190 on the bottom side of the package is provided.Bottom device package 150 may be in the form of individual package or multiple packages connected in a panel form. Inoperation 700,micro balls 180 are placed oninter-package contact pads 155 ofbottom device package 150 and reflowed to form solder interconnection. Inoperation 710,planar stiffener 200 is fabricated fromcore layer 630 material.Stiffener 200 may be formed in a panel form from whichindividual stiffener 200 units may be obtained after singulation. Known process to fabricate package substrate may be used to formstiffener 200 and the key process steps may include: drilling through-holes incore layer 630; plating the sidewalls of through-holes; disposingplug material 610 in the through-holes; forming electrically conductiveplanar contact pads planar contact pads recess 330 instiffener 200. - In operation 720 (
FIG. 8 ),planar stiffener 200 is mounted on the top side ofbottom device package 150.Planar contact pads 240 on the bottom side ofstiffener 200 are aligned and attached tomicro balls 180 connected tointer-package contact pads 155 ofbottom device package 150. The assembly ofstiffener 200 andbottom device package 150 are reflowed to form permanent interconnection. After reflow, die 170 is attached tobottom device package 150 attached tostiffener 200. The assembly ofbottom device package 150 and stiffener 200 (in panel form) may then be singulated to yield individual assemblies ofbottom device package 150 withstiffener 200 attached thereto.Top device package 100 may subsequently be attached toplanar contact pads 210 on the top side ofstiffener 200 to form a package-on-package assembly. - Embodiments of the invention provide a device package electrically interconnected with an interconnect stiffener upon which another device package can be mounted and electrically connected to form a package-on-package assembly. The stiffener in the package-on-package assembly provides the necessary stiffness to the assembly for improved warpage control and the platform on which a top device package can be attached with greater process control.
- In the foregoing specification, reference has been made to specific embodiments of the invention. It will, however be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention. The specification and drawings are, accordingly, to be regarded in an illustrative rather than restrictive sense.
Claims (44)
1. A package-on-package (PoP) assembly, comprising:
a first semiconductor package having a plurality of inter-package contact pads and a plurality of second level interconnect (SLI) pads;
a second semiconductor package having a plurality of SLI pads on the bottom side of the package; and
a planar stiffener having a first plurality of planar contact pads on the top side of the stiffener electrically connected to the SLI pads of the second package, and a second plurality of planar contact pads electrically connected to the inter-package contact pads of the first package.
2. The assembly of claim 1 , wherein the stiffener includes routing features accommodating various circuitry designs of the second package.
3. The assembly of claim 2 , wherein the substrate includes a coefficient of thermal expansion (CTE) approximately between 15 and 25 ppm, and a flexural modulus approximately between 15 and 30 GPa.
4. The assembly of claim 1 , wherein the layout of the second plurality of planar contact pads of the stiffener matches the layout of the inter-package contact pads of the first package.
5. The assembly of claim 1 , wherein the stiffener includes a plug material disposed between the first plurality and the second plurality of planar contact pads.
6. The assembly of claim 1 , wherein the stiffener includes a plug material disposed in the substrate.
7. A method to form a package-on-package (PoP) assembly, comprising:
providing a first semiconductor package having a plurality of inter-package contact pads and a plurality of second level interconnect (SLI) pads;
attaching micro balls to the inter-package contact pads of the first package;
connecting a planar stiffener to the micro balls attached to the first package, the stiffener having a first plurality of planar contact pads on the top side of the stiffener to receive a second semiconductor package, and a second plurality of planar contact pads to connect the stiffener to the micro balls attached to the first package; and
reflowing the micro balls to form electrical connection between the stiffener and the first package.
8. The method of claim 7 , further comprising attaching a bottom side of the stiffener to the first package by way of an adhesive of low glass transition temperature (Tg).
9. The method of claim 7 , wherein the stiffener comprises:
a substrate having a through recess adapted to house a die attached to the first package, and a plurality of through openings through which the first and second pluralities of contact pads are disposed;
a solder-wettable planar surface finish on the first and second pluralities of contact pads; and
a conductive trace electrically connecting the first plurality of contact pads to the corresponding second plurality of contact pads.
10. A semiconductor assembly, comprising:
a first semiconductor package including a first substrate and a first die having a plurality of inter-package contact pads and a plurality of second level interconnect (SLI) pads;
a planar stiffener having a first plurality of planar contact pads on the top side of the stiffener configured to electrically connect the planar stiffener and a second die, and a second plurality of planar contact pads on the bottom side of the stiffener electrically connected to the inter-package contact pads of the first package and a wire bond in contact with the second die and electrically coupled to the first semiconductor package through the planar stiffener;
wherein the second die and the planar stiffener are stacked on the first substrate.
11. The semiconductor assembly of claim 10 , wherein the planar stiffener is configured to electrically connect a second semiconductor package including the planar stiffener and the second die.
12. The semiconductor assembly of claim 10 , wherein the second die is part of a memory package.
13. The semiconductor assembly of claim 10 , wherein the second die is part of a cache unit.
14. The semiconductor assembly of claim 10 , wherein the second die is part of a device package suited for connection with the type of device of the first semiconductor package.
15. The semiconductor assembly of claim 10 , wherein the first die is part of a semiconductor logic package.
16. The semiconductor assembly of claim 10 , wherein the first die is part of a semiconductor logic package, and wherein the second die is part of a memory package.
17. The semiconductor assembly of claim 10 , wherein the first die is part of a semiconductor logic package, and wherein the second die is part of a cache unit.
18. The semiconductor assembly of claim 10 , wherein the first die is part of a semiconductor logic package, and wherein the second die is part of a device package suited for connection with the type of device of the first semiconductor package.
19. The semiconductor assembly of claim 10 , wherein the wire bond is electrically coupled to the planar stiffener by direct contact to a second substrate upon which the second die is disposed.
20. The semiconductor assembly of claim 10 , wherein the first semiconductor package is attachable to a motherboard via the second level interconnect pads.
21. A semiconductor assembly, comprising:
a first semiconductor package including a first substrate and a first die having a plurality of inter-package contact pads and a plurality of second level interconnect (SLI) pads;
a stiffener having a first plurality of planar contact pads on the top side of the stiffener configured to electrically connect the planar stiffener and a second die, and a second plurality of planar contact pads on the bottom side of the stiffener electrically connected to the inter-package contact pads of the first package and
a wire bond in contact with the second die and electrically coupled to the first semiconductor package through the stiffener;
wherein the second die and the stiffener are stacked on the first substrate;
wherein the stiffener is configured to electrically connect a second semiconductor package including the stiffener and the second die; and
wherein the second die is part of a memory package.
22. The semiconductor assembly of claim 21 , wherein the wire bond is electrically coupled to the stiffener by direct contact to a second substrate upon which the second die is disposed.
23. A semiconductor assembly, comprising:
a first semiconductor package including a first substrate and a first die having a plurality of inter-package contact pads and a plurality of second level interconnect (SLI) pads;
a stiffener having a first plurality of planar contact pads on the top side of the stiffener configured to electrically connect the planar stiffener and a second die, and a second plurality of planar contact pads on the bottom side of the stiffener electrically connected to the inter-package contact pads of the first package;
a wire bond in contact with the second die and electrically coupled to the first semiconductor package through the stiffener;
wherein the second die and the stiffener are stacked on the first substrate;
wherein the stiffener is configured to electrically connect a second semiconductor package; and
wherein the second die is part of a memory package; and
wherein the first semiconductor package and the stiffener are electrically coupled through a micro ball.
24. The semiconductor assembly of claim 23 , wherein the first die is part of a semiconductor logic package.
25. The semiconductor assembly of claim 23 , wherein the first die is part of a semiconductor logic package, and wherein the second die is part of a memory package.
26. The semiconductor assembly of claim 23 , wherein the first die is part of a semiconductor logic package, and wherein the second die is part of a cache unit.
27. The semiconductor assembly of claim 23 , wherein the first die is part of a semiconductor logic package, and wherein the second die is part of a device package suited for connection with the type of device of the first semiconductor package.
28. The semiconductor assembly of claim 23 , wherein the wire bond is electrically coupled to the stiffener by direct contact to a second substrate upon which the second die is disposed.
29. A semiconductor assembly, comprising:
a first semiconductor package including a first die and a first substrate having a plurality of inter-package contact pads and a plurality of second level interconnect (SLI) pads;
a planar stiffener having a first plurality of planar contact pads on the top side of the stiffener configured to electrically connect to a second semiconductor package, and a second plurality of planar contact pads on the bottom side of the stiffener electrically connected to the inter-package contact pads of the first package; and
a wire bond that that is wire-bonded to a die in the second semiconductor package.
30. The semiconductor assembly of claim 29 , wherein the second die is part of a memory package.
31. The semiconductor assembly of claim 29 , wherein the second die is part of a cache unit.
32. The semiconductor assembly of claim 29 , wherein the second die is part of a device package suited for connection with the type of device of the first package.
33. The semiconductor assembly of claim 29 , wherein the first die is part of a semiconductor logic package.
34. The semiconductor assembly of claim 29 , wherein the first die is part of a semiconductor logic package, and wherein the second die is part of a memory package.
35. The semiconductor assembly of claim 29 , wherein the first die is part of a semiconductor logic package, and wherein the second die is part of a cache unit.
36. The semiconductor assembly of claim 29 , wherein the first die is part of a semiconductor logic package, and wherein the second die is part of a device package suited for connection with the type of device of the first package.
37. A semiconductor assembly, comprising:
a first semiconductor package including a first substrate and a first die having a plurality of inter-package contact pads and a plurality of second level interconnect (SLI) pads;
a planar stiffener having a first plurality of planar contact pads on the top side of the stiffener configured to electrically connect a second semiconductor package including the planar stiffener and a second die, and a second plurality of planar contact pads on the bottom side of the stiffener electrically connected to the inter-package contact pads of the first package; and
a wire bond in contact with the second die and electrically coupled to the first semiconductor package through the planar stiffener; wherein the second die and the planar stiffener are stacked on the first substrate.
38. The semiconductor assembly of claim 37 , wherein the second die is part of a memory package.
39. The semiconductor assembly of claim 37 , wherein the second die is part of a cache unit.
40. The semiconductor assembly of claim 37 , wherein the second die is part of a device package suited for connection with the type of device of the first package.
41. The semiconductor assembly of claim 37 , wherein the first die is part of a semiconductor logic package.
42. The semiconductor assembly of claim 37 , wherein the first die is part of a semiconductor logic package, and wherein the second die is part of a memory package.
43. The semiconductor assembly of claim 37 , wherein the first die is part of a semiconductor logic package, and wherein the second die is part of a cache unit.
44. The semiconductor assembly of claim 37 , wherein the first die is part of a semiconductor logic package, and wherein the second die is part of a device package suited for connection with the type of device of the first package.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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US13/939,146 US20130292838A1 (en) | 2009-04-10 | 2013-07-10 | Package-on-package interconnect stiffener |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/384,984 US8513792B2 (en) | 2009-04-10 | 2009-04-10 | Package-on-package interconnect stiffener |
US13/939,146 US20130292838A1 (en) | 2009-04-10 | 2013-07-10 | Package-on-package interconnect stiffener |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
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US12/384,984 Continuation US8513792B2 (en) | 2009-04-10 | 2009-04-10 | Package-on-package interconnect stiffener |
Publications (1)
Publication Number | Publication Date |
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US20130292838A1 true US20130292838A1 (en) | 2013-11-07 |
Family
ID=42933723
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/384,984 Active 2029-06-14 US8513792B2 (en) | 2009-04-10 | 2009-04-10 | Package-on-package interconnect stiffener |
US13/939,146 Abandoned US20130292838A1 (en) | 2009-04-10 | 2013-07-10 | Package-on-package interconnect stiffener |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
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US12/384,984 Active 2029-06-14 US8513792B2 (en) | 2009-04-10 | 2009-04-10 | Package-on-package interconnect stiffener |
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US (2) | US8513792B2 (en) |
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US20100258927A1 (en) | 2010-10-14 |
US8513792B2 (en) | 2013-08-20 |
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