US20110037139A1 - Schottky barrier diode (sbd) and its off-shoot merged pn/schottky diode or junction barrier schottky (jbs) diode - Google Patents
Schottky barrier diode (sbd) and its off-shoot merged pn/schottky diode or junction barrier schottky (jbs) diode Download PDFInfo
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- US20110037139A1 US20110037139A1 US12/912,539 US91253910A US2011037139A1 US 20110037139 A1 US20110037139 A1 US 20110037139A1 US 91253910 A US91253910 A US 91253910A US 2011037139 A1 US2011037139 A1 US 2011037139A1
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
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- H01L29/6606—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
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- H01L21/046—Making n or p doped regions or layers, e.g. using diffusion using ion implantation
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
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- H01L2924/1203—Rectifying Diode
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Definitions
- This invention relates generally to semiconductor devices and semiconductor device fabrication, and more particularly to MPS (merged PN/Schottky) devices and fabrication.
- MPS merged PN/Schottky
- the invention combines in a diode the relatively lower forward voltage drop of a Schottky diode with the relatively lower reverse leakage current of a P-N junction diode by implementing an MPS (merged PN/Schottky) design so as to increase the Schottky active area of the MPS diode by embedding wells of a second conductivity beneath the surface of a substrate of a first conductivity.
- An advantage of the invention is to reduce the diode forward voltage drop by embedding the wells.
- FIG. 1 is a cross-sectional diagram showing an embedded junction barrier grid according to an embodiment of the invention.
- FIG. 2 is a cross-sectional diagram showing a conventional prior art JB (Junction Barrier) Schottky structure.
- FIG. 2A is a plan view showing a two-dimensional “embedded network” of p-wells in accordance with an embodiment of the invention.
- FIGS. 3A-3I are diagrams showing a fabrication process in accordance with an embodiment of the invention.
- FIG. 3A is a cross-sectional view of a wafer covered by a buffer layer and further covered by an epitaxial drift layer into which ion implantation is carried out through a patterned oxide mask.
- FIG. 3B is a cross-sectional view of a peripheral region, floating guard ring regions, and grid p-wells formed in the epitaxial drift layer of FIG. 3A , along with an optional n-type implant.
- FIG. 3C is a cross-sectional view showing the removal of a surface portion of the epitaxial drift layer of FIG. 3B in the areas of the peripheral region, the floating guard ring regions, and selected grid p-wells, along with the optional n-type implant of FIG. 3B in such cases.
- FIG. 3D is a cross-sectional view showing the removal of a surface portion of the epitaxial drift layer of FIG. 3B in the areas of the peripheral region, the floating guard ring regions, and selected grid p-wells, without the optional n-type implant of FIG. 3B .
- FIG. 3E is a cross-sectional view showing the deposition of a first dielectric layer on the peripheral region, floating guard ring regions, and selected grid p-wells of FIG. 3D , and the formation of a backside ohmic contact.
- FIG. 3F is a cross-sectional view showing the formation of openings in the passivation layer above the peripheral region and selected grid p-wells of FIG. 3E , and showing the deposition of a Schottky barrier metal layer in the area of those openings.
- FIG. 3G is a cross-sectional view showing the formation of an anode contacting the Schottky barrier metal layer of FIG. 3F .
- FIG. 3H is a cross-sectional view showing the formation of a second dielectric layer on the anode, on portions of the Schottky barrier metal layer, and on portions of the first dielectric material of FIG. 3G .
- FIG. 3I is a cross-sectional view showing the creation of an opening in the second dielectric layer of FIG. 3H , and showing the formation of a cathode contacting the ohmic contact of FIGS. 3E-3H .
- FIG. 4A is a cross-sectional diagram of an alternative embodiment showing an n-type implant region across the whole device.
- FIG. 4B is a cross-sectional diagram of a variation showing an n-type implant region formed only in the active area of the whole device.
- FIG. 5A is a cross-sectional diagram of another embodiment showing a second p-type implant in selected areas in the active area to allow the Schottky barrier metal layer to link to the embedded p-well network, followed by an etch step to remove a surface portion of the n-layer above the peripheral region and in the guard ring area.
- FIG. 5B is a cross-sectional diagram of a variation showing a second p-type implant in the peripheral region and guard ring regions at the same time with the selected areas in the active area.
- FIG. 5C is a cross-sectional diagram showing a first implant step of another embodiment in a process to avoid etching the material.
- FIG. 5D is a cross-sectional diagram showing a second implant step of the process to avoid etching the material in the embodiment of FIG. 5C .
- FIG. 1 is a cross-sectional diagram showing an embodiment of the embedded junction barrier grid according to an embodiment of the invention.
- FIG. 2 is a cross-sectional diagram showing a conventional prior art JB (Junction Barrier) Schottky structure.
- JB Joint Barrier
- a new SiC SBD (Schottky barrier diode) structure 10 with an “embedded” junction barrier grid is disclosed.
- the embedded junction barrier grid is drawn schematically and the layers are identified to illustrate an n-type SiC material with a p-type junction barrier grid.
- the concept applies equally well to a p-type SiC material employing an n-type junction barrier grid.
- the grid spacing is shown for ease of illustration and should be sufficiently wide to avoid obstructing current flow or causing forward voltage to rise.
- the p-well width can be 1 to 3 ⁇ m wide with a spacing of 4 to 8 ⁇ m.
- FIG. 2 A conventional prior art JB Schottky structure (resembling the structure described in Baliga, The Pinch Rectifier: A Low-Forward-Drop High-Speed Power Diode) is shown in FIG. 2 .
- the new structure comprises a p-n junction grid which does not reach the surface for essentially all of the grid area. This feature of the new structure efficiently increases the active Schottky area which lowers the forward voltage drop and at the same time maintains the excellent reverse blocking voltage and low leakage current of prior art structures with improved current capability.
- the junction barrier grid in FIG. 1 includes a grid 42 of p-type regions 64 , 66 with width and spacing characteristic of the drift region doping concentration surrounded by a wide peripheral p-type region 44 .
- most of the grid 42 in the new structure is not at the surface of n ⁇ -SiC drift layer 16 , but rather is at a depth (e.g., 0.5-1.5 ⁇ m) below the upper surface of layer 16 , being formed of “embedded p-wells.” Since most of the embedded p-wells 64 of the grid 42 do not contact Schottky barrier metal layer 52 directly, the area of Schottky barrier contact 74 is essentially the entire top surface of the active area 60 .
- the wide peripheral p-type region 44 connects to some of the embedded p-wells 66 via the Schottky barrier metal layer 52 , through recesses 51 in the semiconductor, to define the p-grid potential. Resistance from the peripheral p-type region 44 along the embedded p-wells is reduced by a selected number of vias 51 etched through an upper portion of the n ⁇ -SiC drift layer 16 to reach selected p-wells 66 in the grid 42 of embedded p-wells within the central active area 60 of the device.
- FIG. 2A is a plan view showing a two-dimensional “embedded network” of p-wells stripes in accordance with an embodiment of the invention.
- a selected number of embedded p-wells can also be created in the direction parallel to the page to create a 2-dimensional “embedded network” to reduce p-well resistance.
- Schottky barrier metal layer 52 contacts the selected p-wells 66 through the recesses 51 in the ensuing metallization process.
- the n ⁇ -SiC drift layer 16 on top of floating guard rings 41 at the periphery of the device is also etched off at the same time the recesses 51 are created to allow the p-type doped guard ring regions 41 to reach the surface.
- the surface is then passivated to provide stable high voltage blocking capability.
- FIGS. 3A-3I are diagrams showing a fabrication process in accordance with an embodiment of the invention.
- FIG. 3A is a cross-sectional view of a wafer 12 covered by a buffer layer 14 and further covered by an epitaxial drift layer 16 into which ion implantation is carried out through a patterned oxide mask 18 .
- FIG. 3B is a cross-sectional view of a peripheral region 44 , floating guard ring regions 41 , and grid 42 p-wells formed in the epitaxial drift layer 16 of FIG. 3A , along with an optional n-type implant 46 .
- a substrate 102 of starting material having an upper surface 104 may include an n-SiC epitaxial drift layer 16 on top of a heavily doped n + -buffer layer 14 on top of an n + wafer 12 .
- SiC is used throughout for ease of discussion. The same principle applies to Schottky Barrier Diode made on all commonly known semiconductor materials such as germanium, silicon, GaAs, GaN, InP, diamond, and ternary derivatives involving II-VI compounds, etc.
- Example doping concentrations are: for n + wafer 12 , 5 ⁇ 10 17 -1 ⁇ 10 19 cm ⁇ 3 ; for n + -buffer layer 14 , 5 ⁇ 10 17 -1 ⁇ 10 19 cm ⁇ 3 ; and for n-SiC epitaxial drift layer 16 , 1 ⁇ 10 15 -1 ⁇ 10 17 cm ⁇ 3 .
- An implant blocking mask 18 is created on the top surface as shown in FIG. 3A by depositing and patterning an oxide layer of sufficient thickness.
- a 2 ⁇ m thick oxide would be sufficient for implant energy around 200 KeV for aluminum.
- Appropriate blocking mask 18 thickness is well-known in the art and can be modified for different implant energy and species.
- p-type ions are embedded below the surface 104 using a single or multiple ion implantation steps to create p-type regions 41 , 42 , and 44 .
- an aluminum dose of between 1 ⁇ 10 13 and 6 ⁇ 10 15 /cm 2 at 170 ⁇ 400 KeV (for example, 1 ⁇ 10 14 /cm 2 at 370 KeV) may be employed for the p-type regions 41 , 42 , and 44 .
- An optional layer 46 of shallow n-type implant of between 1 ⁇ 10 11 and 1 ⁇ 10 13 /cm 2 may be implanted between the top surface and the embedded p-well (e.g. to a depth of 0.2-0.5 ⁇ m) to ensure retaining the desired n-type doping level at the surface.
- the p-type regions 41 , 42 , and 44 and the optional shallow n-type implant layer 46 are established as shown in FIG. 3B .
- FIG. 3C is a cross-sectional view showing the removal of a surface portion of the epitaxial drift layer 16 of FIG. 3B in the areas of the peripheral region 44 , the floating guard ring regions 41 , and selected grid p-wells 66 , along with the optional n-type implant 46 of FIG. 3B in such cases.
- FIG. 3D is a cross-sectional view showing the removal of a surface portion of the epitaxial drift layer 16 of FIG. 3B in the areas of the peripheral region 44 , the floating guard ring regions 41 , and selected grid p-wells 66 , without the optional n-type implant 46 of FIG. 3B .
- an etch step is performed to remove a shallow surface portion of layer 16 , including the optional n-layer 46 , at selected locations above the grid 42 in the active area 60 , above the peripheral region 44 , and in the area of the guard ring regions 41 of the device to selectively expose embedded p-type regions 41 , 42 , and 44 .
- This etch step creates both selected embedded p-wells 66 to which contact can be made at the upper surface 104 and remaining embedded p-wells 64 to which contact cannot be made at the upper surface 104 , as shown in FIG. 3C .
- FIG. 3D shows a construction without the optional n-implant 46 at the surface.
- An example etch depth is 0.5-1.0 ⁇ m.
- FIG. 3E is a cross-sectional view showing the deposition of a first dielectric layer 30 on the peripheral region 44 , floating guard ring regions, and selected grid p-wells 66 of FIG. 3D , and the formation of a backside ohmic contact 50 .
- the top surface is next thermally oxidized to grow a thin layer of oxide followed with deposition of dielectric material 30 to prepare the surface for high voltage. Since very high surface electric field is present at the surface in the area of the guard rings 41 , the dielectric material in conjunction with the semiconductor surface must have the desirable characteristics of possessing high dielectric strength, low flatband voltage, low polarizability, and low charge trapping. Most dielectric films deposited using Plasma Enhanced Chemical Vaper Deposition (PECVD) polarize and trap charges under high electric field. The task is to minimize these adverse effects with specific guard ring geometry.
- PECVD Plasma Enhanced Chemical Vaper Deposition
- Undoped oxide, oxynitride, PSG (phosphorus doped silicon glass), BPSG (boron and phosphorus doped silicon glass), or combinations thereof have been known to have the aforementioned adverse effects minimized and made usable for specific guard ring designs.
- This layer 30 is shown in FIG. 3E .
- An example thickness is 0.5-1.5 ⁇ m.
- nickel is deposited by sputter deposition or evaporation onto the backside as shown in FIG. 3E .
- a thermal process can be performed to form a nickel-silicide ohmic contact 50 to the n + SiC wafer 12 , with an example thickness of 0.1 ⁇ m.
- a Rapid Thermal Process (RTP) or Rapid Thermal Anneal (RTA) may be used for this operation.
- RTP Rapid Thermal Process
- RTA Rapid Thermal Anneal
- a diffusion furnace may be used to form the ohmic contact.
- an inert gas with low moisture content such as Argon is used as carrier gas during the thermal process.
- FIG. 3F is a cross-sectional view showing the formation of openings in the passivation layer 30 above the peripheral region 44 and selected grid p-wells 66 of FIG. 3E , and showing the deposition of a Schottky barrier metal layer 52 in the area of those recesses.
- the dielectric film 30 on the front of the device is patterned to provide an opening for a Schottky barrier contact 74 to the n ⁇ -SiC epitaxial layer and a Schottky barrier contact 76 to the selected embedded p-wells 66 in the active area 60 through the selected recesses 51 formed by the previous etch step of the semiconductor, as well as a Schottky barrier contact to the peripheral guard ring region 44 .
- the Schottky barrier metal layer 52 can be deposited unto the top surface by sputter deposition or evaporation of titanium, tungsten, chromium, nickel, or other suitable metal or alloys to form different barrier heights.
- the Schottky barrier metal layer 52 also overlaps onto the oxide layer 30 as shown in FIG. 3F .
- An example thickness for Ni is 0.1 ⁇ m; or 0.1 ⁇ m for Ti.
- a forming gas (hydrogen containing gas) anneal (FGA) at an elevated temperature is performed on the device to reduce the resistance of the Schottky bather contacts 74 , 76 , and 78 and therefore improve the forward characteristics.
- FIG. 3G is a cross-sectional view showing the formation of an anode 54 contacting the Schottky barrier metal layer 52 of FIG. 3F .
- FIG. 3H is a cross-sectional view showing the formation of a second dielectric layer 32 on the anode 54 , on portions of the Schottky barrier metal layer 52 , and on portions of the first dielectric material 30 of FIG. 3G .
- a front-side anode electrode 54 is formed such as by depositing tungsten, aluminum or aluminum alloys (e.g. at a thickness of 1-5 ⁇ m) using sputter deposition or evaporation followed by a patterning and etch step. This construction is illustrated in FIG. 3G .
- the device surface is covered by another dielectric material 32 for final passivation, as shown in FIG. 3H .
- the dielectric material 32 may be the same as or different from layer 30 but with similar desirable characteristics as suggested previously, including undoped oxide, oxynitride, PSG (phosphorus doped silicon glass), BPSG (boron and phosphorus doped silicon glass), or their combinations. Polyimide is also widely used for this purpose.
- FIG. 3I is a cross-sectional view showing the creation of an opening in the second dielectric layer 32 of FIG. 3H , and showing the formation of a cathode 56 contacting the ohmic contact 50 of FIGS. 3E-3H .
- an opening in the final passivation 32 is created so the device can receive wire-bonding to the anode 54 .
- the die-attach metal 56 which also works as cathode electrode of the diode, usually a triple layer of titanium, nickel and silver, is evaporated or sputtered onto the back-side of the device in contact with the ohmic contact metal 50 .
- the final device structure 10 is shown in FIG. 3I .
- FIG. 4A is a cross-sectional diagram of an alternate embodiment showing an n-type implant region 47 across the whole device.
- FIG. 4B is a cross-sectional diagram of a variation showing an n-type implant region 147 formed only in the active area of the whole device.
- an optional n-type layer 47 can be added on top of the SiC drift layer 16 before the deep p-type ion implantation, by either epitaxial growth with a doping concentration between 1 ⁇ 10 16 and 1 ⁇ 10 17 /cm 3 , or an n-type implantation with dose between 1 ⁇ 10 11 and 1 ⁇ 10 13 /cm 2 .
- the n-type implant region 47 can extend across the whole device as shown in FIG. 4A , or an n-type implant region 147 can be formed just in the active area 60 as shown in FIG. 4B .
- FIG. 5A is a cross-sectional diagram of another embodiment showing a second p-type implant 148 in selected areas in the active area 60 to allow the Schottky barrier metal layer 52 to link to the embedded p-well network, followed by an etch step to remove a surface portion of the n-layer 16 above the peripheral region and in the guard ring area.
- FIG. 5B is a cross-sectional diagram of a variation showing a second p-type implant 48 in the peripheral region 44 and guard ring regions 41 at the same time with the selected areas in the active area 60 .
- FIG. 5C is a cross-sectional diagram showing a first implant step of another embodiment in a process to avoid etching the material.
- FIG. 5D is a cross-sectional diagram showing a second implant step 49 of the process to avoid etching the material in the embodiment of FIG. 5C .
- FIGS. 5A through 5C There are alternative ways other than FIG. 3C to expose the embedded p-wells, as shown in FIGS. 5A through 5C .
- a second p-type implant 148 is performed in selected areas in the active area to allow the Schottky barrier metal layer 52 to link to the embedded p-well network, followed by an etch step to remove the surface portion of the n-layer 16 at the peripheral region 44 and in the guard ring 41 area.
- the second p-type implant 148 is performed such that contact may be made at the upper surface 104 to selected embedded p-wells 66 , but contact may not be made at the upper surface 104 to the remaining embedded p-wells 64 .
- an alternative second p-type implant 48 is performed in the peripheral and guard ring area at the same time with the selected area in the active area, as shown in FIG. 5B .
- FIGS. 5C and 5D show another process to avoid etching the material.
- FIG. 5C during the first p-type implant, only the grid 42 of p-wells in the active area is implanted.
- FIG. 5D the peripheral region 44 and guard ring area 41 , along with extensions of selected p-wells 66 in the device active area 60 , are formed by a second p-type implant 49 .
Abstract
Description
- This application is a continuation of copending U.S. application Ser. No. 12/365,083, filed Feb. 3, 2009, now U.S. Pat. No. ______, which claimed the benefit of U.S. provisional application Ser. No. 61/038,680, filed Mar. 21, 2008, all herein incorporated by reference.
- 1. Technical Field
- This invention relates generally to semiconductor devices and semiconductor device fabrication, and more particularly to MPS (merged PN/Schottky) devices and fabrication.
- 2. Discussion of Related Art
- B. J. Baliga, The Pinch Rectifier: A Low-Forward-Drop High-Speed Power Diode, IEEE Electron Device Letters, June 1984, pp. 194-196, Vol. 5, Issue 6 describes a Schottky barrier diode with a junction grid placed under and in contact with the Schottky metal. The junction grid pinches off current flow under reverse bias but not under forward bias.
- Shang-hui L. Tu & B. Jayant Baliga, Controlling the Characteristics of the MPS Rectifier by Variation of Area of Schottky Region, IEEE Transactions on Electron Devices, July 1993, pp. 1307-1315, Vol. 40,
Issue 7 describes varying the characteristics of an MPS diode (such as forward voltage drop, breakdown voltage, leakage current, and reverse recovery time) by varying the ratio of Schottky junction region area to p-n junction region area. - A. Hefner, Jr. & D. Berning, Silicon Carbide Merged PiN Schottky Diode Switching Characteristics and Evaluation for Power Supply Application, Conference Record of the 2000 IEEE Industry Applications Conference, 8-12 Oct. 2000, pp. 2948-2954 describes a 1500 volt, 0.5 amp silicon carbide based MPS diode. The diode is able to operate at higher temperatures than a comparable silicon based MPS diode, and has low on-state voltage drop, low off-state leakage, and fast switching characteristics.
- U.S. Pat. No. 6,462,393 describes an MPS diode with an array of buried P+ areas.
- U.S. Pat. No. 6,710,419 describes a method of manufacturing an MPS diode with an array of buried P+ areas.
- A need remains for an MPS diode having improved Schottky area and reduced resistance.
- The invention combines in a diode the relatively lower forward voltage drop of a Schottky diode with the relatively lower reverse leakage current of a P-N junction diode by implementing an MPS (merged PN/Schottky) design so as to increase the Schottky active area of the MPS diode by embedding wells of a second conductivity beneath the surface of a substrate of a first conductivity. An advantage of the invention is to reduce the diode forward voltage drop by embedding the wells.
- The foregoing and other objects, features and advantages of the invention will become more readily apparent from the following detailed description of a preferred embodiment of the invention which proceeds with reference to the accompanying drawings.
-
FIG. 1 is a cross-sectional diagram showing an embedded junction barrier grid according to an embodiment of the invention. -
FIG. 2 is a cross-sectional diagram showing a conventional prior art JB (Junction Barrier) Schottky structure. -
FIG. 2A is a plan view showing a two-dimensional “embedded network” of p-wells in accordance with an embodiment of the invention. -
FIGS. 3A-3I are diagrams showing a fabrication process in accordance with an embodiment of the invention. -
FIG. 3A is a cross-sectional view of a wafer covered by a buffer layer and further covered by an epitaxial drift layer into which ion implantation is carried out through a patterned oxide mask. -
FIG. 3B is a cross-sectional view of a peripheral region, floating guard ring regions, and grid p-wells formed in the epitaxial drift layer ofFIG. 3A , along with an optional n-type implant. -
FIG. 3C is a cross-sectional view showing the removal of a surface portion of the epitaxial drift layer ofFIG. 3B in the areas of the peripheral region, the floating guard ring regions, and selected grid p-wells, along with the optional n-type implant ofFIG. 3B in such cases. -
FIG. 3D is a cross-sectional view showing the removal of a surface portion of the epitaxial drift layer ofFIG. 3B in the areas of the peripheral region, the floating guard ring regions, and selected grid p-wells, without the optional n-type implant ofFIG. 3B . -
FIG. 3E is a cross-sectional view showing the deposition of a first dielectric layer on the peripheral region, floating guard ring regions, and selected grid p-wells ofFIG. 3D , and the formation of a backside ohmic contact. -
FIG. 3F is a cross-sectional view showing the formation of openings in the passivation layer above the peripheral region and selected grid p-wells ofFIG. 3E , and showing the deposition of a Schottky barrier metal layer in the area of those openings. -
FIG. 3G is a cross-sectional view showing the formation of an anode contacting the Schottky barrier metal layer ofFIG. 3F . -
FIG. 3H is a cross-sectional view showing the formation of a second dielectric layer on the anode, on portions of the Schottky barrier metal layer, and on portions of the first dielectric material ofFIG. 3G . -
FIG. 3I is a cross-sectional view showing the creation of an opening in the second dielectric layer ofFIG. 3H , and showing the formation of a cathode contacting the ohmic contact ofFIGS. 3E-3H . -
FIG. 4A is a cross-sectional diagram of an alternative embodiment showing an n-type implant region across the whole device. -
FIG. 4B is a cross-sectional diagram of a variation showing an n-type implant region formed only in the active area of the whole device. -
FIG. 5A is a cross-sectional diagram of another embodiment showing a second p-type implant in selected areas in the active area to allow the Schottky barrier metal layer to link to the embedded p-well network, followed by an etch step to remove a surface portion of the n-layer above the peripheral region and in the guard ring area. -
FIG. 5B is a cross-sectional diagram of a variation showing a second p-type implant in the peripheral region and guard ring regions at the same time with the selected areas in the active area. -
FIG. 5C is a cross-sectional diagram showing a first implant step of another embodiment in a process to avoid etching the material. -
FIG. 5D is a cross-sectional diagram showing a second implant step of the process to avoid etching the material in the embodiment ofFIG. 5C . -
FIG. 1 is a cross-sectional diagram showing an embodiment of the embedded junction barrier grid according to an embodiment of the invention.FIG. 2 is a cross-sectional diagram showing a conventional prior art JB (Junction Barrier) Schottky structure. - Referring to
FIG. 1 , a new SiC SBD (Schottky barrier diode)structure 10 with an “embedded” junction barrier grid is disclosed. As shown inFIG. 1 , the embedded junction barrier grid is drawn schematically and the layers are identified to illustrate an n-type SiC material with a p-type junction barrier grid. The concept applies equally well to a p-type SiC material employing an n-type junction barrier grid. The grid spacing is shown for ease of illustration and should be sufficiently wide to avoid obstructing current flow or causing forward voltage to rise. For a 1200V SiC Schottky diode, the p-well width can be 1 to 3 μm wide with a spacing of 4 to 8 μm. - A conventional prior art JB Schottky structure (resembling the structure described in Baliga, The Pinch Rectifier: A Low-Forward-Drop High-Speed Power Diode) is shown in
FIG. 2 . Compared to the conventional SiC JB Schottky diode ofFIG. 2 , the new structure comprises a p-n junction grid which does not reach the surface for essentially all of the grid area. This feature of the new structure efficiently increases the active Schottky area which lowers the forward voltage drop and at the same time maintains the excellent reverse blocking voltage and low leakage current of prior art structures with improved current capability. - The junction barrier grid in
FIG. 1 includes agrid 42 of p-type regions type region 44. Unlike the correspondingconventional grid structure 22 inFIG. 2 , most of thegrid 42 in the new structure is not at the surface of n−-SiC drift layer 16, but rather is at a depth (e.g., 0.5-1.5 μm) below the upper surface oflayer 16, being formed of “embedded p-wells.” Since most of the embedded p-wells 64 of thegrid 42 do not contact Schottkybarrier metal layer 52 directly, the area ofSchottky barrier contact 74 is essentially the entire top surface of theactive area 60. - The wide peripheral p-
type region 44 connects to some of the embedded p-wells 66 via the Schottkybarrier metal layer 52, throughrecesses 51 in the semiconductor, to define the p-grid potential. Resistance from the peripheral p-type region 44 along the embedded p-wells is reduced by a selected number ofvias 51 etched through an upper portion of the n−-SiC drift layer 16 to reach selected p-wells 66 in thegrid 42 of embedded p-wells within the centralactive area 60 of the device. -
FIG. 2A is a plan view showing a two-dimensional “embedded network” of p-wells stripes in accordance with an embodiment of the invention. - Referring to
FIG. 2A , a selected number of embedded p-wells can also be created in the direction parallel to the page to create a 2-dimensional “embedded network” to reduce p-well resistance. Schottkybarrier metal layer 52 contacts the selected p-wells 66 through therecesses 51 in the ensuing metallization process. - Referring to
FIG. 2 , the n−-SiC drift layer 16 on top of floating guard rings 41 at the periphery of the device is also etched off at the same time therecesses 51 are created to allow the p-type dopedguard ring regions 41 to reach the surface. The surface is then passivated to provide stable high voltage blocking capability. -
FIGS. 3A-3I are diagrams showing a fabrication process in accordance with an embodiment of the invention.FIG. 3A is a cross-sectional view of awafer 12 covered by abuffer layer 14 and further covered by anepitaxial drift layer 16 into which ion implantation is carried out through a patternedoxide mask 18.FIG. 3B is a cross-sectional view of aperipheral region 44, floatingguard ring regions 41, and grid 42 p-wells formed in theepitaxial drift layer 16 ofFIG. 3A , along with an optional n-type implant 46. - Referring to
FIGS. 3A and 3B , asubstrate 102 of starting material having anupper surface 104 may include an n-SiCepitaxial drift layer 16 on top of a heavily doped n+-buffer layer 14 on top of an n+ wafer 12. SiC is used throughout for ease of discussion. The same principle applies to Schottky Barrier Diode made on all commonly known semiconductor materials such as germanium, silicon, GaAs, GaN, InP, diamond, and ternary derivatives involving II-VI compounds, etc. Example doping concentrations are: for n+ wafer 12, 5×1017-1×1019 cm−3; for n+-buffer layer 14, 5×1017-1×1019 cm−3; and for n-SiCepitaxial drift layer - An
implant blocking mask 18 is created on the top surface as shown inFIG. 3A by depositing and patterning an oxide layer of sufficient thickness. A 2 μm thick oxide would be sufficient for implant energy around 200 KeV for aluminum. Appropriate blockingmask 18 thickness is well-known in the art and can be modified for different implant energy and species. - Next, p-type ions are embedded below the
surface 104 using a single or multiple ion implantation steps to create p-type regions type regions optional layer 46 of shallow n-type implant of between 1×1011 and 1×1013/cm2 may be implanted between the top surface and the embedded p-well (e.g. to a depth of 0.2-0.5 μm) to ensure retaining the desired n-type doping level at the surface. Following implant activation, the p-type regions type implant layer 46 are established as shown inFIG. 3B . -
FIG. 3C is a cross-sectional view showing the removal of a surface portion of theepitaxial drift layer 16 ofFIG. 3B in the areas of theperipheral region 44, the floatingguard ring regions 41, and selected grid p-wells 66, along with the optional n-type implant 46 ofFIG. 3B in such cases.FIG. 3D is a cross-sectional view showing the removal of a surface portion of theepitaxial drift layer 16 ofFIG. 3B in the areas of theperipheral region 44, the floatingguard ring regions 41, and selected grid p-wells 66, without the optional n-type implant 46 ofFIG. 3B . - Referring to
FIGS. 3C and 3D , an etch step is performed to remove a shallow surface portion oflayer 16, including the optional n-layer 46, at selected locations above thegrid 42 in theactive area 60, above theperipheral region 44, and in the area of theguard ring regions 41 of the device to selectively expose embedded p-type regions wells 66 to which contact can be made at theupper surface 104 and remaining embedded p-wells 64 to which contact cannot be made at theupper surface 104, as shown inFIG. 3C . (The peripheral etch establishes theguard ring regions 41 for blocking high voltage while the etch at selected locations above thegrid 42 in theactive area 60 will allow a Schottkybarrier metal layer 52 to link to theperipheral regions 44 and the selected p-wells 66 of the embedded p-well network.)FIG. 3D shows a construction without the optional n-implant 46 at the surface. An example etch depth is 0.5-1.0 μm. -
FIG. 3E is a cross-sectional view showing the deposition of afirst dielectric layer 30 on theperipheral region 44, floating guard ring regions, and selected grid p-wells 66 ofFIG. 3D , and the formation of a backsideohmic contact 50. - Referring to
FIG. 3E , the top surface is next thermally oxidized to grow a thin layer of oxide followed with deposition ofdielectric material 30 to prepare the surface for high voltage. Since very high surface electric field is present at the surface in the area of the guard rings 41, the dielectric material in conjunction with the semiconductor surface must have the desirable characteristics of possessing high dielectric strength, low flatband voltage, low polarizability, and low charge trapping. Most dielectric films deposited using Plasma Enhanced Chemical Vaper Deposition (PECVD) polarize and trap charges under high electric field. The task is to minimize these adverse effects with specific guard ring geometry. Undoped oxide, oxynitride, PSG (phosphorus doped silicon glass), BPSG (boron and phosphorus doped silicon glass), or combinations thereof have been known to have the aforementioned adverse effects minimized and made usable for specific guard ring designs. Thislayer 30 is shown inFIG. 3E . An example thickness is 0.5-1.5 μm. - Following dielectric film deposition, nickel is deposited by sputter deposition or evaporation onto the backside as shown in
FIG. 3E . A thermal process can be performed to form a nickel-silicide ohmic contact 50 to the n+ SiC wafer 12, with an example thickness of 0.1 μm. A Rapid Thermal Process (RTP) or Rapid Thermal Anneal (RTA) may be used for this operation. Alternatively, a diffusion furnace may be used to form the ohmic contact. To ensure nickel does not form an oxide which is difficult to remove, an inert gas with low moisture content such as Argon is used as carrier gas during the thermal process. -
FIG. 3F is a cross-sectional view showing the formation of openings in thepassivation layer 30 above theperipheral region 44 and selected grid p-wells 66 ofFIG. 3E , and showing the deposition of a Schottkybarrier metal layer 52 in the area of those recesses. Referring toFIG. 3F , in the next step, thedielectric film 30 on the front of the device is patterned to provide an opening for aSchottky barrier contact 74 to the n−-SiC epitaxial layer and aSchottky barrier contact 76 to the selected embedded p-wells 66 in theactive area 60 through the selected recesses 51 formed by the previous etch step of the semiconductor, as well as a Schottky barrier contact to the peripheralguard ring region 44. The Schottkybarrier metal layer 52 can be deposited unto the top surface by sputter deposition or evaporation of titanium, tungsten, chromium, nickel, or other suitable metal or alloys to form different barrier heights. If a lift-off process as is commonly known in the art is employed, no metal etching will be necessary to define the top metal pattern. Alternatively, a masking and etch procedure can be followed to achieve the same objective of defining the top metal pattern. Compared to the nickel barrier, the lower barrier height of titanium gives lower forward voltage drop, while the higher reverse leakage current due to the lower barrier height can be suppressed by the embedded p-well structure. The Schottkybarrier metal layer 52 also overlaps onto theoxide layer 30 as shown inFIG. 3F . An example thickness for Ni is 0.1 μm; or 0.1 μm for Ti. A forming gas (hydrogen containing gas) anneal (FGA) at an elevated temperature is performed on the device to reduce the resistance of theSchottky bather contacts -
FIG. 3G is a cross-sectional view showing the formation of ananode 54 contacting the Schottkybarrier metal layer 52 ofFIG. 3F .FIG. 3H is a cross-sectional view showing the formation of asecond dielectric layer 32 on theanode 54, on portions of the Schottkybarrier metal layer 52, and on portions of the firstdielectric material 30 ofFIG. 3G . - Referring to
FIGS. 3G and 3H , to conduct high current out of the device, a front-side anode electrode 54 is formed such as by depositing tungsten, aluminum or aluminum alloys (e.g. at a thickness of 1-5 μm) using sputter deposition or evaporation followed by a patterning and etch step. This construction is illustrated inFIG. 3G . Next the device surface is covered by anotherdielectric material 32 for final passivation, as shown inFIG. 3H . Thedielectric material 32 may be the same as or different fromlayer 30 but with similar desirable characteristics as suggested previously, including undoped oxide, oxynitride, PSG (phosphorus doped silicon glass), BPSG (boron and phosphorus doped silicon glass), or their combinations. Polyimide is also widely used for this purpose. -
FIG. 3I is a cross-sectional view showing the creation of an opening in thesecond dielectric layer 32 ofFIG. 3H , and showing the formation of acathode 56 contacting theohmic contact 50 ofFIGS. 3E-3H . - Referring to
FIG. 3I , an opening in thefinal passivation 32 is created so the device can receive wire-bonding to theanode 54. The die-attachmetal 56 which also works as cathode electrode of the diode, usually a triple layer of titanium, nickel and silver, is evaporated or sputtered onto the back-side of the device in contact with theohmic contact metal 50. Thefinal device structure 10 is shown inFIG. 3I . -
FIG. 4A is a cross-sectional diagram of an alternate embodiment showing an n-type implant region 47 across the whole device.FIG. 4B is a cross-sectional diagram of a variation showing an n-type implant region 147 formed only in the active area of the whole device. - Referring to
FIGS. 4A and 4B , to reduce the resistance between the adjacent p-wells, an optional n-type layer 47 can be added on top of theSiC drift layer 16 before the deep p-type ion implantation, by either epitaxial growth with a doping concentration between 1×1016 and 1×1017/cm3, or an n-type implantation with dose between 1×1011 and 1×1013/cm2. The n-type implant region 47 can extend across the whole device as shown inFIG. 4A , or an n-type implant region 147 can be formed just in theactive area 60 as shown inFIG. 4B . -
FIG. 5A is a cross-sectional diagram of another embodiment showing a second p-type implant 148 in selected areas in theactive area 60 to allow the Schottkybarrier metal layer 52 to link to the embedded p-well network, followed by an etch step to remove a surface portion of the n-layer 16 above the peripheral region and in the guard ring area.FIG. 5B is a cross-sectional diagram of a variation showing a second p-type implant 48 in theperipheral region 44 andguard ring regions 41 at the same time with the selected areas in theactive area 60.FIG. 5C is a cross-sectional diagram showing a first implant step of another embodiment in a process to avoid etching the material.FIG. 5D is a cross-sectional diagram showing asecond implant step 49 of the process to avoid etching the material in the embodiment ofFIG. 5C . - There are alternative ways other than
FIG. 3C to expose the embedded p-wells, as shown inFIGS. 5A through 5C . InFIG. 5A , a second p-type implant 148 is performed in selected areas in the active area to allow the Schottkybarrier metal layer 52 to link to the embedded p-well network, followed by an etch step to remove the surface portion of the n-layer 16 at theperipheral region 44 and in theguard ring 41 area. The second p-type implant 148 is performed such that contact may be made at theupper surface 104 to selected embedded p-wells 66, but contact may not be made at theupper surface 104 to the remaining embedded p-wells 64. To avoid an etching step and to simplify the process, an alternative second p-type implant 48 is performed in the peripheral and guard ring area at the same time with the selected area in the active area, as shown inFIG. 5B . -
FIGS. 5C and 5D show another process to avoid etching the material. Referring toFIG. 5C , during the first p-type implant, only thegrid 42 of p-wells in the active area is implanted. Referring toFIG. 5D , theperipheral region 44 andguard ring area 41, along with extensions of selected p-wells 66 in the deviceactive area 60, are formed by a second p-type implant 49. - Having described and illustrated the principles of the invention in a preferred embodiment thereof, it should be apparent that the invention can be modified in arrangement and detail without departing from such principles. We claim all modifications and variations coming within the spirit and scope of the following claims.
Claims (8)
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US12/912,539 US20110037139A1 (en) | 2008-03-21 | 2010-10-26 | Schottky barrier diode (sbd) and its off-shoot merged pn/schottky diode or junction barrier schottky (jbs) diode |
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US12/365,083 US7851881B1 (en) | 2008-03-21 | 2009-02-03 | Schottky barrier diode (SBD) and its off-shoot merged PN/Schottky diode or junction barrier Schottky (JBS) diode |
US12/912,539 US20110037139A1 (en) | 2008-03-21 | 2010-10-26 | Schottky barrier diode (sbd) and its off-shoot merged pn/schottky diode or junction barrier schottky (jbs) diode |
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US12/912,539 Abandoned US20110037139A1 (en) | 2008-03-21 | 2010-10-26 | Schottky barrier diode (sbd) and its off-shoot merged pn/schottky diode or junction barrier schottky (jbs) diode |
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