US20090034206A1 - Wafer-level assembly of heat spreaders for dual ihs packages - Google Patents
Wafer-level assembly of heat spreaders for dual ihs packages Download PDFInfo
- Publication number
- US20090034206A1 US20090034206A1 US12/247,193 US24719308A US2009034206A1 US 20090034206 A1 US20090034206 A1 US 20090034206A1 US 24719308 A US24719308 A US 24719308A US 2009034206 A1 US2009034206 A1 US 2009034206A1
- Authority
- US
- United States
- Prior art keywords
- wafer
- tim
- die
- package
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 230000009977 dual effect Effects 0.000 title description 3
- 239000000758 substrate Substances 0.000 claims abstract description 82
- 238000000034 method Methods 0.000 claims abstract description 69
- 230000008569 process Effects 0.000 claims description 51
- 238000012545 processing Methods 0.000 claims description 17
- 239000000463 material Substances 0.000 claims description 15
- 235000012431 wafers Nutrition 0.000 description 98
- 238000010586 diagram Methods 0.000 description 27
- 238000004519 manufacturing process Methods 0.000 description 22
- 229910000679 solder Inorganic materials 0.000 description 17
- 235000013870 dimethyl polysiloxane Nutrition 0.000 description 11
- 239000004205 dimethyl polysiloxane Substances 0.000 description 11
- 238000012360 testing method Methods 0.000 description 11
- 229920001296 polysiloxane Polymers 0.000 description 8
- 239000004065 semiconductor Substances 0.000 description 8
- 230000001070 adhesive effect Effects 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 239000000853 adhesive Substances 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 230000035882 stress Effects 0.000 description 6
- 238000000151 deposition Methods 0.000 description 5
- 230000015654 memory Effects 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 238000012536 packaging technology Methods 0.000 description 5
- 239000002245 particle Substances 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000005411 Van der Waals force Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 239000000945 filler Substances 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 238000004806 packaging method and process Methods 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 239000011810 insulating material Substances 0.000 description 3
- 238000005272 metallurgy Methods 0.000 description 3
- 238000012858 packaging process Methods 0.000 description 3
- 238000002360 preparation method Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 238000013019 agitation Methods 0.000 description 2
- 230000000712 assembly Effects 0.000 description 2
- 238000000429 assembly Methods 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 230000005484 gravity Effects 0.000 description 2
- 238000004377 microelectronic Methods 0.000 description 2
- 238000010295 mobile communication Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 238000009662 stress testing Methods 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 101710149792 Triosephosphate isomerase, chloroplastic Proteins 0.000 description 1
- 101710195516 Triosephosphate isomerase, glycosomal Proteins 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000000356 contaminant Substances 0.000 description 1
- KUNSUQLRTQLHQQ-UHFFFAOYSA-N copper tin Chemical compound [Cu].[Sn] KUNSUQLRTQLHQQ-UHFFFAOYSA-N 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000008367 deionised water Substances 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000004519 grease Substances 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000012782 phase change material Substances 0.000 description 1
- 229920000435 poly(dimethylsiloxane) Polymers 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000001338 self-assembly Methods 0.000 description 1
- 230000035939 shock Effects 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 238000009987 spinning Methods 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
- 230000007480 spreading Effects 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3675—Cooling facilitated by shape of device characterised by the shape of the housing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/27—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4871—Bases, plates or heatsinks
- H01L21/4882—Assembly of heatsink parts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68309—Auxiliary support including alignment aids
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04026—Bonding areas specifically adapted for layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
- H01L2224/29111—Tin [Sn] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
- H01L2924/097—Glass-ceramics, e.g. devitrified glass
- H01L2924/09701—Low temperature co-fired ceramic [LTCC]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
Definitions
- Embodiments of the invention relate to the field of semiconductor, and more specifically, to semiconductor packaging.
- thermal management scheme is the use of heat spreaders on semiconductor dice.
- FIG. 1A is a diagram illustrating a manufacturing system in which one embodiment of the invention can be practiced.
- FIG. 1B is a diagram illustrating a system according to one embodiment of the invention.
- FIG. 2A is a diagram illustrating a carrier template according to one embodiment of the invention.
- FIG. 2B is a diagram illustrating placing heat spreaders into cavities of the carrier template according to one embodiment of the invention.
- FIG. 2C is a diagram illustrating forming a heat spreader (HS) array on a HS support substrate according to one embodiment of the invention.
- FIG. 2D is a diagram illustrating a diced wafer supported by a wafer support substrate (WSS) according to one embodiment of the invention.
- WSS wafer support substrate
- FIG. 2E is a diagram illustrating bonding the thin dice in the diced wafer to the heat spreaders in the HS array according to one embodiment of the invention.
- FIG. 2F is a diagram illustrating an HS-bonded diced wafer supported by a WSS according to one embodiment of the invention.
- FIG. 2G is a diagram illustrating applying a dicing tape to the HS-bonded diced wafer supported by a WSS according to one embodiment of the invention.
- FIG. 2H is a diagram illustrating releasing the WSS from the HS-bonded diced wafer according to one embodiment of the invention.
- FIG. 2I is a diagram illustrating picking an individual die assembly according to one embodiment of the invention.
- FIG. 3 is a diagram illustrating a package according to one embodiment of the invention.
- FIG. 4 is a flowchart illustrating a process to assemble wafer-level heat spreaders for dual HS packages according to one embodiment of the invention.
- FIG. 5 is a flowchart illustrating a process to form a HS array on HS support substrate according to one embodiment of the invention.
- FIG. 6 is a flowchart illustrating a process to form diced wafer supported by a WSS according to one embodiment of the invention.
- FIG. 7 is a flowchart illustrating a process to bond thin dice to heat spreaders according to one embodiment of the invention.
- FIG. 8 is a flowchart illustrating a process to assemble a HS-bonded thin die into a package according to one embodiment of the invention.
- An embodiment of the present invention is a technique to fabricate a package.
- a heat spreader (HS) array on a HS support substrate is formed.
- the HS array has a plurality of heat spreaders.
- a diced wafer supported by a wafer support substrate (WSS) is formed.
- the diced wafer has a plurality of thin dice.
- the thin dice in the diced wafer are bonded to the heat spreaders in the HS array to form HS-bonded thin dice between the HS support substrate and the WSS.
- One embodiment of the invention may be described as a process which is usually depicted as a flowchart, a flow diagram, a structure diagram, or a block diagram. Although a flowchart may describe the operations as a sequential process, many of the operations can be performed in parallel or concurrently. In addition, the order of the operations may be re-arranged. A process is terminated when its operations are completed. A process may correspond to a method, a program, a procedure, a method of manufacturing or fabrication, etc.
- An embodiment of the present invention is a technique to fabricate a package having two heat spreaders.
- the technique includes wafer-level bonding an array of heat spreaders to a diced thinned wafer.
- a carrier template having an array of cavities is fabricated with high precision. The dimensions and positions of the cavities are carefully matched with the dimensions and positions of the dice on the silicon wafer to which the heat spreaders are bonded.
- the heat spreaders (HS) which have a thin layer of a solder layer on one side are placed in the cavities of the carrier template (i.e., the side with the solder of the HS faces the carrier template).
- the thin solder layer acts as a first thermal interface material (TIM) when the dice are assembled into packages.
- a heat spreader support substrate covered by a thin layer of silicone such as polydimethyl siloxane (PDMS) is then placed on the heat spreaders under a pressure. Due to the van der Waals forces between the PDMS and the heat spreaders, all the heat spreaders in the carrier template adhere to the thin PDMS layer.
- the HS array is transferred to the PDMS-coated support substrate.
- a diced wafer is formed by mounting a wafer onto a wafer support substrate (WSS), thinning the wafer, depositing a backside metallurgy (BSM) layer and/or a thin solder layer on backside of the wafer, and dicing the thinned wafer into thin dice without releasing dies from the WSS.
- WSS wafer support substrate
- BSM backside metallurgy
- the HS array is aligned and bonded to the thin dice on the diced wafer by reflowing the solder layer on the HS array and/or Si dice under pressure.
- the HS support substrate is then released from the HS array-bonded wafer.
- the HS array-bonded wafer is then mounted on a dicing tape and the WSS is released.
- the individual HS-bonded dice are then assembled into packages. Each package has a second TIM and a second heat spreader with a larger size for further heat spreading.
- the technique provides efficient placement of HS array because the carrier template may be manufactured in advance with high precision. Therefore, time-consuming high accuracy pick-and-place operation for HS array is eliminated.
- the technique eliminates the use of any adhesive for attaching the heat spreaders on the support substrate and associated support substrate releasing processing operations. Furthermore, the compliant PDMS layer on the HS support substrate may better compensate the non-co-planarity and HS thickness variations, leading to better bond-line control between the heat spreaders and the silicon dice.
- FIG. 1A is a diagram illustrating a manufacturing system 5 in which one embodiment of the invention can be practiced.
- the system 5 includes a wafer fabrication phase 10 , wafer preparation phase 15 , a wafer dicing phase 20 , a carrier template fabrication phase 25 , a heat spreader (HS) support substrate fabrication phase 30 , a HS array formation phase 35 , a wafer-level bonding phase 40 , a support substrate releasing phase 45 , a die attachment phase 50 , an encapsulation and HIS attachment phase 55 , and a stress testing phase 60 .
- the system 5 represents a manufacturing flow of a semiconductor packaging process.
- the wafer fabrication phase 10 fabricates the wafer containing a number of dice.
- the individual dice may be any microelectronic devices such as microprocessors, memory devices, interface circuits, high power optical devices etc.
- the wafer fabrication phase 10 includes typical processes for semiconductor fabrication such as preparation of the wafer surface, growth of silicon dioxide (SiO 2 ), patterning and subsequent implantation or diffusion of dopants to obtain the desired electrical properties, growth or deposition of a gate dielectric, and growth or deposition of insulating materials, depositing layers of metal and insulating material and etching it into the desired patterns.
- the metal layers consist of aluminium or copper.
- the various metal layers are interconnected by etching holes, called “vias,” in the insulating material.
- the wafer preparation phase 15 prepares a wafer containing dice for packaging and testing. During this phase, the wafers are sorted after the patterning process. An inspection may be carried out to check for wafer defects. Then, the wafer may be mounted on a wafer support substrate (WSS) that adheres to the front side (or bump side) of the wafer. The WSS provides mechanical support for handling during subsequent phases. The wafer is then thinned to a desired thickness to provide ultra-thin wafer. Additional processing may be performed to prepare the wafer for subsequent phases, such as deposition of backside metallization (BSM) or solder layer on the wafer.
- BSM backside metallization
- the wafer dicing phase 20 dices, cuts, or saws the wafer into individual dice from the backside of the wafer.
- the dicing depth may be well controlled such that only the thin wafer is diced and the WSS may not be diced.
- High precision saw blade/laser and image recognition unit may be used.
- De-ionized water may be dispensed on the wafer to wash away any residual particles or contaminants during the dicing. Then, the wafer is dried by being spun at high spinning speed.
- the carrier template fabrication phase 25 fabricates one or more carrier templates to carry the heat spreaders to be bonded with the dice on the wafer.
- the fabrication may be performed on facilities outside the semiconductor fabrication facilities such as by other vendors.
- the carrier template fabrication phase 25 receives information or data files regarding the dimensions and positions of the dice on the wafer. This information is used to fabricate the carrier templates with high precision.
- the HS support substrate fabrication phase 30 fabricates the HS support substrate to support the array of heat spreaders.
- the HS support substrate may be used to hold the heat spreaders for precision bonding with the dice.
- the HS array formation phase 35 forms the HS array supported by the HS support substrate.
- the heat spreaders may be fabricated by HS manufacturers and used in this phase.
- the HS array contains the heat spreaders that are positioned to correspond to the positions of the dice on the wafer.
- the wafer-level bonding phase 40 bonds the HS array to the dice on the wafer.
- the bonding essentially attaches the heat spreaders to the corresponding dice at the wafer level.
- the support substrate releasing phase 45 releases the HS support substrate and the wafer support substrate from the assembly.
- the resulting assembly includes array of dice attached to first heat spreaders.
- the die attachment phase 50 attaches the die to a package substrate.
- the substrate material depends on the packaging type. It may be ceramic, organic, or inorganic such as silicon.
- the die may be attached to a package substrate through flip chip technology.
- the encapsulation and IHS attachment phase 55 underfills the gap between the die and the substrate and attaches an IHS. Underfill material may be dispensed between the die and the substrate. Integrated heat spreader (IHS) may be attached to the die and substrate assembly. The fully assembled package 65 is ready to be tested.
- IHS Integrated heat spreader
- the stress testing phase 60 performs one or more tests such as Highly Accelerated Stress Test (HAST) or biased-HAST on the device package under stress conditions.
- a test chamber may be designed to conduct a stress test. It may have monitoring circuits, measurement circuits, and other data processing equipment.
- the package 65 is placed in the test chamber subject to the stress test. It may be powered or non-powered.
- Various stress tests may be performed on the wafer or on the packaged devices 65 at various points of the manufacturing process flow.
- the tests may follow standards such as Joint Electron Device Engineering Council (JEDEC) standards or military standards. Examples of these tests may include electrostatic discharge (ESD), or human body model (HBM), high temperature operational life (HTOL), thermal shock, temperature cycle, high temperature storage, vibration and mechanical loading, shear testing, and accelerated moisture resistance.
- JEDEC Joint Electron Device Engineering Council
- FIG. 1B is a diagram illustrating a system 100 according to one embodiment of the invention.
- the system 100 represents a mobile communication module. It includes a system on package (SOP) 110 , an intermediate frequency processing unit 160 , and a base-band processing unit 170 .
- SOP system on package
- the SOP 110 represents the front end processing unit for the mobile communication module. It is a transceiver incorporating on-package integrated lumped passive components as well as radio frequency (RF) components. It includes an antenna 115 , a duplexer 120 , a filter 125 , a system-on-chip (SOC) 150 , a power amplifier (PA) 180 , and a filter 185 .
- RF radio frequency
- the antenna 115 receives and transmits RF signals.
- the RF signals may be converted to digital data for processing in subsequent stages. It is designed in compact micro-strip and strip-line for L and C-band wireless applications.
- the duplexer 120 acts as a switch to couple to the antenna 115 to the receiver and the transmitter to the antenna 115 .
- the filters 125 and 185 are C-band LTCC-strip-line filter or multilayer organic lumped-element filter at 5.2 GHz and narrowband performance of 200 MHz suitable for the Institute of Electrical and Electronic Engineers (IEEE) 802.11 wireless local area network (WLAN).
- the SOC 150 includes a low noise amplifier (LNA) 130 , a down converter 135 , a local voltage controlled oscillator (VCO) 140 , an up converter 171 , and a driver amplifier 175 .
- the LNA 130 amplifies the received signal.
- the down converter 135 is a mixer to convert the RF signal to the IF band to be processed by the IF processing unit 160 .
- the up converter 171 is a mixer to convert the IF signal to the proper RF signal for transmission.
- the VCO 140 generates modulation signal at appropriate frequencies for down conversion and up conversion.
- the driver amplifier 175 drives the PA 180 .
- the PA 180 amplifies the transmit signal for transmission.
- the IF processing unit 160 includes analog components to process IF signals for receiving and transmission. It may include a band-pass filter and a low pass filter at suitable frequency bands. The filter may provide base-band signal to the base-band processing unit 170 .
- the base-band processing unit 170 may include an analog-to-digital converter (ADC) 172 , a digital-to-analog converter (DAC) 174 , a digital signal processor (DSP) 176 , and memory device 178 .
- ADC 172 and the DAC 174 are used to convert analog signals to digital data and digital data to analog signal, respectively.
- the DSP 176 is a programmable processor that may execute a program to process the digital data.
- the memory device 178 may be flash memories or random access memories.
- the memory device 178 may be packaged using Flip-Chip Ball Grid Array (FCBGA) packaging technology, a molded packaging, or any other suitable packaging technologies.
- the memory device 178 may be manufactured according to the manufacturing flow 5 shown in FIG. 1A . It may be the device package 65 . It may include an ultra-thin die in the package.
- the base-band processing unit 170 may also include memory and peripheral components. The DSP 176 may, therefore, be coupled to the front end processing unit via the IF processing unit 160 and/or the base-band processing unit 170 to process the digital data.
- the SOP 110 may be a multi-layer three-dimensional (3D) architecture for a monolithic microwave integrated circuit (MMIC) with embedded passives (EP) technology. It may be implemented using Low Temperature Co-fired Ceramics (LTCC) and organic-based technologies.
- the 3D architecture may include multiple layers include a layer 117 to implement the antenna 115 , layers 122 , 124 , and 186 for the filters 125 and 185 , and layer 188 for the SOC 150 and the passive components using EP technology.
- the packaging technology involves embedded passives with multiple layers.
- FIG. 2A is a diagram illustrating a carrier template 210 according to one embodiment of the invention.
- the carrier template 210 may be manufactured in advance and separately from the packaging process.
- the carrier template 210 may be made from materials such as silicon. It has a number of cavities 215 with tight dimensional tolerances.
- the cavities 215 may be formed or fabricated using wet etching or any other etching processes.
- the dimensions and positions of the cavities 215 are carefully matched with the dimensions and positions of the heat spreaders that are bonded to the corresponding dice on a wafer.
- the dimensions and positions of the dice on the wafer are typically known in advance and may be available in computer readable forms which may be used to precisely control the formation of the cavities 215 .
- the fabrication of the carrier template 210 and the cavities 215 may be performed independently and separately from the packaging process.
- FIG. 2B is a diagram illustrating placing heat spreaders into cavities of the carrier template according to one embodiment of the invention.
- the carrier template 210 is placed in a shaker 212 .
- the shaker 212 may be a mechanical shaker that shakes or vibrates at a predetermined rate. It typically has enclosure to keep items or articles being shaken from being thrown out during shaking.
- a number of heat spreaders are placed inside the shaker 212 on the carrier template 210 .
- the heat spreaders (HS) are designed to have dimensions fit within the cavities 215 , which in turn fit the dimensions of the dice on the wafer. They may be made by any material having a high thermal conductivity such as copper or SiC. Through gravity and shaking forces, the heat spreaders self assemble and fall into the cavities 215 to become HS 220 .
- Heat spreaders that do not fall into the cavities 215 are excess HS 225 and may be removed from the shaker 212 .
- the heat spreaders may be placed into the cavities 215 by a pick-and-place equipment. Since the carrier template 210 is made of rigid material and is not a fragile object, the pick-and-place equipment may place the heat spreaders in the cavities 215 without high precision or accuracy. Through gravity, the heat spreaders may settle into the cavities 215 when they are slightly misplaced.
- FIG. 2C is a diagram illustrating forming a heat spreader (HS) array on a HS support substrate according to one embodiment of the invention.
- the heat spreaders 220 in the cavities 215 are now transferred to a HS support substrate 230 .
- the HS support substrate 230 may be any suitable material, such as glass. It is coated or covered by a thin layer of silicone 232 .
- the silicone 232 may be any polymer that has good adhesive property.
- One such polymer is the poly-dimethyl siloxane (PDMS), a rubber material.
- the HS support substrate 230 with the PDMS layer 232 is placed, or pressed, on the HS 220 in the cavities 215 of the carrier template 210 .
- the PDMS layer 232 picks up all the HS 220 due to the van der Waals force.
- the HS 220 stay at the same positions on the HS support substrate 230 as they are in the cavities 215 . Therefore, the HS 220 form an array of heat spreaders that are located at positions to correspond or match with positions of dice on a wafer.
- the carrier template 210 may be discarded or re-used to hold a next array of heat spreaders.
- the HS support substrate 230 , the layer of silicone 232 and the HS array 220 form the HS array 235 with HS support substrate.
- FIG. 2D is a diagram illustrating a diced wafer 255 supported by a wafer support substrate (WSS) according to one embodiment of the invention.
- the WSS-supported diced wafer 255 includes a WSS 245 and a number of singulated thinned dice 260 1 , to 260 N .
- the WSS 245 is mounted onto a wafer.
- the mounting may be performed using an adhesive to attach the WSS 245 to the wafer.
- the wafer is then thinned to a desired thickness.
- the thickness may be less than 75 ⁇ m, or may be approximately 50 ⁇ m.
- a backside metallurgy (BSM) layer 250 is deposited on the backside of the wafer.
- This BSM layer 250 may have a thickness of about 3 to 10 ⁇ m. It serves to provide the basis for attachment during bonding. It may consist of a stack of metal layers such as titanium (Ti), nickel (Ni) and gold (Au). Besides these metal layers, it may also include a solder layer such as tin-copper.
- the solder layer serve as the thermal interface material (TIM) and it may have a process temperature range from 180° C. to 280° C.
- the solder material is carefully designed such that, after bonding, the TIM layer has a high remelting temperature (e.g., higher than 250° C.) and thus it does not melt again during die to substrate assembly processes. Then, the thinned wafer and the BSM layer 250 are diced, sawed, or singulated into individual dice.
- FIG. 2E is a diagram illustrating bonding the thin dice in the diced wafer 255 to the heat spreaders in the HS array 235 according to one embodiment of the invention.
- the thin dice 260 j 's in the diced wafer 255 are then aligned to the HS 220 in the HS array with HS support substrate 235 . Since the HS 220 are positioned according to the positions of the cavities, they are matched with the thin dice 260 j 's.
- the thin dice 260 j 's in the diced wafer 255 are then bonded or attached to the HS 220 in the HS array with HS support substrate 235 .
- the bonding may be performed by reflowing the solder layer on the HS array and/or the solder of the BSM layer 250 on the wafer under pressure from at least one of the WSS 245 or the HS support substrate 230 .
- the pressure may be applied to both the WSS 245 and the HS support substrate 230 , or one of them.
- the reflow causes the HS 220 to be bonded or attached to the corresponding thin dice 260 j 's.
- FIG. 2F is a diagram illustrating an HS-bonded diced wafer supported by a WSS according to one embodiment of the invention.
- the adhesion strength between the HS 220 to the thin dice 260 j 's is typically greater than the van der Waals force that keeps the HS 220 to the layer of silicone 232 on the HS support substrate 230 . Therefore, the HS support substrate 230 and the coated layer of silicone 232 may be easily removed from the bonded assembly. The removal may be performed by vacuum sucking. There are other ways to release the HS 220 from the support substrate 230 . Chemical solvent/laser/heat may also be utilized to facilitate the debonding.
- FIG. 2G is a diagram illustrating applying a dicing tape to the HS-bonded diced wafer supported by a WSS according to one embodiment of the invention.
- a dicing tape 270 is then attached or mounted onto the HS 220 of the thin dice assembly.
- the dicing tape 270 essentially holds the individual die assemblies together.
- FIG. 2H is a diagram illustrating releasing the WSS from the HS-bonded diced wafer according to one embodiment of the invention.
- the WSS 245 is then released from the thin die assembly with the dicing tape 270 .
- the release of the WSS 245 may be carried out by a number of methods including mechanical and thermal removal, laser or ultraviolet (UV) light.
- the laser may be used to irradiate the WSS 245 .
- the irradiation may weaken the adhesion of adhesive that is used to attach the WSS 245 to the wafer 240 .
- FIG. 2I is a diagram illustrating picking an individual die assembly according to one embodiment of the invention.
- a pick-and-place equipment or tool may be used to pick up the individual die assemblies and assemble them into packages.
- a die assembly 280 now has a die, a first TIM, and a matching heat spreader.
- FIG. 3 is a diagram illustrating a package 300 according to one embodiment of the invention.
- the package 300 includes a substrate 310 , a die assembly 280 , an underfill 320 , a second TIM 330 , and an integral heat spreader (IHS) 340 .
- the die assembly 280 includes the thin die 240 , a first TIM 250 , and the HS 220 .
- the package 300 may be a package 65 for the memory 178 or the DSP 176 shown in FIGS. 1A and 1B .
- the substrate 310 is a package substrate that provides support for the thin die 240 .
- the substrate 310 may be made of an organic or inorganic materials.
- the substrate 310 may be selected for any suitable packaging technologies including Ball Grid Array (BGA), Pin Grid Array (PGA), or Land Grid Array (LGA).
- a number of solder balls 315 may be attached to the substrate 310 .
- the solder balls 315 allow attachment of the package device 65 / 178 to a circuit board or to any other mounting component.
- the die 240 is any semiconductor die. It may have a microelectronic device such as a microprocessor, a memory, an interface chip, an integrated circuit, etc.
- the die 240 is attached to the substrate 310 by a number of solder bumps 242 .
- the bumps 242 provide contact with the contact pads on the substrate.
- the bumps 242 may be fabricated using any standard manufacturing or fabrication techniques such as the controlled collapse chip connect (C 4 ) technique.
- the underfill 320 is dispensed between die 240 and the substrate 310 to strengthen the attachment of die 240 to the substrate 310 to help prevent the thermal stresses from breaking the connections between die 240 and the substrate 310 .
- the stresses may be caused by the difference between the coefficients of thermal expansion of die 240 and the substrate 310 .
- the underfill 320 may contain filler particles suspended in an organic resin.
- the size of the filler particles are typically selected according to a gap between the die 240 and the substrate 310 , e.g., the filler particles have a diameter about one third the size of the gap.
- the composition and concentration of filler particles are selected to control the coefficient of thermal expansion of the underfill 320 .
- the IHS or second HS 340 may house or cover the die assembly 280 on the substrate 310 . It may include a flat surface and supporting walls on both or four sides of the die assembly 280 .
- the die 240 may generate heat. The heat may be transferred to the IHS 340 through the first TIM 250 and a second TIM 330 .
- the second TIM 330 may have a thickness of approximately 10 to 50 ⁇ m.
- the TIM 330 may be located, or interposed, between the bottom surface of the IHS 250 and the top surface of the HS 220 to encapsulate the cover assembly 260 .
- the TIM 330 may be made of a solder, a thermally conductive adhesive, a thermal grease, phase change material, etc.
- the package 300 thus has two heat spreaders: the first HS 240 and the second HS 340 .
- the two heat spreaders may be of the same or different materials.
- the package 300 also has two TIMs: the first TIM 250 and the second TIM 330 .
- the package 300 therefore has a good heat transfer because the first HS 240 which has a much higher thermal conductivity than silicon is brought closer to the hot spots due to the thin silicon die and thin first TIM 250 .
- FIG. 4 is a flowchart illustrating a process 400 to assemble wafer-level heat spreaders for dual HS packages according to one embodiment of the invention.
- the process 400 forms a heat spreader (HS) array on a HS support substrate (Block 410 ).
- the HS array has a plurality of heat spreaders that have dimensions matched to the individual dice on the wafer.
- the process 400 forms a diced wafer supported by a wafer support substrate (WSS) (Block 420 ).
- the diced wafer has a plurality of thin dice.
- the process 400 bonds the thin dice in the diced wafer to the heat spreaders in the HS array to form HS-bonded thin dice between the HS support substrate and the WSS (Block 430 ).
- the process 400 releases the HS support substrate from the HS array (Block 440 ). Then, the process 400 mounts the bonded diced wafer onto a dicing tape (Block 450 ). Next, the process 400 releases the WSS from the diced wafer (Block 460 ). This may be performed by decomposing adhesive between the WSS and the wafer by laser. Then, the process 400 assembles an HS-bonded thin die into a package (Block 470 ). The process 400 is then terminated.
- FIG. 5 is a flowchart illustrating the process 410 shown in FIG. 4 to form a HS array on HS support substrate according to one embodiment of the invention.
- the process 410 fabricates a carrier template having a plurality of cavities (Block 510 ). The dimensions and positions of the cavities are matched to the dimensions and positions of the thin dice on the wafer.
- the process 410 places the plurality of heat spreaders in the cavities (Block 520 ). This may be performed using self-assembly such as using the shaker shown in FIG. 2B .
- the process 410 places, or presses, the HS support substrate coated with a layer of silicone such as PDMS on the plurality of heat spreaders (Block 530 ). Under the pressing force, the heat spreaders adhere to the layer of silicone through the van der Waals force.
- the process 410 picks up the plurality of heat spreaders from the carrier template (Block 540 ). The process 410 is then terminated.
- FIG. 6 is a flowchart illustrating the process 420 shown in FIG. 4 to form diced wafer supported by a WSS according to one embodiment of the invention.
- the process 420 mounts a wafer on a wafer support substrate (WSS) (Block 610 ).
- WSS wafer support substrate
- the process 420 thins the wafer to a desired thickness (Block 620 ). Any thinning technique may be employed. For ultra-thin wafer, the desired thickness may be less than 50 ⁇ m.
- the process 420 deposits a backside metallurgy (BSM) layer on backside of the thinned wafer (Block 630 ).
- the BSM layer may be made of any suitable material, such as a solder.
- the process 420 dices, saws, or singulates the thinned wafer into the plurality of thin dice (Block 640 ). The process 420 is then terminated.
- FIG. 7 is a flowchart illustrating the process 430 shown in FIG. 4 to bond thin dice to heat spreaders according to one embodiment of the invention.
- the process 430 aligns the diced wafer to the HS array to match the thin dice with the heat spreaders (Block 710 ).
- the process 430 reflows the solder layer under pressure on at least one of the WSS and the HS support substrate (Block 720 ). The reflow causes bonding or attachment of the array of heat spreaders to the diced and thinned dice.
- the process 430 is then terminated.
- FIG. 8 is a flowchart illustrating the process 470 shown in FIG. 4 to assemble a HS-bonded thin die into a package according to one embodiment of the invention.
- the process 470 picks the HS-bonded thin die from the dicing tape (Block 810 ). Next, the process 470 places, or attaches, the HS-bonded thin die on a substrate (Block 820 ). Then, the process 470 dispenses an underfill between the HS-bonded thin die and the substrate (Block 830 ) and then cure the underfill.
- the process 470 applies a thermal interface material (TIM) on the HS (Block 840 ). Then, the process 470 attaches an integral heat spreader to the TIM and the substrate (Block 850 ). The process 470 is then terminated.
- TIM thermal interface material
- the HS support substrate and the WSS provide mechanical support for the HS array or the thin dice. After they serve their function, they may be released from the assembly. The bonding of the thin dice to the HS array is performed at the wafer level.
- the resulting package essentially includes two integrated HSs. One is directly on top of the die and the other is the normal IHS attached to the first HS.
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
An embodiment of the present invention is a technique to fabricate a package. A heat spreader (HS) array on a HS support substrate is formed. The HS array has a plurality of heat spreaders. A diced wafer supported by a wafer support substrate (WSS) is formed. The diced wafer has a plurality of thin dice. The thin dice in the diced wafer are bonded to the heat spreaders in the HS array to form HS-bonded thin dice between the HS support substrate and the WSS.
Description
- 1. Field of the Invention
- Embodiments of the invention relate to the field of semiconductor, and more specifically, to semiconductor packaging.
- 2. Description of Related Art
- Advances in packaging technologies for semiconductor devices have provided many opportunities for development of efficient thermal management. One thermal management scheme is the use of heat spreaders on semiconductor dice.
- Existing techniques for attaching heat spreaders on ultra-thin dice have a number of disadvantages. One technique uses high accuracy pick-and-place equipment. This technique is time-consuming, leading to delay and high cost in the manufacturing cycle. In addition, when adhesive is used to form the heat spreader array, releasing the heat spreaders to ultra-thin die bonding is quite challenging.
- Embodiments of invention may best be understood by referring to the following description and accompanying drawings that are used to illustrate embodiments of the invention. In the drawings:
-
FIG. 1A is a diagram illustrating a manufacturing system in which one embodiment of the invention can be practiced. -
FIG. 1B is a diagram illustrating a system according to one embodiment of the invention. -
FIG. 2A is a diagram illustrating a carrier template according to one embodiment of the invention. -
FIG. 2B is a diagram illustrating placing heat spreaders into cavities of the carrier template according to one embodiment of the invention. -
FIG. 2C is a diagram illustrating forming a heat spreader (HS) array on a HS support substrate according to one embodiment of the invention. -
FIG. 2D is a diagram illustrating a diced wafer supported by a wafer support substrate (WSS) according to one embodiment of the invention. -
FIG. 2E is a diagram illustrating bonding the thin dice in the diced wafer to the heat spreaders in the HS array according to one embodiment of the invention. -
FIG. 2F is a diagram illustrating an HS-bonded diced wafer supported by a WSS according to one embodiment of the invention. -
FIG. 2G is a diagram illustrating applying a dicing tape to the HS-bonded diced wafer supported by a WSS according to one embodiment of the invention. -
FIG. 2H is a diagram illustrating releasing the WSS from the HS-bonded diced wafer according to one embodiment of the invention. -
FIG. 2I is a diagram illustrating picking an individual die assembly according to one embodiment of the invention. -
FIG. 3 is a diagram illustrating a package according to one embodiment of the invention. -
FIG. 4 is a flowchart illustrating a process to assemble wafer-level heat spreaders for dual HS packages according to one embodiment of the invention. -
FIG. 5 is a flowchart illustrating a process to form a HS array on HS support substrate according to one embodiment of the invention. -
FIG. 6 is a flowchart illustrating a process to form diced wafer supported by a WSS according to one embodiment of the invention. -
FIG. 7 is a flowchart illustrating a process to bond thin dice to heat spreaders according to one embodiment of the invention. -
FIG. 8 is a flowchart illustrating a process to assemble a HS-bonded thin die into a package according to one embodiment of the invention. - An embodiment of the present invention is a technique to fabricate a package. A heat spreader (HS) array on a HS support substrate is formed. The HS array has a plurality of heat spreaders. A diced wafer supported by a wafer support substrate (WSS) is formed. The diced wafer has a plurality of thin dice. The thin dice in the diced wafer are bonded to the heat spreaders in the HS array to form HS-bonded thin dice between the HS support substrate and the WSS.
- In the following description, numerous specific details are set forth. However, it is understood that embodiments of the invention may be practiced without these specific details. In other instances, well-known circuits, structures, and techniques have not been shown to avoid obscuring the understanding of this description.
- One embodiment of the invention may be described as a process which is usually depicted as a flowchart, a flow diagram, a structure diagram, or a block diagram. Although a flowchart may describe the operations as a sequential process, many of the operations can be performed in parallel or concurrently. In addition, the order of the operations may be re-arranged. A process is terminated when its operations are completed. A process may correspond to a method, a program, a procedure, a method of manufacturing or fabrication, etc.
- An embodiment of the present invention is a technique to fabricate a package having two heat spreaders. The technique includes wafer-level bonding an array of heat spreaders to a diced thinned wafer. A carrier template having an array of cavities is fabricated with high precision. The dimensions and positions of the cavities are carefully matched with the dimensions and positions of the dice on the silicon wafer to which the heat spreaders are bonded. The heat spreaders (HS) which have a thin layer of a solder layer on one side are placed in the cavities of the carrier template (i.e., the side with the solder of the HS faces the carrier template). The thin solder layer acts as a first thermal interface material (TIM) when the dice are assembled into packages. A heat spreader support substrate covered by a thin layer of silicone such as polydimethyl siloxane (PDMS) is then placed on the heat spreaders under a pressure. Due to the van der Waals forces between the PDMS and the heat spreaders, all the heat spreaders in the carrier template adhere to the thin PDMS layer. The HS array is transferred to the PDMS-coated support substrate. A diced wafer is formed by mounting a wafer onto a wafer support substrate (WSS), thinning the wafer, depositing a backside metallurgy (BSM) layer and/or a thin solder layer on backside of the wafer, and dicing the thinned wafer into thin dice without releasing dies from the WSS. Then, the HS array is aligned and bonded to the thin dice on the diced wafer by reflowing the solder layer on the HS array and/or Si dice under pressure. The HS support substrate is then released from the HS array-bonded wafer. The HS array-bonded wafer is then mounted on a dicing tape and the WSS is released. The individual HS-bonded dice are then assembled into packages. Each package has a second TIM and a second heat spreader with a larger size for further heat spreading.
- The technique provides efficient placement of HS array because the carrier template may be manufactured in advance with high precision. Therefore, time-consuming high accuracy pick-and-place operation for HS array is eliminated. In addition, the technique eliminates the use of any adhesive for attaching the heat spreaders on the support substrate and associated support substrate releasing processing operations. Furthermore, the compliant PDMS layer on the HS support substrate may better compensate the non-co-planarity and HS thickness variations, leading to better bond-line control between the heat spreaders and the silicon dice.
-
FIG. 1A is a diagram illustrating amanufacturing system 5 in which one embodiment of the invention can be practiced. Thesystem 5 includes awafer fabrication phase 10,wafer preparation phase 15, awafer dicing phase 20, a carriertemplate fabrication phase 25, a heat spreader (HS) supportsubstrate fabrication phase 30, a HSarray formation phase 35, a wafer-level bonding phase 40, a supportsubstrate releasing phase 45, adie attachment phase 50, an encapsulation and HISattachment phase 55, and astress testing phase 60. Thesystem 5 represents a manufacturing flow of a semiconductor packaging process. - The
wafer fabrication phase 10 fabricates the wafer containing a number of dice. The individual dice may be any microelectronic devices such as microprocessors, memory devices, interface circuits, high power optical devices etc. Thewafer fabrication phase 10 includes typical processes for semiconductor fabrication such as preparation of the wafer surface, growth of silicon dioxide (SiO2), patterning and subsequent implantation or diffusion of dopants to obtain the desired electrical properties, growth or deposition of a gate dielectric, and growth or deposition of insulating materials, depositing layers of metal and insulating material and etching it into the desired patterns. Typically the metal layers consist of aluminium or copper. The various metal layers are interconnected by etching holes, called “vias,” in the insulating material. - The
wafer preparation phase 15 prepares a wafer containing dice for packaging and testing. During this phase, the wafers are sorted after the patterning process. An inspection may be carried out to check for wafer defects. Then, the wafer may be mounted on a wafer support substrate (WSS) that adheres to the front side (or bump side) of the wafer. The WSS provides mechanical support for handling during subsequent phases. The wafer is then thinned to a desired thickness to provide ultra-thin wafer. Additional processing may be performed to prepare the wafer for subsequent phases, such as deposition of backside metallization (BSM) or solder layer on the wafer. - The
wafer dicing phase 20 dices, cuts, or saws the wafer into individual dice from the backside of the wafer. The dicing depth may be well controlled such that only the thin wafer is diced and the WSS may not be diced. High precision saw blade/laser and image recognition unit may be used. De-ionized water may be dispensed on the wafer to wash away any residual particles or contaminants during the dicing. Then, the wafer is dried by being spun at high spinning speed. - The carrier
template fabrication phase 25 fabricates one or more carrier templates to carry the heat spreaders to be bonded with the dice on the wafer. The fabrication may be performed on facilities outside the semiconductor fabrication facilities such as by other vendors. The carriertemplate fabrication phase 25 receives information or data files regarding the dimensions and positions of the dice on the wafer. This information is used to fabricate the carrier templates with high precision. - The HS support
substrate fabrication phase 30 fabricates the HS support substrate to support the array of heat spreaders. The HS support substrate may be used to hold the heat spreaders for precision bonding with the dice. - The HS
array formation phase 35 forms the HS array supported by the HS support substrate. The heat spreaders may be fabricated by HS manufacturers and used in this phase. The HS array contains the heat spreaders that are positioned to correspond to the positions of the dice on the wafer. - The wafer-
level bonding phase 40 bonds the HS array to the dice on the wafer. The bonding essentially attaches the heat spreaders to the corresponding dice at the wafer level. - The support
substrate releasing phase 45 releases the HS support substrate and the wafer support substrate from the assembly. The resulting assembly includes array of dice attached to first heat spreaders. - The
die attachment phase 50 attaches the die to a package substrate. The substrate material depends on the packaging type. It may be ceramic, organic, or inorganic such as silicon. The die may be attached to a package substrate through flip chip technology. - The encapsulation and
IHS attachment phase 55 underfills the gap between the die and the substrate and attaches an IHS. Underfill material may be dispensed between the die and the substrate. Integrated heat spreader (IHS) may be attached to the die and substrate assembly. The fully assembledpackage 65 is ready to be tested. - The
stress testing phase 60 performs one or more tests such as Highly Accelerated Stress Test (HAST) or biased-HAST on the device package under stress conditions. A test chamber may be designed to conduct a stress test. It may have monitoring circuits, measurement circuits, and other data processing equipment. Thepackage 65 is placed in the test chamber subject to the stress test. It may be powered or non-powered. Various stress tests may be performed on the wafer or on the packageddevices 65 at various points of the manufacturing process flow. The tests may follow standards such as Joint Electron Device Engineering Council (JEDEC) standards or military standards. Examples of these tests may include electrostatic discharge (ESD), or human body model (HBM), high temperature operational life (HTOL), thermal shock, temperature cycle, high temperature storage, vibration and mechanical loading, shear testing, and accelerated moisture resistance. -
FIG. 1B is a diagram illustrating asystem 100 according to one embodiment of the invention. Thesystem 100 represents a mobile communication module. It includes a system on package (SOP) 110, an intermediate frequency processing unit 160, and a base-band processing unit 170. - The
SOP 110 represents the front end processing unit for the mobile communication module. It is a transceiver incorporating on-package integrated lumped passive components as well as radio frequency (RF) components. It includes anantenna 115, aduplexer 120, afilter 125, a system-on-chip (SOC) 150, a power amplifier (PA) 180, and afilter 185. - The
antenna 115 receives and transmits RF signals. The RF signals may be converted to digital data for processing in subsequent stages. It is designed in compact micro-strip and strip-line for L and C-band wireless applications. Theduplexer 120 acts as a switch to couple to theantenna 115 to the receiver and the transmitter to theantenna 115. Thefilters SOC 150 includes a low noise amplifier (LNA) 130, adown converter 135, a local voltage controlled oscillator (VCO) 140, an upconverter 171, and adriver amplifier 175. TheLNA 130 amplifies the received signal. The downconverter 135 is a mixer to convert the RF signal to the IF band to be processed by the IF processing unit 160. The upconverter 171 is a mixer to convert the IF signal to the proper RF signal for transmission. TheVCO 140 generates modulation signal at appropriate frequencies for down conversion and up conversion. Thedriver amplifier 175 drives thePA 180. ThePA 180 amplifies the transmit signal for transmission. - The IF processing unit 160 includes analog components to process IF signals for receiving and transmission. It may include a band-pass filter and a low pass filter at suitable frequency bands. The filter may provide base-band signal to the base-band processing unit 170. The base-band processing unit 170 may include an analog-to-digital converter (ADC) 172, a digital-to-analog converter (DAC) 174, a digital signal processor (DSP) 176, and
memory device 178. TheADC 172 and theDAC 174 are used to convert analog signals to digital data and digital data to analog signal, respectively. TheDSP 176 is a programmable processor that may execute a program to process the digital data. Thememory device 178 may be flash memories or random access memories. It may be packaged using Flip-Chip Ball Grid Array (FCBGA) packaging technology, a molded packaging, or any other suitable packaging technologies. Thememory device 178 may be manufactured according to themanufacturing flow 5 shown inFIG. 1A . It may be thedevice package 65. It may include an ultra-thin die in the package. The base-band processing unit 170 may also include memory and peripheral components. TheDSP 176 may, therefore, be coupled to the front end processing unit via the IF processing unit 160 and/or the base-band processing unit 170 to process the digital data. - The
SOP 110 may be a multi-layer three-dimensional (3D) architecture for a monolithic microwave integrated circuit (MMIC) with embedded passives (EP) technology. It may be implemented using Low Temperature Co-fired Ceramics (LTCC) and organic-based technologies. The 3D architecture may include multiple layers include alayer 117 to implement theantenna 115,layers filters layer 188 for theSOC 150 and the passive components using EP technology. Typically, the packaging technology involves embedded passives with multiple layers. -
FIG. 2A is a diagram illustrating acarrier template 210 according to one embodiment of the invention. Thecarrier template 210 may be manufactured in advance and separately from the packaging process. Thecarrier template 210 may be made from materials such as silicon. It has a number ofcavities 215 with tight dimensional tolerances. Thecavities 215 may be formed or fabricated using wet etching or any other etching processes. - The dimensions and positions of the
cavities 215 are carefully matched with the dimensions and positions of the heat spreaders that are bonded to the corresponding dice on a wafer. The dimensions and positions of the dice on the wafer are typically known in advance and may be available in computer readable forms which may be used to precisely control the formation of thecavities 215. The fabrication of thecarrier template 210 and thecavities 215 may be performed independently and separately from the packaging process. -
FIG. 2B is a diagram illustrating placing heat spreaders into cavities of the carrier template according to one embodiment of the invention. - The
carrier template 210 is placed in ashaker 212. Theshaker 212 may be a mechanical shaker that shakes or vibrates at a predetermined rate. It typically has enclosure to keep items or articles being shaken from being thrown out during shaking. A number of heat spreaders are placed inside theshaker 212 on thecarrier template 210. The heat spreaders (HS) are designed to have dimensions fit within thecavities 215, which in turn fit the dimensions of the dice on the wafer. They may be made by any material having a high thermal conductivity such as copper or SiC. Through gravity and shaking forces, the heat spreaders self assemble and fall into thecavities 215 to becomeHS 220. Heat spreaders that do not fall into thecavities 215 areexcess HS 225 and may be removed from theshaker 212. There are many other methods of achieving the same impact as ‘shaking’ using other agitating methods such as acoustic agitation or electrostatic agitation that results in the HSs self assembling in the required cavities. - Alternatively, the heat spreaders may be placed into the
cavities 215 by a pick-and-place equipment. Since thecarrier template 210 is made of rigid material and is not a fragile object, the pick-and-place equipment may place the heat spreaders in thecavities 215 without high precision or accuracy. Through gravity, the heat spreaders may settle into thecavities 215 when they are slightly misplaced. -
FIG. 2C is a diagram illustrating forming a heat spreader (HS) array on a HS support substrate according to one embodiment of the invention. Theheat spreaders 220 in thecavities 215 are now transferred to aHS support substrate 230. TheHS support substrate 230 may be any suitable material, such as glass. It is coated or covered by a thin layer ofsilicone 232. Thesilicone 232 may be any polymer that has good adhesive property. One such polymer is the poly-dimethyl siloxane (PDMS), a rubber material. - The
HS support substrate 230 with thePDMS layer 232 is placed, or pressed, on theHS 220 in thecavities 215 of thecarrier template 210. ThePDMS layer 232 picks up all theHS 220 due to the van der Waals force. TheHS 220 stay at the same positions on theHS support substrate 230 as they are in thecavities 215. Therefore, theHS 220 form an array of heat spreaders that are located at positions to correspond or match with positions of dice on a wafer. Thecarrier template 210 may be discarded or re-used to hold a next array of heat spreaders. TheHS support substrate 230, the layer ofsilicone 232 and theHS array 220 form the HS array 235 with HS support substrate. -
FIG. 2D is a diagram illustrating adiced wafer 255 supported by a wafer support substrate (WSS) according to one embodiment of the invention. The WSS-supporteddiced wafer 255 includes aWSS 245 and a number of singulated thinneddice 260 1, to 260 N. - First, the
WSS 245 is mounted onto a wafer. The mounting may be performed using an adhesive to attach theWSS 245 to the wafer. The wafer is then thinned to a desired thickness. For ultra-thin wafer, the thickness may be less than 75 μm, or may be approximately 50 μm. Then, a backside metallurgy (BSM)layer 250 is deposited on the backside of the wafer. ThisBSM layer 250 may have a thickness of about 3 to 10 μm. It serves to provide the basis for attachment during bonding. It may consist of a stack of metal layers such as titanium (Ti), nickel (Ni) and gold (Au). Besides these metal layers, it may also include a solder layer such as tin-copper. The solder layer serve as the thermal interface material (TIM) and it may have a process temperature range from 180° C. to 280° C. The solder material is carefully designed such that, after bonding, the TIM layer has a high remelting temperature (e.g., higher than 250° C.) and thus it does not melt again during die to substrate assembly processes. Then, the thinned wafer and theBSM layer 250 are diced, sawed, or singulated into individual dice. -
FIG. 2E is a diagram illustrating bonding the thin dice in the dicedwafer 255 to the heat spreaders in the HS array 235 according to one embodiment of the invention. - The HS array 235 is then positioned so that the
HS 220 face toward to backside of the thinned wafer, or the thin dice 260 j's (j=1, . . . , N). The thin dice 260 j's in the dicedwafer 255 are then aligned to theHS 220 in the HS array with HS support substrate 235. Since theHS 220 are positioned according to the positions of the cavities, they are matched with the thin dice 260 j's. - The thin dice 260 j's in the diced
wafer 255 are then bonded or attached to theHS 220 in the HS array with HS support substrate 235. The bonding may be performed by reflowing the solder layer on the HS array and/or the solder of theBSM layer 250 on the wafer under pressure from at least one of theWSS 245 or theHS support substrate 230. The pressure may be applied to both theWSS 245 and theHS support substrate 230, or one of them. The reflow causes theHS 220 to be bonded or attached to the corresponding thin dice 260 j's. -
FIG. 2F is a diagram illustrating an HS-bonded diced wafer supported by a WSS according to one embodiment of the invention. - The adhesion strength between the
HS 220 to the thin dice 260 j 's is typically greater than the van der Waals force that keeps theHS 220 to the layer ofsilicone 232 on theHS support substrate 230. Therefore, theHS support substrate 230 and the coated layer ofsilicone 232 may be easily removed from the bonded assembly. The removal may be performed by vacuum sucking. There are other ways to release theHS 220 from thesupport substrate 230. Chemical solvent/laser/heat may also be utilized to facilitate the debonding. -
FIG. 2G is a diagram illustrating applying a dicing tape to the HS-bonded diced wafer supported by a WSS according to one embodiment of the invention. - A dicing tape 270 is then attached or mounted onto the
HS 220 of the thin dice assembly. The dicing tape 270 essentially holds the individual die assemblies together. -
FIG. 2H is a diagram illustrating releasing the WSS from the HS-bonded diced wafer according to one embodiment of the invention. - The
WSS 245 is then released from the thin die assembly with the dicing tape 270. The release of theWSS 245 may be carried out by a number of methods including mechanical and thermal removal, laser or ultraviolet (UV) light. The laser may be used to irradiate theWSS 245. The irradiation may weaken the adhesion of adhesive that is used to attach theWSS 245 to thewafer 240. -
FIG. 2I is a diagram illustrating picking an individual die assembly according to one embodiment of the invention. - After the
WSS 245 is removed, a pick-and-place equipment or tool may be used to pick up the individual die assemblies and assemble them into packages. Adie assembly 280 now has a die, a first TIM, and a matching heat spreader. -
FIG. 3 is a diagram illustrating apackage 300 according to one embodiment of the invention. Thepackage 300 includes asubstrate 310, adie assembly 280, anunderfill 320, asecond TIM 330, and an integral heat spreader (IHS) 340. Thedie assembly 280 includes thethin die 240, afirst TIM 250, and theHS 220. Thepackage 300 may be apackage 65 for thememory 178 or theDSP 176 shown inFIGS. 1A and 1B . - The
substrate 310 is a package substrate that provides support for thethin die 240. Thesubstrate 310 may be made of an organic or inorganic materials. Thesubstrate 310 may be selected for any suitable packaging technologies including Ball Grid Array (BGA), Pin Grid Array (PGA), or Land Grid Array (LGA). A number ofsolder balls 315 may be attached to thesubstrate 310. Thesolder balls 315 allow attachment of thepackage device 65/178 to a circuit board or to any other mounting component. Thedie 240 is any semiconductor die. It may have a microelectronic device such as a microprocessor, a memory, an interface chip, an integrated circuit, etc. Thedie 240 is attached to thesubstrate 310 by a number of solder bumps 242. Thebumps 242 provide contact with the contact pads on the substrate. Thebumps 242 may be fabricated using any standard manufacturing or fabrication techniques such as the controlled collapse chip connect (C4) technique. - The
underfill 320 is dispensed betweendie 240 and thesubstrate 310 to strengthen the attachment ofdie 240 to thesubstrate 310 to help prevent the thermal stresses from breaking the connections betweendie 240 and thesubstrate 310. The stresses may be caused by the difference between the coefficients of thermal expansion ofdie 240 and thesubstrate 310. Theunderfill 320 may contain filler particles suspended in an organic resin. The size of the filler particles are typically selected according to a gap between the die 240 and thesubstrate 310, e.g., the filler particles have a diameter about one third the size of the gap. Generally, the composition and concentration of filler particles are selected to control the coefficient of thermal expansion of theunderfill 320. - The IHS or
second HS 340 may house or cover thedie assembly 280 on thesubstrate 310. It may include a flat surface and supporting walls on both or four sides of thedie assembly 280. During operation, thedie 240 may generate heat. The heat may be transferred to theIHS 340 through thefirst TIM 250 and asecond TIM 330. Thesecond TIM 330 may have a thickness of approximately 10 to 50 μm. TheTIM 330 may be located, or interposed, between the bottom surface of theIHS 250 and the top surface of theHS 220 to encapsulate thecover assembly 260. It may be attached to a heat generating device, such as thedie 240, to transfer the heat to a heat spreader or a heat sink or any another heat dissipating device. TheTIM 330 may be made of a solder, a thermally conductive adhesive, a thermal grease, phase change material, etc. - The
package 300 thus has two heat spreaders: thefirst HS 240 and thesecond HS 340. The two heat spreaders may be of the same or different materials. Thepackage 300 also has two TIMs: thefirst TIM 250 and thesecond TIM 330. Thepackage 300 therefore has a good heat transfer because thefirst HS 240 which has a much higher thermal conductivity than silicon is brought closer to the hot spots due to the thin silicon die and thinfirst TIM 250. -
FIG. 4 is a flowchart illustrating aprocess 400 to assemble wafer-level heat spreaders for dual HS packages according to one embodiment of the invention. - Upon START, the
process 400 forms a heat spreader (HS) array on a HS support substrate (Block 410). The HS array has a plurality of heat spreaders that have dimensions matched to the individual dice on the wafer. Next, theprocess 400 forms a diced wafer supported by a wafer support substrate (WSS) (Block 420). The diced wafer has a plurality of thin dice. Then, theprocess 400 bonds the thin dice in the diced wafer to the heat spreaders in the HS array to form HS-bonded thin dice between the HS support substrate and the WSS (Block 430). - Next, the
process 400 releases the HS support substrate from the HS array (Block 440). Then, theprocess 400 mounts the bonded diced wafer onto a dicing tape (Block 450). Next, theprocess 400 releases the WSS from the diced wafer (Block 460). This may be performed by decomposing adhesive between the WSS and the wafer by laser. Then, theprocess 400 assembles an HS-bonded thin die into a package (Block 470). Theprocess 400 is then terminated. -
FIG. 5 is a flowchart illustrating theprocess 410 shown inFIG. 4 to form a HS array on HS support substrate according to one embodiment of the invention. - Upon START, the
process 410 fabricates a carrier template having a plurality of cavities (Block 510). The dimensions and positions of the cavities are matched to the dimensions and positions of the thin dice on the wafer. Next, theprocess 410 places the plurality of heat spreaders in the cavities (Block 520). This may be performed using self-assembly such as using the shaker shown inFIG. 2B . Then, theprocess 410 places, or presses, the HS support substrate coated with a layer of silicone such as PDMS on the plurality of heat spreaders (Block 530). Under the pressing force, the heat spreaders adhere to the layer of silicone through the van der Waals force. Next, theprocess 410 picks up the plurality of heat spreaders from the carrier template (Block 540). Theprocess 410 is then terminated. -
FIG. 6 is a flowchart illustrating theprocess 420 shown inFIG. 4 to form diced wafer supported by a WSS according to one embodiment of the invention. - Upon START, the
process 420 mounts a wafer on a wafer support substrate (WSS) (Block 610). Next, theprocess 420 thins the wafer to a desired thickness (Block 620). Any thinning technique may be employed. For ultra-thin wafer, the desired thickness may be less than 50 μm. Then, theprocess 420 deposits a backside metallurgy (BSM) layer on backside of the thinned wafer (Block 630). The BSM layer may be made of any suitable material, such as a solder. Next, theprocess 420 dices, saws, or singulates the thinned wafer into the plurality of thin dice (Block 640). Theprocess 420 is then terminated. -
FIG. 7 is a flowchart illustrating theprocess 430 shown inFIG. 4 to bond thin dice to heat spreaders according to one embodiment of the invention. - Upon START, the
process 430 aligns the diced wafer to the HS array to match the thin dice with the heat spreaders (Block 710). Next, theprocess 430 reflows the solder layer under pressure on at least one of the WSS and the HS support substrate (Block 720). The reflow causes bonding or attachment of the array of heat spreaders to the diced and thinned dice. Theprocess 430 is then terminated. -
FIG. 8 is a flowchart illustrating theprocess 470 shown inFIG. 4 to assemble a HS-bonded thin die into a package according to one embodiment of the invention. - Upon START, the
process 470 picks the HS-bonded thin die from the dicing tape (Block 810). Next, theprocess 470 places, or attaches, the HS-bonded thin die on a substrate (Block 820). Then, theprocess 470 dispenses an underfill between the HS-bonded thin die and the substrate (Block 830) and then cure the underfill. - Next, the
process 470 applies a thermal interface material (TIM) on the HS (Block 840). Then, theprocess 470 attaches an integral heat spreader to the TIM and the substrate (Block 850). Theprocess 470 is then terminated. - An embodiment of the invention is described to provide superior thermal and mechanical performance. Throughout the process, the HS support substrate and the WSS provide mechanical support for the HS array or the thin dice. After they serve their function, they may be released from the assembly. The bonding of the thin dice to the HS array is performed at the wafer level. The resulting package essentially includes two integrated HSs. One is directly on top of the die and the other is the normal IHS attached to the first HS.
- While the invention has been described in terms of several embodiments, those of ordinary skill in the art will recognize that the invention is not limited to the embodiments described, but can be practiced with modification and alteration within the spirit and scope of the appended claims. The description is thus to be regarded as illustrative instead of limiting.
Claims (15)
1-8. (canceled)
9. A package comprising:
a substrate;
a die assembly attached to the substrate, the die assembly comprising:
a thin die having a thickness,
a first thermal interface material (TIM) deposited on the thin die, and
a first heat spreader (HS) attached to the thin die through the first TIM;
a second TIM attached to the first HS; and
a second heat spreader attached to the substrate and the second TIM, the second heat spreader enclosing the die assembly.
10. The package of claim 9 further comprising:
an underfill dispensed between the die assembly and the substrate.
11. The package of claim 9 wherein the thickness is less than 50 μm.
12. The package of claim 9 wherein the first TIM has a remelting point higher than 250° C.
13. The package of claim 9 wherein the first TIM has thickness less than the second TIM.
14. The package of claim 9 wherein the first TIM has thickness of approximately 5 μm.
15. The package of claim 9 wherein the first heat spreader is approximately equal to the thin die in size.
16. A system comprising:
a front end processing unit to receive and transmit a radio frequency (RF) signal, the RF signal being converted to digital data;
a digital processor coupled to the front end processing unit to process the digital data; and
a memory device coupled to the digital processor, the memory device being packaged in a package, the package comprising:
a substrate,
a die assembly attached to the substrate, the die assembly comprising:
a thin die having a thickness,
a first thermal interface material (TIM) deposited on the thin die, and
a first heat spreader (HS) attached to the first TIM,
a second TIM attached to the first HS, and
a second heat spreader attached to the substrate and the second TIM, the second heat spreader enclosing the die assembly.
17. The system of claim 16 further comprising:
an underfill dispensed between the die assembly and the substrate.
18. The system of claim 16 wherein the thickness is less than 50 μm.
19. The system of claim 16 wherein the first TIM has a remelting point higher than 250° C.
20. The system of claim 16 wherein the first TIM has thickness less than the second TIM.
21. The system of claim 16 wherein the first TIM has thickness of approximately 5 μm.
22. The system of claim 16 wherein the first heat spreader is approximately equal to the thin die in size.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/247,193 US20090034206A1 (en) | 2006-06-30 | 2008-10-07 | Wafer-level assembly of heat spreaders for dual ihs packages |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/479,740 US7476568B2 (en) | 2006-06-30 | 2006-06-30 | Wafer-level assembly of heat spreaders for dual IHS packages |
US12/247,193 US20090034206A1 (en) | 2006-06-30 | 2008-10-07 | Wafer-level assembly of heat spreaders for dual ihs packages |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/479,740 Division US7476568B2 (en) | 2006-06-30 | 2006-06-30 | Wafer-level assembly of heat spreaders for dual IHS packages |
Publications (1)
Publication Number | Publication Date |
---|---|
US20090034206A1 true US20090034206A1 (en) | 2009-02-05 |
Family
ID=38877178
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/479,740 Expired - Fee Related US7476568B2 (en) | 2006-06-30 | 2006-06-30 | Wafer-level assembly of heat spreaders for dual IHS packages |
US12/247,193 Abandoned US20090034206A1 (en) | 2006-06-30 | 2008-10-07 | Wafer-level assembly of heat spreaders for dual ihs packages |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/479,740 Expired - Fee Related US7476568B2 (en) | 2006-06-30 | 2006-06-30 | Wafer-level assembly of heat spreaders for dual IHS packages |
Country Status (1)
Country | Link |
---|---|
US (2) | US7476568B2 (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080001268A1 (en) * | 2006-06-30 | 2008-01-03 | Daoqiang Lu | Heat spreader as mechanical reinforcement for ultra-thin die |
US20100102425A1 (en) * | 2008-10-24 | 2010-04-29 | Electronics And Telecommunications Research Institute | Ultra wideband system-on-package and method of manufacturing the same |
WO2012087330A2 (en) * | 2010-12-23 | 2012-06-28 | Intel Corporation | Test, validation, and debug architecture |
US9806002B2 (en) * | 2015-12-23 | 2017-10-31 | Intel Corporation | Multi-reference integrated heat spreader (IHS) solution |
Families Citing this family (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7435664B2 (en) * | 2006-06-30 | 2008-10-14 | Intel Corporation | Wafer-level bonding for mechanically reinforced ultra-thin die |
US7816785B2 (en) * | 2009-01-22 | 2010-10-19 | International Business Machines Corporation | Low compressive force, non-silicone, high thermal conducting formulation for thermal interface material and package |
US8278749B2 (en) * | 2009-01-30 | 2012-10-02 | Infineon Technologies Ag | Integrated antennas in wafer level package |
WO2011132647A1 (en) * | 2010-04-19 | 2011-10-27 | 日東電工株式会社 | Film for back surface of flip-chip semiconductor |
JP5993845B2 (en) | 2010-06-08 | 2016-09-14 | ヘンケル アイピー アンド ホールディング ゲゼルシャフト ミット ベシュレンクテル ハフツング | Adhesive coating on microfabricated wafers with pre-dicing method |
EP2671249A4 (en) | 2011-02-01 | 2015-10-07 | Henkel IP & Holding GmbH | Pre- cut wafer applied underfill film |
JP2014511560A (en) * | 2011-02-01 | 2014-05-15 | ヘンケル コーポレイション | Underfill film on dicing tape precut and applied to wafer |
US8993378B2 (en) * | 2011-09-06 | 2015-03-31 | Taiwan Semiconductor Manufacturing Co., Ltd. | Flip-chip BGA assembly process |
US9136202B2 (en) | 2012-04-17 | 2015-09-15 | Qualcomm Incorporated | Enhanced package thermal management using external and internal capacitive thermal material |
US10446728B2 (en) * | 2014-10-31 | 2019-10-15 | eLux, Inc. | Pick-and remove system and method for emissive display repair |
WO2019039432A1 (en) * | 2017-08-25 | 2019-02-28 | 東京エレクトロン株式会社 | Substrate processing method, computer storage medium and substrate processing system |
US11652061B2 (en) * | 2019-06-17 | 2023-05-16 | Intel Corporation | Package-level backside metallization (BSM) |
CN116569327A (en) * | 2020-12-09 | 2023-08-08 | 华为技术有限公司 | Packaging structure, manufacturing method thereof and electronic equipment |
EP4402717A1 (en) * | 2021-09-14 | 2024-07-24 | Adeia Semiconductor Bonding Technologies Inc. | Method of bonding thin substrates |
Citations (32)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4323914A (en) * | 1979-02-01 | 1982-04-06 | International Business Machines Corporation | Heat transfer structure for integrated circuit package |
US4801998A (en) * | 1984-08-20 | 1989-01-31 | Oki Electric Industry Co., Ltd. | EPROM device |
US5081067A (en) * | 1989-02-10 | 1992-01-14 | Fujitsu Limited | Ceramic package type semiconductor device and method of assembling the same |
US5291064A (en) * | 1991-04-16 | 1994-03-01 | Nec Corporation | Package structure for semiconductor device having a flexible wiring circuit member spaced from the package casing |
US5371404A (en) * | 1993-02-04 | 1994-12-06 | Motorola, Inc. | Thermally conductive integrated circuit package with radio frequency shielding |
US5396403A (en) * | 1993-07-06 | 1995-03-07 | Hewlett-Packard Company | Heat sink assembly with thermally-conductive plate for a plurality of integrated circuits on a substrate |
US5450283A (en) * | 1992-11-03 | 1995-09-12 | Motorola, Inc. | Thermally enhanced semiconductor device having exposed backside and method for making the same |
US5587882A (en) * | 1995-08-30 | 1996-12-24 | Hewlett-Packard Company | Thermal interface for a heat sink and a plurality of integrated circuits mounted on a substrate |
US5672548A (en) * | 1994-07-11 | 1997-09-30 | International Business Machines Corporation | Method for attaching heat sinks directly to chip carrier modules using flexible-epoxy |
US5907474A (en) * | 1997-04-25 | 1999-05-25 | Advanced Micro Devices, Inc. | Low-profile heat transfer apparatus for a surface-mounted semiconductor device employing a ball grid array (BGA) device package |
US5926371A (en) * | 1997-04-25 | 1999-07-20 | Advanced Micro Devices, Inc. | Heat transfer apparatus which accommodates elevational disparity across an upper surface of a surface-mounted semiconductor device |
US6118177A (en) * | 1998-11-17 | 2000-09-12 | Lucent Technologies, Inc. | Heatspreader for a flip chip device, and method for connecting the heatspreader |
US6117797A (en) * | 1998-09-03 | 2000-09-12 | Micron Technology, Inc. | Attachment method for heat sinks and devices involving removal of misplaced encapsulant |
US6219238B1 (en) * | 1999-05-10 | 2001-04-17 | International Business Machines Corporation | Structure for removably attaching a heat sink to surface mount packages |
US6294408B1 (en) * | 1999-01-06 | 2001-09-25 | International Business Machines Corporation | Method for controlling thermal interface gap distance |
US6504243B1 (en) * | 2000-04-07 | 2003-01-07 | Advanced Micro Devices, Inc. | Removable heat transfer apparatus for a pin grid array (PGA) device, and associated installation and removal methods |
US6519154B1 (en) * | 2001-08-17 | 2003-02-11 | Intel Corporation | Thermal bus design to cool a microelectronic die |
US20030117775A1 (en) * | 2001-12-20 | 2003-06-26 | Vrtis Joan K. | Coated heat spreaders |
US20030131476A1 (en) * | 2001-09-28 | 2003-07-17 | Vlad Ocher | Heat conduits and terminal radiator for microcircuit packaging and manufacturing process |
US6617683B2 (en) * | 2001-09-28 | 2003-09-09 | Intel Corporation | Thermal performance in flip chip/integral heat spreader packages using low modulus thermal interface material |
US20040037059A1 (en) * | 2002-08-21 | 2004-02-26 | Leon Stiborek | Integrated circuit package with spacer |
US20040084764A1 (en) * | 2002-09-16 | 2004-05-06 | Junichi Ishimine | Package structure, printed circuit board mounted with the same, electronic apparatus having the printed circuit board |
US6995463B1 (en) * | 2001-09-27 | 2006-02-07 | Marvell International Ltd. | Integrated chip package having intermediate substrate and multiple semiconductor chips |
US7141454B2 (en) * | 2003-06-30 | 2006-11-28 | Intel Corporation | Wire-bonded package with electrically insulating wire encapsulant and thermally conductive overmold |
US20070069835A1 (en) * | 2005-09-29 | 2007-03-29 | Telesphor Kamgaing | Compact integration of LC resonators |
US7218000B2 (en) * | 2003-06-27 | 2007-05-15 | Intel Corporation | Liquid solder thermal interface material contained within a cold-formed barrier and methods of making same |
US20070148949A1 (en) * | 2005-12-22 | 2007-06-28 | Intel Corporation | Nanostructure-based package interconnect |
US7253523B2 (en) * | 2003-07-29 | 2007-08-07 | Intel Corporation | Reworkable thermal interface material |
US20070232050A1 (en) * | 2006-03-31 | 2007-10-04 | Munehiro Toyama | Embedding device in substrate cavity |
US20070231953A1 (en) * | 2006-03-31 | 2007-10-04 | Yoshihiro Tomita | Flexible interconnect pattern on semiconductor package |
US20070231970A1 (en) * | 2006-03-31 | 2007-10-04 | Tsuyoshi Fukuo | Cured mold compound spacer for stacked-die package |
US20070231969A1 (en) * | 2006-03-30 | 2007-10-04 | Chrysler Gregory M | Covered devices in a semicoductor package |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6314639B1 (en) * | 1998-02-23 | 2001-11-13 | Micron Technology, Inc. | Chip scale package with heat spreader and method of manufacture |
AU2003900180A0 (en) * | 2003-01-16 | 2003-01-30 | Silverbrook Research Pty Ltd | Method and apparatus (dam001) |
US7166540B2 (en) * | 2005-03-03 | 2007-01-23 | Intel Corporation | Method for reducing assembly-induced stress in a semiconductor die |
US7288438B2 (en) * | 2005-04-28 | 2007-10-30 | Intel Corporation | Solder deposition on wafer backside for thin-die thermal interface material |
US8733620B2 (en) * | 2005-12-08 | 2014-05-27 | Intel Corporation | Solder deposition and thermal processing of thin-die thermal interface material |
-
2006
- 2006-06-30 US US11/479,740 patent/US7476568B2/en not_active Expired - Fee Related
-
2008
- 2008-10-07 US US12/247,193 patent/US20090034206A1/en not_active Abandoned
Patent Citations (34)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4323914A (en) * | 1979-02-01 | 1982-04-06 | International Business Machines Corporation | Heat transfer structure for integrated circuit package |
US4801998A (en) * | 1984-08-20 | 1989-01-31 | Oki Electric Industry Co., Ltd. | EPROM device |
US5081067A (en) * | 1989-02-10 | 1992-01-14 | Fujitsu Limited | Ceramic package type semiconductor device and method of assembling the same |
US5291064A (en) * | 1991-04-16 | 1994-03-01 | Nec Corporation | Package structure for semiconductor device having a flexible wiring circuit member spaced from the package casing |
US5450283A (en) * | 1992-11-03 | 1995-09-12 | Motorola, Inc. | Thermally enhanced semiconductor device having exposed backside and method for making the same |
US5371404A (en) * | 1993-02-04 | 1994-12-06 | Motorola, Inc. | Thermally conductive integrated circuit package with radio frequency shielding |
US5396403A (en) * | 1993-07-06 | 1995-03-07 | Hewlett-Packard Company | Heat sink assembly with thermally-conductive plate for a plurality of integrated circuits on a substrate |
US5672548A (en) * | 1994-07-11 | 1997-09-30 | International Business Machines Corporation | Method for attaching heat sinks directly to chip carrier modules using flexible-epoxy |
US5587882A (en) * | 1995-08-30 | 1996-12-24 | Hewlett-Packard Company | Thermal interface for a heat sink and a plurality of integrated circuits mounted on a substrate |
US5907474A (en) * | 1997-04-25 | 1999-05-25 | Advanced Micro Devices, Inc. | Low-profile heat transfer apparatus for a surface-mounted semiconductor device employing a ball grid array (BGA) device package |
US5926371A (en) * | 1997-04-25 | 1999-07-20 | Advanced Micro Devices, Inc. | Heat transfer apparatus which accommodates elevational disparity across an upper surface of a surface-mounted semiconductor device |
US7244637B2 (en) * | 1998-09-03 | 2007-07-17 | Micron Technology, Inc. | Chip on board and heat sink attachment methods |
US6117797A (en) * | 1998-09-03 | 2000-09-12 | Micron Technology, Inc. | Attachment method for heat sinks and devices involving removal of misplaced encapsulant |
US6118177A (en) * | 1998-11-17 | 2000-09-12 | Lucent Technologies, Inc. | Heatspreader for a flip chip device, and method for connecting the heatspreader |
US6294408B1 (en) * | 1999-01-06 | 2001-09-25 | International Business Machines Corporation | Method for controlling thermal interface gap distance |
US6219238B1 (en) * | 1999-05-10 | 2001-04-17 | International Business Machines Corporation | Structure for removably attaching a heat sink to surface mount packages |
US6504243B1 (en) * | 2000-04-07 | 2003-01-07 | Advanced Micro Devices, Inc. | Removable heat transfer apparatus for a pin grid array (PGA) device, and associated installation and removal methods |
US6519154B1 (en) * | 2001-08-17 | 2003-02-11 | Intel Corporation | Thermal bus design to cool a microelectronic die |
US6995463B1 (en) * | 2001-09-27 | 2006-02-07 | Marvell International Ltd. | Integrated chip package having intermediate substrate and multiple semiconductor chips |
US6617683B2 (en) * | 2001-09-28 | 2003-09-09 | Intel Corporation | Thermal performance in flip chip/integral heat spreader packages using low modulus thermal interface material |
US20030131476A1 (en) * | 2001-09-28 | 2003-07-17 | Vlad Ocher | Heat conduits and terminal radiator for microcircuit packaging and manufacturing process |
US20030117775A1 (en) * | 2001-12-20 | 2003-06-26 | Vrtis Joan K. | Coated heat spreaders |
US20040037059A1 (en) * | 2002-08-21 | 2004-02-26 | Leon Stiborek | Integrated circuit package with spacer |
US20040084764A1 (en) * | 2002-09-16 | 2004-05-06 | Junichi Ishimine | Package structure, printed circuit board mounted with the same, electronic apparatus having the printed circuit board |
US7218000B2 (en) * | 2003-06-27 | 2007-05-15 | Intel Corporation | Liquid solder thermal interface material contained within a cold-formed barrier and methods of making same |
US7141454B2 (en) * | 2003-06-30 | 2006-11-28 | Intel Corporation | Wire-bonded package with electrically insulating wire encapsulant and thermally conductive overmold |
US7253523B2 (en) * | 2003-07-29 | 2007-08-07 | Intel Corporation | Reworkable thermal interface material |
US20070069835A1 (en) * | 2005-09-29 | 2007-03-29 | Telesphor Kamgaing | Compact integration of LC resonators |
US20070148949A1 (en) * | 2005-12-22 | 2007-06-28 | Intel Corporation | Nanostructure-based package interconnect |
US7371674B2 (en) * | 2005-12-22 | 2008-05-13 | Intel Corporation | Nanostructure-based package interconnect |
US20070231969A1 (en) * | 2006-03-30 | 2007-10-04 | Chrysler Gregory M | Covered devices in a semicoductor package |
US20070232050A1 (en) * | 2006-03-31 | 2007-10-04 | Munehiro Toyama | Embedding device in substrate cavity |
US20070231953A1 (en) * | 2006-03-31 | 2007-10-04 | Yoshihiro Tomita | Flexible interconnect pattern on semiconductor package |
US20070231970A1 (en) * | 2006-03-31 | 2007-10-04 | Tsuyoshi Fukuo | Cured mold compound spacer for stacked-die package |
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080001268A1 (en) * | 2006-06-30 | 2008-01-03 | Daoqiang Lu | Heat spreader as mechanical reinforcement for ultra-thin die |
US8063482B2 (en) * | 2006-06-30 | 2011-11-22 | Intel Corporation | Heat spreader as mechanical reinforcement for ultra-thin die |
US8642386B2 (en) | 2006-06-30 | 2014-02-04 | Intel Corporation | Heat spreader as mechanical reinforcement for ultra-thin die |
US20100102425A1 (en) * | 2008-10-24 | 2010-04-29 | Electronics And Telecommunications Research Institute | Ultra wideband system-on-package and method of manufacturing the same |
US8049319B2 (en) * | 2008-10-24 | 2011-11-01 | Electronics And Telecommunications Research Institute | Ultra wideband system-on-package |
WO2012087330A2 (en) * | 2010-12-23 | 2012-06-28 | Intel Corporation | Test, validation, and debug architecture |
WO2012087330A3 (en) * | 2010-12-23 | 2013-06-13 | Intel Corporation | Test, validation, and debug architecture |
US10198333B2 (en) | 2010-12-23 | 2019-02-05 | Intel Corporation | Test, validation, and debug architecture |
GB2493793B (en) * | 2010-12-23 | 2020-07-08 | Intel Corp | Test, validation, and debug architecture |
US9806002B2 (en) * | 2015-12-23 | 2017-10-31 | Intel Corporation | Multi-reference integrated heat spreader (IHS) solution |
Also Published As
Publication number | Publication date |
---|---|
US20080003719A1 (en) | 2008-01-03 |
US7476568B2 (en) | 2009-01-13 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7476568B2 (en) | Wafer-level assembly of heat spreaders for dual IHS packages | |
US8642386B2 (en) | Heat spreader as mechanical reinforcement for ultra-thin die | |
US7435664B2 (en) | Wafer-level bonding for mechanically reinforced ultra-thin die | |
US8227907B2 (en) | Flexible interconnect pattern on semiconductor package | |
US20080003780A1 (en) | Detachable stiffener for ultra-thin die | |
US7825503B2 (en) | Covered devices in a semiconductor package | |
US9136159B2 (en) | Method and system for a semiconductor for device package with a die-to-packaging substrate first bond | |
US20070231970A1 (en) | Cured mold compound spacer for stacked-die package | |
TWI413231B (en) | Rf module package | |
US20240087914A1 (en) | Method of manufacturing an electronic device and electronic device manufactured thereby | |
US20230040553A1 (en) | Semiconductor device package and manufacturing method thereof | |
WO2006112576A1 (en) | Method for manufacturing passive device and semiconductor package using thin metal piece | |
TWI779741B (en) | Semiconductor device and method of fabricating the same | |
Garnier et al. | System in package embedding III-V chips by fan-out wafer-level packaging for RF applications | |
US20070231951A1 (en) | Reducing layer count in semiconductor packages | |
US7638867B2 (en) | Microelectronic package having solder-filled through-vias | |
TWI425580B (en) | Process for manufacturing semiconductor chip packaging module | |
US11929293B2 (en) | Semiconductor package with lid structure |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |