TWI425580B - Process for manufacturing semiconductor chip packaging module - Google Patents
Process for manufacturing semiconductor chip packaging module Download PDFInfo
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- TWI425580B TWI425580B TW098130416A TW98130416A TWI425580B TW I425580 B TWI425580 B TW I425580B TW 098130416 A TW098130416 A TW 098130416A TW 98130416 A TW98130416 A TW 98130416A TW I425580 B TWI425580 B TW I425580B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
Description
本發明係關於一種製造半導體晶片封裝模組之方法，特別係關於一種不需要提供具有預形成晶片接收槽來接收晶片之基板，而可將晶片安置於晶片載體之製造半導體晶片封裝模組之方法。The present invention relates to a method of fabricating a semiconductor wafer package module, and more particularly to a method of fabricating a semiconductor chip package module that can be disposed on a wafer carrier without having to provide a substrate having a pre-formed wafer receiving trench to receive the wafer. .
將積體電路晶片安置於印刷電路板的技術，傳統上都會用到晶片載體。在此技術中，積體電路晶片係被提供電性接觸墊，而晶片係被安置於晶片載體上，晶片載體可包含扇出式(fan out)電路，傳統上為多層電路，形成於介電材料上。晶體載體的上方安置有晶片，以及適合藉由錫球將晶片連接於印刷電路板的球形陣列。在某些例子中，晶片載體可載有一個以上之晶片，若有需要，該等晶片可藉由晶片載體彼此連接。The technique of placing an integrated circuit chip on a printed circuit board has conventionally used a wafer carrier. In this technique, the integrated circuit chip is provided with an electrical contact pad, and the wafer is placed on the wafer carrier. The wafer carrier may comprise a fan out circuit, which is conventionally a multilayer circuit formed on the dielectric. On the material. A wafer is placed over the crystal carrier, and a spherical array suitable for attaching the wafer to the printed circuit board by solder balls. In some examples, the wafer carrier can carry more than one wafer, and if desired, the wafers can be connected to each other by a wafer carrier.
美國公開之專利申請案第2008/0197469號及第2008/0136002號皆提供了一種將積體電路晶片設置於晶片載體的方法。在此方法中，積體電路晶片(未封裝之晶粒)的背面係被施加黏著材料，以藉由拾取-放置精密對準系統接合至基板之預形成晶片接收槽內。為了確保積體電路晶片結合至基板，後續通常會再進行真空固化。接著，彈性介電層會填入於積體電路晶片與槽之間的空隙，接著會抽真空以除去氣泡。U.S. Patent Application Publication Nos. 2008/0197469 and 2008/0136002 each provide a method of arranging an integrated circuit wafer on a wafer carrier. In this method, the back side of the integrated circuit wafer (unpackaged die) is coated with an adhesive material for bonding into the preformed wafer receiving trench of the substrate by a pick-and-place precision alignment system. In order to ensure that the integrated circuit wafer is bonded to the substrate, vacuum curing is usually performed later. Next, the elastic dielectric layer fills the gap between the integrated circuit wafer and the trench, and then a vacuum is applied to remove the air bubbles.
雖然上述方法可減少封裝的厚度並增加通量，然晶片的背面需施加黏著材料，且需要抽真空以確保晶片固定於基板，不會因後續的彈性介電層之充填有一絲的移動。此外，為了去除彈性介電層充填時可能產生的氣泡，也需進行抽真空程序。Although the above method can reduce the thickness of the package and increase the flux, the back side of the wafer needs to be coated with an adhesive material, and a vacuum is required to ensure that the wafer is fixed to the substrate without a slight movement of the subsequent filling of the elastic dielectric layer. In addition, in order to remove bubbles that may be generated when the elastic dielectric layer is filled, an evacuation process is also required.
因此，便冀望有一種製造半導體晶片封裝模組的方法，能夠有較佳的生產效率，但不會犧牲掉晶片封裝模組可降低尺寸的優點。Therefore, it is expected that there is a method of manufacturing a semiconductor chip package module, which can have better production efficiency without sacrificing the advantage that the chip package module can be downsized.
本發明係提供一種製造半導體晶片封裝模組的方法。在此方法中，係提供一晶片載體，其包含具有對準標記及載體膜形成於其上的基板。晶片可藉由拾取-放置精密對準系統置放於載體膜上。接著，晶片係被壓入至該載體膜，至該晶片的頂面至少大致上與該載體膜的頂面共平面的程度。接續進行固化以使該載體膜完全固化。前述步驟完成後，可進行提供電性連接(電路)的步驟，其可包括：形成第一介電層於該晶片與該載體膜上；形成至少一開口於該第一介電層以露出至少該晶片之一部份；形成至少一再分佈層(re-distribution layer,RDL)於該第一介電層上以經由該開口連接該晶片；形成第二介電層於該再分佈層及該第一介電層上；形成至少一開口於該第二介電層以露出至少部份的該再分佈層；及形成導電金屬(包含球下金屬層，UBM)於開口中以經由再分佈層提供電性連接至該晶片。若需要，可進一步進行封裝、其它內連接製程及其它方法步驟。若將本發明方法用於在單一載體膜上同時處理多個晶片，可另包含切片步驟以將多個晶片分成單一晶片。若在形成導電金屬後，需要封裝、其它內連接製程及其它方法步驟，此切片步驟會在該等步驟後實施。The present invention provides a method of fabricating a semiconductor wafer package module. In this method, a wafer carrier is provided comprising a substrate having alignment marks and a carrier film formed thereon. The wafer can be placed on the carrier film by a pick-and-place precision alignment system. Next, the wafer is pressed into the carrier film to a level at which the top surface of the wafer is at least substantially coplanar with the top surface of the carrier film. The curing is continued to complete the curing of the carrier film. After the foregoing steps are completed, the step of providing an electrical connection (circuit) may be performed, which may include: forming a first dielectric layer on the wafer and the carrier film; forming at least one opening in the first dielectric layer to expose at least a portion of the wafer; forming at least one redistribution layer (RDL) on the first dielectric layer to connect the wafer via the opening; forming a second dielectric layer on the redistribution layer and the a dielectric layer; forming at least one opening of the second dielectric layer to expose at least a portion of the redistribution layer; and forming a conductive metal (including a sub-ball metal layer, UBM) in the opening to provide via the redistribution layer Electrically connected to the wafer. If necessary, further packaging, other internal connection processes, and other method steps can be performed. If the method of the present invention is used to simultaneously process a plurality of wafers on a single carrier film, a slicing step can be further included to separate the plurality of wafers into a single wafer. If a package, other interconnect process, and other method steps are required after forming the conductive metal, the slicing step will be performed after the steps.
根據本發明方法，基板不需要晶片接收槽。因此，介電材料不需要充填至晶片與槽壁間的空間，因而不需要後續的抽真空程序以去除充填彈性介電材料過程中可能產生的氣泡。其結果為，本發明方法能夠更有生產效率，而且因無彈性介電材料充填至槽中所產生的氣泡，其產率可提升。According to the method of the present invention, the substrate does not require a wafer receiving slot. Therefore, the dielectric material does not need to be filled into the space between the wafer and the wall of the groove, so that a subsequent vacuuming process is not required to remove bubbles that may be generated during the filling of the elastic dielectric material. As a result, the method of the present invention can be more productive, and the yield can be improved by the bubbles generated by the inelastic dielectric material being filled into the grooves.
以下實施例將對本發明作進一步之說明，唯非用以限制本發明之範圍，任何熟悉本發明技術領域者，在不違背本發明之精神下所得以達成之修飾及變化，均屬本發明之範圍。The invention is further illustrated by the following examples, which are not intended to limit the scope of the invention, and any modifications and variations which may be obtained without departing from the spirit of the invention are range.
以下不同實施例中之特徵為申請專利範圍中引述的元件的實例，且在不偏離申請專利範圍的情況下，可彼此結合為實施例。The following various embodiments are characterized by examples of the elements recited in the claims, and may be combined with each other as examples without departing from the scope of the claims.
圖1A至1I，係顯示本發明一實施例之各種操作及其順序。1A through 1I show various operations and sequences thereof in accordance with an embodiment of the present invention.
如圖1A所示，係提供晶片載體，其包含基板2及形成於基板2上之載體膜4。基板2可由具有低熱膨脹係數(CTE)之有機、玻璃、陶瓷、或矽材料組成。較佳地，基板2為具有高玻璃轉移溫度之有機基板，例如環氧樹脂型的FR5或雙馬來醯亞胺三嗪(bismaleimide triazine,BT)型基板。基板2可為圓形，如晶圓，或為矩形，如面板。載體膜4應由可讓物件在壓力及/或加熱下壓入，且可進一步藉由加熱或固化步驟來硬化之材料所組成(如由模製化合物組成之乾膜)。例如，載體膜4可由聚對苯二甲酸乙二酯(PET)、聚四氟乙烯(鐵氟龍)、聚醯亞胺或環氧樹脂型材料組成。載體膜4的厚度係根據要被壓入於其中的晶片厚度來決定。例如，若晶片的厚度為約100微米，載體膜的厚度應大於100微米。As shown in FIG. 1A, a wafer carrier is provided which comprises a substrate 2 and a carrier film 4 formed on the substrate 2. The substrate 2 may be composed of an organic, glass, ceramic, or tantalum material having a low coefficient of thermal expansion (CTE). Preferably, the substrate 2 is an organic substrate having a high glass transition temperature, such as an epoxy resin type FR5 or a bismaleimide triazine (BT) type substrate. The substrate 2 can be circular, such as a wafer, or rectangular, such as a panel. The carrier film 4 should be composed of a material which allows the article to be pressed under pressure and/or heat and which can be further hardened by a heating or curing step (e.g., a dry film composed of a molding compound). For example, the carrier film 4 may be composed of polyethylene terephthalate (PET), polytetrafluoroethylene (Teflon), polyimide or epoxy type materials. The thickness of the carrier film 4 is determined according to the thickness of the wafer to be pressed therein. For example, if the thickness of the wafer is about 100 microns, the thickness of the carrier film should be greater than 100 microns.
在圖1B中，晶片6係被放置於載體膜4上。晶片6可以以所需的位置放置或分佈在載體膜4上。為了達到此目的，本發明領域中任何已知的技術皆可使用，例如，拾取-放置對準系統。在一實施例中，黏合機，如精密對準之黏晶機，可用來將晶片6黏合至載體膜4。在一實施例中，黏著材料(如膠帶)可施加於晶片6的背面或施加於載體膜4想要的位置上，以使該晶片6連結至該載體膜4。若係多個晶片進行處理，可使用具有對準圖樣於其上之對準工具(板)。圖樣膠係可印刷於工具上(用於黏晶粒的表面)，接著藉由使用具有覆晶(flip chip)功能之拾放精密對準系統將晶片們以想要的間隔重分佈在工具上，再以圖樣膠將晶片黏在工具上。接續，晶片黏著材料可印在晶片背面。黏合機接著可用於將載體膜4結合至晶片的背面。In FIG. 1B, the wafer 6 is placed on the carrier film 4. The wafer 6 can be placed or distributed on the carrier film 4 in a desired position. To this end, any known technique in the field of the invention can be used, for example, a pick-and-place alignment system. In one embodiment, a bonding machine, such as a precision aligned die bonder, can be used to bond the wafer 6 to the carrier film 4. In an embodiment, an adhesive material such as an adhesive tape may be applied to the back side of the wafer 6 or to a desired position of the carrier film 4 to bond the wafer 6 to the carrier film 4. If multiple wafers are processed, an alignment tool (plate) having an alignment pattern thereon can be used. The pattern glue can be printed on the tool (for the surface of the bonded die), and then the wafers are redistributed on the tool at the desired interval by using a pick and place precision alignment system with a flip chip function. Then, the wafer is glued to the tool with a pattern glue. Successively, the wafer adhesive material can be printed on the back side of the wafer. A bonding machine can then be used to bond the carrier film 4 to the back side of the wafer.
晶片6，通常為電子元件，為半導體晶粒，其有時會稱作積體電路晶片或主動元件。在一些實施例中，晶片6為另一種形式的電子元件，如被動元件，例如電阻器、電容器或電感器。The wafer 6, typically an electronic component, is a semiconductor die, which is sometimes referred to as an integrated circuit die or active component. In some embodiments, wafer 6 is another form of electronic component, such as a passive component, such as a resistor, capacitor, or inductor.
當晶片6放置於載體膜4上後，如圖1C所示，晶片6會被壓入至載體膜4，至晶片6的頂面係至少大致上與載體膜4的表面共平面。晶片6的相當部份係埋入於該載體膜4中。晶片6的表面可高於載體膜4的表面之程度係根據晶片6的厚度決定。例如，晶片6的頂面可高於載體膜4的表面約晶片6厚度的約0%至20%，較佳為晶片6厚度的約10%，再較佳為晶片6厚度的約5%。在一實施例中，晶片6的頂面與載體膜4表面的差不超過約3微米。此步驟係可藉由壓縮機，例如熱壓縮機、真空層壓機或晶圓黏合機在適當的壓力及視情況地加熱上進行。施加的壓力及溫度係根據載體膜4所使用的材料而定。例如，在100至150℃的溫度設定及0.6托的腔室真空壓力設定下，晶片係可成功地藉由施加1公斤/平方公分的附加壓力60秒埋入典型的載體膜。After the wafer 6 is placed on the carrier film 4, as shown in FIG. 1C, the wafer 6 is pressed into the carrier film 4, and the top surface of the wafer 6 is at least substantially coplanar with the surface of the carrier film 4. A substantial portion of the wafer 6 is embedded in the carrier film 4. The extent to which the surface of the wafer 6 can be higher than the surface of the carrier film 4 is determined according to the thickness of the wafer 6. For example, the top surface of the wafer 6 may be higher than about 0% to 20% of the thickness of the wafer 6 of the surface of the carrier film 4, preferably about 10% of the thickness of the wafer 6, and more preferably about 5% of the thickness of the wafer 6. In one embodiment, the difference between the top surface of the wafer 6 and the surface of the carrier film 4 is no more than about 3 microns. This step can be carried out by a suitable pressure and optionally heating by a compressor such as a thermal compressor, a vacuum laminator or a wafer bonder. The pressure and temperature applied are based on the materials used for the carrier film 4. For example, at a temperature setting of 100 to 150 ° C and a chamber vacuum pressure setting of 0.6 Torr, the wafer system can be successfully embedded into a typical carrier film by applying an additional pressure of 1 kg/cm 2 for 60 seconds.
在晶片6被埋入載體膜4後，載體膜4可被固化以硬化。在一實施例中，載體膜4可在約250℃固化。對於環氧樹脂為基材之載體膜，其固化溫度通常介於100至200℃；對於聚醯亞胺為基材之載體膜，其固化溫度通常介於200至370℃；對於丙烯酸類為基材之載體膜，其固化溫度通常介於100至250℃。After the wafer 6 is buried in the carrier film 4, the carrier film 4 can be cured to be hardened. In an embodiment, the carrier film 4 can be cured at about 250 °C. For the carrier film of epoxy resin as the substrate, the curing temperature is usually between 100 and 200 ° C; for the carrier film of polyimine as the substrate, the curing temperature is usually between 200 and 370 ° C; for acrylic based The carrier film of the material usually has a curing temperature of from 100 to 250 °C.
接著，可進行一系列的步驟以提供電性連接(電路)至該晶片6。如圖1D至1I所示，其步驟可包括但不限於：形成第一介電層8於該晶片6及該載體膜4上；形成開口10於該第一介電層8以露出該晶片6的至少一部份；形成再分佈層12於開口10中；形成第二介電層14於該再分佈層12、開口10及第一介電層8上；形成開口16於該第二介電層14以露出該再分佈層12的至少一部份；形成接觸墊18(球下金屬層，UBM)於該再分佈層12上；以及形成導電金屬20於該接觸墊18上。Next, a series of steps can be performed to provide an electrical connection (circuit) to the wafer 6. As shown in FIGS. 1D to 1I, the steps may include, but are not limited to, forming a first dielectric layer 8 on the wafer 6 and the carrier film 4; forming an opening 10 in the first dielectric layer 8 to expose the wafer 6. Forming at least a portion of the redistribution layer 12 in the opening 10; forming a second dielectric layer 14 on the redistribution layer 12, the opening 10 and the first dielectric layer 8; forming an opening 16 in the second dielectric Layer 14 exposes at least a portion of the redistribution layer 12; a contact pad 18 (sub-ball metal layer, UBM) is formed over the redistribution layer 12; and a conductive metal 20 is formed over the contact pad 18.
本發明領域中任何已知的技術皆可利用以實施上述步驟。例如，介電層8及14可藉由旋轉塗佈或印刷，及在需要時可配合後續的熱固化製程來形成。微影與蝕刻製程可用來在介電層8及14中形成開口10及16。濺鍍或電鍍製程與微影及蝕刻製程一起可在開口10及16形成圖案化的再分佈層12及接觸墊18。導電金屬20可包含錫球或錫塊。在一實施例中，錫球可藉由球置放或錫糊狀物印刷技術形成接觸於該接觸墊18。此步驟可進一步包含再流動步驟以形成錫球。Any of the techniques known in the art can be utilized to carry out the above steps. For example, dielectric layers 8 and 14 can be formed by spin coating or printing, and if desired, in conjunction with subsequent thermal curing processes. The lithography and etching processes can be used to form openings 10 and 16 in dielectric layers 8 and 14. Sputtering or electroplating processes, along with lithography and etching processes, can form patterned redistribution layer 12 and contact pads 18 in openings 10 and 16. The conductive metal 20 may comprise solder balls or tin blocks. In one embodiment, the solder balls may be contacted to the contact pads 18 by ball placement or tin paste printing techniques. This step may further comprise a reflow step to form a solder ball.
用於第一介電層8之介電材料應具有與載體膜4相容或類似之物理性質，或該兩者之材料的選擇應使第一介電層8與載體膜4可緊密地彼此黏合而不會在後續的操作中剝離。舉例而言，介電材料應與載體膜4的材料具有接近的熱膨脹係數(CTE)。介電材料可包含聚對苯二甲酸乙二酯(PET)、聚四氟乙烯(鐵氟龍)、聚醯亞胺或環氧樹脂型材料。再分佈層12的材料可包含可藉由濺鍍形成之Ti/Cu或Ti/Al/Ti，及可藉由電鍍形成之Cu/Au或Cu/Ni/Au。該接觸墊18可包含Au、Al或Cu或其組合。該導電金屬20可為錫塊或錫球，由此領域中已知的材料組成。舉例而言，導電金屬20可包含Al/NiV/Cu、Ti/NiV/Cu、TiW/Au或Ti/Cu/Ni。The dielectric material used for the first dielectric layer 8 should have physical properties compatible or similar to the carrier film 4, or the materials of the two should be selected such that the first dielectric layer 8 and the carrier film 4 can closely closely each other. Bonded without peeling off in subsequent operations. For example, the dielectric material should have a coefficient of thermal expansion (CTE) close to the material of the carrier film 4. The dielectric material may comprise polyethylene terephthalate (PET), polytetrafluoroethylene (Teflon), polyimide or epoxy type materials. The material of the redistribution layer 12 may comprise Ti/Cu or Ti/Al/Ti which may be formed by sputtering, and Cu/Au or Cu/Ni/Au which may be formed by electroplating. The contact pad 18 can comprise Au, Al or Cu or a combination thereof. The conductive metal 20 can be a tin block or a solder ball, and is composed of materials known in the art. For example, the conductive metal 20 may comprise Al/NiV/Cu, Ti/NiV/Cu, TiW/Au, or Ti/Cu/Ni.
若有需要，在導電金屬形成後，可進一步實施封裝及其它內連接製程以及其它處理步驟。若本發明係用於在單一載體膜上同時處理多個晶片，可另外包含切割步驟以將多個晶片分成個別的晶片。若在導電金屬形成後，有需要進一步實施封裝及其它內連接製程以及其它處理步驟，切割步驟會在該等步驟實施後進行。If necessary, the package and other interconnect processes and other processing steps can be further performed after the conductive metal is formed. If the invention is used to simultaneously process a plurality of wafers on a single carrier film, a further cutting step can be included to separate the plurality of wafers into individual wafers. If the package and other interconnect processes and other processing steps are required after the formation of the conductive metal, the cutting step will be performed after the steps are implemented.
在導電金屬形成後，可進行測試。若單一載體膜上係處理多個晶片，多個晶片可在測試後再切割為個別的晶片After the conductive metal is formed, it can be tested. If a single carrier film is processed on multiple wafers, multiple wafers can be diced into individual wafers after testing
如此領域中所了解，本發明方法可應用於包含多晶片的半導體晶片模組或單一載體膜上的多個晶片。雖然圖式中僅顯示兩個晶片，根據本發明的方法也可應用於包含單一晶片或兩個晶片以上的半導體晶片模組。As is recognized in the art, the method of the present invention is applicable to a plurality of wafers comprising a multi-wafer semiconductor wafer module or a single carrier film. Although only two wafers are shown in the drawings, the method according to the present invention is also applicable to semiconductor wafer modules comprising a single wafer or more than two wafers.
以下申請專利範圍係用以界定本發明之合理保護範圍。然應明瞭者，技藝人士基於本發明之揭示所可達成之種種顯而易見之改良，亦應歸屬本發明合理之保護範圍。The following patent claims are intended to define the scope of the invention. It should be understood that the obvious modifications that can be made by the skilled person based on the disclosure of the present invention are also within the scope of the present invention.
2．．．基板2. . . Substrate
4．．．載體膜4. . . Carrier film
6．．．晶片6. . . Wafer
8．．．第一介電層8. . . First dielectric layer
10．．．開口10. . . Opening
12．．．再分佈層12. . . Redistribution layer
14．．．第二介電層14. . . Second dielectric layer
16．．．開口16. . . Opening
18．．．接觸墊18. . . Contact pad
20．．．導電金屬20. . . Conductive metal
第1A至1I圖為構成過程中之半導體晶片封裝模組之橫截面，顯示根據本發明之方法步驟。1A through 1I are cross sections of a semiconductor wafer package module in the process of construction, showing the steps of the method in accordance with the present invention.
圖中相對應的元件係以相同的標號表示。圖中的尺寸並非根據實際尺寸。Corresponding elements in the figures are denoted by the same reference numerals. The dimensions in the figures are not based on actual dimensions.
2．．．基板2. . . Substrate
4．．．載體膜4. . . Carrier film
6．．．晶片6. . . Wafer
8．．．第一介電層8. . . First dielectric layer
12．．．再分佈層12. . . Redistribution layer
14．．．第二介電層14. . . Second dielectric layer
18．．．接觸墊18. . . Contact pad
20．．．導電金屬20. . . Conductive metal
Claims (23)
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| TW200926323A (en) * | 2007-12-14 | 2009-06-16 | Stats Chippac Ltd | Semiconductor device and method of forming interconnect structure for encapsulated die having pre-applied protective layer |
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