US20080314742A1 - Electrolytic ni plating apparatus and method of manufacturing semiconductor device - Google Patents

Electrolytic ni plating apparatus and method of manufacturing semiconductor device Download PDF

Info

Publication number
US20080314742A1
US20080314742A1 US12/021,357 US2135708A US2008314742A1 US 20080314742 A1 US20080314742 A1 US 20080314742A1 US 2135708 A US2135708 A US 2135708A US 2008314742 A1 US2008314742 A1 US 2008314742A1
Authority
US
United States
Prior art keywords
anode
plating
electrolytic
grain size
average grain
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US12/021,357
Inventor
Hiroaki Tachibana
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Electronics Corp
Original Assignee
NEC Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Electronics Corp filed Critical NEC Electronics Corp
Assigned to NEC ELECTRONICS CORPORATION reassignment NEC ELECTRONICS CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: TACHIBANA, HIROAKI
Publication of US20080314742A1 publication Critical patent/US20080314742A1/en
Assigned to RENESAS ELECTRONICS CORPORATION reassignment RENESAS ELECTRONICS CORPORATION CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: NEC ELECTRONICS CORPORATION
Assigned to MICROWIRE, LLC reassignment MICROWIRE, LLC SECURITY INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: TSI TECHNOLOGIES LLC
Abandoned legal-status Critical Current

Links

Images

Classifications

    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D17/00Constructional parts, or assemblies thereof, of cells for electrolytic coating
    • C25D17/10Electrodes, e.g. composition, counter electrode
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D17/00Constructional parts, or assemblies thereof, of cells for electrolytic coating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/03Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/741Apparatus for manufacturing means for bonding, e.g. connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/03Manufacturing methods
    • H01L2224/034Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/0346Plating
    • H01L2224/03462Electroplating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/03Manufacturing methods
    • H01L2224/036Manufacturing methods by patterning a pre-deposited material
    • H01L2224/03618Manufacturing methods by patterning a pre-deposited material with selective exposure, development and removal of a photosensitive material, e.g. of a photosensitive conductive resin
    • H01L2224/0362Photolithography
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05655Nickel [Ni] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13116Lead [Pb] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/741Apparatus for manufacturing means for bonding, e.g. connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01004Beryllium [Be]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys

Definitions

  • the present invention relates to an electrolytic Ni plating apparatus and relates to a method of manufacturing a semiconductor device.
  • Lead-free solder has rapidly been disseminated as a measure for environmental preservation. There is an ongoing trend of replacement of barrier metal adapted to the lead-free solder which is used for flip-chip products of semiconductor devices, from Cu to Ni. Cu shows a large rate of alloying while Ni shows a small rate of alloying.
  • a Ni film is formed generally by electroless plating or electrolytic plating. Ni plating apparatuses, in particular those used for semiconductor manufacturing processes, are required that they can form a Ni plating film in a stable and high-throughput manner. In conventional electrolytic plating apparatuses applied to semiconductor manufacturing processes, a soluble Ni anode has generally been adopted as an anode.
  • FIG. 5 is a drawing showing a configuration of a conventional Ni plating apparatus 200 .
  • the Ni plating apparatus 200 is composed of an inner bath 101 , an outer bath 102 , a wafer holder 103 , and a reservoir tank 104 .
  • a Ni anode 105 and a plating solution jetting port 106 are provided at the bottom of the inner bath 101 .
  • a plating solution discharging port 107 is provided at the bottom of the outer bath 102 .
  • a pump 108 and a filter 109 are provided at the bottom of the outer bath 102 .
  • the Ni anode 105 and a contact portion 110 are connected to a power source 111 .
  • a wafer 112 is brought down to and placed on the contact portion 110 , while being held by a wafer holder 103 .
  • a plating solution jetted out from the plating solution jetting port 106 is allowed to contact with the wafer 112 .
  • voltage is applied by the power source 111 , so as to define the wafer 112 as a cathode and the Ni anode 105 as an anode
  • Ni deposits on the surface of the wafer 112
  • Ni dissolves out from the surface of the Ni anode 105 , thereby the plating proceeds.
  • the Ni anode 105 is kept under a state of high potential.
  • the anode used for the electrolytic Ni plating apparatus includes insoluble anodes such as those composed of Pt, Ti and so forth, and soluble Ni anode.
  • the Ni anode which produces only a small amount of oxygen from the anode, is generally used for plating onto a silicon wafer having fine patterns formed thereon.
  • the reaction expressed as Ni ⁇ Ni 2+ +2e ⁇ occurs with respect to the Ni anode used as an anode, thereby the Ni anode gradually dissolves as a consequence.
  • a reaction of producing Ni oxide or Ni hydroxide may proceed, besides the above-described dissolution reaction.
  • the surface of the Ni anode may be passivated.
  • Ni anode In electrolytic Ni plating using the Ni anode as an anode, it is generally known that a state of high potential appears in the initial stage of film formation within several seconds to several tens of seconds after the start of the voltage application, as compared with potential in the later stage of the film formation. For this reason, in the process of successive plating of wafers under conditions of large current density, the Ni anode is placed under large potential in a high rate, and is more likely to produce thereon Ni oxide or Ni hydroxide.
  • the present inventor found that the conventional Ni anode has a large average grain size and thus the conventional Ni anode has a small ratio of grain boundary and shows a small rate of dissolution.
  • Ni anode is therefore likely to produce Ni oxide or Ni hydroxide thereon, or in other words, likely to be passivated. Passivation of the surface of the anode creates a problem of the lowering in the current efficiency and the decrease in the rate of film formation.
  • Japanese Laid-Open Patent Publication No. 2003-171797 discloses a technique of suppressing generation of particles such as sludge on the anode side, by controlling the grain size of a copper anode. However, it is not aimed at solving the problem of passivation. The copper anode will not raise the problem described in the above. The present invention is to solve the problem specific to the case where the Ni anode is used.
  • the present invention is conceived after considering the above-described situation, and is aimed at suppressing passivation of the surface of a Ni anode, and thereby preventing the current efficiency and the rate of film formation from degrading.
  • an electrolytic Ni plating apparatus provided with a nickel (Ni) anode having an average grain size of 10 ⁇ m or smaller.
  • Ni anode having an average grain size of 10 ⁇ m or smaller By using the Ni anode having an average grain size of 10 ⁇ m or smaller, the passivation of the surface of Ni anode is suppressed, and thereby the current efficiency and the rate of film formation are prevented from degrading.
  • Ni anode for electrolytic Ni plating having an average grain size of 10 ⁇ m or smaller.
  • a method of manufacturing a semiconductor device containing an electrolytic Ni plating process wherein, in the electrolytic Ni plating process, a Ni anode having an average grain size of 10 ⁇ m or smaller is used as an anode.
  • passivation of the surface of a Ni anode is suppressed, and thereby the current efficiency and the rate of film formation are prevented from degrading, by adopting the Ni anode having an average grain size of 10 ⁇ m or smaller.
  • Providing a stable Ni plating film contributes to improvement in quality, and to maintenance of stable production capacity.
  • FIG. 1 is a drawing showing one configuration of an electrolytic Ni plating apparatus according to one embodiment of the present invention
  • FIG. 2 is an enlarged sectional view of the wafer shown in FIG. 1 ;
  • FIG. 3 is a SIM image of the Ni anode of Example 1;
  • FIG. 4 is a graph showing relations between the number of runs of wafer processing and thickness of Ni plating in Example 1;
  • FIG. 5 is a drawing showing one configuration of a conventional Ni plating apparatus
  • FIG. 6 is a SIM image of a Ni anode of Comparative Example 1.
  • FIG. 7 is a graph showing relations between the number of runs of wafer processing and thickness of Ni plating in Comparative Example 1.
  • FIG. 1 is a drawing showing an exemplary electrolytic Ni plating apparatus 100 according to the present invention.
  • the Ni plating apparatus 100 has an inner bath 101 , an outer bath 102 , a wafer holder 103 , and a reservoir tank 104 .
  • a Ni anode 105 having an average grain size of 10 ⁇ m or smaller, and a plating solution jetting port 106 , through which plating solution is fed into the inner bath 101 , are provided.
  • a plating solution discharging port 107 is provided at the bottom of the outer bath 102 .
  • FIG. 2 is an enlarged sectional view of the wafer 112 shown in FIG. 1 , showing the wafer adapted to formation of lead solder bumps or lead-free solder bumps.
  • a Cu seed film 114 is formed over the surface of a semiconductor substrate 113 , and a photoresist 115 is patterned over the Cu seed film 114 .
  • the wafer 112 is held face-down by the wafer holder 103 , so as to downwardly direct the surface having the photoresist 115 patterned thereon.
  • the wafer holder 103 and the wafer 112 are brought down to and placed on the contact portion 110 , and allowed to contact with the plating solution jetted from the plating solution jetting port 106 .
  • voltage is applied by the power source 111 , so as to define the wafer 112 which is in contact with the contact portion 110 , as a cathode, and the Ni anode 105 as an anode
  • Ni deposits on the surface of the wafer 112 in the portion where the Cu seed film 114 is exposed, and Ni dissolves out from the surface of the Ni anode 105 .
  • the upper limit of average grain size of the Ni anode is 10 ⁇ m or smaller, and more preferably 3 ⁇ m or smaller.
  • the lower limit of the average grain size of the Ni anode is not specifically limited, it is preferably 0.1 ⁇ m or larger.
  • the average grain size of the Ni anode may be calculated typically according to the procedures below. First, a clean section of an anode is produced using an FIB (focused ion beam) apparatus. An image of this section is taken by a SIM (scanning ion microscope). The number of grains per unit area is then counted on the SIM image. The counted number of grains is divided by the unit area to obtain the average grain size.
  • FIB focused ion beam
  • the conventionally used Ni anode Since the conventionally used Ni anode has a large average grain size and consequently has only a small ratio of grain boundary, it has the slow rate of dissolution. As a consequence, the Ni anode has been likely to produce Ni oxide or Ni hydroxide, and has been likely to be passivated.
  • the Ni anode used for the Ni plating apparatus of the present invention has an average grain size of as small as 10 ⁇ m or below.
  • the Ni anode therefore has a large ratio of grain boundary, shows a large rate of dissolution, and is consequently less likely to produce Ni oxide nor Ni hydroxide. In other words, the Ni anode of this embodiment is less likely to be passivated.
  • the current density and the rate of film formation can be prevented from degrading even when the wafers are successively processed under conditions of large current density.
  • the conditions of the large current density referred to herein means that the anode current density is equal to or more than 1.5 A/dm 2 .
  • the Ni anode of this embodiment is less likely to be passivated even under the conditions of such large current density.
  • the Ni anode of this embodiment may be used.
  • the Ni anode having an average grain size of 10 ⁇ m or smaller as an anode in the plating process the passivation of the surface of the Ni anode can be suppressed, and thereby a stable Ni plating film may be provided.
  • this embodiment contributes to improvement in quality, and to maintenance of stable production capacity.
  • FIG. 3 shows a SIM image of the Ni anode of this Example.
  • Mean grain area S can be obtained by dividing the unit area by the number of grains. In the SIM image of the Example, the number of grains per unit area was counted. The mean grain area S was obtained by dividing the unit area by the counted number of grains. Next, in order to convert the area into length, the grain was approximated by a circle, to thereby calculate the average grain size L.
  • the average grain size L is calculated by the equation below:
  • the average grain size L was 0.8 ⁇ m.
  • FIG. 4 is a graph showing relations between the number of runs of wafer processing and thickness of the Ni plating film.
  • maximum values, minimum values, and average values of the Ni plating film were shown for every number of runs of wafer processing. It was found that the Ni anode was not passivated even under successive processing of wafers under conditions of large current density, or in other words, even for the case where the Ni anode was placed under high potential for a long duration of time. Accordingly, the current efficiency was not degraded, and consequently also the rate of film formation was not degraded. From the graph in FIG. 4 , the thickness of the film did not change even after the number of runs of wafer processing increased.
  • Example 6 is a SIM image of the Ni anode of this Comparative Example.
  • FIG. 7 is a graph showing relations between the number of runs of wafer processing and thickness of the Ni plating film, when the wafers were successively processed under conditions of large current density. As a result of passivation of the surface of the Ni anode, the current efficiency gradually decreased, and thereby the rate of film formation decreased. It is obvious from FIG. 7 that film thickness gradually decreased.
  • Example 1 was largely improved in the rate of film formation as compared with Comparative Example 1.
  • the Ni anode of the Ni plating apparatus of Example 1 By reducing the average grain size of the Ni anode of the Ni plating apparatus of Example 1 to equal to or smaller than 10 ⁇ m, as described in the above, the Ni anode became less likely to produce Ni oxide or Ni hydroxide. Thus, the passivation was prevented, even when the wafers were successively processed under conditions of large current density. Since the passivation was suppressed, the lowering in the current efficiency and in the rate of film formation was avoided. As a consequence, the Example 1 successfully achieved stable provision of Ni plating film.

Abstract

Aimed at providing an electrolytic Ni plating apparatus capable of suppressing passivation of the surface of a Ni anode, preventing current efficiency and rate of film formation from being degraded, providing a stable Ni plating so as to contribute to improvement in quality, and maintaining a stable production capacity. The electrolytic Ni plating apparatus of the present invention is provided with a nickel (Ni) anode having an average grain size of 10 μm or smaller.

Description

  • This application is based on Japanese patent application No. 2007-017703 the content of which is incorporated hereinto by reference.
  • BACKGROUND
  • 1. Technical Field
  • The present invention relates to an electrolytic Ni plating apparatus and relates to a method of manufacturing a semiconductor device.
  • 2. Related Art
  • Lead-free solder has rapidly been disseminated as a measure for environmental preservation. There is an ongoing trend of replacement of barrier metal adapted to the lead-free solder which is used for flip-chip products of semiconductor devices, from Cu to Ni. Cu shows a large rate of alloying while Ni shows a small rate of alloying. A Ni film is formed generally by electroless plating or electrolytic plating. Ni plating apparatuses, in particular those used for semiconductor manufacturing processes, are required that they can form a Ni plating film in a stable and high-throughput manner. In conventional electrolytic plating apparatuses applied to semiconductor manufacturing processes, a soluble Ni anode has generally been adopted as an anode.
  • FIG. 5 is a drawing showing a configuration of a conventional Ni plating apparatus 200. As shown in FIG. 5, the Ni plating apparatus 200 is composed of an inner bath 101, an outer bath 102, a wafer holder 103, and a reservoir tank 104. At the bottom of the inner bath 101, a Ni anode 105 and a plating solution jetting port 106 are provided. On the other hand, at the bottom of the outer bath 102, a plating solution discharging port 107 is provided. Also a pump 108 and a filter 109 are provided. The Ni anode 105 and a contact portion 110 are connected to a power source 111. A wafer 112 is brought down to and placed on the contact portion 110, while being held by a wafer holder 103. Thus, a plating solution jetted out from the plating solution jetting port 106 is allowed to contact with the wafer 112. When voltage is applied by the power source 111, so as to define the wafer 112 as a cathode and the Ni anode 105 as an anode, Ni deposits on the surface of the wafer 112, and Ni dissolves out from the surface of the Ni anode 105, thereby the plating proceeds. During the initial film formation in the period up to several seconds to several tens of seconds after the start of the voltage application, the Ni anode 105 is kept under a state of high potential. Therefore, there is a problem that, for the case where the wafers are successively processed under conditions of large current density, or in other words, for the case where the Ni anode 105 is kept under high potential for a long duration of time, the surface of the Ni anode 105 is passivated, and thereby current efficiency degrades, and the rate of film formation decreases.
  • The anode used for the electrolytic Ni plating apparatus includes insoluble anodes such as those composed of Pt, Ti and so forth, and soluble Ni anode. The Ni anode, which produces only a small amount of oxygen from the anode, is generally used for plating onto a silicon wafer having fine patterns formed thereon.
  • In the course of general film formation based on Ni plating, the reaction expressed as Ni→Ni2++2e occurs with respect to the Ni anode used as an anode, thereby the Ni anode gradually dissolves as a consequence. However, if the Ni anode is exposed to a potential higher than a predetermined level, a reaction of producing Ni oxide or Ni hydroxide may proceed, besides the above-described dissolution reaction. Thus, the surface of the Ni anode may be passivated. In electrolytic Ni plating using the Ni anode as an anode, it is generally known that a state of high potential appears in the initial stage of film formation within several seconds to several tens of seconds after the start of the voltage application, as compared with potential in the later stage of the film formation. For this reason, in the process of successive plating of wafers under conditions of large current density, the Ni anode is placed under large potential in a high rate, and is more likely to produce thereon Ni oxide or Ni hydroxide. The present inventor found that the conventional Ni anode has a large average grain size and thus the conventional Ni anode has a small ratio of grain boundary and shows a small rate of dissolution. Such a Ni anode is therefore likely to produce Ni oxide or Ni hydroxide thereon, or in other words, likely to be passivated. Passivation of the surface of the anode creates a problem of the lowering in the current efficiency and the decrease in the rate of film formation.
  • Japanese Laid-Open Patent Publication No. 2003-171797 discloses a technique of suppressing generation of particles such as sludge on the anode side, by controlling the grain size of a copper anode. However, it is not aimed at solving the problem of passivation. The copper anode will not raise the problem described in the above. The present invention is to solve the problem specific to the case where the Ni anode is used.
  • The present invention is conceived after considering the above-described situation, and is aimed at suppressing passivation of the surface of a Ni anode, and thereby preventing the current efficiency and the rate of film formation from degrading.
  • SUMMARY
  • According to the present invention, there is provided an electrolytic Ni plating apparatus provided with a nickel (Ni) anode having an average grain size of 10 μm or smaller.
  • By using the Ni anode having an average grain size of 10 μm or smaller, the passivation of the surface of Ni anode is suppressed, and thereby the current efficiency and the rate of film formation are prevented from degrading.
  • According to the present invention, there is also provided a Ni anode for electrolytic Ni plating having an average grain size of 10 μm or smaller.
  • According to the present invention, there is also provided a method of manufacturing a semiconductor device containing an electrolytic Ni plating process, wherein, in the electrolytic Ni plating process, a Ni anode having an average grain size of 10 μm or smaller is used as an anode.
  • According to the present invention, passivation of the surface of a Ni anode is suppressed, and thereby the current efficiency and the rate of film formation are prevented from degrading, by adopting the Ni anode having an average grain size of 10 μm or smaller. Providing a stable Ni plating film contributes to improvement in quality, and to maintenance of stable production capacity.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • The above and other objects, advantages and features of the present invention will be more apparent from the following description of certain preferred embodiments taken in conjunction with the accompanying drawings, in which:
  • FIG. 1 is a drawing showing one configuration of an electrolytic Ni plating apparatus according to one embodiment of the present invention;
  • FIG. 2 is an enlarged sectional view of the wafer shown in FIG. 1;
  • FIG. 3 is a SIM image of the Ni anode of Example 1;
  • FIG. 4 is a graph showing relations between the number of runs of wafer processing and thickness of Ni plating in Example 1;
  • FIG. 5 is a drawing showing one configuration of a conventional Ni plating apparatus;
  • FIG. 6 is a SIM image of a Ni anode of Comparative Example 1; and
  • FIG. 7 is a graph showing relations between the number of runs of wafer processing and thickness of Ni plating in Comparative Example 1.
  • DETAILED DESCRIPTION
  • The invention will now be described herein with reference to an illustrative embodiment. Those skilled in the art will recognize that many alternative embodiments can be accomplished using the teachings of the present invention and that the invention is not limited to the embodiment illustrated for explanatory purposes.
  • Paragraphs below will detail embodiments of the electrolytic Ni plating apparatus according to the present invention, referring to the attached drawings. It is to be noted that any constituents commonly appear in all drawings will be given with the same reference numerals, and those explanations will not be repeated.
  • FIG. 1 is a drawing showing an exemplary electrolytic Ni plating apparatus 100 according to the present invention. The Ni plating apparatus 100 has an inner bath 101, an outer bath 102, a wafer holder 103, and a reservoir tank 104. At the bottom of the inner bath 101, a Ni anode 105 having an average grain size of 10 μm or smaller, and a plating solution jetting port 106, through which plating solution is fed into the inner bath 101, are provided. At the bottom of the outer bath 102, a plating solution discharging port 107, through which the plating solution overflown from the inner bath 101 is returned to the reservoir tank 104, is provided. There are also provided a pump 108 for jetting the plating solution reserved in the reservoir tank 104 into the inner bath 101, and a filter 109 for removing dust or particles from the solution to be jetted. The Ni anode 105 and the contact portion 110 are connected to a power source 111 for current supply. FIG. 2 is an enlarged sectional view of the wafer 112 shown in FIG. 1, showing the wafer adapted to formation of lead solder bumps or lead-free solder bumps. A Cu seed film 114 is formed over the surface of a semiconductor substrate 113, and a photoresist 115 is patterned over the Cu seed film 114.
  • The wafer 112 is held face-down by the wafer holder 103, so as to downwardly direct the surface having the photoresist 115 patterned thereon. The wafer holder 103 and the wafer 112 are brought down to and placed on the contact portion 110, and allowed to contact with the plating solution jetted from the plating solution jetting port 106. When voltage is applied by the power source 111, so as to define the wafer 112 which is in contact with the contact portion 110, as a cathode, and the Ni anode 105 as an anode, Ni deposits on the surface of the wafer 112 in the portion where the Cu seed film 114 is exposed, and Ni dissolves out from the surface of the Ni anode 105.
  • In this embodiment, the upper limit of average grain size of the Ni anode is 10 μm or smaller, and more preferably 3 μm or smaller. Although the lower limit of the average grain size of the Ni anode is not specifically limited, it is preferably 0.1 μm or larger.
  • The average grain size of the Ni anode may be calculated typically according to the procedures below. First, a clean section of an anode is produced using an FIB (focused ion beam) apparatus. An image of this section is taken by a SIM (scanning ion microscope). The number of grains per unit area is then counted on the SIM image. The counted number of grains is divided by the unit area to obtain the average grain size.
  • Since the conventionally used Ni anode has a large average grain size and consequently has only a small ratio of grain boundary, it has the slow rate of dissolution. As a consequence, the Ni anode has been likely to produce Ni oxide or Ni hydroxide, and has been likely to be passivated. In contrast, the Ni anode used for the Ni plating apparatus of the present invention has an average grain size of as small as 10 μm or below. The Ni anode therefore has a large ratio of grain boundary, shows a large rate of dissolution, and is consequently less likely to produce Ni oxide nor Ni hydroxide. In other words, the Ni anode of this embodiment is less likely to be passivated. Thus, the current density and the rate of film formation can be prevented from degrading even when the wafers are successively processed under conditions of large current density.
  • The conditions of the large current density referred to herein means that the anode current density is equal to or more than 1.5 A/dm2. The Ni anode of this embodiment is less likely to be passivated even under the conditions of such large current density.
  • In the method of manufacturing a semiconductor device containing an electrolytic Ni plating process, the Ni anode of this embodiment may be used. By using the Ni anode having an average grain size of 10 μm or smaller as an anode in the plating process, the passivation of the surface of the Ni anode can be suppressed, and thereby a stable Ni plating film may be provided.
  • As described in the above, the lowering in the rate of film formation can be prevented, even when the wafers are successively processed under conditions of large current density. As a consequence, a stable Ni plating film can be provided. Thus, this embodiment contributes to improvement in quality, and to maintenance of stable production capacity.
  • The present invention will be explained into further details, referring to a specific Example.
  • EXAMPLE Example 1
  • Using an electrolytic Ni plating apparatus provided with the Ni anode having an average grain size of 10 μm or smaller, the wafers were successively processed under conditions of large current density. The average grain size of the Ni anode was calculated as follows. First, a clean section of the anode was produced using an FIB (focused ion beam) apparatus, and an image of this section is taken by a SIM (scanning ion microscope). FIG. 3 shows a SIM image of the Ni anode of this Example.
  • Mean grain area S can be obtained by dividing the unit area by the number of grains. In the SIM image of the Example, the number of grains per unit area was counted. The mean grain area S was obtained by dividing the unit area by the counted number of grains. Next, in order to convert the area into length, the grain was approximated by a circle, to thereby calculate the average grain size L. The average grain size L is calculated by the equation below:

  • L=2*√{square root over ( )}(S/n)
  • (where, L represents average grain size, and S represents mean grain area).
  • By calculation using the equation above, the average grain size L was 0.8 μm.
  • FIG. 4 is a graph showing relations between the number of runs of wafer processing and thickness of the Ni plating film. In the graph, maximum values, minimum values, and average values of the Ni plating film were shown for every number of runs of wafer processing. It was found that the Ni anode was not passivated even under successive processing of wafers under conditions of large current density, or in other words, even for the case where the Ni anode was placed under high potential for a long duration of time. Accordingly, the current efficiency was not degraded, and consequently also the rate of film formation was not degraded. From the graph in FIG. 4, the thickness of the film did not change even after the number of runs of wafer processing increased.
  • Comparative Example 1
  • The wafers were successively processed under the same conditions with Example 1, except that an electrolytic Ni plating apparatus provided with a Ni anode having an average grain size of 15 μm was used. The average grain size was calculated by the same procedure as in Example 1. FIG. 6 is a SIM image of the Ni anode of this Comparative Example.
  • FIG. 7 is a graph showing relations between the number of runs of wafer processing and thickness of the Ni plating film, when the wafers were successively processed under conditions of large current density. As a result of passivation of the surface of the Ni anode, the current efficiency gradually decreased, and thereby the rate of film formation decreased. It is obvious from FIG. 7 that film thickness gradually decreased.
  • Example 1 was largely improved in the rate of film formation as compared with Comparative Example 1. By reducing the average grain size of the Ni anode of the Ni plating apparatus of Example 1 to equal to or smaller than 10 μm, as described in the above, the Ni anode became less likely to produce Ni oxide or Ni hydroxide. Thus, the passivation was prevented, even when the wafers were successively processed under conditions of large current density. Since the passivation was suppressed, the lowering in the current efficiency and in the rate of film formation was avoided. As a consequence, the Example 1 successfully achieved stable provision of Ni plating film.
  • Also for the case where the electrolytic Ni plating apparatus provided with the Ni anode having an average grain size of 8 μm was used, it was confirmed that the rate of film formation was not lowered and the passivation was suppressed when successive processing of the wafers was carried out as described in Example 1.
  • Although the present invention has been explained based on the embodiments and Example, they are merely examples of the present invention, allowing adoption of various configurations other than those described in the above.
  • It is apparent that the present invention is not limited to the above embodiment, that may be modified and changed without departing from the scope and spirit of the invention.

Claims (5)

1. An electrolytic Ni plating apparatus provided with a nickel (Ni) anode having an average grain size of 10 μm or smaller.
2. The electrolytic Ni plating apparatus as claimed in claim 1,
wherein said average grain size is 3 μm or smaller.
3. A Ni anode for electrolytic Ni plating having an average grain size of 10 μm or smaller.
4. A method of manufacturing a semiconductor device comprising an electrolytic Ni plating process,
wherein, in said electrolytic Ni plating process, a Ni anode having an average grain size of 10 μm or smaller is used as an anode.
5. A semiconductor device manufactured using the electrolytic Ni plating apparatus described in claim 1.
US12/021,357 2007-01-29 2008-01-29 Electrolytic ni plating apparatus and method of manufacturing semiconductor device Abandoned US20080314742A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007017703A JP2008184637A (en) 2007-01-29 2007-01-29 ELECTROLYTIC Ni PLATING APPARATUS AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
JP2007-017703 2007-01-29

Publications (1)

Publication Number Publication Date
US20080314742A1 true US20080314742A1 (en) 2008-12-25

Family

ID=39727879

Family Applications (1)

Application Number Title Priority Date Filing Date
US12/021,357 Abandoned US20080314742A1 (en) 2007-01-29 2008-01-29 Electrolytic ni plating apparatus and method of manufacturing semiconductor device

Country Status (5)

Country Link
US (1) US20080314742A1 (en)
JP (1) JP2008184637A (en)
KR (1) KR20080071075A (en)
CN (1) CN101307482A (en)
TW (1) TW200844265A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130112563A1 (en) * 2011-11-04 2013-05-09 Integran Technologies Inc. Flow-through consumable anodes

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9404194B2 (en) 2010-12-01 2016-08-02 Novellus Systems, Inc. Electroplating apparatus and process for wafer level packaging
US9534308B2 (en) 2012-06-05 2017-01-03 Novellus Systems, Inc. Protecting anodes from passivation in alloy plating systems

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050000821A1 (en) * 2001-11-16 2005-01-06 White Tamara L Anodes for electroplating operations, and methods of forming materials over semiconductor substrates

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS533904A (en) * 1976-06-30 1978-01-14 Sumitomo Metal Mining Co Method of manufacturing nickel anode for electroplating
JP3985130B2 (en) * 2001-08-22 2007-10-03 三菱マテリアル株式会社 High purity Ni alloy anode material for electrolytic Ni plating showing high plating yield
JP3895638B2 (en) * 2002-05-24 2007-03-22 株式会社荏原製作所 Method for forming tin-silver-copper solder alloy, lead-free bump using the alloy, and method for manufacturing semiconductor element

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050000821A1 (en) * 2001-11-16 2005-01-06 White Tamara L Anodes for electroplating operations, and methods of forming materials over semiconductor substrates

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130112563A1 (en) * 2011-11-04 2013-05-09 Integran Technologies Inc. Flow-through consumable anodes
US9249521B2 (en) * 2011-11-04 2016-02-02 Integran Technologies Inc. Flow-through consumable anodes
US9970120B2 (en) 2011-11-04 2018-05-15 Integran Technologies Inc. Porous, flow-through consumable anodes for use in selective electroplating

Also Published As

Publication number Publication date
JP2008184637A (en) 2008-08-14
CN101307482A (en) 2008-11-19
KR20080071075A (en) 2008-08-01
TW200844265A (en) 2008-11-16

Similar Documents

Publication Publication Date Title
JP3462970B2 (en) Plating apparatus and plating method
JP6585434B2 (en) Plating method
KR102092416B1 (en) Cleaning electroplating substrate holders using reverse current deplating
US20120325671A2 (en) Electroplated lead-free bump deposition
US20220018036A1 (en) Low temperature direct copper-copper bonding
US20070045120A1 (en) Methods and apparatus for filling features in microfeature workpieces
CN1337064A (en) Method for galvanically forming conductor structures of high-purity copper in the production of integrated circuits
WO2007095439A2 (en) Electrochemical etching of circuitry for high density interconnect electronic modules
US8691597B2 (en) Method for manufacturing a semiconductor device including application of a plating voltage
KR102061026B1 (en) Plating method
KR102067001B1 (en) Electroplating method and electroplating device
US20080314742A1 (en) Electrolytic ni plating apparatus and method of manufacturing semiconductor device
KR101657460B1 (en) 2 2-22 - Tin silver plating bath using 2 or 2-22
US20080217183A1 (en) Electropolishing metal features on a semiconductor wafer
KR101014839B1 (en) Electrochemical polishing and plating method for manufacturing of through via and bumps in 3D SiP
US20040231978A1 (en) Electrode attachment to anode assembly
JP2005290444A (en) Golden electrolytic stripping liquid and electrolytic stripping method using the same
US20070080066A1 (en) Plating apparatus and manufacturing process for semiconductor device
JP2006291289A (en) Apparatus and method for producing semiconductor device
JP2016184695A (en) Bump electrode manufacturing method
JP3606795B2 (en) Jet type bump forming equipment
Kim et al. High rate electrodeposition of near-eutectic PbSn solders
JP2015198193A (en) Plating method for solder bump and method of manufacturing bump electrode
TWI406976B (en) Tin-silver solder bumping in electronics manufacture
JPH09219404A (en) Formation of bump electrode

Legal Events

Date Code Title Description
AS Assignment

Owner name: NEC ELECTRONICS CORPORATION, JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:TACHIBANA, HIROAKI;REEL/FRAME:020430/0988

Effective date: 20071226

AS Assignment

Owner name: RENESAS ELECTRONICS CORPORATION, JAPAN

Free format text: CHANGE OF NAME;ASSIGNOR:NEC ELECTRONICS CORPORATION;REEL/FRAME:025235/0423

Effective date: 20100401

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION

AS Assignment

Owner name: MICROWIRE, LLC, KANSAS

Free format text: SECURITY INTEREST;ASSIGNOR:TSI TECHNOLOGIES LLC;REEL/FRAME:037949/0799

Effective date: 20151201