US20070187827A1

US20070187827A1 - Semiconductor package, stack package using the same package and method of fabricating the same

Info

Publication number: US20070187827A1
Application number: US11/586,615
Authority: US
Inventors: Jong-Ung Lee; Jun-Young Lee; Jung-hyeon Kim; Min-Jung Kim
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 2005-10-27
Filing date: 2006-10-26
Publication date: 2007-08-16
Also published as: US8040975B2; KR100652440B1; US20080285677A1

Abstract

A semiconductor package may include a substrate. A conductive bump may be provided on a bottom surface of the substrate. A semiconductor chip may be provided on a top surface of the substrate. A sealing material may seal the semiconductor chip on the top of the substrate. A first conductive adhesive may be provided on a top surface of the sealing material. A second conductive adhesive may be provided on a side surface of the substrate and a side surface of the sealing material.

Description

PRIORITY STATEMENT

This application claims the benefit of Korean Patent Application No. 10-2005-0101755, filed on Oct. 27, 2005, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.

BACKGROUND

1. Field of the Invention
Example embodiments of the present invention relate to a semiconductor package, and more particularly, to a semiconductor package that may be implemented in a stack package, a stack package using the same, and a method that may be implemented to fabricate the stack package.
2. Description of the Related Art
A semiconductor package may be molded using an epoxy molding compound (EMC), for example, that may seal and/or protect a semiconductor chip with micro-circuits. An external terminal of the semiconductor chip may be electrically connected to the PCB through a wire, for example.
Numerous attempts may have been pursued to miniaturize semiconductor packages.
The components of a semiconductor package may be disposed close to each other and/or provided in a group. If numerous semiconductor chips are implemented, then various structures may be provided to reduce a space therebetween. Conventional structures may include a chip stack package and a stack package. In the chip stack package, a plurality of semiconductor chips may be implemented in an individual package. In the stack package, two or more unit semiconductor packages may be stacked together.
FIG. 1 is a schematic sectional view of a conventional chip stack package. Here, a conductive bump 40 may be provided on a bottom of a PCB 10. A plurality of semiconductor chips 20 may be stacked on a top of the PCB 10. The semiconductor chips 20 may be sealed using a sealing material 30 (e.g., EMC). Although the chip stack package is generally thought to provide acceptable performance, it is not without shortcomings. For example, the chips 20 may be damaged during a stacking process, thereby reducing a production yield.
A chip scale package (CSP) may provide a reduced package size and maintain the characteristics of a bare chip in a package state. A fine ball-grid array (FBGA) package is one example of a CSP.
FIG. 2A is a schematic sectional view of a conventional stack package. Here, the stack package may include a second unit semiconductor package B that may be stacked on a first unit semiconductor package A. The first and the second unit semiconductor packages may include PCBs 10 and 10 a, sealing materials 30 and 30 a sealing a single chip (not shown), and conductive bumps 40. The first and the second unit semiconductor packages A and B (including the chips) may become warped during a stacking process (for example), as shown in phantom. Such warp may cause a defective adhesion of the conductive bumps 40 (e.g., non-wet) located within the stacked structure.
FIG. 2B is a sectional view of another conventional stack package. The structure of FIG. 2B may be stronger than the structure illustrated in FIG. 2A. As shown, a substrate 80 may be disposed between the first unit semiconductor package A and the second unit semiconductor package B. The substrate 80 may reduce the package warp that might otherwise occur. A via hole (not shown) may be provided on the substrate 80. The unit packages A and B may be electrically connected to each other through a post that may be provided in the via hole. However, the structure shown in FIG. 2 b may be difficult to manufacture and/or involve cumbersome processes.
In the stack packages in FIGS. 2A and 2B, the sealing materials 30 and 30 a may be provided on only a portion of the surface of the PCB that supports the chip. Further, the location of the conductive bumps 40 may be somewhat limited to the extent that the conductive bumps 40 may be positioned laterally outward of the sealing materials 30 and 30 a to facilitate stacking.

SUMMARY

According to an example, non-limiting embodiment, a semiconductor package may include a substrate. A conductive bump may be provided on a bottom surface of the substrate. A semiconductor chip may be provided on a top surface of the substrate. A sealing material may seal the semiconductor chip. A first conductive adhesive may be provided on a top surface of the sealing material. A second conductive adhesive may be provided on a side surface of the printed circuit board and a side surface of the sealing material.
According to another example, non-limiting embodiment, a method of fabricating a stack package may involve providing a frame having a top surface that may support a semiconductor chip and a sealing material that may seal the semiconductor chip. A first conductive adhesive may be provided on a top surface of the sealing material. A conductive bump may be provided on a bottom surface of the frame. A first semiconductor package may be separated from the frame. A second conductive adhesive may be provided on a side surface of the first semiconductor package to electrically connect the first conductive adhesive with the conductive bump.

BRIEF DESCRIPTION OF THE DRAWINGS

Example, non-limiting embodiments of the present invention will be described with reference to the attached drawings.
FIG. 1 is a sectional view of a conventional chip stack package.
FIGS. 2A and 2B are sectional views of conventional stack packages.
FIGS. 3A and 3B are a plan view and a side view, respectively, of a semiconductor package according to an example, non-limiting embodiment of the present invention.
FIG. 4 is a side view of a stack package according to another example, non-limiting embodiment of the present invention.
FIG. 5 is a side view of stack package according to another example, non-limiting embodiment of the present invention.
FIGS. 6A through 6F are schematic views of a method that may be implemented to manufacture the stack package of FIG. 4.
The drawings are provided for illustrative purposes only and are not drawn to scale. The spatial relationships and relative sizing of the elements illustrated in the various embodiments may be reduced, expanded and/or rearranged to improve the clarity of the figure with respect to the corresponding description. The figures, therefore, should not be interpreted as accurately reflecting the relative sizing or positioning of the corresponding structural elements that could be encompassed by an actual device manufactured according to example embodiments of the invention. Like reference numerals in the drawings denote like elements, and thus their description may be omitted.

DETAILED DESCRIPTION OF EXAMPLE, NON-LIMITING EMBODIMENTS

Example, non-limiting embodiments of the present invention will be described with reference to the accompanying drawings. The invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, the disclosed embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art.
Well-known structures and processes are not described or illustrated in detail to avoid obscuring the present invention.
An element is considered as being mounted (or provided) “on” another element when mounted (or provided) either directly on the referenced element or mounted (or provided) on other elements overlaying the referenced element. Throughout this disclosure, spatial terms such as “upper,” “lower,” “above” and “below” (for example) are used for convenience in describing various elements or portions or regions of the elements as shown in the figures. These terms do not, however, require that the structure be maintained in any particular orientation.
FIGS. 3A and 3B are a plan view and a side view, respectively, of a semiconductor package 1A according to an example, non-limiting embodiment of the present invention.
Referring to FIG. 3A, a first conductive adhesive 500 may be provided on a top surface of a sealing material 300. The first conductive adhesive 500 may include conductive bump lands 510 and connecting portions 520. As shown, the connecting portions 520 may extend between the conductive bump lands 510 and/or may extend from a conductive bump land 510 up to a side surface of the sealing material 300. By way of example only, the first conductive adhesive 500 may be provided via a screen printing process with a printable adhesive.
In this example embodiment, the conductive bump lands 510 may have a circular shape and the connecting portions 520 may have a rectangular shape. In alternative embodiments, the conductive bump lands 510 and the connecting portions 520 may have numerous and varied shapes.
FIG. 3B is a side view of the semiconductor package 1A illustrated in FIG. 3A. As shown, the sealing material 300 may be provided on a top surface of a PCB 100. The sealing material 300 may cover the entire top surface of the PCB 100, which may support a chip (not shown). In alternative embodiments, the sealing material 300 may cover only a portion of the top surface of the PCB 100.
A conductive bump 400 may be provided on a conductive bump land 410 that may be provided on a bottom surface of the PCB 100. By way of example only, the conductive bump 400 may be solder ball.
A second conductive adhesive 600 may electrically connect the first conductive adhesive 500 with the conductive bump land 410. The second conductive adhesive 600 may extend along a side surface of the PCB 100 and a side surface of the sealing material 300. By way of example only, the second conductive adhesive 600 may have a ball-stacked shape, as illustrated in FIG. 3B. The second conductive adhesive 600 may be fabricated using a jettable adhesive. A size of the balls in the ball-stack may have a diameter of 50 μm, for example.
FIG. 4 is a side view of a stack package according to another example, non-limiting embodiment of the present invention. The stack package may implement the semiconductor package 1A of FIGS. 3A and 3B. Referring to FIG. 4, the stack package may include a conventional semiconductor package 2B that may be stacked on the semiconductor package 1A. The conventional semiconductor package 2B may include a PCB 100 a, a conductive bump land 410 a and a conductive bump 400 a on a bottom of the PCB 100 a, and a sealing material 300 a sealing a chip (not shown) on the PCB 100 a.
The conductive bumps 400 a of the conventional semiconductor package 2B may be attached to the conductive bump lands 510 of the first conductive adhesive 500 in the semiconductor package 1A. A marking for package information (for example) may be provided on a top surface of the sealing material 300 a in the conventional semiconductor package 2B.
The conventional semiconductor package 2B may be connected electrically with the semiconductor package 1A through the first conductive adhesive 500 and the second conductive adhesive 600 of the semiconductor package 1A. In this way, conventional semiconductor packages 2B (without modifications) may be suitably implemented in the stack package. Additionally, the sealing materials 300 and 300 a may be provided on an entire surface of the PCBs 100 and 100 a. In this way, a conventional packaging processes (without modifications) may be suitably implemented. Also, the occurrence of a defective contact of the conductive bump that may occur as a result of package warp may be reduced.
FIG. 5 is a side view of stack package according to another example, non-limiting embodiment of the present invention. Here, the stack package may implement two semiconductor packages of FIGS. 3A and 3B. Referring to FIG. 5, a semiconductor package 2A may be stacked on the semiconductor package 1A. A conventional semiconductor package 3B may be stacked on the semiconductor package 2A. The conventional semiconductor package 3B shown in FIG. 5 may have the same structure as the conventional semiconductor package 2B shown in FIG. 4.
The semiconductor packages 1A and 2A may have the same structure as that shown in FIGS. 3A and 3B. For example, the semiconductor package 2A may include a PCB 100 b, a conductive bump 400 b and a conductive bump land 410 b on a bottom of the PCB 100 b, a sealing material 300 b on a top of the PCB 100 b, a first conductive adhesive 500 b on the top surface of the sealing material 300 b, and a second conductive adhesive 600 b on a side surface of the PCB 100 b and the sealing material 300 b.
This example embodiment may implement a three-story stack package that may include two semiconductor packages having the structure shown in FIGS. 3A and 3B. In alternative embodiments, the stack package may implement more than two semiconductor packages having the structure shown in FIGS. 3A and 3B.
FIGS. 6A through 6F are schematic views of a method that may be implemented to manufacture the stack package of FIG. 4.
Referring to FIG. 6A, a package may include a sealing material 350 that may be provided on a PCB 150, which may serve as a frame. A printing mask 700 may be provided on the sealing material 350. A first conductive adhesive 500 a may be spread (along the direction of the arrow) and pressed through the printing mask 700 using a blade 710. Such processes may be carried out using screen printing techniques that are well known in this art. In this example embodiment, the first conductive adhesive 500 a may be a printable adhesive. As a result of screen printing, the first conductive adhesive 550 may be provided on each of the sealing materials 350, as shown in FIG. 6C.
Referring to FIG. 6B, a marking process, which may be a general packaging process, may be omitted. A conductive bump 400 may be provided on a conductive bump land (not shown) on a bottom surface of the PCB 150. The printing mask 700 may be removed.
Referring to FIG. 6C, each sealing material 350 may seal a plurality of chips (not shown) that may be provided on the PCB 150. The structure may be separated (along the phantom lines) into unit semiconductor packages by performing a singulation process. Singulation may be performed by sawing, for example. The separated semiconductor packages may be tested.
FIG. 6D is a perspective view of a unit semiconductor package. A conductive bump land 410 and a conductive bump (not shown) may be provided on a bottom surface of the PCB 100. The sealing material 300 (which may seal a chip (not shown)) may be provided on a top surface of the PCB 100. The first conductive adhesive 500 (inclusive of conductive bump lands 510 and connecting portions 520) may be provided on a top surface of the sealing material 300.
Referring to FIG. 6E, a second conductive adhesive 600 electrically connecting the first conductive adhesive 500 with the conductive bump land 410 may be provided on a side surface of the unit semiconductor package of FIG. 6D. By way of example only, the second conductive adhesive 600 may be provided and stacked in a ball shape with a diameter of 50 μm by jetting. In this example embodiment, the second conductive adhesive 600 may be a material suitable for jetting.
Referring to FIG. 6F, a flux dotting process may be performed on the conductive bump lands 510 of the first conductive adhesive 500 to remove a foreign substance. The conventional semiconductor package 2B may be stacked on the semiconductor package 1A. The conductive bump 400 a of the conventional semiconductor package may be adhered to the conductive bump land 510 of the first conductive adhesive 500. The conductive bump 400 a of the conventional semiconductor package 2B may be melted and adhered through an infrared re-flow (IR re-flow) process, for example. A marking for package information may be provided on the sealing material 300 a of the conventional semiconductor package 2B. A two-story stack package may be provided by stacking the conventional semiconductor package 2B on the semiconductor package 1A. In alternative embodiments, a three-story (or more) stack package may be provided by stacking more than two semiconductor packages that may have a structure that may be the same as that of the semiconductor package 1A.
The second conductive adhesive 600 (which may serve as a wiring) may be provided on a side surface of the semiconductor package, conventional semiconductor packages (without modifications) may be stacked.
The sealing material may be provided on an entire surface of the PCB. As a, result, a conventional packaging process (without modification) may be suitably implemented. Also, the occurrence of a defective contact of the conductive bump may be reduced.
The present invention has been shown and described with reference to example, non-limiting embodiments. It will be understood by those of ordinary skill in the art that various changes in form and details may be implemented without departing from the spirit and scope of the present invention as defined by the following claims.

Claims

1. A semiconductor package comprising:

a substrate;

a conductive bump provided on a bottom surface of the substrate;

a semiconductor chip provided on a top surface of the substrate;

a sealing material provided on the semiconductor chip;

a first conductive adhesive provided on a top surface of the sealing material; and

a second conductive adhesive provided on a side surface of the substrate and a side surface of the sealing material.

2. The semiconductor package of claim 1, wherein the first conductive adhesive is a printable adhesive.

3. The semiconductor package of claim 1, wherein the second conductive adhesive is a jettable adhesive.

4. The semiconductor package of claim 1, wherein the second conductive adhesive is fabricated by jetting the second conductive adhesive onto a side surface of the substrate and a side surface of the sealing material.

5. The semiconductor package of claim 4, wherein the second conductive adhesive has a stacked-ball shape, each ball in the stack having a diameter of 50 μm.

6. The semiconductor package of claim 1, wherein the first conductive adhesive includes a conductive bump land.

7. A stack package comprising:

a first semiconductor package according to claim 1; and

a second semiconductor package stacked on the first semiconductor package.

8. The stack package of claim 7, wherein the first conductive adhesive includes a conductive bump land attached to the second semiconductor package.

9. The stack package of claim 8, wherein the second semiconductor package includes a second printed circuit board with a second conductive bump provided on a bottom of the second semiconductor package, and

wherein the second conductive bump is attached to the conductive bump land of the first conductive adhesive.

10. The stack package of claim 9, wherein the second semiconductor package includes

a second sealing material sealing a semiconductor chip provided on a top surface of the second printed circuit board, and

a marking for package information is provided on a top surface of the second sealing material.

11. The stack package of claim 7, further comprising at least one semiconductor package with the same structure as the first semiconductor package, the at least one semiconductor package provided between the first semiconductor package and the second semiconductor package.

12. The package of claim 1, wherein the substrate is printed circuit board.

13. The package of claim 1, wherein the second conductive adhesive electrically connects the conductive bump with the first conductive adhesive.

14. A method of fabricating a stack package comprising:

providing a frame having a top surface supporting a semiconductor chip and a sealing material sealing the semiconductor chip;

providing a first conductive adhesive on a top surface of the sealing material;

providing a conductive bump on a bottom surface of the frame;

separating a first semiconductor package from the frame;

providing a second conductive adhesive on a side surface of the first semiconductor package to electrically connect the first conductive adhesive with the conductive bump.

15. The method of claim 14, further comprising screen printing the first conductive adhesive onto the sealing material.

16. The method of claim 14, further comprising jetting the second conductive adhesive onto a side surface of the first semiconductor package.

17. The method of claim 16, wherein jetting the second conductive adhesive provides a stacked-ball shape, each ball in the stack having a diameter of 50 μm.

18. The method of claim 14, further comprising:

attaching a second semiconductor package to a conductive bump land of the first conductive adhesive of the first semiconductor package.

19. The method of claim 18, wherein the second semiconductor package includes a second printed circuit board with a second conductive bump provided on a bottom of the second semiconductor package, and

wherein attaching of the second semiconductor package includes

performing a flux dotting process on the conductive bump land, and

performing an infrared re-flow process to attach the second conductive bump to the conductive bump land.

20. The method of claim 18, further comprising:

attaching the first semiconductor package to the top of at least one additional semiconductor package having the same structure as that of the first semiconductor package.