US20070170501A1 - MOS Transistors Including Silicide Layers on Source/Drain Regions - Google Patents

MOS Transistors Including Silicide Layers on Source/Drain Regions Download PDF

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US20070170501A1
US20070170501A1 US11/693,317 US69331707A US2007170501A1 US 20070170501 A1 US20070170501 A1 US 20070170501A1 US 69331707 A US69331707 A US 69331707A US 2007170501 A1 US2007170501 A1 US 2007170501A1
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silicide layer
layer
gate electrode
region
doped region
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US11/693,317
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Young-ki Lee
Heon-jong Shin
Hwa-sook Shin
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Assigned to SAMSUNG ELECTRONICS CO., LTD. reassignment SAMSUNG ELECTRONICS CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: LEE, YOUNG-KI, SHIN, HEON-JONG, SHIN, HWA-SOOK
Publication of US20070170501A1 publication Critical patent/US20070170501A1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6653—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using the removal of at least part of spacer, e.g. disposable spacer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's

Definitions

  • the present invention relates to Metal-Oxide-Semiconductor (MOS) transistors and, more specifically, to MOS transistors having silicided source/drain regions.
  • MOS Metal-Oxide-Semiconductor
  • Salicide Self-aligned silicide processes have been widely used to lower resistances of gate and source/drain regions of transistors.
  • a Salicide process is a method of simultaneously forming a silicide layer on a polysilicon gate electrode and on an active region of a silicon substrate.
  • a Salicide process can lower the contact resistance and the sheet resistance.
  • FIG. 1 is a cross-sectional view illustrating a conventional MOS transistor having a lightly doped drain (LDD) region.
  • field regions 4 are formed on a semiconductor substrate 2 to define an active region therebetween.
  • a gate stack including a gate insulation layer 6 , a gate electrode 8 , and a gate silicide layer 16 a, are formed on a predetermined region of the active region.
  • a gate spacer 12 is formed on both sidewalls of the gate stack.
  • a lightly doped region 10 is formed in the semiconductor substrate 2 under the gate spacer 12 by, for example, implanting ions into the substrate 2 prior to formation of the gate spacer 12 .
  • a heavily doped region 14 is formed in the active region of the semiconductor substrate 2 adjacent to the gate spacer 12 .
  • a silicide layer 16 b is formed on a surface of the heavily doped region 14 .
  • the lightly doped region 10 can be self-aligned to the gate stack between a channel region that underlies the gate stack and the heavily doped region 14 .
  • the lightly doped region 10 allows an electric field between the source/drain region and the channel region to be decreased which may prevent or reduce the rapid acceleration of carriers emitted from the source (i.e., hot carrier effects).
  • Embodiments according to the present invention can provide MOS transistors including silicide layers.
  • a MOS transistor can include a substrate and a field region formed at the semiconductor substrate to define an active region.
  • An I-shaped spacer is on sidewalls of the gate electrode.
  • a lightly doped region and a heavily doped region are on the semiconductor substrate on sides of the gate electrode.
  • a first silicide layer is on a surface of the heavily doped region and a second silicide layer is on the lightly doped region between the I-shaped spacer and the first silicide layer.
  • a MOS transistor includes a first silicide layer having a first thickness on a source/drain region self-aligned to a sidewall spacer of a gate electrode and a second silicide layer having a second thickness, less than the first thickness, on the source/drain region adjacent to the first silicide layer.
  • FIG. 1 is a cross-sectional view illustrating a conventional MOS transistor with an LDD structure.
  • FIG. 2 is a cross-sectional view illustrating MOS transistors including a silicide layer on a lightly doped region according to embodiments of the present invention.
  • FIGS. 3A to 3 H are cross-sectional views illustrating methods of fabricating MOS transistors including an extended silicide layer on a source/drain region according to embodiments of the present invention.
  • FIGS. 4A to 4 H are cross-sectional views illustrating methods of fabricating MOS transistors including an extended silicide layer on a source/drain region according to embodiments of the present invention.
  • relative terms such as “beneath”, may be used herein to describe one element's relationship to another element as illustrated in the Figures. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures. For example, if the device in the Figures is turned over, elements described as “below” other elements would then be oriented “above” the other elements. The exemplary term “below”, can therefore, encompasses both an orientation of above and below.
  • first and second are used herein to describe various regions, layers and/or sections, these regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one region, layer or section from another region, layer or section. Thus, a first region, layer or section discussed below could be termed a second region, layer or section, and similarly, a second region, layer or section may be termed a first region, layer or section without departing from the teachings of the present invention.
  • Like numbers refer to like elements throughout.
  • FIG. 2 illustrates a configuration of a MOS transistor in which a silicide layer is formed on a surface of a lightly doped region according to embodiments of the present invention.
  • a field region 22 is formed in a substrate 20 to define an active region.
  • a gate insulation layer 24 is formed on the active region and a gate electrode 26 is formed on the gate insulation layer 24 .
  • a lightly doped region 28 is formed in the substrate 20 self-aligned to the gate electrode 26 .
  • An I-shaped spacer 35 is formed on both sidewalls of the gate electrode 26 .
  • a heavily doped region 40 is formed in the substrate 20 on both sides of and adjacent to the gate electrode 26 .
  • a first silicide layer 42 a is formed on a surface of the heavily doped region 40 .
  • a gate silicide layer 42 b is formed on the gate electrode 26 .
  • a second silicide layer 46 is formed on a portion of the lightly doped region 28 . In some embodiments according to the present invention, the second silicide layer 46 is formed thinner than the first silicide layer 42 a.
  • the foregoing structure can allow formation of the silicide layer on the surface of the lightly doped region 28 .
  • the resistance of contacts thereon may be reduced to improve the speed of the device.
  • the I-shaped spacer 35 can prevent an electric short between the gate electrode 26 and the impurity regions 28 and 40 .
  • a gate spacer used to form an LDD region in a conventional structure may prevent the formation of silicide on the LDD region which could prevent further reductions in the resistance.
  • the length of the gate electrode may be shortened as the associated design rule for the device is reduced, using conventional approaches it may be difficult to correspondingly increase the area of the silicide layer by reducing the width of the gate spacer 12 as to do so may promote lateral diffusion of impurities in the source/drain region.
  • FIGS. 3A to 3 H are cross-sectional views illustrating methods of fabricating MOS transistors including an extended silicide layer on a source/drain region according to embodiments of the present invention.
  • field regions 22 are formed on the substrate 20 to define an active region therebetween.
  • the substrate 20 is etched to form a trench that is filled with an insulating material.
  • the insulating material is polished using, for example CMP, to form the field regions 22 .
  • the conductive layer for the gate electrode can be formed of silicon germanium (SiGe), cobalt (Co), tungsten (W), titanium (Ti), nickel (Ni), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), and tungsten nitride (WN), in addition to impurity-doped polysilicon. Impurity ions are implanted into the active region at a low concentration using the gate electrode 26 and the field region 22 as an ion implantation mask, to form a lightly doped region 28 .
  • a thin insulation layer is formed on the substrate 20 and the gate electrode 26 .
  • the insulation layer is etched to form an insulating spacer 30 .
  • the insulating spacer 30 can be a silicon oxide layer.
  • the lightly doped region 28 can be formed after the insulating spacer 30 is formed, using for example, diffusion.
  • an inner insulation layer 32 and an outer insulation layer 38 are sequentially formed on the substrate.
  • the inner insulation layer 32 can be formed of a silicon oxide layer.
  • the outer insulation layer 38 can be formed of a first outer insulation layer 34 and a second outer insulation layer 36 .
  • the first and second outer insulation layers 34 are formed of materials having different etch rates.
  • the first outer insulation layer 34 can be a silicon nitride layer and the second outer insulation layer 36 can be a silicon oxide layer.
  • the first outer insulation layer 34 is thinner than the inner insulation layer 32 .
  • the inner and outer insulation layers 32 and 38 are patterned by dry etching using an anisotropic etch process, to form a gate spacer on the sidewalls of the insulating spacer 30 .
  • the gate spacer 39 includes the patterned inner insulation layer 32 and the patterned outer insulation layer 38 .
  • the patterned outer insulation layer 38 includes the patterned first outer insulation layer 34 and the patterned second outer insulation layer 36 .
  • the dry etching is carried out such that the inner insulation layer 32 is not completely etched so that a remaining portions has a thickness of about 50 Angstroms.
  • the heavily doped region 40 is formed by ion implantation using the gate electrode 26 , the insulating spacer 30 , the gate spacer 39 , and the field region 22 as an ion implantation mask.
  • the inner insulation layer 32 remaining on the substrate can provide a buffer layer during the high-concentration ion implantation process.
  • the patterned outer insulation layer 38 (constituting the gate spacer 39 ) is removed using a wet etch process, thereby forming an L-shaped spacer 33 of the insulating spacer 30 and the patterned inner insulation layer 32 .
  • the L-shaped spacer 33 includes an I-shaped portion adjacent to the sidewall of the gate electrode 26 and a projected portion that extends from a bottom (or base) of the I-shaped portion away from the sidewall of the gate electrode 26 .
  • the patterned second outer insulation layer 36 is removed using a buffered oxide etchant (BOE), whereas the patterned first outer insulation layer 34 is removed with a wet etching using a phosphoric acid (such as H 3 PO 4 ).
  • BOE buffered oxide etchant
  • the first outer insulation layer 34 can be thinner than the inner insulation layer 32 which may promote formation of the L-shaped spacer 33 to have the desired shape.
  • a thin layer of about 50 ⁇ ngstroms of the inner insulation layer 32 may remain on the substrate after the wet etching to act as a buffer layer to protect the substrate.
  • the remaining layer of the inner insulation layer 32 may also prevent wet etching of the projected portion at the base of the L-shaped spacer 33 .
  • a Salicide process is applied to a surface of the heavily doped region 40 and to a top of the gate electrode 26 , thereby forming a first silicide layer 42 a on the heavily doped region 40 and a gate silicide layer 42 b.
  • a silicide layer may not be formed on the gate electrode 26 depending on the material constituting the gate electrode 26 .
  • the first silicide layer 42 a and the gate silicide layer 42 b may be selected from the group consisting of cobalt (Co), titanium (Ti), nickel (Ni), tungsten (W), platinum (Pt), hafnium (Hf), and palladium (Pd).
  • cobalt Co
  • Ti titanium
  • Ni nickel
  • Pt platinum
  • Hf hafnium
  • palladium palladium
  • a wet cleaning process is carried out to remove a natural oxide layer on a surface of the heavily doped region 40 and on a surface of the gate electrode 26 .
  • a cobalt layer is deposited using, for example, sputtering.
  • a cobalt monosilicide (CoSi) is formed by a first thermal process. The first thermal process is carried out at a temperature in a range between about 400° C. and about 600° C. in a conventional rapid thermal annealer. This can cause a silicide reaction in regions where the cobalt contacts silicon.
  • the regions of the substrate having the silicide reaction are cleaned using a mixed solution of sulfuric acid (H 2 SO 4 ), oxygenated water (H 2 O 2 ), and water (H 2 O).
  • the unsilicided cobalt layer can be removed.
  • a second thermal process is carried out at a temperature of about 750° C. or higher. The second thermal process can promote the cobalt monosilicide (CoSi) to change phase to cobalt disilicide (CoSi 2 ) which can have a low resistivity.
  • the silicide layer may be formed using a one-step thermal process.
  • a cobalt layer can be formed and then annealed at about 750° C. or higher. Thereafter, a cleaning process is carried out to remove the unreacted metal, thereby forming the silicide layer.
  • the inner insulation layer 32 is at least partially removed using wet etching to remove the portion of the L-shaped spacer 33 that projects from the base, to expose a surface of the lightly doped region 28 . Therefore, the I-shaped spacer 35 remains on the sidewalls of the gate electrode 26 , but the portion of the L-shaped spacer 33 that projects from the base is removed.
  • the I-shaped spacer 35 may be formed of only the insulating spacer 30 or a combination of the insulating spacer 30 and a portion of the inner insulation layer 32 .
  • a thin metal layer 44 is formed on the gate electrode 26 , the sidewalls of the gate electrode 26 , and the substrate.
  • the metal layer 44 may be the same material described above as part of the Salicide process and may be formed by sputtering.
  • a natural silicide layer is formed via a natural reaction rather than via the thermal process described above.
  • the natural silicide layer can be formed, for example, by a thermodynamic reaction generated when two different materials are brought into proximity with one another. In particular, when two materials are brought into proximity with one another they may diffuse into each other and can mixed at an interface therebetween.
  • cobalt reacts on silicon at an interface therebetween and creates cobalt monosilicide (CoSi) layer having a thickness of about 30 ⁇ ngstroms.
  • a cleaning process is carried out to remove metal that did not react with the silicon substrate.
  • a thin second silicide layer 46 is formed on the exposed lightly doped region 28 . Furthermore, in the case of cobalt, cobalt monosilicide (CoSi) may be changed in phase to cobalt disilicide (CoSi 2 ) by a thermal process so as to lower resistance.
  • the second silicide layer 46 is thinner than the first silicide layer 42 a formed on the heavily doped region 40 . This is because if the second silicide layer 46 were too thick, the junction formed between the impurity regions 28 and 40 and the substrate 20 may be degraded thereby causing an increase in leakage current. Accordingly, the surface of the first silicide layer 42 a extends beyond the adjacent surface of the second silicide layer 46 .
  • the upper surface of the first silicide layer 42 a is higher than the adjacent upper surface of the second silicide layer 46 . Furthermore, the lower surface of the first silicide layer 42 a is lower than the adjacent lower surface of the second silicide layer 46 .
  • the I-shaped spacer 35 remaining on the sidewalls of the gate electrode 26 prevents an electric short between the gate electrode 26 and the impurity regions 28 and 40 due to the second silicide layer 46 .
  • FIGS. 4A to 4 H are cross-sectional views illustrating methods of fabricating MOS transistors having an extended silicide layer on a source/drain region according to other embodiments of the present invention.
  • the field regions 22 are formed on the semiconductor substrate 20 to define an active region therebetween.
  • An insulation layer and a conductive layer are formed on a surface of the substrate and patterned to form a gate insulation layer 24 and the gate electrode 26 .
  • Impurities are implanted, using the gate electrode 26 and the field region 22 as an ion implantation mask, into the active region at a low concentration to form a lightly doped region 28 .
  • an inner insulation layer 32 and an outer insulation layer 38 are sequentially formed on the surface of the substrate and on the gate electrode 26 .
  • the inner insulation layer 32 is a silicon oxide layer.
  • the outer insulation layer 38 includes a first outer insulation layer 34 and a second outer insulation layer 36 as disclosed above, for example, in reference to FIG. 3B .
  • the first and second outer insulation layers 34 and 36 are materials having different etch rates.
  • the first outer insulation layer 34 can be a silicon nitride layer
  • the second outer insulation layer 36 can be a silicon oxide layer.
  • the inner insulation layer 32 and the outer insulation layer 38 are patterned by dry etching using an anisotropic etch process, thereby forming a gate spacer 39 on the sidewalls of the gate electrode 26 .
  • the gate spacer 39 includes the patterned inner insulation layer 32 and the patterned outer insulation layer 38 .
  • the patterned outer insulation layer 38 includes the patterned first outer insulation layer 34 and the second outer insulation layer 36 .
  • the inner insulation layer 32 is not completely removed by the dry etch and a thin layer of about 50 ⁇ ngstroms may remain on the surface of the substrate.
  • a heavily doped region 40 is formed by ion implantation using the gate electrode 26 , the gate spacer 39 , and the field region 22 as an ion implantation mask.
  • the inner insulation layer 32 remaining on the substrate can serve as a buffer layer during the ion implantation.
  • the patterned outer insulation layer 38 constituting the gate spacer 39 is removed using a wet etch process.
  • the L-shaped spacer 32 includes I-shaped main portion and a projecting portion that extends from a bottom (or base) of the I-shaped main portion.
  • the L-shaped spacer 32 includes only the inner insulation layer 32 .
  • a Salicide process is applied to a surface of the heavily doped region 40 and to a top of the gate electrode 26 , to form a first silicide layer 42 a and a gate silicide layer 42 b.
  • the gate silicide layer may not be formed on the gate electrode 26 depending on the materials constituting the gate electrode 26 .
  • the L-shaped spacer 32 is dry etched to remove the portion of the L-shaped spacer 32 that projects from the base to expose a partial surface of the lightly doped region 28 and to form an I-shaped spacer 35 . Therefore, in some embodiments according to the present invention disclosed herein (such as in reference to FIG. 3F ), the etching process used to remove the projecting portion of the L-shaped spacer 32 is a dry etch process rather than a wet etch process. Furthermore, in the present embodiment according to the present invention, the insulating spacer disclosed in reference to other embodiments can be eliminated. Accordingly, if the wet etch process is applied, the L-shaped spacer may be wholly or partially removed. If the L-shaped spacer is wholly removed or the I-shaped spacer is thinly formed on the sidewalls of the gate electrode, a leakage current may be generated through the silicide layer between the gate electrode 26 and the impurity regions 28 and 40 .
  • a metal layer 44 is formed on the surface of the substrate including on at least a portion of the lightly doped region 28 .
  • the metal can react with the silicon in the exposed lightly doped region 28 .
  • the reaction between the substrate and the metal occurs naturally (i.e., without a thermal process being applied).
  • any metal that does not react with the silicon in the substrate is removed to form the thin second silicide layer 46 on the exposed lightly doped region 28 .
  • a resistance of a contact made to the lightly doped region 28 and the heavily doped region 40 can be reduced.
  • a thermal process can be performed after the second silicide layer 46 is formed to further reduce the resistance.
  • a silicide layer can be formed even at a lightly doped region. As a result, a resistance of a source/drain region may be reduced.

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Abstract

A MOS transistor can include a substrate and a field region formed at the semiconductor substrate to define an active region. An I-shaped spacer is on sidewalls of the gate electrode. A lightly doped region and a heavily doped region are on the semiconductor substrate on sides of the gate electrode. A first silicide layer is on a surface of the heavily doped region and a second silicide layer is on the lightly doped region between the I-shaped spacer and the first silicide layer.

Description

    RELATED APPLICATION
  • This application is a divisional of application Ser. No. 10/388,354 entitled Methods of Forming Silicide Layers on Source/Drain Regions of MOS Transistors, filed Mar. 13, 2003 and claims the benefit of Korean Patent Application No. 2002-17088, filed on Mar. 28, 2002, the disclosures of both are herein incorporated by reference in their entirety.
    • FIELD OF THE INVENTION
  • The present invention relates to Metal-Oxide-Semiconductor (MOS) transistors and, more specifically, to MOS transistors having silicided source/drain regions.
    • BACKGROUND
  • Self-aligned silicide (Salicide) processes have been widely used to lower resistances of gate and source/drain regions of transistors. Generally, a Salicide process is a method of simultaneously forming a silicide layer on a polysilicon gate electrode and on an active region of a silicon substrate. A Salicide process can lower the contact resistance and the sheet resistance.
  • FIG. 1 is a cross-sectional view illustrating a conventional MOS transistor having a lightly doped drain (LDD) region. Referring to FIG. 1, field regions 4 are formed on a semiconductor substrate 2 to define an active region therebetween. A gate stack, including a gate insulation layer 6, a gate electrode 8, and a gate silicide layer 16 a, are formed on a predetermined region of the active region. A gate spacer 12 is formed on both sidewalls of the gate stack. A lightly doped region 10 is formed in the semiconductor substrate 2 under the gate spacer 12 by, for example, implanting ions into the substrate 2 prior to formation of the gate spacer 12. A heavily doped region 14 is formed in the active region of the semiconductor substrate 2 adjacent to the gate spacer 12. A silicide layer 16 b is formed on a surface of the heavily doped region 14.
  • The lightly doped region 10 can be self-aligned to the gate stack between a channel region that underlies the gate stack and the heavily doped region 14. The lightly doped region 10 allows an electric field between the source/drain region and the channel region to be decreased which may prevent or reduce the rapid acceleration of carriers emitted from the source (i.e., hot carrier effects).
    • SUMMARY
  • Embodiments according to the present invention can provide MOS transistors including silicide layers. Pursuant to these embodiments a MOS transistor can include a substrate and a field region formed at the semiconductor substrate to define an active region. An I-shaped spacer is on sidewalls of the gate electrode. A lightly doped region and a heavily doped region are on the semiconductor substrate on sides of the gate electrode. A first silicide layer is on a surface of the heavily doped region and a second silicide layer is on the lightly doped region between the I-shaped spacer and the first silicide layer.
  • In some embodiments according to the invention, a MOS transistor includes a first silicide layer having a first thickness on a source/drain region self-aligned to a sidewall spacer of a gate electrode and a second silicide layer having a second thickness, less than the first thickness, on the source/drain region adjacent to the first silicide layer.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a cross-sectional view illustrating a conventional MOS transistor with an LDD structure.
  • FIG. 2 is a cross-sectional view illustrating MOS transistors including a silicide layer on a lightly doped region according to embodiments of the present invention.
  • FIGS. 3A to 3H are cross-sectional views illustrating methods of fabricating MOS transistors including an extended silicide layer on a source/drain region according to embodiments of the present invention.
  • FIGS. 4A to 4H are cross-sectional views illustrating methods of fabricating MOS transistors including an extended silicide layer on a source/drain region according to embodiments of the present invention.
    • DESCRIPTION OF EMBODIMENTS ACCORDING TO THE PRESENT INVENTION
  • The present invention now will be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.
  • In the drawings, the thickness of layers and regions are exaggerated for clarity. It will be understood that when an element such as a layer, region or substrate is referred to as being “on” another element, it can be directly on the other element or intervening elements may also be present.
  • Furthermore, relative terms, such as “beneath”, may be used herein to describe one element's relationship to another element as illustrated in the Figures. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures. For example, if the device in the Figures is turned over, elements described as “below” other elements would then be oriented “above” the other elements. The exemplary term “below”, can therefore, encompasses both an orientation of above and below.
  • It will be understood that although the terms first and second are used herein to describe various regions, layers and/or sections, these regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one region, layer or section from another region, layer or section. Thus, a first region, layer or section discussed below could be termed a second region, layer or section, and similarly, a second region, layer or section may be termed a first region, layer or section without departing from the teachings of the present invention. Like numbers refer to like elements throughout.
  • FIG. 2 illustrates a configuration of a MOS transistor in which a silicide layer is formed on a surface of a lightly doped region according to embodiments of the present invention. Referring to FIG. 2, a field region 22 is formed in a substrate 20 to define an active region. A gate insulation layer 24 is formed on the active region and a gate electrode 26 is formed on the gate insulation layer 24. A lightly doped region 28 is formed in the substrate 20 self-aligned to the gate electrode 26. An I-shaped spacer 35 is formed on both sidewalls of the gate electrode 26. A heavily doped region 40 is formed in the substrate 20 on both sides of and adjacent to the gate electrode 26. A first silicide layer 42 a is formed on a surface of the heavily doped region 40. A gate silicide layer 42 b is formed on the gate electrode 26. A second silicide layer 46 is formed on a portion of the lightly doped region 28. In some embodiments according to the present invention, the second silicide layer 46 is formed thinner than the first silicide layer 42 a.
  • The foregoing structure can allow formation of the silicide layer on the surface of the lightly doped region 28. Thus, the resistance of contacts thereon may be reduced to improve the speed of the device. The I-shaped spacer 35 can prevent an electric short between the gate electrode 26 and the impurity regions 28 and 40. In contrast to embodiments according to the present invention, a gate spacer used to form an LDD region in a conventional structure may prevent the formation of silicide on the LDD region which could prevent further reductions in the resistance. While the length of the gate electrode may be shortened as the associated design rule for the device is reduced, using conventional approaches it may be difficult to correspondingly increase the area of the silicide layer by reducing the width of the gate spacer 12 as to do so may promote lateral diffusion of impurities in the source/drain region.
  • Methods of fabricating embodiments according to the present invention will be described with reference to the drawings. FIGS. 3A to 3H are cross-sectional views illustrating methods of fabricating MOS transistors including an extended silicide layer on a source/drain region according to embodiments of the present invention.
  • Referring to FIG. 3A, field regions 22 are formed on the substrate 20 to define an active region therebetween. The substrate 20 is etched to form a trench that is filled with an insulating material. The insulating material is polished using, for example CMP, to form the field regions 22.
  • An insulation layer and a conductive layer for a gate electrode are formed on the substrate 20 and then patterned to form a gate insulation layer 24 and a gate electrode 26. The conductive layer for the gate electrode can be formed of silicon germanium (SiGe), cobalt (Co), tungsten (W), titanium (Ti), nickel (Ni), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), and tungsten nitride (WN), in addition to impurity-doped polysilicon. Impurity ions are implanted into the active region at a low concentration using the gate electrode 26 and the field region 22 as an ion implantation mask, to form a lightly doped region 28. In some embodiments according to the present invention, a thin insulation layer is formed on the substrate 20 and the gate electrode 26. The insulation layer is etched to form an insulating spacer 30. The insulating spacer 30 can be a silicon oxide layer. In some embodiments according to the present invention, the lightly doped region 28 can be formed after the insulating spacer 30 is formed, using for example, diffusion.
  • Referring to FIG. 3B, an inner insulation layer 32 and an outer insulation layer 38 are sequentially formed on the substrate. The inner insulation layer 32 can be formed of a silicon oxide layer. The outer insulation layer 38 can be formed of a first outer insulation layer 34 and a second outer insulation layer 36. In some embodiments according to the present invention, the first and second outer insulation layers 34 are formed of materials having different etch rates. For example, the first outer insulation layer 34 can be a silicon nitride layer and the second outer insulation layer 36 can be a silicon oxide layer. In some embodiments according to the present invention, the first outer insulation layer 34 is thinner than the inner insulation layer 32.
  • Referring to FIG. 3C, the inner and outer insulation layers 32 and 38 are patterned by dry etching using an anisotropic etch process, to form a gate spacer on the sidewalls of the insulating spacer 30. The gate spacer 39 includes the patterned inner insulation layer 32 and the patterned outer insulation layer 38. The patterned outer insulation layer 38 includes the patterned first outer insulation layer 34 and the patterned second outer insulation layer 36. In some embodiments according to the present invention, the dry etching is carried out such that the inner insulation layer 32 is not completely etched so that a remaining portions has a thickness of about 50 Angstroms.
  • The heavily doped region 40 is formed by ion implantation using the gate electrode 26, the insulating spacer 30, the gate spacer 39, and the field region 22 as an ion implantation mask. The inner insulation layer 32 remaining on the substrate can provide a buffer layer during the high-concentration ion implantation process.
  • Referring to FIG. 3D, the patterned outer insulation layer 38 (constituting the gate spacer 39) is removed using a wet etch process, thereby forming an L-shaped spacer 33 of the insulating spacer 30 and the patterned inner insulation layer 32. The L-shaped spacer 33 includes an I-shaped portion adjacent to the sidewall of the gate electrode 26 and a projected portion that extends from a bottom (or base) of the I-shaped portion away from the sidewall of the gate electrode 26.
  • In embodiments according to the present invention where the first outer insulation layer 34 is a silicon nitride layer and the patterned second outer insulation layer 36 is a silicon oxide layer, the patterned second outer insulation layer 36 is removed using a buffered oxide etchant (BOE), whereas the patterned first outer insulation layer 34 is removed with a wet etching using a phosphoric acid (such as H3PO4). As mentioned above, the first outer insulation layer 34 can be thinner than the inner insulation layer 32 which may promote formation of the L-shaped spacer 33 to have the desired shape.
  • In some embodiments according to the present invention, a thin layer of about 50 Ångstroms of the inner insulation layer 32 may remain on the substrate after the wet etching to act as a buffer layer to protect the substrate. The remaining layer of the inner insulation layer 32 may also prevent wet etching of the projected portion at the base of the L-shaped spacer 33.
  • Referring to FIG. 3E, a Salicide process is applied to a surface of the heavily doped region 40 and to a top of the gate electrode 26, thereby forming a first silicide layer 42 a on the heavily doped region 40 and a gate silicide layer 42 b. In some embodiments according to the present invention, a silicide layer may not be formed on the gate electrode 26 depending on the material constituting the gate electrode 26. The first silicide layer 42 a and the gate silicide layer 42 b may be selected from the group consisting of cobalt (Co), titanium (Ti), nickel (Ni), tungsten (W), platinum (Pt), hafnium (Hf), and palladium (Pd). Embodiments according to the present invention, including cobalt as the silicide layer will be described herein in greater detail.
  • A wet cleaning process is carried out to remove a natural oxide layer on a surface of the heavily doped region 40 and on a surface of the gate electrode 26. A cobalt layer is deposited using, for example, sputtering. A cobalt monosilicide (CoSi) is formed by a first thermal process. The first thermal process is carried out at a temperature in a range between about 400° C. and about 600° C. in a conventional rapid thermal annealer. This can cause a silicide reaction in regions where the cobalt contacts silicon. The regions of the substrate having the silicide reaction are cleaned using a mixed solution of sulfuric acid (H2SO4), oxygenated water (H2O2), and water (H2O). Thus, the unsilicided cobalt layer can be removed. A second thermal process is carried out at a temperature of about 750° C. or higher. The second thermal process can promote the cobalt monosilicide (CoSi) to change phase to cobalt disilicide (CoSi2) which can have a low resistivity.
  • In some embodiments according to the present invention, the silicide layer may be formed using a one-step thermal process. For example, a cobalt layer can be formed and then annealed at about 750° C. or higher. Thereafter, a cleaning process is carried out to remove the unreacted metal, thereby forming the silicide layer.
  • Referring to FIG. 3F, the inner insulation layer 32 is at least partially removed using wet etching to remove the portion of the L-shaped spacer 33 that projects from the base, to expose a surface of the lightly doped region 28. Therefore, the I-shaped spacer 35 remains on the sidewalls of the gate electrode 26, but the portion of the L-shaped spacer 33 that projects from the base is removed. The I-shaped spacer 35 may be formed of only the insulating spacer 30 or a combination of the insulating spacer 30 and a portion of the inner insulation layer 32.
  • Referring to FIG. 3G, a thin metal layer 44 is formed on the gate electrode 26, the sidewalls of the gate electrode 26, and the substrate. The metal layer 44 may be the same material described above as part of the Salicide process and may be formed by sputtering. In some embodiments according to the present invention, a natural silicide layer is formed via a natural reaction rather than via the thermal process described above. The natural silicide layer can be formed, for example, by a thermodynamic reaction generated when two different materials are brought into proximity with one another. In particular, when two materials are brought into proximity with one another they may diffuse into each other and can mixed at an interface therebetween. For example, it is known that cobalt (Co) reacts on silicon at an interface therebetween and creates cobalt monosilicide (CoSi) layer having a thickness of about 30 Ångstroms. A cleaning process is carried out to remove metal that did not react with the silicon substrate.
  • Referring to FIG. 3H, a thin second silicide layer 46 is formed on the exposed lightly doped region 28. Furthermore, in the case of cobalt, cobalt monosilicide (CoSi) may be changed in phase to cobalt disilicide (CoSi2) by a thermal process so as to lower resistance. The second silicide layer 46 is thinner than the first silicide layer 42 a formed on the heavily doped region 40. This is because if the second silicide layer 46 were too thick, the junction formed between the impurity regions 28 and 40 and the substrate 20 may be degraded thereby causing an increase in leakage current. Accordingly, the surface of the first silicide layer 42 a extends beyond the adjacent surface of the second silicide layer 46. In other words, the upper surface of the first silicide layer 42 a is higher than the adjacent upper surface of the second silicide layer 46. Furthermore, the lower surface of the first silicide layer 42 a is lower than the adjacent lower surface of the second silicide layer 46.
  • The I-shaped spacer 35 remaining on the sidewalls of the gate electrode 26 prevents an electric short between the gate electrode 26 and the impurity regions 28 and 40 due to the second silicide layer 46.
  • FIGS. 4A to 4H are cross-sectional views illustrating methods of fabricating MOS transistors having an extended silicide layer on a source/drain region according to other embodiments of the present invention. Referring to FIG. 4A, the field regions 22 are formed on the semiconductor substrate 20 to define an active region therebetween. An insulation layer and a conductive layer are formed on a surface of the substrate and patterned to form a gate insulation layer 24 and the gate electrode 26. Impurities are implanted, using the gate electrode 26 and the field region 22 as an ion implantation mask, into the active region at a low concentration to form a lightly doped region 28.
  • Referring to FIG. 4B, an inner insulation layer 32 and an outer insulation layer 38 are sequentially formed on the surface of the substrate and on the gate electrode 26. In some embodiments according to the present invention, the inner insulation layer 32 is a silicon oxide layer. In some embodiments according to the present invention, the outer insulation layer 38 includes a first outer insulation layer 34 and a second outer insulation layer 36 as disclosed above, for example, in reference to FIG. 3B. In some embodiments according to the present invention, the first and second outer insulation layers 34 and 36 are materials having different etch rates. For example, the first outer insulation layer 34 can be a silicon nitride layer, while the second outer insulation layer 36 can be a silicon oxide layer.
  • Referring to FIG. 4C, the inner insulation layer 32 and the outer insulation layer 38 are patterned by dry etching using an anisotropic etch process, thereby forming a gate spacer 39 on the sidewalls of the gate electrode 26. Accordingly, the gate spacer 39 includes the patterned inner insulation layer 32 and the patterned outer insulation layer 38. The patterned outer insulation layer 38 includes the patterned first outer insulation layer 34 and the second outer insulation layer 36. The inner insulation layer 32 is not completely removed by the dry etch and a thin layer of about 50 Ångstroms may remain on the surface of the substrate. A heavily doped region 40 is formed by ion implantation using the gate electrode 26, the gate spacer 39, and the field region 22 as an ion implantation mask. The inner insulation layer 32 remaining on the substrate can serve as a buffer layer during the ion implantation.
  • Referring to FIG. 4D, the patterned outer insulation layer 38 constituting the gate spacer 39 is removed using a wet etch process. Thus, forming the L-shaped spacer 32 including the patterned inner insulation layer. The L-shaped spacer 32 includes I-shaped main portion and a projecting portion that extends from a bottom (or base) of the I-shaped main portion. Unlike some of the other embodiments disclosed herein (such as those disclosed in reference to FIG. 3D, the L-shaped spacer 32 includes only the inner insulation layer 32.
  • Referring to FIG. 4E, a Salicide process is applied to a surface of the heavily doped region 40 and to a top of the gate electrode 26, to form a first silicide layer 42 a and a gate silicide layer 42 b. The gate silicide layer may not be formed on the gate electrode 26 depending on the materials constituting the gate electrode 26.
  • Referring to FIG. 4F, the L-shaped spacer 32 is dry etched to remove the portion of the L-shaped spacer 32 that projects from the base to expose a partial surface of the lightly doped region 28 and to form an I-shaped spacer 35. Therefore, in some embodiments according to the present invention disclosed herein (such as in reference to FIG. 3F), the etching process used to remove the projecting portion of the L-shaped spacer 32 is a dry etch process rather than a wet etch process. Furthermore, in the present embodiment according to the present invention, the insulating spacer disclosed in reference to other embodiments can be eliminated. Accordingly, if the wet etch process is applied, the L-shaped spacer may be wholly or partially removed. If the L-shaped spacer is wholly removed or the I-shaped spacer is thinly formed on the sidewalls of the gate electrode, a leakage current may be generated through the silicide layer between the gate electrode 26 and the impurity regions 28 and 40.
  • Referring to FIG. 4G, a metal layer 44 is formed on the surface of the substrate including on at least a portion of the lightly doped region 28. The metal can react with the silicon in the exposed lightly doped region 28. In some embodiments according to the present invention, the reaction between the substrate and the metal occurs naturally (i.e., without a thermal process being applied).
  • Referring to FIG. 4H, any metal that does not react with the silicon in the substrate is removed to form the thin second silicide layer 46 on the exposed lightly doped region 28. As a result, a resistance of a contact made to the lightly doped region 28 and the heavily doped region 40 can be reduced. In other embodiments according to the present invention, a thermal process can be performed after the second silicide layer 46 is formed to further reduce the resistance.
  • As set forth before, according to some embodiments of the present invention, when a MOS transistor with an LDD structure is fabricated, a silicide layer can be formed even at a lightly doped region. As a result, a resistance of a source/drain region may be reduced.
  • In the drawings and specification, there have been disclosed typical preferred embodiments of the invention and, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the following claims.

Claims (8)

1. A MOS transistor comprising:
a substrate;
a field region on the semiconductor substrate to define an active region;
an I-shaped spacer on sidewalls of the gate electrode;
a lightly doped region and a heavily doped region n the semiconductor substrate on sides of the gate electrode;
a first silicide layer on a surface of the heavily doped region; and
a second silicide layer on the lightly doped region between the I-shaped spacer and the first silicide layer.
2. The MOS transistor as claimed in claim 1, wherein the second silicide layer is thinner than the first silicide layer.
3. The MOS transistor as claimed in claim 1, further comprising a gate silicide layer on the gate electrode.
4. A MOS transistor comprising:
a first silicide layer having a first thickness on a source/drain region self-aligned to a sidewall spacer of a gate electrode; and
a second silicide layer having a second thickness, less than the first thickness, on the source/drain region adjacent to the first silicide layer.
5. The MOS transistor according to claim 4 further comprising:
lightly and heavily doped source/drain regions adjacent to one another in a substrate having the gate electrode with the sidewall spacer thereon;
6. The MOS transistor according to claim 4 wherein a surface of the first silicide layer extends beyond an adjacent surface of the second silicide layer.
7. The MOS transistor according to claim 4 wherein the first silicide layer extends deeper into the source/drain region that the second silicide layer.
8. The MOS transistor according to claim 4 wherein the first silicide layer is elevated farther above the source/drain region that the second silicide layer.
US11/693,317 2002-03-28 2007-03-29 MOS Transistors Including Silicide Layers on Source/Drain Regions Abandoned US20070170501A1 (en)

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