US20060292801A1 - Bit line of a semiconductor device and method for fabricating the same - Google Patents
Bit line of a semiconductor device and method for fabricating the same Download PDFInfo
- Publication number
- US20060292801A1 US20060292801A1 US11/291,016 US29101605A US2006292801A1 US 20060292801 A1 US20060292801 A1 US 20060292801A1 US 29101605 A US29101605 A US 29101605A US 2006292801 A1 US2006292801 A1 US 2006292801A1
- Authority
- US
- United States
- Prior art keywords
- bit line
- film
- interlayer dielectric
- stacks
- dielectric film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 31
- 238000000034 method Methods 0.000 title claims abstract description 27
- 239000011229 interlayer Substances 0.000 claims abstract description 35
- 125000006850 spacer group Chemical group 0.000 claims abstract description 28
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 150000004767 nitrides Chemical class 0.000 claims description 16
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 10
- 238000000231 atomic layer deposition Methods 0.000 claims description 9
- 239000000463 material Substances 0.000 claims description 9
- 229910052721 tungsten Inorganic materials 0.000 claims description 9
- 239000010937 tungsten Substances 0.000 claims description 9
- JUJWROOIHBZHMG-UHFFFAOYSA-N Pyridine Chemical compound C1=CC=NC=C1 JUJWROOIHBZHMG-UHFFFAOYSA-N 0.000 claims description 6
- 238000000137 annealing Methods 0.000 claims description 6
- 239000003054 catalyst Substances 0.000 claims description 3
- UMJSCPRVCHMLSP-UHFFFAOYSA-N pyridine Natural products COC1=CC=CN=C1 UMJSCPRVCHMLSP-UHFFFAOYSA-N 0.000 claims description 3
- 239000012299 nitrogen atmosphere Substances 0.000 claims description 2
- 239000007789 gas Substances 0.000 description 11
- 238000010926 purge Methods 0.000 description 6
- 239000000376 reactant Substances 0.000 description 4
- LXEXBJXDGVGRAR-UHFFFAOYSA-N trichloro(trichlorosilyl)silane Chemical compound Cl[Si](Cl)(Cl)[Si](Cl)(Cl)Cl LXEXBJXDGVGRAR-UHFFFAOYSA-N 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 2
- 230000006835 compression Effects 0.000 description 2
- 238000007906 compression Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000010410 layer Substances 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- 238000007792 addition Methods 0.000 description 1
- 239000012298 atmosphere Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000006227 byproduct Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/495—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
Definitions
- the present invention relates to a method for fabricating a semiconductor device, and more particularly to a method for fabricating a bit line of a semiconductor device.
- bit line is known as a signal-transmission passage between components constituting unit memory devices which can store 1-bit unit data.
- FIG. 1 illustrates a bit line formed by a method for fabricating a bit line of a semiconductor device in accordance with conventional methods.
- a first interlayer dielectric film 110 is formed on a semiconductor substrate 100 having gates (not shown) and landing plugs (not shown) formed thereon.
- a portion of the first interlayer dielectric film 110 is etched such that the upper parts of the landing plugs are exposed, thereby forming a bit line contact hole (not shown).
- a barrier metal film (not shown) is formed inside the bit line contact hole.
- a conductive material (not shown) is formed such that the bit line contact hole is embedded, thereby forming a bit line contact (not shown).
- a bit line-forming material (not shown), e.g., tungsten and nitride material, is deposited on the bit line contact and first interlayer dielectric film 110 .
- bit line-forming material is then etched to overlap with the bit line contact, thereby forming bit line stacks 120 in which, for example, tungsten 125 and a hard mask nitride film 127 are sequentially stacked.
- bit line spacers 130 are formed on the sidewalls of the bit line stacks 120 .
- the bit line spacers 130 may be formed from a nitride film, which has high tensile stress.
- an oxide film (not shown), which is a second interlayer dielectric film, is formed on the first interlayer dielectric film 110 , via a high density plasma (HDP) process, such that the gap between the bit line stacks 120 is embedded.
- the oxide film, formed by the high density plasma (HDP) process has compression stress.
- bit line of the semiconductor device in accordance with conventional methods suffer from collapse of the bit line stacks 120 due to different properties between the bit line spacer 130 and the oxide film in the course of embedding the oxide film, as the second interlayer dielectric film, during a high density plasma (HDP) process.
- Bit line spacers 130 exhibit high tensile stress, while the oxide film, as the second interlayer dielectric film, exhibits compression stress.
- the different types of stress results in a collapse of the bit line stacks 120 , as represented by ‘A’ in FIG. 1 .
- Such stress-induced collapse of the bit line stacks 120 becomes more severe as the semiconductor device is highly integrated.
- a conventional 80 nm-sized semiconductor device can resist stress with the second interlayer dielectric film by securing a final critical dimension of about 70 nm of the bit line stacks 120 .
- a final critical dimension of the bit line stacks is sharply decreased to 30 nm. Consequently, capability of the bit line stacks to withstand stress with the second interlayer dielectric film is lowered, thereby resulting in a collapse thereof, which in turn leads to a short-circuit with adjacent bit line stacks, thus deteriorating characteristics of the devices. As such, it is difficult to fabricate high-reliability devices.
- Embodiments of the present invention alleviate stress between the bit line stack and the second interlayer dielectric film for insulating bit line stacks.
- a bit line of a semiconductor device comprises a first interlayer dielectric film disposed on a semiconductor substrate; a plurality of bit line stacks disposed on the first interlayer dielectric film; bit line spacers disposed on side walls of the bit line stacks; and a buffer film disposed on the bit line spacers, the first interlayer dielectric film, and the bit line stacks.
- the bit line stacks may be made of a tungsten film and a hard mask nitride film sequentially stacked.
- the bit line spacers may be made of a nitride film.
- a method for fabricating a bit line of a semiconductor device comprises forming bit line stacks on a first interlayer dielectric film formed on a semiconductor substrate; forming bit line spacers on side walls of the bit line stacks; forming a buffer film on the first interlayer dielectric film and the bit line stacks; annealing the buffer film to lower tensile stress thereof; and forming a second interlayer dielectric film on an entire surface of the resulting structure having the buffer film formed thereon.
- the bit line stack-forming material may be made of a tungsten film and a hard mask nitride film sequentially stacked.
- the bit line spacers may be formed of a nitride film.
- the buffer film may be formed of an oxide film, via atomic layer deposition (ALD) utilizing pyridine as a catalyst.
- annealing can be carried out at a temperature of about 650° C. to 700° C. for about 120 seconds under nitrogen atmosphere.
- FIG. 1 illustrates a bit line formed by a method for fabricating a bit line of a semiconductor device in accordance with conventional methods
- FIGS. 2 through 4 are cross-sectional views illustrating bit line of a semiconductor device in accordance with an embodiment of the present invention.
- FIGS. 2 through 4 are cross-sectional views illustrating a bit line of a semiconductor device in accordance with an embodiment of the present invention.
- FIG. 4 is a cross-sectional view showing the structure of bit line of a semiconductor device in accordance with an embodiment of the present invention.
- a first interlayer dielectric film 210 is disposed on a semiconductor substrate 200 and a plurality of bit line stacks 220 are disposed on the first interlayer dielectric film 210 .
- a plurality of bit line stacks 220 may have a structure in which a tungsten film 225 and a hard mask nitride film 227 are sequentially stacked.
- Bit line spacers 230 are disposed on side walls of the bit line stacks 220 .
- Bit line spacers 230 are made from nitride films.
- a buffer film 240 is disposed on bit line spacers 230 , first interlayer dielectric film 210 , and bit line stacks 220 .
- the buffer film 240 is made from an oxide film.
- the buffer film 240 serves to alleviate stress between the bit line spacers 230 and a second interlayer dielectric film (not shown) which will be formed on the buffer film 240 via a subsequent process, preventing a collapse of the bit line stacks 220 due to such stress.
- bit line-forming material (not shown) is deposited on the first interlayer dielectric film 210 , which was formed on the semiconductor substrate 200 .
- the bit line-forming material is composed of a tungsten film 225 and a hard mask nitride film 227 sequentially stacked.
- the bit line-forming material is selectively etched to form bit line stacks 220 composed of the tungsten film 225 and hard mask nitride film 227 sequentially stacked.
- gates (not shown) and landing plugs (not shown) are formed on the semiconductor substrate 200 , and a bit line contact (not shown) providing electrical connection between the bit line stacks 220 and landing plug is formed on the landing plugs.
- DRAM dynamic random access memory
- source/drain impurity regions are formed inside the semiconductor substrate 200 .
- bit line spacer-forming material (not shown) is deposited on the first interlayer dielectric film 210 such that the bit line stacks 220 are embedded, followed by an etching process such as a blank etching process, thereby forming bit line spacers 230 on side walls of the bit line stacks 220 .
- the bit line spacers 230 can be deposited to a thickness of about 130 A, using a nitride film.
- bit line spacers 230 exhibit tensile stress of about 1.3 ⁇ 10 10 dyne/cm 2 .
- Such bit line spacers 230 are used as barrier films, upon forming a subsequent self aligned contact.
- a buffer film 240 is formed on the entire surface of the resulting structure having the bit line spacers 230 formed thereon.
- Methods of forming the buffer film may be formed via use of atomic layer deposition (ALD) utilizing pyridine (C 5 H 5 N) as a catalyst.
- hexachlorodisilane Si 2 Cl 6
- the source gas is supplied and adsorbed and a purging gas is supplied to purge the remaining non-adsorbed source gas.
- water vapor H 2 O
- the purging gas is supplied to purge by-products of the reactant gas which did not participate in the reaction.
- such atomic layer deposition of the buffer oxide film is carried out at a deposition temperature of about 100 to 105° C.
- a process cycle may comprise first supplying a hexachlorodisilane source gas and purging, then supplying a reactant gas and purging, and repeating this process to form the buffer film 240 to a desired thickness.
- the buffer film 240 formed via one cycle of the process, has a thickness of about 1.0 to 1.5 ⁇ .
- the buffer film 240 After formation of the buffer film 240 via atomic layer deposition, annealing is carried out at a temperature of about 650 to 700° C. under nitrogen (N 2 ) atmosphere for about 100 to 120 seconds. As a result, the resulting buffer film 240 may have a tensile stress of about 3 ⁇ 10 9 dyne/cm 2 .
- the buffer film 240 Upon forming the buffer film via atomic layer deposition, followed by annealing, as described above, the buffer film 240 has a relatively low tensile stress as compared to the bit line spacers 230 . Therefore, it is possible to alleviate stress between the buffer film 240 and an oxide film which will be formed via a subsequent high density plasma (HDP) process, namely a second interlayer dielectric film.
- HDP high density plasma
- the oxide film, as the second interlayer dielectric film is formed on the entire surface of the resulting structure having the buffer film 240 formed thereon, via the high density plasma process.
- a buffer film having low tensile stress is formed between the bit line spacers, which are formed for use as a barrier film of a self aligned contact, and the second interlayer dielectric film.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Semiconductor Memories (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
A bit line of a semiconductor device includes a first interlayer dielectric film disposed on a semiconductor substrate, a plurality of bit line stacks disposed on the first interlayer dielectric film, a plurality of bit line spacers disposed on side walls of the bit line stacks, and a buffer film disposed on the bit line spacers, the first interlayer dielectric film and the bit line stacks; and a method for fabricating the same.
Description
- 1. Field of the Invention
- The present invention relates to a method for fabricating a semiconductor device, and more particularly to a method for fabricating a bit line of a semiconductor device.
- 2. Description of the Related Art
- Generally, in memory cells of semiconductor devices, a bit line is known as a signal-transmission passage between components constituting unit memory devices which can store 1-bit unit data.
-
FIG. 1 illustrates a bit line formed by a method for fabricating a bit line of a semiconductor device in accordance with conventional methods. - Referring to
FIG. 1 , in fabricating the bit line of a semiconductor device, a first interlayerdielectric film 110 is formed on asemiconductor substrate 100 having gates (not shown) and landing plugs (not shown) formed thereon. Next, a portion of the first interlayerdielectric film 110 is etched such that the upper parts of the landing plugs are exposed, thereby forming a bit line contact hole (not shown). A barrier metal film (not shown) is formed inside the bit line contact hole. Next, a conductive material (not shown) is formed such that the bit line contact hole is embedded, thereby forming a bit line contact (not shown). Next, a bit line-forming material (not shown), e.g., tungsten and nitride material, is deposited on the bit line contact and first interlayerdielectric film 110. - The bit line-forming material is then etched to overlap with the bit line contact, thereby forming bit line stacks 120 in which, for example,
tungsten 125 and a hardmask nitride film 127 are sequentially stacked. Next,bit line spacers 130 are formed on the sidewalls of the bit line stacks 120. Thebit line spacers 130 may be formed from a nitride film, which has high tensile stress. Then, an oxide film (not shown), which is a second interlayer dielectric film, is formed on the first interlayerdielectric film 110, via a high density plasma (HDP) process, such that the gap between the bit line stacks 120 is embedded. The oxide film, formed by the high density plasma (HDP) process, has compression stress. - The bit line of the semiconductor device in accordance with conventional methods suffer from collapse of the bit line stacks 120 due to different properties between the
bit line spacer 130 and the oxide film in the course of embedding the oxide film, as the second interlayer dielectric film, during a high density plasma (HDP) process.Bit line spacers 130 exhibit high tensile stress, while the oxide film, as the second interlayer dielectric film, exhibits compression stress. The different types of stress results in a collapse of the bit line stacks 120, as represented by ‘A’ inFIG. 1 . - Such stress-induced collapse of the bit line stacks 120 becomes more severe as the semiconductor device is highly integrated. For example, a conventional 80 nm-sized semiconductor device can resist stress with the second interlayer dielectric film by securing a final critical dimension of about 70 nm of the bit line stacks 120. As the dimensions of semiconductor devices have recently been reduced to 65 nm due to high degree of integration thereof, a final critical dimension of the bit line stacks is sharply decreased to 30 nm. Consequently, capability of the bit line stacks to withstand stress with the second interlayer dielectric film is lowered, thereby resulting in a collapse thereof, which in turn leads to a short-circuit with adjacent bit line stacks, thus deteriorating characteristics of the devices. As such, it is difficult to fabricate high-reliability devices.
- Embodiments of the present invention alleviate stress between the bit line stack and the second interlayer dielectric film for insulating bit line stacks.
- In accordance with an aspect of the present invention, a bit line of a semiconductor device comprises a first interlayer dielectric film disposed on a semiconductor substrate; a plurality of bit line stacks disposed on the first interlayer dielectric film; bit line spacers disposed on side walls of the bit line stacks; and a buffer film disposed on the bit line spacers, the first interlayer dielectric film, and the bit line stacks. The bit line stacks may be made of a tungsten film and a hard mask nitride film sequentially stacked. The bit line spacers may be made of a nitride film.
- In accordance with another aspect of the present invention, a method for fabricating a bit line of a semiconductor device comprises forming bit line stacks on a first interlayer dielectric film formed on a semiconductor substrate; forming bit line spacers on side walls of the bit line stacks; forming a buffer film on the first interlayer dielectric film and the bit line stacks; annealing the buffer film to lower tensile stress thereof; and forming a second interlayer dielectric film on an entire surface of the resulting structure having the buffer film formed thereon. The bit line stack-forming material may be made of a tungsten film and a hard mask nitride film sequentially stacked. The bit line spacers may be formed of a nitride film. The buffer film may be formed of an oxide film, via atomic layer deposition (ALD) utilizing pyridine as a catalyst.
- In one embodiment of the present invention, annealing can be carried out at a temperature of about 650° C. to 700° C. for about 120 seconds under nitrogen atmosphere.
- Embodiments of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:
-
FIG. 1 illustrates a bit line formed by a method for fabricating a bit line of a semiconductor device in accordance with conventional methods; and -
FIGS. 2 through 4 are cross-sectional views illustrating bit line of a semiconductor device in accordance with an embodiment of the present invention. - Embodiments of the present invention will be described in more detail with reference to accompanying drawings, such that those skilled in the art can easily practice the present invention. In the drawings, thicknesses of various layers and regions are exaggerated for clarity. Like numbers refer to like elements throughout the specification and drawings.
-
FIGS. 2 through 4 are cross-sectional views illustrating a bit line of a semiconductor device in accordance with an embodiment of the present invention. -
FIG. 4 is a cross-sectional view showing the structure of bit line of a semiconductor device in accordance with an embodiment of the present invention. Referring toFIG. 4 , a first interlayerdielectric film 210 is disposed on asemiconductor substrate 200 and a plurality ofbit line stacks 220 are disposed on the first interlayerdielectric film 210. A plurality ofbit line stacks 220 may have a structure in which atungsten film 225 and a hardmask nitride film 227 are sequentially stacked.Bit line spacers 230 are disposed on side walls of thebit line stacks 220.Bit line spacers 230 are made from nitride films. Abuffer film 240 is disposed onbit line spacers 230, first interlayerdielectric film 210, andbit line stacks 220. Thebuffer film 240 is made from an oxide film. - In such a structure, the
buffer film 240 serves to alleviate stress between thebit line spacers 230 and a second interlayer dielectric film (not shown) which will be formed on thebuffer film 240 via a subsequent process, preventing a collapse of thebit line stacks 220 due to such stress. - Hereinafter, a method for fabricating the bit line of a semiconductor device in accordance with an embodiment the present invention will be described with reference to
FIGS. 2 through 4 . - First, referring to
FIG. 2 , a bit line-forming material (not shown) is deposited on the first interlayerdielectric film 210, which was formed on thesemiconductor substrate 200. The bit line-forming material is composed of atungsten film 225 and a hardmask nitride film 227 sequentially stacked. Next, the bit line-forming material is selectively etched to formbit line stacks 220 composed of thetungsten film 225 and hardmask nitride film 227 sequentially stacked. - Although not shown in
FIG. 2 , gates (not shown) and landing plugs (not shown) are formed on thesemiconductor substrate 200, and a bit line contact (not shown) providing electrical connection between thebit line stacks 220 and landing plug is formed on the landing plugs. In addition, in dynamic random access memory (DRAM) devices, source/drain impurity regions (not shown) are formed inside thesemiconductor substrate 200. - Next, referring to
FIG. 3 , a bit line spacer-forming material (not shown) is deposited on the first interlayerdielectric film 210 such that thebit line stacks 220 are embedded, followed by an etching process such as a blank etching process, thereby formingbit line spacers 230 on side walls of thebit line stacks 220. Thebit line spacers 230 can be deposited to a thickness of about 130A, using a nitride film. In one embodiment of the present invention,bit line spacers 230 exhibit tensile stress of about 1.3×1010 dyne/cm2. Suchbit line spacers 230 are used as barrier films, upon forming a subsequent self aligned contact. - Next, referring to
FIG. 4 , abuffer film 240 is formed on the entire surface of the resulting structure having thebit line spacers 230 formed thereon. Methods of forming the buffer film may be formed via use of atomic layer deposition (ALD) utilizing pyridine (C5H5N) as a catalyst. - More specifically, hexachlorodisilane (Si2Cl6) may be used as a source gas. The source gas is supplied and adsorbed and a purging gas is supplied to purge the remaining non-adsorbed source gas. Next, water vapor (H2O), as a reactant gas, is supplied to initiate a reaction between the absorbed hexachlorodisilane source gas and the reactant gas, thereby forming a buffer oxide film as an atomic layer unit. Next, the purging gas is supplied to purge by-products of the reactant gas which did not participate in the reaction. In one embodiment of the present invention, such atomic layer deposition of the buffer oxide film is carried out at a deposition temperature of about 100 to 105° C. As such, a process cycle may comprise first supplying a hexachlorodisilane source gas and purging, then supplying a reactant gas and purging, and repeating this process to form the
buffer film 240 to a desired thickness. In one embodiment of the present invention, thebuffer film 240, formed via one cycle of the process, has a thickness of about 1.0 to 1.5 Å. - After formation of the
buffer film 240 via atomic layer deposition, annealing is carried out at a temperature of about 650 to 700° C. under nitrogen (N2) atmosphere for about 100 to 120 seconds. As a result, the resultingbuffer film 240 may have a tensile stress of about 3×109 dyne/cm2. - Upon forming the buffer film via atomic layer deposition, followed by annealing, as described above, the
buffer film 240 has a relatively low tensile stress as compared to thebit line spacers 230. Therefore, it is possible to alleviate stress between thebuffer film 240 and an oxide film which will be formed via a subsequent high density plasma (HDP) process, namely a second interlayer dielectric film. Although not shown inFIG. 4 , the oxide film, as the second interlayer dielectric film, is formed on the entire surface of the resulting structure having thebuffer film 240 formed thereon, via the high density plasma process. - As apparent from the above description, via application of a method for fabricating a bit line of a semiconductor device in accordance with the present invention, a buffer film having low tensile stress is formed between the bit line spacers, which are formed for use as a barrier film of a self aligned contact, and the second interlayer dielectric film. As a result, it is possible to prevent collapse of the bit line stacks due to different stress between the bit line spacers and second interlayer dielectric film.
- Although the embodiments of the present invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims.
Claims (8)
1. A bit line of a semiconductor device, comprising:
a first interlayer dielectric film disposed on a semiconductor substrate;
a plurality of bit line stacks disposed on the first interlayer dielectric film;
a plurality of bit line spacers disposed on side walls of the bit line stacks; and
a buffer film disposed on the bit line spacers, the first interlayer dielectric film, and the bit line stacks.
2. The bit line according to claim 1 , wherein the bit line stacks includes a tungsten film and a hard mask nitride film that are sequentially stacked.
3. The bit line according to claim 1 , wherein the bit line spacers include a nitride film.
4. A method for fabricating a bit line of a semiconductor device, comprising:
forming bit line stacks on a first interlayer dielectric film formed on a semiconductor substrate;
forming bit line spacers on side walls of the bit line stacks;
forming a buffer film on the first interlayer dielectric film and bit line stacks;
annealing the buffer film to lower tensile stress thereof; and
forming a second interlayer dielectric film on an entire surface of the resulting structure having the buffer film formed thereon.
5. The method according to claim 4 , wherein the bit line stack-forming material includes a tungsten film and a hard mask nitride film sequentially stacked.
6. The method according to claim 4 , wherein the bit line spacers include a nitride film.
7. The method according to claim 4 , wherein the buffer film includes an oxide film formed via an atomic layer deposition (ALD) process utilizing pyridine as a catalyst.
8. The method according to claim 4 , wherein annealing is carried out at a temperature of about 650° C. to 700° C. for about 120 seconds under nitrogen atmosphere.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/141,859 US7846795B2 (en) | 2005-06-22 | 2008-06-18 | Bit line of a semiconductor device and method for fabricating the same |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020050053919A KR100732759B1 (en) | 2005-06-22 | 2005-06-22 | Bit line in semiconductor device and method for fabricating the same |
KR2005-53919 | 2005-06-22 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/141,859 Division US7846795B2 (en) | 2005-06-22 | 2008-06-18 | Bit line of a semiconductor device and method for fabricating the same |
Publications (1)
Publication Number | Publication Date |
---|---|
US20060292801A1 true US20060292801A1 (en) | 2006-12-28 |
Family
ID=37568067
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/291,016 Abandoned US20060292801A1 (en) | 2005-06-22 | 2005-11-29 | Bit line of a semiconductor device and method for fabricating the same |
US12/141,859 Expired - Fee Related US7846795B2 (en) | 2005-06-22 | 2008-06-18 | Bit line of a semiconductor device and method for fabricating the same |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/141,859 Expired - Fee Related US7846795B2 (en) | 2005-06-22 | 2008-06-18 | Bit line of a semiconductor device and method for fabricating the same |
Country Status (2)
Country | Link |
---|---|
US (2) | US20060292801A1 (en) |
KR (1) | KR100732759B1 (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090032963A1 (en) * | 2007-08-03 | 2009-02-05 | Micron Technology, Inc. | Semiconductor structures including tight pitch contacts and methods to form same |
US20140045325A1 (en) * | 2007-06-28 | 2014-02-13 | SK Hynix Inc. | Method for fabricating an inter dielectric layer in semiconductor device |
CN111211088A (en) * | 2018-11-21 | 2020-05-29 | 台湾积体电路制造股份有限公司 | Semiconductor device and method of forming the same |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100908821B1 (en) * | 2007-11-08 | 2009-07-21 | 주식회사 하이닉스반도체 | Method of forming insulating film of semiconductor device |
KR101725446B1 (en) * | 2011-08-24 | 2017-04-12 | 삼성전자주식회사 | Semiconductor Devices and Methods of Fabricating the Same |
Citations (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6022778A (en) * | 1995-03-09 | 2000-02-08 | Sgs-Thomson Microelectronics, S.R.L. | Process for the manufacturing of integrated circuits comprising low-voltage and high-voltage DMOS-technology power devices and non-volatile memory cells |
US6022776A (en) * | 1999-04-07 | 2000-02-08 | Worldwide Semiconductor Manufacturing Corporation | Method of using silicon oxynitride to improve fabricating of DRAM contacts and landing pads |
US6114767A (en) * | 1997-07-31 | 2000-09-05 | Nec Corporation | EEPROM semiconductor device and method of fabricating the same |
US20010009810A1 (en) * | 1997-03-14 | 2001-07-26 | Li Li | Etching process using a buffer layer |
US6331495B1 (en) * | 1998-01-22 | 2001-12-18 | Micron Technology, Inc. | Semiconductor structure useful in a self-aligned contact etch and method for making same |
US20020047151A1 (en) * | 2000-10-19 | 2002-04-25 | Kim Yeong-Kwan | Semiconductor device having thin film formed by atomic layer deposition and method for fabricating the same |
US6380042B1 (en) * | 2001-02-15 | 2002-04-30 | Winbond Electronics Corp. | Self-aligned contact process using stacked spacers |
US20020105088A1 (en) * | 2001-02-08 | 2002-08-08 | Samsung Electronics Co., Ltd. | Semiconductor device having multilayer interconnection structure and manfacturing method thereof |
US6630739B1 (en) * | 1996-12-24 | 2003-10-07 | Stmicroelectronics S.R.L. | Planarization structure and method for dielectric layers |
US20030203113A1 (en) * | 2002-04-25 | 2003-10-30 | Cho Byoung Ha | Method for atomic layer deposition (ALD) of silicon oxide film |
US6700143B2 (en) * | 2000-08-15 | 2004-03-02 | Mosel Vitelic, Inc. | Dummy structures that protect circuit elements during polishing |
US20050196114A1 (en) * | 2004-02-25 | 2005-09-08 | National Research Council Of Canada | Stress-induced control of polarization dependent properties in photonic devices |
US6972223B2 (en) * | 2001-03-15 | 2005-12-06 | Micron Technology, Inc. | Use of atomic oxygen process for improved barrier layer |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100345672B1 (en) * | 1999-05-25 | 2002-07-24 | 주식회사 하이닉스반도체 | Method of forming interlayer dielectric layer using high density plasma oxide in semiconductor device |
US6261891B1 (en) * | 2000-01-28 | 2001-07-17 | United Microelectronics Corp. | Method of forming a passivation layer of a DRAM |
KR20040028244A (en) * | 2002-09-30 | 2004-04-03 | 주식회사 하이닉스반도체 | Fabricating method of semiconductor device |
-
2005
- 2005-06-22 KR KR1020050053919A patent/KR100732759B1/en not_active IP Right Cessation
- 2005-11-29 US US11/291,016 patent/US20060292801A1/en not_active Abandoned
-
2008
- 2008-06-18 US US12/141,859 patent/US7846795B2/en not_active Expired - Fee Related
Patent Citations (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6022778A (en) * | 1995-03-09 | 2000-02-08 | Sgs-Thomson Microelectronics, S.R.L. | Process for the manufacturing of integrated circuits comprising low-voltage and high-voltage DMOS-technology power devices and non-volatile memory cells |
US6630739B1 (en) * | 1996-12-24 | 2003-10-07 | Stmicroelectronics S.R.L. | Planarization structure and method for dielectric layers |
US20010009810A1 (en) * | 1997-03-14 | 2001-07-26 | Li Li | Etching process using a buffer layer |
US6114767A (en) * | 1997-07-31 | 2000-09-05 | Nec Corporation | EEPROM semiconductor device and method of fabricating the same |
US6331495B1 (en) * | 1998-01-22 | 2001-12-18 | Micron Technology, Inc. | Semiconductor structure useful in a self-aligned contact etch and method for making same |
US6022776A (en) * | 1999-04-07 | 2000-02-08 | Worldwide Semiconductor Manufacturing Corporation | Method of using silicon oxynitride to improve fabricating of DRAM contacts and landing pads |
US6700143B2 (en) * | 2000-08-15 | 2004-03-02 | Mosel Vitelic, Inc. | Dummy structures that protect circuit elements during polishing |
US20020047151A1 (en) * | 2000-10-19 | 2002-04-25 | Kim Yeong-Kwan | Semiconductor device having thin film formed by atomic layer deposition and method for fabricating the same |
US20020105088A1 (en) * | 2001-02-08 | 2002-08-08 | Samsung Electronics Co., Ltd. | Semiconductor device having multilayer interconnection structure and manfacturing method thereof |
US6380042B1 (en) * | 2001-02-15 | 2002-04-30 | Winbond Electronics Corp. | Self-aligned contact process using stacked spacers |
US6972223B2 (en) * | 2001-03-15 | 2005-12-06 | Micron Technology, Inc. | Use of atomic oxygen process for improved barrier layer |
US20030203113A1 (en) * | 2002-04-25 | 2003-10-30 | Cho Byoung Ha | Method for atomic layer deposition (ALD) of silicon oxide film |
US20050196114A1 (en) * | 2004-02-25 | 2005-09-08 | National Research Council Of Canada | Stress-induced control of polarization dependent properties in photonic devices |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20140045325A1 (en) * | 2007-06-28 | 2014-02-13 | SK Hynix Inc. | Method for fabricating an inter dielectric layer in semiconductor device |
US9437423B2 (en) * | 2007-06-28 | 2016-09-06 | SK Hynix Inc. | Method for fabricating an inter dielectric layer in semiconductor device |
US20090032963A1 (en) * | 2007-08-03 | 2009-02-05 | Micron Technology, Inc. | Semiconductor structures including tight pitch contacts and methods to form same |
US8481417B2 (en) | 2007-08-03 | 2013-07-09 | Micron Technology, Inc. | Semiconductor structures including tight pitch contacts and methods to form same |
US8723326B2 (en) | 2007-08-03 | 2014-05-13 | Micron Technology, Inc. | Semiconductor structures including tight pitch contacts |
US8994189B2 (en) | 2007-08-03 | 2015-03-31 | Micron Technology, Inc. | Semiconductor structures including tight pitch contacts |
US9437480B2 (en) | 2007-08-03 | 2016-09-06 | Micron Technology, Inc. | Methods of forming semiconductor structures including tight pitch contacts and lines |
CN111211088A (en) * | 2018-11-21 | 2020-05-29 | 台湾积体电路制造股份有限公司 | Semiconductor device and method of forming the same |
Also Published As
Publication number | Publication date |
---|---|
KR20060134321A (en) | 2006-12-28 |
US7846795B2 (en) | 2010-12-07 |
US20080286926A1 (en) | 2008-11-20 |
KR100732759B1 (en) | 2007-06-27 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6836019B2 (en) | Semiconductor device having multilayer interconnection structure and manufacturing method thereof | |
KR100724566B1 (en) | Flash memory device having multilayer gate interlayer dielectric layer and methods of fabricating the same | |
WO2014077209A1 (en) | Semiconductor device and method for manufacturing same | |
US7741671B2 (en) | Capacitor for a semiconductor device and manufacturing method thereof | |
KR20110115319A (en) | Semiconductor device and method for forming the same | |
KR102171265B1 (en) | Patterning method using metal mask, and method for fabricating semiconductor device comprising the same patterning method | |
US20130075909A1 (en) | Semiconductor device including metal-containing conductive line and method of manufacturing the same | |
KR101949981B1 (en) | Semiconductor device and method for fabricating the same | |
US7846795B2 (en) | Bit line of a semiconductor device and method for fabricating the same | |
JP4493295B2 (en) | Method for manufacturing a semiconductor device including a silicon oxide layer | |
US20080268612A1 (en) | Method of forming isolation layer in semiconductor device | |
TWI721546B (en) | Memory device and manufacturing method thereof | |
KR100801736B1 (en) | Method of fabricating the semiconductor memory device having increased sensing margin | |
US20080303075A1 (en) | Method for forming element isolation structure of semiconductor device, element isolation structure of semiconductor device, and semiconductor memory device | |
US20180366573A1 (en) | Semiconductor device, memory device and manufacturing method of the same | |
US11177215B2 (en) | Integrated circuit device | |
KR100600288B1 (en) | Method of forming a semiconductor device | |
JP2008288260A (en) | Semiconductor device and its manufacturing method | |
TWI612643B (en) | Memory device and manufacturing method of the same | |
KR100972718B1 (en) | Method for manufacturing flash memory device | |
US20070202710A1 (en) | Method for fabricating semiconductor device using hard mask | |
US7615451B2 (en) | Method for forming semiconductor device | |
KR100881749B1 (en) | Method for fabrication of semiconductor device | |
CN116033737A (en) | Semiconductor structure and forming method thereof | |
KR20080024365A (en) | Method of fabricating the gate in semiconductor device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: HYNIX SEMICONDUCTOR INC., KOREA, REPUBLIC OF Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:GHUNG, JIE WON;REEL/FRAME:017309/0221 Effective date: 20051104 |
|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |