US20060180848A1 - Wing gate transistor for integrated circuits - Google Patents

Wing gate transistor for integrated circuits Download PDF

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US20060180848A1
US20060180848A1 US11/380,378 US38037806A US2006180848A1 US 20060180848 A1 US20060180848 A1 US 20060180848A1 US 38037806 A US38037806 A US 38037806A US 2006180848 A1 US2006180848 A1 US 2006180848A1
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Prior art keywords
gate
wing
spacer
drain region
source
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US7528445B2 (en
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Timothy Phua
Kheng Chok Tee
Liang Choo Hsia
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GlobalFoundries Singapore Pte Ltd
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Chartered Semiconductor Manufacturing Pte Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6653—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using the removal of at least part of spacer, e.g. disposable spacer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28114—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor characterised by the sectional shape, e.g. T, inverted-T
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide

Definitions

  • the present invention relates generally to integrated circuits, and more particularly to reduced-size transistors.
  • the present invention relates generally to electronics and more particularly to electronic components.
  • Semiconductor devices such as transistors, are formed in and upon semiconductor substrates. These circuit elements are interconnected by contacts and vias, which connect to patterned conductor layers which are separated by various dielectric layers.
  • a critical objective of the semiconductor industry has been to continually decrease the size of semiconductor devices to increase performance and reduce cost for applications such as cellphones and portable CD players.
  • semiconductor technology has advanced, there has been a continuing concentration on reducing the size of the semiconductor devices to allow for increased levels of circuit integration, improved performance, and higher density.
  • the present invention provides a system for forming a semiconductor device. Layers of gate dielectric material, gate material, and cap material are formed on a semiconductor substrate. The cap material and a portion of the gate material are processed to form a cap and a gate body portion. A wing on the gate body portion is formed from a remaining portion of the gate material. The gate dielectric material under a portion of the wing on the gate body portion is removed to form a gate dielectric. A lightly-doped source/drain is formed in the semiconductor substrate using the gate body portion and the wing.
  • the present invention permits shrinking of transistors while improving punch-through performance, threshold voltage roll-off, and other short-channel effects.
  • FIG. 1 is a view of a semiconductor device in an intermediate stage of manufacture in accordance with the present invention
  • FIG. 2 is the structure of FIG. 1 after further processing of cap and gate material layers;
  • FIG. 3 is the structure of FIG. 2 after deposition of a first spacer material layer
  • FIG. 4 is the structure of FIG. 3 after formation of a first spacer
  • FIG. 5 is the structure of FIG. 4 after deposition of a second spacer layer
  • FIG. 6 is the structure of FIG. 5 after formation of a second spacer
  • FIG. 7 is the structure of FIG. 6 after formation of a wing gate
  • FIG. 8 is the structure of FIG. 7 after removing the second spacer and exposure of the tips of the gate wings;
  • FIG. 9 is the structure of FIG. 8 after implantation of a dopant to form lightly-doped source/drains regions
  • FIG. 10 is the structure of FIG. 9 after removal of the first spacer
  • FIG. 11 is the structure of FIG. 10 after salicidation
  • FIG. 12 is the semiconductor device completed in accordance with the present invention to before formation of the source/drain and gate contacts;
  • FIG. 13 is an alternative metal gate embodiment of the present invention and FIG. 14 is a flow chart of a method of manufacture in accordance with the present invention.
  • a semiconductor device 100 such as a transistor, in an intermediate stage of manufacture.
  • a well has been formed in a semiconductor substrate 102 , such as a silicon substrate, and processing performed to form a gate dielectric layer 104 , such as a silicon dioxide or nitrided oxide.
  • a gate material layer 106 such as amorphous or polycrystalline silicon, has been deposited on the gate dielectric layer 104
  • a cap material layer 108 such as nitride, has been deposited on the gate material layer 106 .
  • horizontal as used herein is defined as a plane parallel to the conventional plane or surface of the semiconductor substrate, regardless of its orientation.
  • vertical refers to a direction perpendicular to the horizontal as just defined. Terms, such as “on”, “above”, “below”, “bottom”, “top”, “over”, and “under”, are defined with respect to the horizontal plane.
  • FIG. 2 therein is shown the structure of FIG. 1 after further processing of the cap and gate material layers 106 and 108 .
  • a mask (not shown) has been deposited and processed for the etching of the cap material layer 108 to form a cap 200 .
  • the cap 200 is used as a mask for the etching of the gate material layer 106 to form a gate body portion 202 with a gate thin layer portion 204 of gate material still remaining over the gate dielectric layer 104 .
  • the gate thin layer portion 204 has a thickness “t” under about 100 ⁇ .
  • FIG. 3 therein is shown the structure of FIG. 2 after deposition of a first spacer material layer 300 , such as nitride.
  • the first spacer material layer 300 is conformal and has a thickness of from 50 to 500 ⁇ .
  • FIG. 4 therein is shown the structure of FIG. 3 after formation of a first spacer 400 .
  • Anisotropic etching of the first spacer material layer 300 of FIG. 3 forms the first spacer 400 .
  • the first spacer 400 serves four purposes. First, it acts as a spacer for lightly doped drain/source (LDD) formation. Second, the first spacer 400 insures the formation of “wings” outside of the channel region in accordance with the present invention. Third, the gate body portion 202 is protected during the subsequent oxidation. Fourth, the first spacer 400 insures better contrast of the amorphous or polycrystalline silicon line width for optical measurement.
  • LDD lightly doped drain/source
  • the gate body portion 202 and the gate thin layer portion 204 are of the same material, accurate optical measurement of the width of the gate body portion 202 (the amorphous or polycrystalline silicon line width) is difficult because there is little contrast between the two. The contrast is greater or better between the gate body portion 202 and the first spacer 400 , which are of different materials.
  • a second spacer layer 500 which may be oxide formed by tetraethyoxysilane (TEOS) deposition or may be oxynitride.
  • TEOS tetraethyoxysilane
  • FIG. 6 therein is shown the structure of FIG. 5 after formation of a second spacer 600 .
  • the second spacer 600 is of oxide
  • anisotropic oxide etching is used that stops on the thin amorphous or polycrystalline silicon material of the gate thin layer portion 204 .
  • the thickness of the second spacer layer 500 determines the width of the second spacer 600 and hence the length of the wing in accordance with the present invention.
  • the thickness is preferably in the range of from 50 to 800 ⁇ .
  • the present invention provides a method of forming a wing gate without major changes to a conventional process flow through the use of the first and second spacers 400 and 600 . This also provides good control of the amount of wing protrusion and of the source, drain, and emitter (SDE) profile.
  • SDE source, drain, and emitter
  • FIG. 7 therein is shown the structure of FIG. 6 after formation of a wing gate 700 from the gate thin layer portion 204 .
  • Anisotropic etching of the amorphous or polycrystalline silicon layer of the gate thin layer portion 204 exposed by the second spacer 600 forms the gate wings 702 of the wing gate 700 .
  • the second spacer 600 could also be multiple spacers, such as double spacers, as represented by a third spacer 710 .
  • FIG. 8 therein is shown the structure of FIG. 7 after removal of the second spacer 600 and exposure of the tips of the gate wings 702 .
  • the tips of the gate wings 702 are rounded off by high-pressure (5 to 25 atmospheres)/high-temperature oxidation (800 to 1100° C.) for an amorphous or polycrystalline gate.
  • rounding off the gate wings 702 reduces the carrier concentration at the edges of the gate. It has also been discovered that rounding off the corners of the gate wings 702 improves the I off /I on curve and lowers the threshold roll-off for short-channel devices.
  • a gate dielectric 800 is a silicon dioxide or nitrided oxide
  • a time controlled oxide strip used to remove the gate dielectric layer 104 except under the first spacer 400 .
  • FIG. 9 therein is shown the structure of FIG. 8 after implantation to form lightly doped drain/source (LDD) regions 900 . It has been further discovered that the overhangs of the gate wings 702 cause the LDD regions 900 to be graded with a dopant concentration gradually increasing away from the gate dielectric 800 and substantially increasing away from the overhang of the gate wings 702 .
  • LDD lightly doped drain/source
  • FIG. 10 therein is shown the structure of FIG. 9 after removal of the first spacer 400 .
  • the first spacer 400 is a nitride
  • a nitride strip is used.
  • an amorphous or polycrystalline silicon re-oxidation is used to improve transistor lifetimes and gate dielectric reliability due to higher fields occurring at the etched polycrystalline silicon transistor edges.
  • a further spacer material layer (not shown), such as an oxide formed by TEOS deposition, is deposited and etched to form a further spacer 1000 .
  • the further spacer 1000 is used for the implantation of source/drain regions 1002 .
  • the source/drain regions 1002 and the LDD regions 900 form a three-step source/drain profile.
  • the strong electric field in the interface between the source/drain regions 1002 and the gate dielectric 800 can be reduced so as to improve hot carrier injection (HCI) by reducing the generation of the hot carrier effect.
  • HCI hot carrier injection
  • the mobility and drive current can be reduced by the elimination of the high parasitic resistance in the LDD region 900 .
  • FIG. 11 therein is shown the structure of FIG. 10 after salicidation to form silicide 1100 over the source/drain regions 1002 and the wing gate 700 .
  • FIG. 12 therein is shown the semiconductor device 100 completed in accordance with the present invention to before formation of source/drain and gate contacts.
  • a poly-metal dielectric (PMD) 1200 has been deposited over the structure of FIG. 11 , and a fixed-time or end point controlled chemical mechanical polishing (CMP) has been performed to expose the silicide 1100 over the gate wings 702 .
  • CMP chemical mechanical polishing
  • FIG. 13 therein is shown an alternative metal gate embodiment 1300 of the present invention.
  • the structure of FIG. 12 is subject to chemical mechanical polishing (CMP) until the silicide 1100 over the gate body portion 202 is removed.
  • the gate body portion 202 is anisotropically etched for a fixed time, followed by chemical vapor deposition (CVD) of a metal contact 1302 , of a material such as Tungsten (W), to be self-aligned over the wing gate 700 .
  • CVD chemical vapor deposition
  • W Tungsten
  • the method 1400 includes: a block 1402 of forming layers of gate dielectric material, gate material, and cap material on a semiconductor substrate; a block 1404 where the cap material and a portion of the gate material are processed to form a cap and a gate body portion; a block 1406 where a wing is formed on the gate body portion from the remaining portion of the gate material; a block 1408 where the gate dielectric material under a portion of the wing on the gate body portion is removed to form a gate dielectric; and a block 1410 where a lightly-doped source/drain is formed in the semiconductor substrate using the gate body portion and the wing.

Abstract

A system is provided for forming a semiconductor device. Layers of gate dielectric material, gate material, and cap material are formed on a semiconductor substrate. The cap material and a portion of the gate material are processed to form a cap and a gate body portion. A wing on the gate body portion is formed from a remaining portion of the gate material. The gate dielectric material under a portion of the wing on the gate body portion is removed to form a gate dielectric. A lightly-doped source/drain region is formed in the semiconductor substrate using the gate body portion and the wing.

Description

    CROSS-REFERENCE TO RELATED APPLICATION(S)
  • This is a divisional of co-pending application Ser. No. 10/820,664 filed Apr. 7, 2004, which is hereby incorporated by reference thereto.
    • BACKGROUND
  • 1. Field of the Invention
  • The present invention relates generally to integrated circuits, and more particularly to reduced-size transistors.
  • 2. Background of the Invention
  • The present invention relates generally to electronics and more particularly to electronic components.
  • Semiconductor devices such as transistors, are formed in and upon semiconductor substrates. These circuit elements are interconnected by contacts and vias, which connect to patterned conductor layers which are separated by various dielectric layers.
  • A critical objective of the semiconductor industry has been to continually decrease the size of semiconductor devices to increase performance and reduce cost for applications such as cellphones and portable CD players. As semiconductor technology has advanced, there has been a continuing concentration on reducing the size of the semiconductor devices to allow for increased levels of circuit integration, improved performance, and higher density.
  • As the advancement in semiconductor technology accelerates according to Moore's Law, much of the work being done is to reduce the channel length of for semiconductor devices such as transistors. However, as the size of the transistor is reduced, the punch-through performance, threshold voltage roll-off, and other short channel effects become problematic.
  • Performance of shrinking transistors, like off/on state current, threshold roll-off, etc. are becoming a major concern. Moreover, for short-channel devices, the threshold voltage and leakages are reaching the point where the transistors would not be operational.
  • As semiconductor devices continue to be reduced in size, it is clear that a breakthrough solution to these problems is required for continued success in reducing semiconductor device size and thus increasing device integration, performance, and function while at the same time reducing cost.
  • Solutions to these problems have been long sought, but have also long eluded those skilled in the art.
    • SUMMARY OF THE INVENTION
  • The present invention provides a system for forming a semiconductor device. Layers of gate dielectric material, gate material, and cap material are formed on a semiconductor substrate. The cap material and a portion of the gate material are processed to form a cap and a gate body portion. A wing on the gate body portion is formed from a remaining portion of the gate material. The gate dielectric material under a portion of the wing on the gate body portion is removed to form a gate dielectric. A lightly-doped source/drain is formed in the semiconductor substrate using the gate body portion and the wing. The present invention permits shrinking of transistors while improving punch-through performance, threshold voltage roll-off, and other short-channel effects.
  • Certain embodiments of the invention have other advantages in addition to or in place of those mentioned above. The advantages will become apparent to those skilled in the art from a reading of the following detailed description when taken with reference to the accompanying drawings.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a view of a semiconductor device in an intermediate stage of manufacture in accordance with the present invention;
  • FIG. 2 is the structure of FIG. 1 after further processing of cap and gate material layers;
  • FIG. 3 is the structure of FIG. 2 after deposition of a first spacer material layer;
  • FIG. 4 is the structure of FIG. 3 after formation of a first spacer;
  • FIG. 5 is the structure of FIG. 4 after deposition of a second spacer layer;
  • FIG. 6 is the structure of FIG. 5 after formation of a second spacer;
  • FIG. 7 is the structure of FIG. 6 after formation of a wing gate;
  • FIG. 8 is the structure of FIG. 7 after removing the second spacer and exposure of the tips of the gate wings;
  • FIG. 9 is the structure of FIG. 8 after implantation of a dopant to form lightly-doped source/drains regions;
  • FIG. 10 is the structure of FIG. 9 after removal of the first spacer;
  • FIG. 11 is the structure of FIG. 10 after salicidation;
  • FIG. 12 is the semiconductor device completed in accordance with the present invention to before formation of the source/drain and gate contacts;
  • FIG. 13, is an alternative metal gate embodiment of the present invention and FIG. 14 is a flow chart of a method of manufacture in accordance with the present invention.
    • DESCRIPTION OF THE PREFERRED EMBODIMENT
  • Referring now to FIG. 1, therein is shown a semiconductor device 100, such as a transistor, in an intermediate stage of manufacture. A well has been formed in a semiconductor substrate 102, such as a silicon substrate, and processing performed to form a gate dielectric layer 104, such as a silicon dioxide or nitrided oxide. A gate material layer 106, such as amorphous or polycrystalline silicon, has been deposited on the gate dielectric layer 104, and a cap material layer 108, such as nitride, has been deposited on the gate material layer 106.
  • The drawings showing embodiments of the invention are semi-diagrammatic and not to scale and, particularly, some of the dimensions are for the clarity of presentation and are shown greatly exaggerated in the FIGs. In addition, where multiple embodiments are disclosed and described having some features in common, for clarity and ease of illustration and description thereof like features one to another will ordinarily be described with like reference numerals.
  • Likewise, in the following description, numerous specific details are given to provide a thorough understanding of the invention. However, it will apparent that the invention may be practiced without these specific details. In order to avoid obscuring the present invention, some well-known system configurations and process steps are not disclosed in detail.
  • The term “horizontal” as used herein is defined as a plane parallel to the conventional plane or surface of the semiconductor substrate, regardless of its orientation. The term “vertical” refers to a direction perpendicular to the horizontal as just defined. Terms, such as “on”, “above”, “below”, “bottom”, “top”, “over”, and “under”, are defined with respect to the horizontal plane.
  • Referring now to FIG. 2, therein is shown the structure of FIG. 1 after further processing of the cap and gate material layers 106 and 108. A mask (not shown) has been deposited and processed for the etching of the cap material layer 108 to form a cap 200. The cap 200 is used as a mask for the etching of the gate material layer 106 to form a gate body portion 202 with a gate thin layer portion 204 of gate material still remaining over the gate dielectric layer 104. The gate thin layer portion 204 has a thickness “t” under about 100 Å.
  • Referring now to FIG. 3, therein is shown the structure of FIG. 2 after deposition of a first spacer material layer 300, such as nitride. The first spacer material layer 300 is conformal and has a thickness of from 50 to 500 Å. Referring now to FIG. 4, therein is shown the structure of FIG. 3 after formation of a first spacer 400. Anisotropic etching of the first spacer material layer 300 of FIG. 3 forms the first spacer 400. The first spacer 400 serves four purposes. First, it acts as a spacer for lightly doped drain/source (LDD) formation. Second, the first spacer 400 insures the formation of “wings” outside of the channel region in accordance with the present invention. Third, the gate body portion 202 is protected during the subsequent oxidation. Fourth, the first spacer 400 insures better contrast of the amorphous or polycrystalline silicon line width for optical measurement.
  • Since the gate body portion 202 and the gate thin layer portion 204 are of the same material, accurate optical measurement of the width of the gate body portion 202 (the amorphous or polycrystalline silicon line width) is difficult because there is little contrast between the two. The contrast is greater or better between the gate body portion 202 and the first spacer 400, which are of different materials.
  • Referring now to FIG. 5, therein is shown the structure of FIG. 4 after deposition of a second spacer layer 500, which may be oxide formed by tetraethyoxysilane (TEOS) deposition or may be oxynitride.
  • Referring now to FIG. 6, therein is shown the structure of FIG. 5 after formation of a second spacer 600. Where the second spacer 600 is of oxide, anisotropic oxide etching is used that stops on the thin amorphous or polycrystalline silicon material of the gate thin layer portion 204.
  • The thickness of the second spacer layer 500 determines the width of the second spacer 600 and hence the length of the wing in accordance with the present invention. The thickness is preferably in the range of from 50 to 800 Å.
  • The present invention provides a method of forming a wing gate without major changes to a conventional process flow through the use of the first and second spacers 400 and 600. This also provides good control of the amount of wing protrusion and of the source, drain, and emitter (SDE) profile.
  • Referring now to FIG. 7, therein is shown the structure of FIG. 6 after formation of a wing gate 700 from the gate thin layer portion 204. Anisotropic etching of the amorphous or polycrystalline silicon layer of the gate thin layer portion 204 exposed by the second spacer 600 forms the gate wings 702 of the wing gate 700.
  • It will be understood that the second spacer 600 could also be multiple spacers, such as double spacers, as represented by a third spacer 710.
  • Referring now to FIG. 8, therein is shown the structure of FIG. 7 after removal of the second spacer 600 and exposure of the tips of the gate wings 702.
  • The tips of the gate wings 702 are rounded off by high-pressure (5 to 25 atmospheres)/high-temperature oxidation (800 to 1100° C.) for an amorphous or polycrystalline gate.
  • In the present invention, it has been discovered that rounding off the gate wings 702 reduces the carrier concentration at the edges of the gate. It has also been discovered that rounding off the corners of the gate wings 702 improves the Ioff/Ion curve and lowers the threshold roll-off for short-channel devices.
  • Also shown in FIG. 8 the formation of a gate dielectric 800. Where the gate dielectric 800 is a silicon dioxide or nitrided oxide, a time controlled oxide strip used to remove the gate dielectric layer 104 except under the first spacer 400.
  • This forms what can be described as an inverted-T gate with the gate dielectric 800 being wider than the body portion of the wing gate 700.
  • Referring now to FIG. 9, therein is shown the structure of FIG. 8 after implantation to form lightly doped drain/source (LDD) regions 900. It has been further discovered that the overhangs of the gate wings 702 cause the LDD regions 900 to be graded with a dopant concentration gradually increasing away from the gate dielectric 800 and substantially increasing away from the overhang of the gate wings 702.
  • Referring now to FIG. 10, therein is shown the structure of FIG. 9 after removal of the first spacer 400. Where the first spacer 400 is a nitride, a nitride strip is used. After nitride strip, in manufacturing transistors, a further gate processing, an amorphous or polycrystalline silicon re-oxidation, is used to improve transistor lifetimes and gate dielectric reliability due to higher fields occurring at the etched polycrystalline silicon transistor edges.
  • A further spacer material layer (not shown), such as an oxide formed by TEOS deposition, is deposited and etched to form a further spacer 1000. The further spacer 1000 is used for the implantation of source/drain regions 1002. The source/drain regions 1002 and the LDD regions 900 form a three-step source/drain profile.
  • A major problem in the past has been in the formation of the LDD regions of a transistor. Even if the electric field is reduced at the interface between the source/drain regions and gate dielectric, the gate voltage is not applied to the bottom of the conventional sidewall spacer since no gate electrode is formed there. Hence, a strong electric field is still formed in the interface between the source/drain region and the gate dielectric, and this results in generation of the undesirable hot carrier effect. Furthermore, since the conventional gate has no control over the LDD region, the mobility and drive current are reduced due to high parasitic resistance in the LDD region.
  • It has been discovered that by using the inverted-T gate transistor structure, the strong electric field in the interface between the source/drain regions 1002 and the gate dielectric 800 can be reduced so as to improve hot carrier injection (HCI) by reducing the generation of the hot carrier effect. At the same time, the mobility and drive current can be reduced by the elimination of the high parasitic resistance in the LDD region 900.
  • Referring now to FIG. 11, therein is shown the structure of FIG. 10 after salicidation to form silicide 1100 over the source/drain regions 1002 and the wing gate 700.
  • Referring now to FIG. 12, therein is shown the semiconductor device 100 completed in accordance with the present invention to before formation of source/drain and gate contacts. A poly-metal dielectric (PMD) 1200 has been deposited over the structure of FIG. 11, and a fixed-time or end point controlled chemical mechanical polishing (CMP) has been performed to expose the silicide 1100 over the gate wings 702.
  • Referring now to FIG. 13, therein is shown an alternative metal gate embodiment 1300 of the present invention. The structure of FIG. 12 is subject to chemical mechanical polishing (CMP) until the silicide 1100 over the gate body portion 202 is removed. The gate body portion 202 is anisotropically etched for a fixed time, followed by chemical vapor deposition (CVD) of a metal contact 1302, of a material such as Tungsten (W), to be self-aligned over the wing gate 700. A metal CMP is then performed which stops on the PMD 1200.
  • Referring now to FIG. 14, therein is shown a method 1400 for manufacturing the semiconductor device 100 in accordance with the present invention. The method 1400 includes: a block 1402 of forming layers of gate dielectric material, gate material, and cap material on a semiconductor substrate; a block 1404 where the cap material and a portion of the gate material are processed to form a cap and a gate body portion; a block 1406 where a wing is formed on the gate body portion from the remaining portion of the gate material; a block 1408 where the gate dielectric material under a portion of the wing on the gate body portion is removed to form a gate dielectric; and a block 1410 where a lightly-doped source/drain is formed in the semiconductor substrate using the gate body portion and the wing.
  • While the invention has been described in conjunction with a specific best mode, it is to be understood that many alternatives, modifications, and variations will be apparent to those skilled in the art in light of the aforegoing description. Accordingly, it is intended to embrace all such alternatives, modifications, and variations which fall within the scope of the included claims. All matters set forth herein or shown in the accompanying drawings are to be interpreted in an illustrative and non-limiting sense.

Claims (8)

1. A semiconductor device comprising:
a semiconductor substrate;
a gate dielectric on the semiconductor substrate, the gate dielectric having a first width;
a wing gate on the gate dielectric, the wing gate having a body portion narrower than the first width and a gate wing wider than the first width; and
a lightly-doped source/drain region in the semiconductor substrate adjacent the gate dielectric.
2. The semiconductor device as claimed in claim 1 further comprising:
a spacer wider than the first width and positioned around the wing gate; and
a source/drain region in the semiconductor substrate adjacent the spacer and connected to the lightly-doped source/drain region.
3. The semiconductor device as claimed in claim 1 wherein:
the wing gate comprises the gate wing having a rounded tip.
4. The semiconductor device as claimed in claim 1 further comprising:
a metal contact over the wing gate.
5. A semiconductor device comprising:
a silicon substrate;
a gate dielectric on the silicon substrate, the gate dielectric having a first width;
a wing gate on the gate dielectric, the wing gate of amorphous or polycrystalline silicon having a body portion narrower than the first width and a gate wing wider than the first width; and
a lightly-doped source/drain region in the silicon substrate adjacent the gate dielectric.
6. The semiconductor device as claimed in claim 5 further comprising:
an oxide spacer wider than the first width and positioned around the wing gate; and
a source/drain region in the silicon substrate adjacent the oxide spacer and connected to the lightly-doped source/drain region.
7. The semiconductor device as claimed in claim 5 wherein:
the wing gate comprises the gate wing having a rounded tip;
a source/drain region in the silicon substrate connected to the lightly-doped source/drain region; and
an oxide spacer wider than the first width and positioned around the wing gate, the oxide spacer cooperating with the gate wing to form a three-step source/drain profile of the lightly-doped source/drain region and the source/drain region.
8. The semiconductor device as claimed in claim 5 further comprising:
a metal contact over the body portion of the wing gate.
US11/380,378 2004-04-07 2006-04-26 Wing gate transistor for integrated circuits Active 2024-05-30 US7528445B2 (en)

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US20060197088A1 (en) * 2005-03-07 2006-09-07 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method of the same
KR101163224B1 (en) * 2011-02-15 2012-07-06 에스케이하이닉스 주식회사 Method of fabricating dual poly-gate and method of fabricating semiconductor device using the same
US9893060B2 (en) 2015-12-17 2018-02-13 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof

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SG136147A1 (en) 2007-10-29
TW200534470A (en) 2005-10-16

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