US20060104111A1 - Diode array architecture for addressing nanoscale resistive memory arrays - Google Patents

Diode array architecture for addressing nanoscale resistive memory arrays Download PDF

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Publication number
US20060104111A1
US20060104111A1 US10/990,706 US99070604A US2006104111A1 US 20060104111 A1 US20060104111 A1 US 20060104111A1 US 99070604 A US99070604 A US 99070604A US 2006104111 A1 US2006104111 A1 US 2006104111A1
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Prior art keywords
memory cell
conductor
diode
resistive memory
voltage
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US7035141B1 (en
Inventor
Nicholas Tripsas
Colin Bill
Michael VanBuskirk
Matthew Buynoski
Tzu-Ning Fang
Wei Cai
Suzette Pangrle
Steven Avanzino
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Monterey Research LLC
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Spansion LLC
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Priority to US10/990,706 priority Critical patent/US7035141B1/en
Priority to PCT/US2005/041173 priority patent/WO2006055482A1/en
Priority to GB0708857A priority patent/GB2434694B/en
Priority to CN2005800390251A priority patent/CN101057330B/en
Priority to JP2007543155A priority patent/JP4547008B2/en
Priority to KR1020077010971A priority patent/KR20070084213A/en
Priority to DE200511002818 priority patent/DE112005002818B4/en
Priority to TW094139852A priority patent/TWI402840B/en
Publication of US7035141B1 publication Critical patent/US7035141B1/en
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/003—Cell access
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0007—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising metal oxide memory material, e.g. perovskites
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/101—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including resistors or capacitors only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/102—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including bipolar components
    • H01L27/1021—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including bipolar components including diodes only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/50—Resistive cell structure aspects
    • G11C2213/56—Structure including two electrodes, a memory active layer and a so called passive or source or reservoir layer which is NOT an electrode, wherein the passive or source or reservoir layer is a source of ions which migrate afterwards in the memory active layer to be only trapped there, to form conductive filaments there or to react with the material of the memory active layer in redox way
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/72—Array wherein the access device being a diode
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/74—Array wherein each memory cell has more than one access device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/76—Array using an access device for each cell which being not a transistor and not a diode

Definitions

  • This invention relates generally to memory devices, and more particularly, to a memory array incorporating resistive memory cells.
  • memory devices associated with computers and other electronic devices are employed to store and maintain information for the operation thereof.
  • a memory device includes an array of memory cells, wherein each memory cell can be accessed for programming, erasing, and reading thereof.
  • Each memory cell maintains information in an “off” state or an “on” state, also referred to as “0” and “1” respectively, which can be read during the reading step of that memory cell.
  • FIG. 1 illustrates a type of memory cell known as a nanoscale resistive memory cell 30 , which includes advantageous characteristics for meeting these needs.
  • the memory cell 30 includes, for example, a Cu electrode 32 , a superionic layer 34 such as Cu 2 S on the electrode 32 , an active layer 36 such as Cu 2 O or various polymers on the Cu 2 S layer 34 , and a Ti electrode 38 on the active layer 36 .
  • a negative voltage is applied to the electrode 38 , while the electrode 32 is held at ground, so that an electrical potential V pg (the “programming” electrical potential) is applied across the memory cell 30 from a higher to a lower potential in the direction from electrode 32 to electrode 38 (see FIG. 2 , a plot of memory cell current vs. electrical potential applied across the memory cell 30 ).
  • V pg the “programming” electrical potential
  • This potential is sufficient to cause copper ions to be attracted from the superionic layer 34 toward the electrode 38 and into the active layer 36 , causing the active layer 36 (and the overall memory cell 30 ) to be in a low-resistance or conductive state (A).
  • the copper ions drawn into the active layer 36 during the programming step remain therein, so that the active layer 36 (and memory cell 30 ) remain in a conductive or low-resistance state.
  • a positive voltage is applied to the electrode 38 , while the electrode 32 is held at ground, so that an electrical potential V er (the “erase” electrical potential) is applied across the memory cell 30 from a higher to a lower electrical potential in the reverse direction.
  • V er the “erase” electrical potential
  • This potential causes current to flow through the memory cell in the reverse direction (C), and is sufficient to cause copper ions to be repelled from the active layer 36 toward the electrode 32 and into the superionic layer 34 , in turn causing the active layer 36 (and the overall memory cell 30 ) to be in a high-resistance or substantially non-conductive state. This state remains upon removal of such potential from the memory cell 30 .
  • FIG. 2 also illustrates the read step of the memory cell 30 in its programmed (conductive) state and in its erased (nonconductive) state.
  • An electrical potential V r (the “read” electrical potential) is applied across the memory cell 30 from a higher to a lower electrical potential in the same direction as the electrical potential V pg . This electrical potential is less than the electrical potential V pg applied across the memory cell 30 for programming (see above).
  • V r the “read” electrical potential
  • V pg the “read” electrical potential
  • FIGS. 3, 4 and 5 illustrate a memory cell array 40 which incorporates memory cells 30 of the type described above.
  • the memory cell array 40 includes a first plurality 42 of parallel conductors (bit lines) BL 0 , BL 1 , . . . BL n , and a second plurality 44 of parallel conductors (word lines) WL 0 , WL 1 , . . . WL n overlying and spaced from, orthogonal to, and crossing the first plurality of conductors 42 .
  • a plurality of memory cells 30 of the type described above are included, each associated with a select diode 50 having a (forward) threshold V t and a (reverse) breakdown voltage V b , to form a memory cell-diode structure.
  • Each memory cell 30 is connected in series with a select diode 50 between a conductor BL of the first plurality 42 thereof and a conductor WL of the second plurality 44 thereof at the intersection of those conductors, with the diode 50 oriented in a forward direction from the conductor BL of the first plurality 42 thereof to the conductor WL of the second plurality 44 thereof. For example, as shown in FIG.
  • memory cell 30 00 and diode 50 00 in series connect conductor BL 0 of the first plurality of conductors 42 with conductor WL 0 of the second plurality of conductors 44 at the intersection of those conductors BL 0 , WL 0 , memory cell 30 10 and diode 50 10 in series connect conductor BL 1 of the first plurality of conductors 42 with conductor WL 0 of the second plurality of conductors 44 at the intersection of those conductors BL 1 , WL 0 , etc.
  • each of the memory cell-diode structures (other than the selected memory cell 30 00 and diode 50 00 structure) connected to the conductor BL 0 and the conductor WL 0 .
  • Each of the other memory cell-diode structures has applied thereacross, from higher to lower potential in the reverse direction of the diode 50 , an electrical potential which is equal to V pg +V t .
  • This electrical potential is less than the breakdown voltage V b of the diode 50 , and thus no current flows through the associated memory cell.
  • the incorporation of the diodes 50 allows one to properly select and program a memory cell, without disturbing any of the other memory cells in the array.
  • a voltage of for example 0.5(V pg +V t ) is applied to each of the conductors WL 1 , . . . WL n , and each of the conductors BL 1 , . . . BL n .
  • each of the memory cell-diode structures (other than the selected memory cell 30 00 and diode 50 00 structure) connected to the conductor BL 1 and WL 0 .
  • Each of the other memory cell-diode structures has applied thereacross, from higher to lower potential in the reverse direction of the diode 50 , an electrical potential which is equal to V r +V t .
  • This potential V r +V t is less than the breakdown voltage of the diode 50 , so that no current passes through the associated memory cell.
  • FIG. 6 illustrates ideal (G) and actual (H) voltage-current characteristics for a diode of the type incorporated in the memory array of FIGS. 3-5 . It is to be noted that in order to achieve erasing of a selected memory cell, current must be conducted through the selected memory cell, and in order to achieve this conduction of current, the diode associated therewith must be in breakdown.
  • such a diode would have a low threshold voltage (forward direction of the diode) on the order of 0.6 volts, and a low breakdown voltage (reverse direction of the diode) on the order of 2.0 volts, as these voltages would readily allow rapid and effective programming, reading, erasing of a selected cell with relatively low electrical potentials applied thereto, so that a low potential power supply can be used.
  • the breakdown voltage is substantially greater than 2.0 volts (illustrated at in FIG. 6 ), i.e., for example, 4.5 volts or substantially more. This leads to problems in achieving breakdown of the diode, which is essential in erasing the associated memory cell as described above.
  • the present memory structure comprises a first conductor, a second conductor, a resistive memory cell connected to the second conductor, a first diode connected to the resistive memory cell and the first conductor, and oriented in the forward direction from the resistive memory cell to the first conductor, and a second diode connected to the resistive memory cell and the first conductor, in parallel with the first diode, and oriented in the reverse direction from the resistive memory cell to the first conductor.
  • FIG. 1 is a cross-sectional view of a typical resistive memory cell
  • FIG. 2 is a plot of current vs. voltage in the programming, reading and erasing of the memory cell of FIG. 1 ;
  • FIG. 3 is a schematic illustration of a memory array which includes memory cells in accordance with FIG. 1 , illustrating programming of a selected memory cell;
  • FIG. 4 is a schematic illustration of a memory array which includes memory cells in accordance with FIG. 1 , illustrating erasing of a selected memory cell;
  • FIG. 5 is a schematic illustration of a memory array which includes memory cells in accordance with FIG. 1 , illustrating reading of a selected memory cell;
  • FIG. 6 is a plot of current vs. voltage illustrating diode characteristics
  • FIG. 7 is a schematic illustration of the first embodiment of the invention.
  • FIG. 8 is a plot of current vs. voltage for the invention of FIG. 7 and the invention of FIG. 10 ;
  • FIG. 9 is a schematic illustration of a memory array incorporating the invention of FIG. 7 , illustrating programming of a selected memory cell
  • FIG. 10 is a schematic illustration of a memory array incorporating the invention of FIG. 7 , illustrating erasing of a selected memory cell
  • FIG. 11 is a schematic illustration of a memory array incorporating the invention of FIG. 7 , illustrating reading of a selected memory cell.
  • FIG. 7 illustrates an embodiment of the present invention.
  • a conductor BL is shown therein, and a conductor WL overlies, crosses and is spaced from the conductor BL.
  • a structure 60 interconnects the conductor BL and the conductor WL at the intersection thereof.
  • the structure 60 includes a resistive memory cell 130 , similar to the resistive memory cell 30 above, connected to the conductor WL, a first diode 132 connected to the resistive memory cell 130 and the conductor BL, and a second diode 134 also connected to the resistive memory cell 130 and the conductor BL, in parallel with the first diode 132 .
  • the first diode 132 is oriented in the forward direction from the resistive memory cell 130 to the conductor BL
  • the second diode 134 is oriented in the reverse direction from the resistive memory cell 130 to the conductor BL.
  • the two diodes in parallel making up the parallel diode structure 62 connected between the resistive memory cell 130 and the conductor BL have the current-voltage characteristic shown in FIG. 8 .
  • the diode 132 will begin to conduct at its threshold voltage of 0.6 volts, well below the breakdown voltage (4.5 volts) of the diode 134 .
  • the diode 134 will begin to conduct at its threshold voltage of 2.0 volts, well below the breakdown voltage (4.5 volts) of the diode 132 .
  • the parallel diode structure 62 including diodes 132 , 134 in parallel is substantially the equivalent of a single diode having the characteristics shown in FIG. 8 , close to the ideal diode ( FIG. 6 ) as discussed above.
  • FIGS. 9, 10 and 11 illustrate a memory cell array 140 which incorporates memory cells 130 of the type described above.
  • the memory cell array 140 includes a first plurality 142 of parallel conductors (bit lines) BL 0 , BL 1 , . . . BL n , and a second plurality 144 of parallel conductors (word lines) WL 0 , WL 1 , . . . WL n overlying and spaced from, orthogonal to, and crossing the first plurality of conductors 142 .
  • a plurality of structures 60 as set forth above are included, each connecting a conductor BL with a conductor WL at the intersection thereof.
  • Each structure includes a resistive memory cell 130 and a parallel diode structure 62 , connected and configured as described above.
  • memory cell 130 00 and parallel diode structure 62 00 in series connect conductor BL 0 of the first plurality of conductors 142 with conductor WL 0 of the second plurality of conductors 144 at the intersection of those conductors BL 0 , WL 0
  • memory cell 130 10 and parallel diode structure 62 10 in series connect conductor BL 1 of the first plurality of conductors 142 with conductor WL 0 of the second plurality of conductors 144 at the intersection of those conductors BL 1 , WL 0 , etc.
  • This electrical potential is less than the threshold voltage V t2 (2 volts) of the diode 134 (and less than the breakdown voltage V b , 4.5 volts, of the diode 132 ), and thus no current flows through the associated memory cells 130 .
  • V t2 2 volts
  • V b breakdown voltage
  • V b breakdown voltage
  • This potential V r +V t1 1.1 volts is less than the threshold voltage Vt2 (2.0 volts) of the diode 134 (and is less than the breakdown voltage of the diode 132 , 4.5 volts), so that no current passes through the associated memory cell 130 .
  • Vt2 2.0 volts
  • Vt1 the threshold voltage of the diode 134

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  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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  • Microelectronics & Electronic Packaging (AREA)
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Abstract

The present memory structure includes thereof a first conductor, a second conductor, a resistive memory cell connected to the second conductor, a first diode connected to the resistive memory cell and the first conductor, and oriented in the forward direction from the resistive memory cell to the first conductor, and a second diode connected to the resistive memory cell and the first conductor, in parallel with the first diode, and oriented in the reverse direction from the resistive memory cell to the first conductor. The first and second diodes have different threshold voltages

Description

    BACKGROUND OF THE INVENTION
  • 1. Technical Field
  • This invention relates generally to memory devices, and more particularly, to a memory array incorporating resistive memory cells.
  • 2. Background Art
  • Generally, memory devices associated with computers and other electronic devices are employed to store and maintain information for the operation thereof. Typically, such a memory device includes an array of memory cells, wherein each memory cell can be accessed for programming, erasing, and reading thereof. Each memory cell maintains information in an “off” state or an “on” state, also referred to as “0” and “1” respectively, which can be read during the reading step of that memory cell.
  • As such electronic devices continue to be developed and improved, the amount of information required to be stored and maintained continues to increase. FIG. 1 illustrates a type of memory cell known as a nanoscale resistive memory cell 30, which includes advantageous characteristics for meeting these needs. The memory cell 30 includes, for example, a Cu electrode 32, a superionic layer 34 such as Cu2S on the electrode 32, an active layer 36 such as Cu2O or various polymers on the Cu2S layer 34, and a Ti electrode 38 on the active layer 36. Initially, assuming that the memory cell 30 is unprogrammed, in order to program the memory cell 30, a negative voltage is applied to the electrode 38, while the electrode 32 is held at ground, so that an electrical potential Vpg (the “programming” electrical potential) is applied across the memory cell 30 from a higher to a lower potential in the direction from electrode 32 to electrode 38 (see FIG. 2, a plot of memory cell current vs. electrical potential applied across the memory cell 30). This potential is sufficient to cause copper ions to be attracted from the superionic layer 34 toward the electrode 38 and into the active layer 36, causing the active layer 36 (and the overall memory cell 30) to be in a low-resistance or conductive state (A). Upon removal of such potential (B), the copper ions drawn into the active layer 36 during the programming step remain therein, so that the active layer 36 (and memory cell 30) remain in a conductive or low-resistance state.
  • In order to erase the memory cell (FIG. 2), a positive voltage is applied to the electrode 38, while the electrode 32 is held at ground, so that an electrical potential Ver (the “erase” electrical potential) is applied across the memory cell 30 from a higher to a lower electrical potential in the reverse direction. This potential causes current to flow through the memory cell in the reverse direction (C), and is sufficient to cause copper ions to be repelled from the active layer 36 toward the electrode 32 and into the superionic layer 34, in turn causing the active layer 36 (and the overall memory cell 30) to be in a high-resistance or substantially non-conductive state. This state remains upon removal of such potential from the memory cell 30.
  • FIG. 2 also illustrates the read step of the memory cell 30 in its programmed (conductive) state and in its erased (nonconductive) state. An electrical potential Vr (the “read” electrical potential) is applied across the memory cell 30 from a higher to a lower electrical potential in the same direction as the electrical potential Vpg. This electrical potential is less than the electrical potential Vpg applied across the memory cell 30 for programming (see above). In this situation, if the memory cell 30 is programmed, the memory cell 30 will readily conduct current (level L1), indicating that the memory cell 30 is in its programmed state. If the memory cell 30 is erased, the memory cell 30 will not conduct current (level L2), indicating that the memory cell 30 is in its erased state.
  • FIGS. 3, 4 and 5 illustrate a memory cell array 40 which incorporates memory cells 30 of the type described above. As illustrated in FIG. 3, the memory cell array 40 includes a first plurality 42 of parallel conductors (bit lines) BL0, BL1, . . . BLn, and a second plurality 44 of parallel conductors (word lines) WL0, WL1, . . . WLn overlying and spaced from, orthogonal to, and crossing the first plurality of conductors 42. A plurality of memory cells 30 of the type described above are included, each associated with a select diode 50 having a (forward) threshold Vt and a (reverse) breakdown voltage Vb, to form a memory cell-diode structure. Each memory cell 30 is connected in series with a select diode 50 between a conductor BL of the first plurality 42 thereof and a conductor WL of the second plurality 44 thereof at the intersection of those conductors, with the diode 50 oriented in a forward direction from the conductor BL of the first plurality 42 thereof to the conductor WL of the second plurality 44 thereof. For example, as shown in FIG. 3, memory cell 30 00 and diode 50 00 in series connect conductor BL0 of the first plurality of conductors 42 with conductor WL0 of the second plurality of conductors 44 at the intersection of those conductors BL0, WL0, memory cell 30 10 and diode 50 10 in series connect conductor BL1 of the first plurality of conductors 42 with conductor WL0 of the second plurality of conductors 44 at the intersection of those conductors BL1, WL0, etc.
  • In order to program a selected memory cell (FIG. 3), for example selected memory cell 30 00, the voltage applied to the conductor BL0 is selected as (Vpg+Vt) greater than the voltage (0) applied to the conductor WL0, where Vpg is as defined above and Vt=(forward) threshold voltage of diode 50 00. Additionally, this same voltage Vpg+Vt is applied to each of the conductors WL1, . . . WLn, and zero voltage is applied to each of the conductors BL1, . . . BLn. This results in zero potential being applied across each of the memory cell-diode structures (other than the selected memory cell 30 00 and diode 50 00 structure) connected to the conductor BL0 and the conductor WL0. Each of the other memory cell-diode structures has applied thereacross, from higher to lower potential in the reverse direction of the diode 50, an electrical potential which is equal to Vpg+Vt. This electrical potential is less than the breakdown voltage Vb of the diode 50, and thus no current flows through the associated memory cell. Thus, the incorporation of the diodes 50 allows one to properly select and program a memory cell, without disturbing any of the other memory cells in the array.
  • In order to erase a selected memory cell (FIG. 4), for example selected memory cell 30 00, the voltage applied to the conductor WL0 is (Ver+Vb) greater than the voltage (0) applied to the conductor BL0, where Ver is as defined above and Vb=(reverse) breakdown voltage of diode 50 00. Additionally, a voltage of for example 0.5(Vpg+Vt) is applied to each of the conductors WL1, . . . WLn, and each of the conductors BL1, . . . BLn. This results a potential of 0.5(Vpg+Vt) being applied across each of the diode-memory cell structures (other than the selected memory cell 30 00 and diode 50 00 structure) connected to the conductor BL0 and the conductor WL0, from higher to lower potential in the reverse direction of the diode 50. This electrical potential 0.5(Vpg+Vt) is less than the breakdown voltage Vb of the diode 50, and thus no current will flow through the associated memory cell. Each of the other memory cell-diode structures has applied thereacross an electrical potential of zero. Similar to the above, the incorporation of the diodes 50 allows one to properly select and erase a memory cell, without disturbing any of the other memory cells in the array.
  • In order to read a selected memory cell (FIG. 5), for example selected memory cell 30 00, the voltage applied to the conductor BL0 is (Vr+Vt) greater than the voltage (0) applied to the conductor WL0, where Vr is as defined above and Vt=threshold voltage of diode 50 00). Additionally, a voltage of Vr+Vt is applied to each of the conductors WL1, . . . WLn, and zero voltage is applied to each of the conductors BL1, . . . BLn. This results in zero potential applied across each of the memory cell-diode structures (other than the selected memory cell 30 00 and diode 50 00 structure) connected to the conductor BL1 and WL0. Each of the other memory cell-diode structures has applied thereacross, from higher to lower potential in the reverse direction of the diode 50, an electrical potential which is equal to Vr+Vt. This potential Vr+Vt is less than the breakdown voltage of the diode 50, so that no current passes through the associated memory cell. Thus, the incorporation of the diodes 50 allows one to properly select and read a memory cell, without disturbing or otherwise influencing any of the other memory cells in the array.
  • FIG. 6 illustrates ideal (G) and actual (H) voltage-current characteristics for a diode of the type incorporated in the memory array of FIGS. 3-5. It is to be noted that in order to achieve erasing of a selected memory cell, current must be conducted through the selected memory cell, and in order to achieve this conduction of current, the diode associated therewith must be in breakdown. Ideally, such a diode would have a low threshold voltage (forward direction of the diode) on the order of 0.6 volts, and a low breakdown voltage (reverse direction of the diode) on the order of 2.0 volts, as these voltages would readily allow rapid and effective programming, reading, erasing of a selected cell with relatively low electrical potentials applied thereto, so that a low potential power supply can be used.
  • However, in reality, while a typical diode may indeed have a threshold voltage on then order of 0.6 volts, the breakdown voltage is substantially greater than 2.0 volts (illustrated at in FIG. 6), i.e., for example, 4.5 volts or substantially more. This leads to problems in achieving breakdown of the diode, which is essential in erasing the associated memory cell as described above.
  • Therefore, what is needed is an approach wherein the ideal characteristics described above are achieved.
    • DISCLOSURE OF THE INVENTION
  • Broadly stated, the present memory structure comprises a first conductor, a second conductor, a resistive memory cell connected to the second conductor, a first diode connected to the resistive memory cell and the first conductor, and oriented in the forward direction from the resistive memory cell to the first conductor, and a second diode connected to the resistive memory cell and the first conductor, in parallel with the first diode, and oriented in the reverse direction from the resistive memory cell to the first conductor.
  • The present invention is better understood upon consideration of the detailed description below, in conjunction with the accompanying drawings. As will become readily apparent to those skilled in the art from the following description, there is shown and described an embodiment of this invention simply by way of the illustration of the best mode to carry out the invention. As will be realized, the invention is capable of other embodiments and its several details are capable of modifications and various obvious aspects, all without departing from the scope of the invention. Accordingly, the drawings and detailed description will be regarded as illustrative in nature and not as restrictive.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The novel features believed characteristic of the invention are set forth in the appended claims. The invention itself, however, as well as said preferred mode of use, and further objects and advantages thereof, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein:
  • FIG. 1 is a cross-sectional view of a typical resistive memory cell;
  • FIG. 2 is a plot of current vs. voltage in the programming, reading and erasing of the memory cell of FIG. 1;
  • FIG. 3 is a schematic illustration of a memory array which includes memory cells in accordance with FIG. 1, illustrating programming of a selected memory cell;
  • FIG. 4 is a schematic illustration of a memory array which includes memory cells in accordance with FIG. 1, illustrating erasing of a selected memory cell;
  • FIG. 5 is a schematic illustration of a memory array which includes memory cells in accordance with FIG. 1, illustrating reading of a selected memory cell;
  • FIG. 6 is a plot of current vs. voltage illustrating diode characteristics;
  • FIG. 7 is a schematic illustration of the first embodiment of the invention;
  • FIG. 8 is a plot of current vs. voltage for the invention of FIG. 7 and the invention of FIG. 10;
  • FIG. 9 is a schematic illustration of a memory array incorporating the invention of FIG. 7, illustrating programming of a selected memory cell;
  • FIG. 10 is a schematic illustration of a memory array incorporating the invention of FIG. 7, illustrating erasing of a selected memory cell; and
  • FIG. 11 is a schematic illustration of a memory array incorporating the invention of FIG. 7, illustrating reading of a selected memory cell.
    • BEST MODE(S) FOR CARRYING OUT THE INVENTION
  • Reference is now made in detail to a specific embodiment of the present invention which illustrates the best mode presently contemplated by the inventors for practicing the invention.
  • FIG. 7 illustrates an embodiment of the present invention. A conductor BL is shown therein, and a conductor WL overlies, crosses and is spaced from the conductor BL. A structure 60 interconnects the conductor BL and the conductor WL at the intersection thereof. The structure 60 includes a resistive memory cell 130, similar to the resistive memory cell 30 above, connected to the conductor WL, a first diode 132 connected to the resistive memory cell 130 and the conductor BL, and a second diode 134 also connected to the resistive memory cell 130 and the conductor BL, in parallel with the first diode 132. The first diode 132 is oriented in the forward direction from the resistive memory cell 130 to the conductor BL, and the second diode 134 is oriented in the reverse direction from the resistive memory cell 130 to the conductor BL. The diodes 132,134 are selected to have different (forward) threshold voltages, for example, diode 132 has threshold voltage Vt1=0.6 volts, while diode 134 has threshold voltage Vt2=2.0 volts. Both diodes 132 and 134 have (reverse) breakdown voltages of Vb=4.5 volts as previously described. When considered as a unit, the two diodes in parallel making up the parallel diode structure 62 connected between the resistive memory cell 130 and the conductor BL have the current-voltage characteristic shown in FIG. 8. In the direction from the conductor BL to the resistive memory cell 130, the diode 132 will begin to conduct at its threshold voltage of 0.6 volts, well below the breakdown voltage (4.5 volts) of the diode 134. In the direction from the memory cell 130 to the conductor BL, the diode 134 will begin to conduct at its threshold voltage of 2.0 volts, well below the breakdown voltage (4.5 volts) of the diode 132. The net result is that the parallel diode structure 62 including diodes 132,134 in parallel is substantially the equivalent of a single diode having the characteristics shown in FIG. 8, close to the ideal diode (FIG. 6) as discussed above.
  • FIGS. 9, 10 and 11 illustrate a memory cell array 140 which incorporates memory cells 130 of the type described above. As illustrated in FIG. 9, the memory cell array 140 includes a first plurality 142 of parallel conductors (bit lines) BL0, BL1, . . . BLn, and a second plurality 144 of parallel conductors (word lines) WL0, WL1, . . . WLn overlying and spaced from, orthogonal to, and crossing the first plurality of conductors 142. A plurality of structures 60 as set forth above are included, each connecting a conductor BL with a conductor WL at the intersection thereof. Each structure includes a resistive memory cell 130 and a parallel diode structure 62, connected and configured as described above. For example, as shown in FIG. 9, memory cell 130 00 and parallel diode structure 62 00 in series connect conductor BL0 of the first plurality of conductors 142 with conductor WL0 of the second plurality of conductors 144 at the intersection of those conductors BL0, WL0, memory cell 130 10 and parallel diode structure 62 10 in series connect conductor BL1 of the first plurality of conductors 142 with conductor WL0 of the second plurality of conductors 144 at the intersection of those conductors BL1, WL0, etc.
  • In order to program a selected memory cell (FIG. 9), for example selected memory cell 130 00, the voltage applied to the conductor BL0 is selected as (Vpg+Vt1) greater than the voltage (0) applied to the conductor WL0, where Vpg, as defined above, is in this embodiment 1.0 volts, and Vt1, (forward) threshold voltage of diode=0.6 volts, so that Vpg+Vt1=1.6 volts. Additionally, this same voltage Vpg+Vt1 of 1.6 volts is applied to each of the conductors WL1, . . . WLn, and zero voltage is applied to each of the conductors BL1, . . . BLn. This results in zero potential being applied across each of the structures 60 (other than the structure 60 00) connected to the conductor BL0 and the conductor WL0. Each of the other structures 60 in the array 140 has applied thereacross, from higher to lower potential in the direction from conductor WL to conductor BL, an electrical potential which is equal to Vpg+Vt1=1.6 volts. This electrical potential is less than the threshold voltage Vt2 (2 volts) of the diode 134 (and less than the breakdown voltage Vb, 4.5 volts, of the diode 132), and thus no current flows through the associated memory cells 130. Thus, the incorporation of the diode structure 60 allows one to properly select and program a memory cell, without disturbing or otherwise influencing any of the other memory cells in the array.
  • In order to erase a selected memory cell (FIG. 10), for example selected memory cell 130 00, the voltage applied to the conductor WL0 is (Ver+Vt2) greater than the voltage (0) applied to the conductor BL0, where Ver is as defined above and is in this embodiment 1.0 volts, and Vt2, the threshold voltage of the diode, is 2.0 volts, so that Ver+Vt2=3.0 volts. Additionally, a voltage of for example 0.5(Vpg+Vt2)=1.5 volts is applied to each of the conductors WL1, . . . WLn, and each of the conductors BL1, . . . . BLn. This results in a potential of 1.5 volts being applied across each of the structures 60 (other than the structure 60 00) connected to the conductor BL0 and the conductor WL0, from higher to lower potential in the direction from conductor WL to conductor BL. This electrical potential of 1.5 volts is less than the threshold voltage Vt2 (2.0 volts) of the diode 134 (and less than the breakdown voltage Vb, 4.5 volts, of the diode 132), and thus no current will flow through the other memory cells 130 associated with conductor BL0 and conductor WL0. Each of the other structures 60 in the array 140 has applied thereacross an electrical potential of zero. Similar to the above, the incorporation of the diode structure 62 allows one to properly select and erase a memory cell, without disturbing any of the other memory cells in the array.
  • In order to read a selected memory cell (FIG. 11), for example selected memory cell 130 00, the voltage applied to the conductor BL0 is (Vr+Vt1) greater than the voltage (0) applied to the conductor WL0, where Vr is as defined above and in this example equals 0.5 volts and Vt1=threshold voltage of diode 132 00, i.e., 0.6 volts, so that Vr+Vt1=1.1 volts. Additionally, a voltage of Vr+Vt1=1.1 volts is applied to each of the conductors WL1, . . . WLn, and zero voltage is applied to each of the conductors BL1, . . . BLn. This results in zero potential applied across each of the structures 60 (other than the structure 60 00) connected to the conductor BL1 and WL0. Each of the other structures 60 of the array has applied thereacross, from higher to lower potential in the direction from conductor WL to conductor BL, an electrical potential which is equal to Vr+Vt1. This potential Vr+Vt1=1.1 volts is less than the threshold voltage Vt2 (2.0 volts) of the diode 134 (and is less than the breakdown voltage of the diode 132, 4.5 volts), so that no current passes through the associated memory cell 130. Thus, the incorporation of the diode structure 62 allows one to properly select and read a memory cell, without disturbing any of the other memory cells in the array.
  • It will be seen that a highly efficient and effective approach for programming, erasing and reading resistive memory cells is provided. Of particular importance is the achievement of a diode structure which incorporates an ideal characteristic for threshold voltage and breakdown voltage thereof.
  • The foregoing description of the embodiment of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Other modifications or variations are possible in light of the above teachings.
  • The embodiment was chosen and described to provide the best illustration of the principles of the invention and its practical application to thereby enable one of ordinary skill of the art to utilize the invention in various embodiments and with various modifications as are suited to the particular use contemplated. All such modifications and variations are within the scope of the invention as determined by the appended claims when interpreted in accordance with the breadth to which they are fairly, legally and equitably entitled.

Claims (8)

1. (canceled)
2. A memory structure comprising:
a first conductor;
a second conductor;
a resistive memory cell connected to the second conductor;
a first diode connected to the resistive memory cell and the first conductor, and oriented in the forward direction from the resistive memory cell to the first conductor; and
a second diode connected to the resistive memory cell and the first conductor, in parallel with the first diode, and oriented in the reverse direction from the resistive memory cell to the first conductor;
wherein the first and second diodes have different threshold voltages.
3. (canceled)
4. A memory structure comprising:
a first conductor;
a second conductor;
a memory cell connected to the second conductor;
a first diode connected to the memory cell and the first conductor; and
a second diode connected to the memory cell and the first conductor, in parallel with the first diode;
wherein the first and second diodes have different threshold voltages.
5. The memory structure of claim 4 wherein the first diode is oriented in the forward direction from the memory cell to the first conductor, and the second diode is oriented in the reverse direction from the memory cell to the first conductor.
6. The memory structure of claim 4 wherein the memory cell is a resistive memory cell.
7. (canceled)
8. A memory array comprising;
a first plurality of conductors;
a second plurality of conductors, and;
a plurality of memory structures, each connecting a conductor of the first plurality thereof with a conductor of the second plurality thereof, each memory structure comprising;
a resistive memory cell connected to a conductor of the second plurality thereof;
a first diode connected to the resistive memory cell and a conductor of the first plurality thereof, and oriented in the forward direction from the resistive memory cell to the conductor of the first plurality thereof; and
a second diode connected to the resistive memory cell and the conductor of the first plurality thereof, in parallel with the first diode, and oriented in the reverse direction from the resistive memory cell to the conductor of the first plurality thereof;
wherein the first and second diodes have different threshold voltages.
US10/990,706 2004-11-17 2004-11-17 Diode array architecture for addressing nanoscale resistive memory arrays Active US7035141B1 (en)

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GB0708857A GB2434694B (en) 2004-11-17 2005-11-10 Diode array architecture for addressing nanoscale resistive memory arrays
CN2005800390251A CN101057330B (en) 2004-11-17 2005-11-10 Diode array architecture for addressing nanoscale resistive memory arrays
JP2007543155A JP4547008B2 (en) 2004-11-17 2005-11-10 Diode array architecture for handling nanoscale resistive memory arrays
KR1020077010971A KR20070084213A (en) 2004-11-17 2005-11-10 Diode array architecture for addressing nanoscale resistive memory arrays
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Cited By (65)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060221713A1 (en) * 2005-03-31 2006-10-05 Spansion Llc Write-once read-many times memory
US20080130392A1 (en) * 2006-12-05 2008-06-05 Spansion Llc Method of erasing a resistive memory device
US20090180310A1 (en) * 2008-01-11 2009-07-16 Naoharu Shimomura Resistance change type memory
US20100003782A1 (en) * 2008-07-02 2010-01-07 Nishant Sinha Methods Of Forming A Non-Volatile Resistive Oxide Memory Cell And Methods Of Forming A Non-Volatile Resistive Oxide Memory Array
US20100118602A1 (en) * 2008-11-13 2010-05-13 Seagate Technology Llc Double source line-based memory array and memory cells thereof
US20120057391A1 (en) * 2008-01-15 2012-03-08 Jun Liu Memory Cells, Memory Cell Programming Methods, Memory Cell Reading Methods, Memory Cell Operating Methods, and Memory Devices
US8411477B2 (en) 2010-04-22 2013-04-02 Micron Technology, Inc. Arrays of vertically stacked tiers of non-volatile cross point memory cells, methods of forming arrays of vertically stacked tiers of non-volatile cross point memory cells, and methods of reading a data value stored by an array of vertically stacked tiers of non-volatile cross point memory cells
US8427859B2 (en) 2010-04-22 2013-04-23 Micron Technology, Inc. Arrays of vertically stacked tiers of non-volatile cross point memory cells, methods of forming arrays of vertically stacked tiers of non-volatile cross point memory cells, and methods of reading a data value stored by an array of vertically stacked tiers of non-volatile cross point memory cells
US8431458B2 (en) 2010-12-27 2013-04-30 Micron Technology, Inc. Methods of forming a nonvolatile memory cell and methods of forming an array of nonvolatile memory cells
US8559208B2 (en) 2010-08-20 2013-10-15 Shine C. Chung Programmably reversible resistive device cells using polysilicon diodes
US8674336B2 (en) 2008-04-08 2014-03-18 Micron Technology, Inc. Non-volatile resistive oxide memory cells, non-volatile resistive oxide memory arrays, and methods of forming non-volatile resistive oxide memory cells and memory arrays
US8681531B2 (en) 2011-02-24 2014-03-25 Micron Technology, Inc. Memory cells, methods of forming memory cells, and methods of programming memory cells
US8753949B2 (en) 2010-11-01 2014-06-17 Micron Technology, Inc. Nonvolatile memory cells and methods of forming nonvolatile memory cells
US8759809B2 (en) 2010-10-21 2014-06-24 Micron Technology, Inc. Integrated circuitry comprising nonvolatile memory cells having platelike electrode and ion conductive material layer
US8791447B2 (en) 2011-01-20 2014-07-29 Micron Technology, Inc. Arrays of nonvolatile memory cells and methods of forming arrays of nonvolatile memory cells
US8804398B2 (en) 2010-08-20 2014-08-12 Shine C. Chung Reversible resistive memory using diodes formed in CMOS processes as program selectors
US8811063B2 (en) 2010-11-01 2014-08-19 Micron Technology, Inc. Memory cells, methods of programming memory cells, and methods of forming memory cells
US8830720B2 (en) 2010-08-20 2014-09-09 Shine C. Chung Circuit and system of using junction diode as program selector and MOS as read selector for one-time programmable devices
US8848423B2 (en) 2011-02-14 2014-09-30 Shine C. Chung Circuit and system of using FinFET for building programmable resistive devices
US8854863B2 (en) 2011-04-15 2014-10-07 Micron Technology, Inc. Arrays of nonvolatile memory cells and methods of forming arrays of nonvolatile memory cells
US8861249B2 (en) 2012-02-06 2014-10-14 Shine C. Chung Circuit and system of a low density one-time programmable memory
US8912576B2 (en) 2011-11-15 2014-12-16 Shine C. Chung Structures and techniques for using semiconductor body to construct bipolar junction transistors
US8913415B2 (en) 2010-08-20 2014-12-16 Shine C. Chung Circuit and system for using junction diode as program selector for one-time programmable devices
US8913449B2 (en) 2012-03-11 2014-12-16 Shine C. Chung System and method of in-system repairs or configurations for memories
US8917533B2 (en) 2012-02-06 2014-12-23 Shine C. Chung Circuit and system for testing a one-time programmable (OTP) memory
US8923085B2 (en) 2010-11-03 2014-12-30 Shine C. Chung Low-pin-count non-volatile memory embedded in a integrated circuit without any additional pins for access
US8976566B2 (en) 2010-09-29 2015-03-10 Micron Technology, Inc. Electronic devices, memory devices and memory arrays
US8988965B2 (en) 2010-11-03 2015-03-24 Shine C. Chung Low-pin-count non-volatile memory interface
US9007804B2 (en) 2012-02-06 2015-04-14 Shine C. Chung Circuit and system of protective mechanisms for programmable resistive memories
US9019791B2 (en) 2010-11-03 2015-04-28 Shine C. Chung Low-pin-count non-volatile memory interface for 3D IC
US9019742B2 (en) 2010-08-20 2015-04-28 Shine C. Chung Multiple-state one-time programmable (OTP) memory to function as multi-time programmable (MTP) memory
US9025357B2 (en) 2010-08-20 2015-05-05 Shine C. Chung Programmable resistive memory unit with data and reference cells
US9042153B2 (en) 2010-08-20 2015-05-26 Shine C. Chung Programmable resistive memory unit with multiple cells to improve yield and reliability
US9070437B2 (en) 2010-08-20 2015-06-30 Shine C. Chung Circuit and system of using junction diode as program selector for one-time programmable devices with heat sink
US9076526B2 (en) 2012-09-10 2015-07-07 Shine C. Chung OTP memories functioning as an MTP memory
US9111788B2 (en) 2008-06-18 2015-08-18 Micron Technology, Inc. Memory device constructions, memory cell forming methods, and semiconductor construction forming methods
US9136261B2 (en) 2011-11-15 2015-09-15 Shine C. Chung Structures and techniques for using mesh-structure diodes for electro-static discharge (ESD) protection
US9183897B2 (en) 2012-09-30 2015-11-10 Shine C. Chung Circuits and methods of a self-timed high speed SRAM
US9224496B2 (en) 2010-08-11 2015-12-29 Shine C. Chung Circuit and system of aggregated area anti-fuse in CMOS processes
US9236141B2 (en) 2010-08-20 2016-01-12 Shine C. Chung Circuit and system of using junction diode of MOS as program selector for programmable resistive devices
US9251893B2 (en) 2010-08-20 2016-02-02 Shine C. Chung Multiple-bit programmable resistive memory using diode as program selector
US9324849B2 (en) 2011-11-15 2016-04-26 Shine C. Chung Structures and techniques for using semiconductor body to construct SCR, DIAC, or TRIAC
US9324447B2 (en) 2012-11-20 2016-04-26 Shine C. Chung Circuit and system for concurrently programming multiple bits of OTP memory devices
US9412473B2 (en) 2014-06-16 2016-08-09 Shine C. Chung System and method of a novel redundancy scheme for OTP
US9412421B2 (en) 2010-06-07 2016-08-09 Micron Technology, Inc. Memory arrays
US9431127B2 (en) 2010-08-20 2016-08-30 Shine C. Chung Circuit and system of using junction diode as program selector for metal fuses for one-time programmable devices
US9454997B2 (en) 2010-12-02 2016-09-27 Micron Technology, Inc. Array of nonvolatile memory cells having at least five memory cells per unit cell, having a plurality of the unit cells which individually comprise three elevational regions of programmable material, and/or having a continuous volume having a combination of a plurality of vertically oriented memory cells and a plurality of horizontally oriented memory cells; array of vertically stacked tiers of nonvolatile memory cells
US9460807B2 (en) 2010-08-20 2016-10-04 Shine C. Chung One-time programmable memory devices using FinFET technology
US9496033B2 (en) 2010-08-20 2016-11-15 Attopsemi Technology Co., Ltd Method and system of programmable resistive devices with read capability using a low supply voltage
US9496265B2 (en) 2010-12-08 2016-11-15 Attopsemi Technology Co., Ltd Circuit and system of a high density anti-fuse
US9577186B2 (en) 2008-05-02 2017-02-21 Micron Technology, Inc. Non-volatile resistive oxide memory cells and methods of forming non-volatile resistive oxide memory cells
US9711237B2 (en) 2010-08-20 2017-07-18 Attopsemi Technology Co., Ltd. Method and structure for reliable electrical fuse programming
US9818478B2 (en) 2012-12-07 2017-11-14 Attopsemi Technology Co., Ltd Programmable resistive device and memory using diode as selector
US9824768B2 (en) 2015-03-22 2017-11-21 Attopsemi Technology Co., Ltd Integrated OTP memory for providing MTP memory
US10192615B2 (en) 2011-02-14 2019-01-29 Attopsemi Technology Co., Ltd One-time programmable devices having a semiconductor fin structure with a divided active region
US10229746B2 (en) 2010-08-20 2019-03-12 Attopsemi Technology Co., Ltd OTP memory with high data security
US10249379B2 (en) 2010-08-20 2019-04-02 Attopsemi Technology Co., Ltd One-time programmable devices having program selector for electrical fuses with extended area
US10535413B2 (en) 2017-04-14 2020-01-14 Attopsemi Technology Co., Ltd Low power read operation for programmable resistive memories
US10586832B2 (en) 2011-02-14 2020-03-10 Attopsemi Technology Co., Ltd One-time programmable devices using gate-all-around structures
US10726914B2 (en) 2017-04-14 2020-07-28 Attopsemi Technology Co. Ltd Programmable resistive memories with low power read operation and novel sensing scheme
US10770160B2 (en) 2017-11-30 2020-09-08 Attopsemi Technology Co., Ltd Programmable resistive memory formed by bit slices from a standard cell library
US10916317B2 (en) 2010-08-20 2021-02-09 Attopsemi Technology Co., Ltd Programmable resistance memory on thin film transistor technology
US10923204B2 (en) 2010-08-20 2021-02-16 Attopsemi Technology Co., Ltd Fully testible OTP memory
US11062786B2 (en) 2017-04-14 2021-07-13 Attopsemi Technology Co., Ltd One-time programmable memories with low power read operation and novel sensing scheme
US11615859B2 (en) 2017-04-14 2023-03-28 Attopsemi Technology Co., Ltd One-time programmable memories with ultra-low power read operation and novel sensing scheme

Families Citing this family (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7450416B1 (en) * 2004-12-23 2008-11-11 Spansion Llc Utilization of memory-diode which may have each of a plurality of different memory states
US7379317B2 (en) * 2004-12-23 2008-05-27 Spansion Llc Method of programming, reading and erasing memory-diode in a memory-diode array
US7145824B2 (en) * 2005-03-22 2006-12-05 Spansion Llc Temperature compensation of thin film diode voltage threshold in memory sensing circuit
US7564708B2 (en) * 2006-12-05 2009-07-21 Spansion Llc Method of programming memory device
US8487450B2 (en) * 2007-05-01 2013-07-16 Micron Technology, Inc. Semiconductor constructions comprising vertically-stacked memory units that include diodes utilizing at least two different dielectric materials, and electronic systems
US8987702B2 (en) 2007-05-01 2015-03-24 Micron Technology, Inc. Selectively conducting devices, diode constructions, constructions, and diode forming methods
KR100904737B1 (en) * 2007-12-20 2009-06-26 주식회사 하이닉스반도체 Semiconductor memory device having threshold voltage switching device and method for storing data therein
US20090185410A1 (en) * 2008-01-22 2009-07-23 Grandis, Inc. Method and system for providing spin transfer tunneling magnetic memories utilizing unidirectional polarity selection devices
US8120951B2 (en) * 2008-05-22 2012-02-21 Micron Technology, Inc. Memory devices, memory device constructions, constructions, memory device forming methods, current conducting devices, and memory cell programming methods
US8134194B2 (en) * 2008-05-22 2012-03-13 Micron Technology, Inc. Memory cells, memory cell constructions, and memory cell programming methods
US7733685B2 (en) * 2008-07-09 2010-06-08 Sandisk 3D Llc Cross point memory cell with distributed diodes and method of making same
US8014185B2 (en) * 2008-07-09 2011-09-06 Sandisk 3D Llc Multiple series passive element matrix cell for three-dimensional arrays
US7923812B2 (en) * 2008-12-19 2011-04-12 Sandisk 3D Llc Quad memory cell and method of making same
US7910407B2 (en) * 2008-12-19 2011-03-22 Sandisk 3D Llc Quad memory cell and method of making same
KR101098302B1 (en) * 2009-09-30 2011-12-26 주식회사 하이닉스반도체 Method For Fabricating Spin Transfer Torque Random Access Memory Device
KR20110061912A (en) * 2009-12-02 2011-06-10 삼성전자주식회사 Nonvolatile memory cell and nonvolatile memory device including the same
KR20110074354A (en) * 2009-12-24 2011-06-30 삼성전자주식회사 Memory device and method of operating the same
TWI452680B (en) * 2010-08-20 2014-09-11 Chien Shine Chung Phase-change memory, electronics system, reversible resistive memory and method for providing the same
US8638590B2 (en) 2010-09-28 2014-01-28 Qualcomm Incorporated Resistance based memory having two-diode access device
US9305644B2 (en) 2011-06-24 2016-04-05 Rambus Inc. Resistance memory cell
KR101634194B1 (en) * 2011-10-12 2016-06-28 휴렛 팩커드 엔터프라이즈 디벨롭먼트 엘피 Select device for cross point memory structures
US8941089B2 (en) 2012-02-22 2015-01-27 Adesto Technologies Corporation Resistive switching devices and methods of formation thereof
JP6107472B2 (en) * 2012-06-28 2017-04-05 凸版印刷株式会社 Nonvolatile memory cell and nonvolatile memory including the nonvolatile memory cell
CN103579238A (en) * 2012-08-10 2014-02-12 中国科学院微电子研究所 Memorizer device
US9076523B2 (en) * 2012-12-13 2015-07-07 Intermolecular, Inc. Methods of manufacturing embedded bipolar switching resistive memory
US9373786B1 (en) 2013-01-23 2016-06-21 Adesto Technologies Corporation Two terminal resistive access devices and methods of formation thereof
TWI493548B (en) 2013-01-31 2015-07-21 Ind Tech Res Inst Configurable logic block and operation method thereof
JP6163817B2 (en) * 2013-03-26 2017-07-19 凸版印刷株式会社 Nonvolatile memory cell and nonvolatile memory
JP6232821B2 (en) * 2013-08-07 2017-11-22 凸版印刷株式会社 Nonvolatile flip-flop, nonvolatile latch, and nonvolatile memory element
KR20160137148A (en) 2015-05-22 2016-11-30 에스케이하이닉스 주식회사 Electronic device
US10991756B2 (en) 2018-10-23 2021-04-27 Taiwan Semiconductor Manufacturing Co., Ltd. Bipolar selector with independently tunable threshold voltages
US11107859B2 (en) 2019-08-05 2021-08-31 Taiwan Semiconductor Manufacturing Company, Ltd. Memory cell with unipolar selectors
FR3117258B1 (en) * 2020-12-07 2023-12-22 Commissariat Energie Atomique SELECTOR DEVICE, RESISTIVE TYPE MEMORY DEVICE AND ASSOCIATED MANUFACTURING METHOD

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6937528B2 (en) * 2002-03-05 2005-08-30 Micron Technology, Inc. Variable resistance memory and method for sensing same

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4715685A (en) * 1985-03-04 1987-12-29 Energy Conversion Devices, Inc. Liquid crystal display having potential source in a diode ring
JP3035331B2 (en) * 1990-11-15 2000-04-24 オリンパス光学工業株式会社 Memory cell and memory device
US5818749A (en) * 1993-08-20 1998-10-06 Micron Technology, Inc. Integrated circuit memory device
US5825687A (en) * 1996-12-04 1998-10-20 Yin; Ronald Loh-Hwa Low voltage memory cell, circuit array formed thereby and method of operation therefor
WO2003028124A1 (en) * 2001-09-25 2003-04-03 Japan Science And Technology Agency Electric device comprising solid electrolyte
US6909656B2 (en) * 2002-01-04 2005-06-21 Micron Technology, Inc. PCRAM rewrite prevention
US20030218905A1 (en) * 2002-05-22 2003-11-27 Perner Frederick A. Equi-potential sensing magnetic random access memory (MRAM) with series diodes
US6847047B2 (en) * 2002-11-04 2005-01-25 Advanced Micro Devices, Inc. Methods that facilitate control of memory arrays utilizing zener diode-like devices
JP4377817B2 (en) * 2003-03-18 2009-12-02 株式会社東芝 Programmable resistance memory device
TWI310237B (en) * 2006-10-27 2009-05-21 Macronix Int Co Ltd Methods of operating a bistable resistance random access memory with multiple memory layers and multilevel memory states
US7813167B2 (en) * 2008-03-21 2010-10-12 Micron Technology, Inc. Memory cell
US7551473B2 (en) * 2007-10-12 2009-06-23 Macronix International Co., Ltd. Programmable resistive memory with diode structure
US7729163B2 (en) * 2008-03-26 2010-06-01 Micron Technology, Inc. Phase change memory
US8431923B2 (en) * 2011-02-07 2013-04-30 Micron Technology, Inc. Semiconductor structure and semiconductor device including a diode structure and methods of forming same

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6937528B2 (en) * 2002-03-05 2005-08-30 Micron Technology, Inc. Variable resistance memory and method for sensing same

Cited By (127)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060221713A1 (en) * 2005-03-31 2006-10-05 Spansion Llc Write-once read-many times memory
US8098521B2 (en) * 2005-03-31 2012-01-17 Spansion Llc Method of providing an erase activation energy of a memory device
US7916523B2 (en) * 2006-12-05 2011-03-29 Spansion Llc Method of erasing a resistive memory device
US20080130392A1 (en) * 2006-12-05 2008-06-05 Spansion Llc Method of erasing a resistive memory device
US20090180310A1 (en) * 2008-01-11 2009-07-16 Naoharu Shimomura Resistance change type memory
EP3926632A3 (en) * 2008-01-15 2022-03-09 Micron Technology, Inc. Memory cells, memory cell programming methods, memory cell reading methods, memory cell operating methods, and memory devices
US20120057391A1 (en) * 2008-01-15 2012-03-08 Jun Liu Memory Cells, Memory Cell Programming Methods, Memory Cell Reading Methods, Memory Cell Operating Methods, and Memory Devices
US9343145B2 (en) * 2008-01-15 2016-05-17 Micron Technology, Inc. Memory cells, memory cell programming methods, memory cell reading methods, memory cell operating methods, and memory devices
US20160211019A1 (en) * 2008-01-15 2016-07-21 Micron Technology, Inc. Memory Cells, Memory Cell Programming Methods, Memory Cell Reading Methods, Memory Cell Operating Methods, and Memory Devices
US11393530B2 (en) 2008-01-15 2022-07-19 Micron Technology, Inc. Memory cells, memory cell programming methods, memory cell reading methods, memory cell operating methods, and memory devices
US10790020B2 (en) 2008-01-15 2020-09-29 Micron Technology, Inc. Memory cells, memory cell programming methods, memory cell reading methods, memory cell operating methods, and memory devices
US9805792B2 (en) * 2008-01-15 2017-10-31 Micron Technology, Inc. Memory cells, memory cell programming methods, memory cell reading methods, memory cell operating methods, and memory devices
US10262734B2 (en) 2008-01-15 2019-04-16 Micron Technology, Inc. Memory cells, memory cell programming methods, memory cell reading methods, memory cell operating methods, and memory devices
US8674336B2 (en) 2008-04-08 2014-03-18 Micron Technology, Inc. Non-volatile resistive oxide memory cells, non-volatile resistive oxide memory arrays, and methods of forming non-volatile resistive oxide memory cells and memory arrays
US9577186B2 (en) 2008-05-02 2017-02-21 Micron Technology, Inc. Non-volatile resistive oxide memory cells and methods of forming non-volatile resistive oxide memory cells
US9257430B2 (en) 2008-06-18 2016-02-09 Micron Technology, Inc. Semiconductor construction forming methods
US9111788B2 (en) 2008-06-18 2015-08-18 Micron Technology, Inc. Memory device constructions, memory cell forming methods, and semiconductor construction forming methods
US9559301B2 (en) 2008-06-18 2017-01-31 Micron Technology, Inc. Methods of forming memory device constructions, methods of forming memory cells, and methods of forming semiconductor constructions
US9666801B2 (en) 2008-07-02 2017-05-30 Micron Technology, Inc. Methods of forming a non-volatile resistive oxide memory cell and methods of forming a non-volatile resistive oxide memory array
US9343665B2 (en) 2008-07-02 2016-05-17 Micron Technology, Inc. Methods of forming a non-volatile resistive oxide memory cell and methods of forming a non-volatile resistive oxide memory array
US20100003782A1 (en) * 2008-07-02 2010-01-07 Nishant Sinha Methods Of Forming A Non-Volatile Resistive Oxide Memory Cell And Methods Of Forming A Non-Volatile Resistive Oxide Memory Array
US20100118602A1 (en) * 2008-11-13 2010-05-13 Seagate Technology Llc Double source line-based memory array and memory cells thereof
US8542513B2 (en) 2010-04-22 2013-09-24 Micron Technology, Inc. Arrays of vertically stacked tiers of non-volatile cross point memory cells, methods of forming arrays of vertically stacked tiers of non-volatile cross point memory cells, and methods of reading a data value stored by an array of vertically stacked tiers of non-volatile cross point memory cells
US8427859B2 (en) 2010-04-22 2013-04-23 Micron Technology, Inc. Arrays of vertically stacked tiers of non-volatile cross point memory cells, methods of forming arrays of vertically stacked tiers of non-volatile cross point memory cells, and methods of reading a data value stored by an array of vertically stacked tiers of non-volatile cross point memory cells
US8743589B2 (en) 2010-04-22 2014-06-03 Micron Technology, Inc. Arrays of vertically stacked tiers of non-volatile cross point memory cells and methods of reading a data value stored by an array of vertically stacked tiers of non-volatile cross point memory cells
US8411477B2 (en) 2010-04-22 2013-04-02 Micron Technology, Inc. Arrays of vertically stacked tiers of non-volatile cross point memory cells, methods of forming arrays of vertically stacked tiers of non-volatile cross point memory cells, and methods of reading a data value stored by an array of vertically stacked tiers of non-volatile cross point memory cells
US8760910B2 (en) 2010-04-22 2014-06-24 Micron Technology, Inc. Arrays of vertically stacked tiers of non-volatile cross point memory cells, methods of forming arrays of vertically stacked tiers of non-volatile cross point memory cells, and methods of reading a data value stored by an array of vertically stacked tiers of non-volatile cross point memory cells
US9036402B2 (en) 2010-04-22 2015-05-19 Micron Technology, Inc. Arrays of vertically stacked tiers of non-volatile cross point memory cells
US9697873B2 (en) 2010-06-07 2017-07-04 Micron Technology, Inc. Memory arrays
US10859661B2 (en) 2010-06-07 2020-12-08 Micron Technology, Inc. Memory arrays
US9412421B2 (en) 2010-06-07 2016-08-09 Micron Technology, Inc. Memory arrays
US10613184B2 (en) 2010-06-07 2020-04-07 Micron Technology, Inc. Memory arrays
US10746835B1 (en) 2010-06-07 2020-08-18 Micron Technology, Inc. Memory arrays
US9989616B2 (en) 2010-06-07 2018-06-05 Micron Technology, Inc. Memory arrays
US10656231B1 (en) 2010-06-07 2020-05-19 Micron Technology, Inc. Memory Arrays
US10241185B2 (en) 2010-06-07 2019-03-26 Micron Technology, Inc. Memory arrays
US9887239B2 (en) 2010-06-07 2018-02-06 Micron Technology, Inc. Memory arrays
US9224496B2 (en) 2010-08-11 2015-12-29 Shine C. Chung Circuit and system of aggregated area anti-fuse in CMOS processes
US8830720B2 (en) 2010-08-20 2014-09-09 Shine C. Chung Circuit and system of using junction diode as program selector and MOS as read selector for one-time programmable devices
US9236141B2 (en) 2010-08-20 2016-01-12 Shine C. Chung Circuit and system of using junction diode of MOS as program selector for programmable resistive devices
US8559208B2 (en) 2010-08-20 2013-10-15 Shine C. Chung Programmably reversible resistive device cells using polysilicon diodes
US10923204B2 (en) 2010-08-20 2021-02-16 Attopsemi Technology Co., Ltd Fully testible OTP memory
US8804398B2 (en) 2010-08-20 2014-08-12 Shine C. Chung Reversible resistive memory using diodes formed in CMOS processes as program selectors
US8929122B2 (en) 2010-08-20 2015-01-06 Shine C. Chung Circuit and system of using a junction diode as program selector for resistive devices
US9496033B2 (en) 2010-08-20 2016-11-15 Attopsemi Technology Co., Ltd Method and system of programmable resistive devices with read capability using a low supply voltage
US9478306B2 (en) 2010-08-20 2016-10-25 Attopsemi Technology Co., Ltd. Circuit and system of using junction diode as program selector for one-time programmable devices with heat sink
US10916317B2 (en) 2010-08-20 2021-02-09 Attopsemi Technology Co., Ltd Programmable resistance memory on thin film transistor technology
US9460807B2 (en) 2010-08-20 2016-10-04 Shine C. Chung One-time programmable memory devices using FinFET technology
US9019742B2 (en) 2010-08-20 2015-04-28 Shine C. Chung Multiple-state one-time programmable (OTP) memory to function as multi-time programmable (MTP) memory
US9025357B2 (en) 2010-08-20 2015-05-05 Shine C. Chung Programmable resistive memory unit with data and reference cells
US8570800B2 (en) 2010-08-20 2013-10-29 Shine C. Chung Memory using a plurality of diodes as program selectors with at least one being a polysilicon diode
US8576602B2 (en) 2010-08-20 2013-11-05 Shine C. Chung One-time programmable memories using polysilicon diodes as program selectors
US9042153B2 (en) 2010-08-20 2015-05-26 Shine C. Chung Programmable resistive memory unit with multiple cells to improve yield and reliability
US9070437B2 (en) 2010-08-20 2015-06-30 Shine C. Chung Circuit and system of using junction diode as program selector for one-time programmable devices with heat sink
US8644049B2 (en) 2010-08-20 2014-02-04 Shine C. Chung Circuit and system of using polysilicon diode as program selector for one-time programmable devices
US8913415B2 (en) 2010-08-20 2014-12-16 Shine C. Chung Circuit and system for using junction diode as program selector for one-time programmable devices
US8649203B2 (en) 2010-08-20 2014-02-11 Shine C. Chung Reversible resistive memory using polysilicon diodes as program selectors
US9431127B2 (en) 2010-08-20 2016-08-30 Shine C. Chung Circuit and system of using junction diode as program selector for metal fuses for one-time programmable devices
US8817563B2 (en) 2010-08-20 2014-08-26 Shine C. Chung Sensing circuit for programmable resistive device using diode as program selector
US10249379B2 (en) 2010-08-20 2019-04-02 Attopsemi Technology Co., Ltd One-time programmable devices having program selector for electrical fuses with extended area
US9711237B2 (en) 2010-08-20 2017-07-18 Attopsemi Technology Co., Ltd. Method and structure for reliable electrical fuse programming
US10229746B2 (en) 2010-08-20 2019-03-12 Attopsemi Technology Co., Ltd OTP memory with high data security
US8873268B2 (en) 2010-08-20 2014-10-28 Shine C. Chung Circuit and system of using junction diode as program selector for one-time programmable devices
US9754679B2 (en) 2010-08-20 2017-09-05 Attopsemi Technology Co., Ltd One-time programmable memory devices using FinFET technology
US9385162B2 (en) 2010-08-20 2016-07-05 Shine C. Chung Programmably reversible resistive device cells using CMOS logic processes
US9251893B2 (en) 2010-08-20 2016-02-02 Shine C. Chung Multiple-bit programmable resistive memory using diode as program selector
US10127992B2 (en) 2010-08-20 2018-11-13 Attopsemi Technology Co., Ltd. Method and structure for reliable electrical fuse programming
US8760904B2 (en) 2010-08-20 2014-06-24 Shine C. Chung One-Time Programmable memories using junction diodes as program selectors
US9349773B2 (en) 2010-08-20 2016-05-24 Shine C. Chung Memory devices using a plurality of diodes as program selectors for memory cells
US8854859B2 (en) 2010-08-20 2014-10-07 Shine C. Chung Programmably reversible resistive device cells using CMOS logic processes
US9305973B2 (en) 2010-08-20 2016-04-05 Shine C. Chung One-time programmable memories using polysilicon diodes as program selectors
US9767915B2 (en) 2010-08-20 2017-09-19 Attopsemi Technology Co., Ltd One-time programmable device with integrated heat sink
US8760916B2 (en) 2010-08-20 2014-06-24 Shine C. Chung Circuit and system of using at least one junction diode as program selector for memories
US8976566B2 (en) 2010-09-29 2015-03-10 Micron Technology, Inc. Electronic devices, memory devices and memory arrays
US9705078B2 (en) 2010-10-21 2017-07-11 Micron Technology, Inc. Integrated circuitry comprising nonvolatile memory cells and methods of forming a nonvolatile memory cell
US8759809B2 (en) 2010-10-21 2014-06-24 Micron Technology, Inc. Integrated circuitry comprising nonvolatile memory cells having platelike electrode and ion conductive material layer
US8883604B2 (en) 2010-10-21 2014-11-11 Micron Technology, Inc. Integrated circuitry comprising nonvolatile memory cells and methods of forming a nonvolatile memory cell
US9245964B2 (en) 2010-10-21 2016-01-26 Micron Technology, Inc. Integrated circuitry comprising nonvolatile memory cells and methods of forming a nonvolatile memory cell
US9117998B2 (en) 2010-11-01 2015-08-25 Micron Technology, Inc. Nonvolatile memory cells and methods of forming nonvolatile memory cells
US9406878B2 (en) 2010-11-01 2016-08-02 Micron Technology, Inc. Resistive memory cells with two discrete layers of programmable material, methods of programming memory cells, and methods of forming memory cells
US8753949B2 (en) 2010-11-01 2014-06-17 Micron Technology, Inc. Nonvolatile memory cells and methods of forming nonvolatile memory cells
US8811063B2 (en) 2010-11-01 2014-08-19 Micron Technology, Inc. Memory cells, methods of programming memory cells, and methods of forming memory cells
US8796661B2 (en) 2010-11-01 2014-08-05 Micron Technology, Inc. Nonvolatile memory cells and methods of forming nonvolatile memory cell
US9343176B2 (en) 2010-11-03 2016-05-17 Shine C. Chung Low-pin-count non-volatile memory interface with soft programming capability
US9281038B2 (en) 2010-11-03 2016-03-08 Shine C. Chung Low-pin-count non-volatile memory interface
US9076513B2 (en) 2010-11-03 2015-07-07 Shine C. Chung Low-pin-count non-volatile memory interface with soft programming capability
US9019791B2 (en) 2010-11-03 2015-04-28 Shine C. Chung Low-pin-count non-volatile memory interface for 3D IC
US8988965B2 (en) 2010-11-03 2015-03-24 Shine C. Chung Low-pin-count non-volatile memory interface
US9293220B2 (en) 2010-11-03 2016-03-22 Shine C. Chung Low-pin-count non-volatile memory interface for 3D IC
US8923085B2 (en) 2010-11-03 2014-12-30 Shine C. Chung Low-pin-count non-volatile memory embedded in a integrated circuit without any additional pins for access
US9454997B2 (en) 2010-12-02 2016-09-27 Micron Technology, Inc. Array of nonvolatile memory cells having at least five memory cells per unit cell, having a plurality of the unit cells which individually comprise three elevational regions of programmable material, and/or having a continuous volume having a combination of a plurality of vertically oriented memory cells and a plurality of horizontally oriented memory cells; array of vertically stacked tiers of nonvolatile memory cells
US9496265B2 (en) 2010-12-08 2016-11-15 Attopsemi Technology Co., Ltd Circuit and system of a high density anti-fuse
US8431458B2 (en) 2010-12-27 2013-04-30 Micron Technology, Inc. Methods of forming a nonvolatile memory cell and methods of forming an array of nonvolatile memory cells
US9034710B2 (en) 2010-12-27 2015-05-19 Micron Technology, Inc. Methods of forming a nonvolatile memory cell and methods of forming an array of nonvolatile memory cells
US8652909B2 (en) 2010-12-27 2014-02-18 Micron Technology, Inc. Methods of forming a nonvolatile memory cell and methods of forming an array of nonvolatile memory cells array of nonvolatile memory cells
US8791447B2 (en) 2011-01-20 2014-07-29 Micron Technology, Inc. Arrays of nonvolatile memory cells and methods of forming arrays of nonvolatile memory cells
US9093368B2 (en) 2011-01-20 2015-07-28 Micron Technology, Inc. Nonvolatile memory cells and arrays of nonvolatile memory cells
US10192615B2 (en) 2011-02-14 2019-01-29 Attopsemi Technology Co., Ltd One-time programmable devices having a semiconductor fin structure with a divided active region
US11011577B2 (en) 2011-02-14 2021-05-18 Attopsemi Technology Co., Ltd One-time programmable memory using gate-all-around structures
US8848423B2 (en) 2011-02-14 2014-09-30 Shine C. Chung Circuit and system of using FinFET for building programmable resistive devices
US10586832B2 (en) 2011-02-14 2020-03-10 Attopsemi Technology Co., Ltd One-time programmable devices using gate-all-around structures
US9881970B2 (en) 2011-02-14 2018-01-30 Attopsemi Technology Co. LTD. Programmable resistive devices using Finfet structures for selectors
US9548109B2 (en) 2011-02-14 2017-01-17 Attopsemi Technology Co., Ltd Circuit and system of using FinFET for building programmable resistive devices
US8681531B2 (en) 2011-02-24 2014-03-25 Micron Technology, Inc. Memory cells, methods of forming memory cells, and methods of programming memory cells
US9424920B2 (en) 2011-02-24 2016-08-23 Micron Technology, Inc. Memory cells, methods of forming memory cells, and methods of programming memory cells
US9257648B2 (en) 2011-02-24 2016-02-09 Micron Technology, Inc. Memory cells, methods of forming memory cells, and methods of programming memory cells
US8854863B2 (en) 2011-04-15 2014-10-07 Micron Technology, Inc. Arrays of nonvolatile memory cells and methods of forming arrays of nonvolatile memory cells
US9184385B2 (en) 2011-04-15 2015-11-10 Micron Technology, Inc. Arrays of nonvolatile memory cells and methods of forming arrays of nonvolatile memory cells
US8912576B2 (en) 2011-11-15 2014-12-16 Shine C. Chung Structures and techniques for using semiconductor body to construct bipolar junction transistors
US9136261B2 (en) 2011-11-15 2015-09-15 Shine C. Chung Structures and techniques for using mesh-structure diodes for electro-static discharge (ESD) protection
US9324849B2 (en) 2011-11-15 2016-04-26 Shine C. Chung Structures and techniques for using semiconductor body to construct SCR, DIAC, or TRIAC
US8861249B2 (en) 2012-02-06 2014-10-14 Shine C. Chung Circuit and system of a low density one-time programmable memory
US8917533B2 (en) 2012-02-06 2014-12-23 Shine C. Chung Circuit and system for testing a one-time programmable (OTP) memory
US9007804B2 (en) 2012-02-06 2015-04-14 Shine C. Chung Circuit and system of protective mechanisms for programmable resistive memories
US8913449B2 (en) 2012-03-11 2014-12-16 Shine C. Chung System and method of in-system repairs or configurations for memories
US9076526B2 (en) 2012-09-10 2015-07-07 Shine C. Chung OTP memories functioning as an MTP memory
US9183897B2 (en) 2012-09-30 2015-11-10 Shine C. Chung Circuits and methods of a self-timed high speed SRAM
US9324447B2 (en) 2012-11-20 2016-04-26 Shine C. Chung Circuit and system for concurrently programming multiple bits of OTP memory devices
US9818478B2 (en) 2012-12-07 2017-11-14 Attopsemi Technology Co., Ltd Programmable resistive device and memory using diode as selector
US10586593B2 (en) 2012-12-07 2020-03-10 Attopsemi Technology Co., Ltd Programmable resistive device and memory using diode as selector
US9412473B2 (en) 2014-06-16 2016-08-09 Shine C. Chung System and method of a novel redundancy scheme for OTP
US9824768B2 (en) 2015-03-22 2017-11-21 Attopsemi Technology Co., Ltd Integrated OTP memory for providing MTP memory
US10726914B2 (en) 2017-04-14 2020-07-28 Attopsemi Technology Co. Ltd Programmable resistive memories with low power read operation and novel sensing scheme
US11062786B2 (en) 2017-04-14 2021-07-13 Attopsemi Technology Co., Ltd One-time programmable memories with low power read operation and novel sensing scheme
US10535413B2 (en) 2017-04-14 2020-01-14 Attopsemi Technology Co., Ltd Low power read operation for programmable resistive memories
US11615859B2 (en) 2017-04-14 2023-03-28 Attopsemi Technology Co., Ltd One-time programmable memories with ultra-low power read operation and novel sensing scheme
US10770160B2 (en) 2017-11-30 2020-09-08 Attopsemi Technology Co., Ltd Programmable resistive memory formed by bit slices from a standard cell library

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