US7379317B2 - Method of programming, reading and erasing memory-diode in a memory-diode array - Google Patents
Method of programming, reading and erasing memory-diode in a memory-diode array Download PDFInfo
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- US7379317B2 US7379317B2 US11/021,958 US2195804A US7379317B2 US 7379317 B2 US7379317 B2 US 7379317B2 US 2195804 A US2195804 A US 2195804A US 7379317 B2 US7379317 B2 US 7379317B2
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/02—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using elements whose operation depends upon chemical change
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/36—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using diodes, e.g. as threshold elements, i.e. diodes assuming a stable ON-stage when driven above their threshold (S- or N-characteristic)
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
Definitions
- This invention relates generally to memory devices, and more particularly, to a memory array incorporating memory-diodes.
- memory devices associated with computers and other electronic devices are employed to store and maintain information for the operation thereof.
- a memory device includes an array of memory cells, wherein each memory cell can be accessed for programming, erasing, and reading thereof.
- Each memory cell maintains information in an “off” state or an “on” state, also referred to as “0” and “1” respectively, which can be read during the reading step of that memory cell.
- FIG. 1 illustrates a type of memory cell known as a memory-diode 30 , which includes advantageous characteristics for meeting these needs.
- the memory-diode 30 includes an electrode 32 , a superionic layer 34 on the electrode 32 , an active layer 36 on the superionic layer 34 , and an electrode 38 on the active layer 36 .
- a negative voltage is applied to the electrode 38 , while the electrode 32 is held at ground, so that an electrical potential V pg (the “programming” electrical potential) is applied across the memory-diode 30 from a higher to a lower electrical potential in the forward direction of the memory-diode 30 (see FIG. 2 , a plot of memory diode current vs. electrical potential applied across the memory-diode 30 ).
- This potential is sufficient to cause copper ions to be attracted from the superionic layer 34 toward the electrode 38 and into the active layer 36 (A), causing the active layer 36 (and the overall memory-diode 30 ) to be in a (forward) low-resistance or conductive state.
- the copper ions drawn into the active layer 36 during the programming step remain therein, so that the active layer 36 (and memory-diode 30 ) remain in a conductive or low-resistance state.
- FIG. 3 illustrates the read step of the memory-diode 30 in its programmed (conductive) state.
- An electrical potential V r (the “read” electrical potential) is applied across the memory-diode 30 from a higher to a lower electrical potential in the forward direction of the memory-diode 30 .
- This electrical potential is sufficient to overcome the threshold voltage V t of the inherent diode characteristic of the memory-diode 30 , but is less than the electrical potential V pg applied across the memory-diode 30 for programming (see above). In this situation, the memory-diode 30 will readily conduct current, which indicates that the memory-diode 30 is in its programmed state.
- a positive voltage is applied to the electrode 38 , while the electrode 32 is held at ground, so that an electrical potential V er (the “erase” electrical potential) is applied across the memory-diode 30 from a higher to a lower electrical potential in the reverse direction of the memory-diode 30 .
- V er the “erase” electrical potential
- This potential is sufficient to cause copper ions to be repelled from the active layer 36 toward the electrode 32 and into the superionic layer 34 , causing the active layer 36 (and the overall memory-diode 30 ) to be in a high-resistance or substantially non-conductive state (see FIG. 5 , illustrating application of electrical potential V er across the memory-diode 30 ). This state remains upon removal of such potential from the memory-diode 30 .
- FIG. 6 illustrates the read step of the memory-diode 30 in its erased (substantially non-conductive) state.
- the electrical potential V r is again applied across the memory-diode 30 from a higher to a lower electrical potential in the forward direction of the memory-diode 30 , as described above.
- the active layer 34 and memory-diode 30 ) in a high-resistance or substantially non-conductive state, the memory-diode 30 will not conduct significant current, which indicates that the memory-diode 30 is in its erased state.
- FIG. 7 illustrates a memory-diode array 40 which incorporates memory-diodes 30 of the type described above.
- the memory-diode array 40 includes a first plurality 42 of parallel conductors (bit lines) BL 0 , BL 1 , . . . BL n , and a second plurality 44 of parallel conductors (word lines) WL 0 , WL 1 , . . . WL n overlying and spaced from, orthogonal to, and crossing the first plurality of conductors 42 .
- a plurality of memory-diodes 30 ( 30 00 , 30 10 , 30 n0 , 30 01 , 30 11 , 30 n1 , 30 0n , 30 1n , 30 nn shown) of the type described above are included.
- Each memory-diode 30 connects a conductor BL of the first plurality 42 thereof with a conductor WL of the second plurality 44 thereof at the intersection of those conductors, with the memory-diode 30 thereof in a forward direction from the conductor BL of the first plurality 42 thereof to the conductor WL of the second plurality 44 thereof. For example, as shown in FIG.
- memory-diode 30 00 connects conductor BL 0 of the first plurality of conductors 42 with conductor WL 0 of the second plurality of conductors 44 at the intersection of those conductors BL 0 , WL 0
- memory-diode 30 10 connects conductor BL 1 of the first plurality of conductors 42 with conductor WL 0 of the second plurality of conductors 44 at the intersection of those conductors BL 1 , WL 0 , etc.
- the voltage V 1 applied to the conductor BL 0 must be V pg greater than the voltage V 2 applied to the conductor WL 0 .
- the following approach can be undertaken.
- a voltage V 3 greater than voltage V 2 is applied to each of the conductors WL 1 -WL n , with the difference between voltage V 1 and voltage V 3 being less than V pg .
- a voltage V 4 greater than voltage V 2 is applied to each of the conductors BL 1 -BL n , with the difference between voltage V 4 and voltage V 2 being less than V pg .
- voltages V 3 and V 4 can be chosen as equal, so that each of the great majority of memory-diodes in the array 40 , i.e., those memory-diodes not connected to either conductor BL 0 or conductor WL 0 , has substantially no electrical potential applied thereacross, so as to minimize current leakage therethrough.
- V pg i.e., (V 1 -V 2 ) in the forward direction of that memory-diode 30 00 .
- each of the other memory-diodes 30 01 -30 0n connected to the conductor BL 0 has applied thereacross (V 1 -V 3 ) in the forward direction, which is less than V pg .
- the present invention is a method of undertaking a procedure on a selected memory-diode of a memory array, the memory array comprising a first plurality of parallel conductors, a second plurality of parallel conductors orthogonal to and crossing the first plurality of conductors, and a plurality of memory-diodes, each connecting in a forward direction a conductor of the first plurality thereof with a conductor of the second plurality thereof adjacent the intersection of those conductors.
- the method comprises providing an electrical potential across the selected memory-diode, from higher to lower potential in the forward direction of the selected memory-diode, intended to program the selected memory-diode to a conductive state, providing that, during the intended programming of the selected memory-diode, each other memory-diode in the array has provided thereacross in the forward direction thereof an electrical potential lower than its threshold voltage, providing an electrical potential across the selected memory-diode, from higher to lower potential in the reverse direction of the selected memory-diode, intended to erase the selected memory-diode, and providing that, during the intended erasing of the selected memory-diode, each other memory-diode in the array has provided thereacross in the reverse direction thereof an electrical potential lower than the electrical potential provided to erase the selected memory-diode.
- FIG. 1 is a cross-sectional view of a typical memory-diode, illustrating the programming thereof;
- FIG. 2 is a plot of current vs. voltage in the programming of the memory-diode of FIG. 1 ;
- FIG. 3 is a plot of current vs. voltage in the reading of the programmed memory-diode of FIG. 1 ;
- FIG. 4 is a view similar to that shown in FIG. 1 , illustrating the erasing of the memory-diode
- FIG. 5 is a plot of current vs. voltage in the erasing of a programmed memory-diode in accordance with FIG. 4 ;
- FIG. 6 is a plot of current vs. voltage in the reading of the erased memory-diode in accordance with FIG. 5 ;
- FIG. 7 is a schematic illustration of a memory array which includes memory-diodes in accordance with FIG. 1 ;
- FIG. 8 is the plot of current vs. voltage illustrating the problem of leakage current of a programmed memory-diode of the array of FIG. 7 ;
- FIG. 9 is a view similar to that shown in FIGS. 1 and 4 , illustrating the programming of the memory-diode
- FIG. 10 is a plot of current vs. voltage in the programming of the memory-diode of FIG. 9 , illustrating the inherent voltage threshold characteristic resulting from the programming of the memory-diode;
- FIG. 11 is a plot of current vs. voltage illustrating the shifting of the threshold voltage of the programmed memory-diode
- FIG. 12 is a plot of current vs. voltage illustrating the reading of the programmed memory-diode having a shifted threshold voltage
- FIG. 13 is a plot of current vs. voltage illustrating resetting of the threshold voltage of the memory-diode subsequent to the read step
- FIG. 14 is a plot of current vs. voltage illustrating the shifting of the threshold voltage thereof to a different level
- FIG. 15 is a plot of current vs. voltage illustrating the reading of the memory-diode having the threshold voltage thereof shifted to a different level
- FIG. 16 is a view similar to that shown in FIGS. 1 , 4 and 9 , illustrating the erasing of the memory-diode
- FIG. 17 is a plot of current vs. voltage in the erasing of the memory-diode of FIG. 16 ;
- FIG. 18 is a plot of current vs. voltage illustrating the reading of the erased memory-diode
- FIG. 19 is a schematic illustration of a memory array which includes memory-diodes, and further illustrating programming of a selected memory-diode;
- FIG. 20 is a plot of current vs. voltage illustrating characteristics of a programmed memory-diode under different conditions
- FIG. 21 is a schematic illustration of the memory array of FIG. 19 , further illustrating erasing of a selected memory-diode
- FIG. 22 is a plot of current vs. voltage illustrating characteristics of an erased memory-diode under different conditions
- FIG. 23 is a schematic illustration of the memory array of FIGS. 19 and 21 , further illustrating reading of a selected memory-diode.
- FIG. 24 is a plot of current vs. voltage illustrating characteristics of a memory diode under read conditions.
- FIG. 9 is similar to FIG. 1 , illustrating the programming of a memory-diode 130 .
- the memory diode 130 includes for example a Cu electrode 132 , a superionic Cu 2 S layer 134 on the electrode 132 , an active WO 3 or F8T2 layer 136 on the Cu 2 S layer 134 , and a Ti electrode 138 on the active layer 136 .
- a negative voltage is applied to the electrode 138 , while the electrode 132 is held at ground, so that a programming electrical potential V pg is applied across the memory-diode 130 from a higher to a lower electrical potential in the forward direction of the memory-diode 130 (see also FIG. 10 ).
- This potential is sufficient to cause copper ions to be attracted from the superionic layer 134 toward the electrode and 132 into the active layer 136 , causing the active layer 136 (and the overall memory-diode 130 ) to be in a (forward) low-resistance or conductive state.
- the copper ions drawn into the active layer 136 during the program step remain therein, so that the active layer 136 (and memory-diode 130 ) remain in a conductive or low-resistance state.
- the inherent diode characteristic of the memory-diode 130 may well have a very low threshold voltage V t1 ( FIG. 10 ), leading to the problems described above. It had been found, however, that the threshold voltage V t of the memory-diode 130 may be increased by applying an electric field across the memory-diode 130 , from higher to lower electrical potential in the reverse direction of the memory-diode 130 , as a program completion step. For example, as illustrated in FIG.
- FIG. 12 illustrates the read step of the memory-diode 130 in the so-programmed (conductive) state as illustrated in FIG. 11 .
- An electrical potential V r is applied across the memory-diode 130 from a higher to a lower electrical potential in the forward direction of the memory-diode 130 .
- This electrical potential V r is sufficient to overcome the threshold voltage V t2 of the memory-diode 130 , but is less than the electrical potential V pg applied across the memory-diode 130 for programming. In this situation, the memory-diode 130 will readily conduct current, which indicates that the memory-diode 130 is in its programmed state.
- the read step as just described may disturb the established threshold voltage of the memory-diode 130 , by lowering such threshold voltage from its previously selected and established level V t2 .
- a read-completion step is undertaken ( FIG.
- the threshold voltage V t of the memory-diode 130 is increased to the previously established level V t2 by applying an electric field V s1 across the memory-diode 130 , from higher to lower electrical potential in the reverse direction of the memory-diode 130 , which causes the threshold voltage of the memory-diode 130 to increase to V t2 , again establishing the threshold voltage of the memory-diode at V t2 .
- the amount of increase in threshold voltage V t of the memory-diode 130 is dependent on the magnitude of electrical potential so applied across the memory-diode 130 from higher to lower electrical potential in the reverse direction thereof. That is, while such an electrical potential of a magnitude V s1 determines a threshold voltage of V t2 , an electrical potential of a magnitude V s2 , chosen as greater than V s1 , determines a threshold voltage V t3 which is greater than V t2 (compare FIGS. 11 and 14 ), i.e., a proportionality exists between the magnitude of the electrical potential and the magnitude of the threshold voltage V t .
- the threshold voltage of the memory-diode 130 can be tailored to the specific needs of the application. Again, this electrical potential applied to the memory-diode 130 to establish a new threshold voltage is less than the electrical potential V er applied in the reverse direction of the memory-diode 130 to erase the memory-diode 130 , so as to avoid a disturb condition of the state of the programmed memory-diode 130 .
- FIG. 15 illustrates the read step of the so-programmed memory-diode 130 in its programmed (conductive) state as illustrated in FIG. 14 .
- An electrical potential V r is applied across the memory-diode 130 from a higher to a lower electrical potential in the forward direction of the memory-diode 130 .
- This electrical potential is sufficient to overcome the threshold voltage V t3 of the memory-diode 130 , but is less than the electrical potential V pg applied across the memory-diode 130 for programming. In this situation, the memory-diode 130 will readily conduct current, which indicates that the memory-diode 130 is in its programmed state.
- a read-completion step as described above is undertaken to re-establish the threshold voltage V t3 of the memory-diode 130 .
- FIG. 16 is similar to FIG. 4 , illustrating the erasing of the memory-diode 130 .
- a positive voltage is applied to the electrode 138 , while the electrode 132 is held at ground, so that an electrical potential V er is applied across the memory-diode 130 from a higher to a lower electrical potential in the reverse direction of the memory-diode 130 (see also FIG. 17 ).
- This potential is greater than the electrical potential V s applied to establish a memory-diode threshold voltage as described above, and is sufficient to cause copper ions to be repelled from the active layer 136 toward the electrode 132 and into the superionic layer 134 , causing the active layer 136 (and the overall memory-diode 130 ) to be in a high-resistance or substantially non-conductive state. This state remains upon removal of such potential from the memory-diode 130 .
- FIG. 18 illustrates a verification step for the memory-diode 130 in its erased (substantially non-conductive) state, which is undertaken immediately after the erase procedure.
- the electrical potential V r (which is the electrical potential applied in reading the state of the memory-diode 130 , see below, since the present step is actually a read step) is applied across the memory-diode 130 from a higher to a lower electrical potential in the forward direction of the memory-diode 130 . This electrical potential is less than the electrical potential V pg applied across the memory-diode 130 for programming. If the memory-diode 130 has been properly erased, i.e., the memory-diode 130 is in a high-resistance or substantially non-conductive state, the memory-diode 130 will not conduct significant current.
- FIG. 18 also illustrates the read step for the memory-diode 130 in its erased state, undertaken to determine the state of that memory-diode 130 .
- the electrical potential V r is applied across the memory-diode 130 from a higher to a lower electrical potential in the forward direction of the memory-diode 130 .
- the memory-diode 130 will not conduct significant current in its erased, i.e., high resistance or substantially non-conductive state.
- FIG. 19 is similar to FIG. 7 and illustrates a memory diode array 140 which incorporates memory-diodes 130 of the type described.
- the memory-diode array 140 includes a first plurality 142 of parallel conductors (bit lines) BL 0 , BL 1 , . . . BL n , and a second plurality 144 of parallel conductors (word lines) WL 0 , WL 1 , . . . WL n overlying and spaced from, orthogonal to, and crossing the first plurality of conductors 142 .
- a plurality of memory-diodes 130 ( 130 00 , 130 10 , 130 n0 , 130 01 , 130 11 , 130 n1 , 130 0n , 130 1n , 130 nn shown) of the type described above are included.
- Each memory-diode 130 connects a conductor BL of the first plurality 142 thereof with a conductor WL of the second plurality 144 thereof at the intersection of those conductors, with the memory-diode 130 thereof in a forward direction from the conductor BL of the first plurality 142 thereof to the conductor WL of the second plurality 144 thereof. For example, as shown in FIG.
- memory-diode 130 00 connects conductor BL 0 of the first plurality of conductors 142 with conductor WL 0 of the second plurality of conductors 144 at the intersection of those conductors BL 0 , WL 0
- memory-diode 130 10 connects conductor BL 1 of the first plurality of conductors 142 with conductor WL 0 of the second plurality of conductors 144 at the intersection of those conductors BL 1 , WL 0 , etc.
- an electrical potential V pg is to be applied thereacross in the forward direction of the memory-diode 130 00 .
- the voltage V pg is shown as applied to the conductor BL 0
- 0 voltage is shown as applied to the conductor WL 0 , so that the potential V pg is established across the memory-diode 130 00 in the forward direction thereof.
- the selection of the value of r can be tied to the selection of the level of established threshold voltage, and vice versa. That is, if a relatively high level of threshold voltage is established, the value r can be relatively high, and if conversely a relatively low level of threshold voltage is established, the value of r must be relatively low.
- the electrical potential rV pg can be established across each of the memory-diodes connected to the conductor WL 0 (other than the selected memory-diode 130 00 ) by applying a voltage rV pg to each of the conductors BL 1 -BL n .
- a voltage (1 ⁇ r)V pg is applied to each conductor WL 1 -WL n .
- the value of r is selected to provide that each of the programmed memory-diodes connected to the conductor BL 0 and the conductor WL 0 , other than the selected memory-diode 130 00 , has an electrical potential applied thereacross in the forward direction thereof which is lower than the its threshold voltage V t2 . Furthermore, each of the other memory-diodes in the array 140 , i.e., those memory-diodes 130 connected to neither the conductor BL 0 nor the conductor WL 0 , has applied thereacross in the forward direction thereof an electrical potential of (2r ⁇ 1)V pg .
- (2r ⁇ 1)V pg is negative, the value of r is provided so that electrical potential (2r ⁇ 1)V pg applied across the memory-diode from higher to lower potential in the reverse direction is less than the electrical potential V s1 (establishing threshold value V t2 ) applied from higher to lower potential in the reverse direction, avoiding disturbance of the threshold voltage V t2 . This also establishes that electrical potential (2r ⁇ 1)V pg applied across the memory-diode from higher to lower potential in the reverse direction is less than the electrical potential V er applied from higher to lower potential in the reverse direction.
- the ability to select the threshold voltages of the memory-diodes in the array allows for wide latitude in the selection of the value r, increasing flexibility of overall approach.
- FIG. 21 is similar to FIG. 19 , but illustrates the erasing of a selected memory diode.
- an electrical potential V er In order to erase a selected memory-diode, for example selected memory-diode 130 00 , an electrical potential V er must be applied thereacross in the reverse direction of the memory-diode.
- the voltage V er is shown as applied to the conductor WL 0
- 0 voltage is shown as applied to the conductor BL 0 , so that the potential V er is established across the memory-diode 130 00 , from higher to lower electrical potential, in the reverse direction thereof.
- Voltages are applied to the conductors BL 1 -BLn and the conductors WL 1 -WL n to establish that each of the memory-diodes connected to the conductor BL 0 and each of the memory-diodes connected to the conductor WL 0 (other than the selected memory-diode 130 00 ) has applied thereto in a reverse direction an electrical potential pV er (forward direction ⁇ pV er ), where p ⁇ 1 (see also FIG. 22 ).
- This electrical potential pV er in the reverse direction can be established across each of the memory-diodes connected to the conductor BL 0 (other than the selected memory-diode 130 00 ) by applying a voltage pV er to each of the conductors WL 1 -WL n .
- a voltage (1 ⁇ p)V er is applied to each of the conductors BL 1 -BL n .
- each of the memory-diodes connected to the conductor BL 0 and the conductor WL 0 , other than the selected memory-diode 130 00 has an electrical potential applied thereacross in the forward direction thereof which is lower than the its threshold voltage (indeed is negative in the forward direction).
- the value of r is chosen so that the value pV er , applied from higher to lower potential in the reverse direction of the memory-diode is less than the value V s1 establishing the threshold voltage V t2 for that memory-diode, avoiding disturbance of the threshold value V t2 .
- each of the other memory-diodes in the array 140 i.e., those memory-diodes connected to neither the conductor BL 0 nor the conductor WL 0 , has applied thereacross in the forward direction thereof an electrical potential of (1 ⁇ 2p)V er . If (1 ⁇ 2p)V er is positive, the value of p is provided so that the electrical potential (1 ⁇ 2p)V er applied from higher to lower potential in the forward direction of a memory-diode subjected thereto is less than the threshold voltage thereof, insuring that programmed memory-diodes subject to this potential will not turn on.
- any such electrical potential as specified above considered as applied in the forward direction of a memory-diode is clearly less than the threshold voltage V t of that memory diode. It will thus be seen that each memory-diode in the array 140 (other than the selected memory-diode 130 00 ) has applied thereacross in the forward direction an electrical potential lower than the threshold voltage V t2 of that memory-diode.
- FIG. 23 is similar to FIGS. 19 and 21 but illustrates the reading of a selected memory-diode 130 00 .
- an electrical potential V r In order to read the state of a selected memory-diode 130 00 , an electrical potential V r must be applied thereacross from a higher to a lower electrical potential in the forward direction of the memory-diode 130 00 . This electrical potential is sufficient to overcome the threshold voltage V t2 of the selected memory diode 130 00 if that memory-diode 130 00 is in a programmed state, but is less than the electrical potential V pg which would undesirably program a memory-diode in an erased state.
- the voltage V r is shown as applied to the conductor BL 0
- 0 voltage is shown as applied to the conductor WL 0
- the electrical potential V r is established across the memory-diode 130 00 in the forward direction thereof.
- each of the other conductors BL 1 -BL n also has applied thereto V r .
- Each of the other conductors has applied thereto voltage (1 ⁇ q)V r , where q ⁇ 1. If q has a value chosen as close to 0, the electrical potential applied across each of the memory-diodes connected to the conductors WL 1 -WLn, i.e., electrical potential qV r , will be close to 0.
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Priority Applications (7)
Application Number | Priority Date | Filing Date | Title |
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US11/021,958 US7379317B2 (en) | 2004-12-23 | 2004-12-23 | Method of programming, reading and erasing memory-diode in a memory-diode array |
EP05855031A EP1829048B1 (en) | 2004-12-23 | 2005-12-20 | Method of programming, reading and erasing memory-diode in a memory-diode array |
CNA200580043866XA CN101084555A (en) | 2004-12-23 | 2005-12-20 | Method of programming, reading and erasing memory-diode in a memory-diode array |
JP2007548434A JP4616355B2 (en) | 2004-12-23 | 2005-12-20 | Method for programming, reading and erasing memory diodes in a memory diode array |
KR1020077014373A KR20070086608A (en) | 2004-12-23 | 2005-12-20 | Method of programming, reading and erasing memory-diode in a memory-diode array |
PCT/US2005/046406 WO2006071683A1 (en) | 2004-12-23 | 2005-12-20 | Method of programming, reading and erasing memory-diode in a memory-diode array |
TW094145795A TWI404062B (en) | 2004-12-23 | 2005-12-22 | Method of programming, reading and erasing memory-diode in a memory-diode array |
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US11/021,958 US7379317B2 (en) | 2004-12-23 | 2004-12-23 | Method of programming, reading and erasing memory-diode in a memory-diode array |
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US20060139994A1 US20060139994A1 (en) | 2006-06-29 |
US7379317B2 true US7379317B2 (en) | 2008-05-27 |
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US (1) | US7379317B2 (en) |
EP (1) | EP1829048B1 (en) |
JP (1) | JP4616355B2 (en) |
KR (1) | KR20070086608A (en) |
CN (1) | CN101084555A (en) |
TW (1) | TWI404062B (en) |
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US20060221713A1 (en) * | 2005-03-31 | 2006-10-05 | Spansion Llc | Write-once read-many times memory |
US20080130357A1 (en) * | 2006-12-05 | 2008-06-05 | Spansion Llc | Method of programming memory device |
US20090225581A1 (en) * | 2008-03-04 | 2009-09-10 | Kim Deok-Kee | Multi-bit memory device using multi-plug |
US8284597B2 (en) | 2010-05-06 | 2012-10-09 | Macronix International Co., Ltd. | Diode memory |
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US7450416B1 (en) * | 2004-12-23 | 2008-11-11 | Spansion Llc | Utilization of memory-diode which may have each of a plurality of different memory states |
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US7589989B2 (en) | 2006-10-24 | 2009-09-15 | Sandisk 3D Llc | Method for protecting memory cells during programming |
US7420850B2 (en) * | 2006-10-24 | 2008-09-02 | Sandisk 3D Llc | Method for controlling current during programming of memory cells |
US7391638B2 (en) * | 2006-10-24 | 2008-06-24 | Sandisk 3D Llc | Memory device for protecting memory cells during programming |
US7420851B2 (en) * | 2006-10-24 | 2008-09-02 | San Disk 3D Llc | Memory device for controlling current during programming of memory cells |
CN108615812B (en) | 2018-05-14 | 2020-02-07 | 浙江大学 | Ternary content addressable memory based on memory diode |
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2005
- 2005-12-20 KR KR1020077014373A patent/KR20070086608A/en not_active Application Discontinuation
- 2005-12-20 EP EP05855031A patent/EP1829048B1/en active Active
- 2005-12-20 CN CNA200580043866XA patent/CN101084555A/en active Pending
- 2005-12-20 WO PCT/US2005/046406 patent/WO2006071683A1/en active Application Filing
- 2005-12-20 JP JP2007548434A patent/JP4616355B2/en not_active Expired - Fee Related
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US20060221713A1 (en) * | 2005-03-31 | 2006-10-05 | Spansion Llc | Write-once read-many times memory |
US8098521B2 (en) * | 2005-03-31 | 2012-01-17 | Spansion Llc | Method of providing an erase activation energy of a memory device |
US20080130357A1 (en) * | 2006-12-05 | 2008-06-05 | Spansion Llc | Method of programming memory device |
US7564708B2 (en) * | 2006-12-05 | 2009-07-21 | Spansion Llc | Method of programming memory device |
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Also Published As
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KR20070086608A (en) | 2007-08-27 |
CN101084555A (en) | 2007-12-05 |
TW200632908A (en) | 2006-09-16 |
JP2008525935A (en) | 2008-07-17 |
TWI404062B (en) | 2013-08-01 |
WO2006071683A1 (en) | 2006-07-06 |
EP1829048B1 (en) | 2011-06-15 |
US20060139994A1 (en) | 2006-06-29 |
EP1829048A1 (en) | 2007-09-05 |
JP4616355B2 (en) | 2011-01-19 |
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