US20050067295A1 - Deep via seed repair using electroless plating chemistry - Google Patents

Deep via seed repair using electroless plating chemistry Download PDF

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US20050067295A1
US20050067295A1 US10/672,029 US67202903A US2005067295A1 US 20050067295 A1 US20050067295 A1 US 20050067295A1 US 67202903 A US67202903 A US 67202903A US 2005067295 A1 US2005067295 A1 US 2005067295A1
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layer
recess
forming
continuous
continuous metal
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US10/672,029
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Thomas Dory
Kenneth Wong
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Intel Corp
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Intel Corp
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Priority to US10/672,029 priority Critical patent/US20050067295A1/en
Assigned to INTEL CORPORATION reassignment INTEL CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: DORY, THOMAS S., WONG, KENNETH N.
Priority to TW93114521A priority patent/TWI241665B/en
Priority to JP2006528242A priority patent/JP4563389B2/en
Priority to PCT/US2004/031447 priority patent/WO2005031834A1/en
Priority to KR1020067005728A priority patent/KR101242289B1/en
Priority to DE200411001684 priority patent/DE112004001684B4/en
Priority to CNB2004100806921A priority patent/CN100442498C/en
Publication of US20050067295A1 publication Critical patent/US20050067295A1/en
Priority to US11/280,067 priority patent/US7479687B2/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
    • C23C18/54—Contact plating, i.e. electroless electrochemical plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76846—Layer combinations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76868—Forming or treating discontinuous thin films, e.g. repair, enhancement or reinforcement of discontinuous thin films
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L21/76874—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroless plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1068—Formation and after-treatment of conductors
    • H01L2221/1073—Barrier, adhesion or liner layers
    • H01L2221/1084—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L2221/1089—Stacks of seed layers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24802—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]
    • Y10T428/24917—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.] including metal layer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24802—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]
    • Y10T428/24926—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.] including ceramic, glass, porcelain or quartz layer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/249921—Web or sheet containing structurally defined element or component
    • Y10T428/249953—Composite having voids in a component [e.g., porous, cellular, etc.]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/249921—Web or sheet containing structurally defined element or component
    • Y10T428/249953—Composite having voids in a component [e.g., porous, cellular, etc.]
    • Y10T428/249967—Inorganic matrix in void-containing component

Definitions

  • the present invention relates to the field of microelectronic processing, and more particularly to methods of forming continuous metal films in deep vias and structures formed thereby.
  • conductive typically metal
  • the multiple metallization layers are employed in order to accommodate higher densities as device dimensions shrink well below one micron design rules.
  • One type of metal film that is widely used as a material for via metallization is copper.
  • a copper seed layer 12 (see FIG. 2 ) is sputtered into a via opening 14 , and then the via opening 14 is filled by electroplating it with a copper fill layer (not shown).
  • one serious disadvantage of sputtering the copper seed layer 12 into the via opening 14 is that the deposition rate of the copper seed layer 12 near the top corners 16 of the via opening 14 will be greater than near the sidewalls 18 and bottom 20 of the via opening 14 . This results in an overhang 22 being formed at the top of the via opening 14 which shadows, (i.e., impairs) the copper deposition on the sidewalls 18 and bottom 20 of the via opening 14 .
  • This shadowing effect may cause voids 24 , or areas of metal discontinuity, to form in the via opening 14 , since additional sputter deposition cannot adequately reach the bottom 20 and sidewalls 18 of the via opening 14 due to the overhang 22 at the top of the via opening 14 which tends to block further sputter deposition into the via opening 14 .
  • FIGS. 1 a - 1 i represent cross-sections of structures that may be formed when carrying out an embodiment of the method of the present invention.
  • FIG. 2 represents a cross section of a structure in the Prior Art.
  • Methods of forming a copper film in a high aspect ratio recess and its associated structures comprise forming a recess, forming a non-continuous metal layer within the recess, activating the non-continuous metal layer and a plurality of non-deposited regions within the recess, electrolessly plating a seed layer within the recess, and electroplating a metal fill layer over the seed layer, to form a substantially void-free, metal filled recess.
  • the combination of sputtering a non-continuous metal layer followed by electrolessly plating a seed layer on the non-continuous metal layer enables the substantially void free, substantially 100% metal coverage over the bottom and inner sidewall of the recess.
  • FIGS. 1 a - 1 f illustrate a method of fabricating a microelectronic structure.
  • FIG. 1 a illustrates a substrate 102 , including but not limited to silicon, silicon dioxide, silicon nitride, silicon oxynitride, and the like. It is, of course, understood that the substrate 102 can occur anywhere within a microelectronic device.
  • the substrate may also include the side opposite to the primary device side, i.e., the “backside” of a silicon wafer, as is well known in the art.
  • the substrate 102 comprises a first surface 106 .
  • the substrate 102 is then patterned and etched, by methods well known in the art, to form a recess 104 (such as a trench or via) which extends from the first surface 106 of the substrate 102 into the substrate 102 .
  • the recess 104 comprises inner walls 108 and a bottom 110 .
  • the recess 104 may be a high aspect ratio recess, in which the ratio of the width 120 of the recess 104 to the height 122 of the recess 104 may be greater than 3:1, i.e., the recess 104 preferably comprises an aspect ratio greater than 3:1.
  • a non-continuous metal layer 112 may be formed within the recess 104 due to the shadowing effects previously discussed herein.
  • the non-continuous metal layer 112 may be formed by a sputter deposition process, or by other physical sputtering deposition processes, such as atomic layer deposition (ALD), or chemical depositon processes such as plasma enhanced chemical deposition, (PECVD) as is well known in the art.
  • ALD atomic layer deposition
  • PECVD plasma enhanced chemical deposition
  • the temperature of the deposition may be about 100 to 200 degrees Celsius.
  • the pressure may be from about 1 to about 10 milliTorr, and the power may be from 5 to about 10 KW.
  • the materials used to form the non-continuous metal layer 112 may include but are not limited to tantalum, tantalum nitride, tantalum silicon nitride, tungsten, titanium, titanium tungsten, titanium nitride, titanium silicon nitride and combinations of these materials.
  • the non-continuous metal layer 112 may provide a diffusion barrier to subsequently formed copper or copper alloy layers.
  • the thickness of the non-continuous metal layer 112 may be from about 300 to about 500 Angstroms, and is preferably less than 500 Angstroms.
  • the non-continuous metal layer 112 may not substantially form over, or entirely cover the inner walls 108 and bottom 110 of the recess 104 .
  • Non-deposited regions within the recess 104 may be formed due to the phenomenon of the sputter shadowing effect (previously described herein, see FIG. 2 ), wherein a thicker sputtered layer forms near the top of a high aspect recess, such as recess 104 , than near the bottom of the recess, and the thicker layer near the top of the recess tends to block the complete metal coverage within the high aspect ratio recess.
  • non-deposited regions within the recess 104 may be a plurality of non-deposited regions within the recess 104 that are not covered by the non-continuous metal layer 112 , shown in FIG. 1 c as a non-deposited inner wall region 109 and a non-deposited bottom region 111 . These non-deposited regions within the recess 104 do not have the non-continuous metal layer 112 disposed upon them.
  • the non-continuous metal layer 112 , the non-deposited inner wall region 109 and the non-deposited bottom region 111 within the recess 104 may be activated by forming an activation layer 114 on the non-continuous metal layer 112 , on the non-deposited inner wall region 109 and on the non-deposited bottom region 111 .
  • the activation layer 114 may include, but is not limited to palladium or platinum, and may be contained in a solution comprising palladium chloride (PdCl 2 ) or platinum chloride (Pt Cl 2 ), for example.
  • the activation layer 114 may be formed on the non-continuous metal layer 112 by a contact displacement method, in which the non-continuous metal layer 112 is placed in a solution bath that may comprise Pd or Pt ions, a reducing agent (such as, but not limited to hypophosphite, dimethlyamine borane or hydrazine) a complexing agent (such as acetic acid or citric acid) and an acid (such as, but not limited to hydrofluoric acid, hydrochloric acid, or nitric acid) or a base (such as but not limited to tetramethylammonium hydroxide or potassium hydroxide).
  • the activation layer 114 may be less than 300 Angstroms, and is typically about 100 Angstroms.
  • the activation layer 114 activates, or prepares, the non-continuous metal layer 112 , the non-deposited inner wall region 109 and the non-deposited bottom region 111 for an autocatalytic reaction, such as an electroless deposition reaction.
  • a seed layer 116 may be formed on the activation layer 114 by electroless deposition.
  • the seed layer 116 may comprise metallic materials including but not limited to copper.
  • the seed layer 116 forms a substantially 100% continuous metal film coverage over the activation layer 114 (and therefore provides substantially 100% step coverage over the inner wall 108 and bottom 110 of the recess 104 ).
  • the electrolessly plated seed layer 116 comprises a plurality of grains 117 that generally comprise a diameter 118 that is about 1 micron (see FIG. 1 f ) or greater.
  • the activation layer 114 may be substantially subsumed during the electroless deposition of the seed layer 116 (see FIG. 1 g ) or may remain intact as depicted in FIG. 1 e.
  • the electroless solution of the preferred embodiment may comprise copper sulfate to supply the copper 2+ cations, ethylenediaminetetraacetic acid (EDTA) as a complexing agent for the copper 2+ cations, quaternary ammonium hydroxides to supply the hydroxide anions, formaldehyde (HCHO) or glyoxylic acid as a reducing agent, RHODAFAC RE 610TM or polyethylene glycols as a surfactant and wetting agent, and ammonium cyanide or 2,2′′-dipyridyl as stabilizer and ductility promoter.
  • EDTA ethylenediaminetetraacetic acid
  • HCHO formaldehyde
  • RHODAFAC RE 610TM polyethylene glycols as a surfactant and wetting agent
  • ammonium cyanide or 2,2′′-dipyridyl as stabilizer and ductility promoter.
  • the substrate 102 may be rinsed in deionized water to remove the electroless deposition solution. It is appreciated that the formation of the seed layer 116 is timed so that it does not substantially fill the recess 104 .
  • a metal fill layer 120 may be formed on the seed layer 116 .
  • the metal fill layer 120 may comprise metallic materials including but not limited to copper.
  • the metal fill layer 120 may be formed on the seed layer 116 by utilizing an electroplating process, as is well known in the art.
  • the metal fill layer 120 forms on the seed layer 116 within the recess 104 such that the recess is substantially filled with the metal fill layer 120 , with the absence of voids (such as are present in prior art recesses without an electroless seed layer 116 deposited over the non-continuous metal layer 112 ).
  • the electrolessly deposited seed layer 116 prevents the formation of voids in the metal fill layer 120 , since the metal fill layer 120 can plate or form over a continuous electroplated seed layer film, such as the seed layer 116 .
  • a continuous seed layer would not be possible with the use of a sputtered seed layer deposited directly on the non-continuous metal layer 112 (such as is used in the prior art), since using a sputtered seed layer would not result in a continuous film within the recess due to the shadowing effects previously described herein.
  • the metal fill layer 120 may be subsequently polished using a chemical mechanical polishing technique, for example, as is well known in the art (see FIG. 1 i ).
  • the present invention provides methods and associated structures of forming a continuous seed layer in a high aspect recess that enables a substantially void free metal fill layer, thus greatly enhancing the reliability and performance of a microelectronic device fabricated according to the various embodiments of the present invention.

Abstract

Methods of forming a continuous seed layer in a high aspect via and its associated structures are described. Those methods comprise forming a recess in a substrate, forming a non-continuous metal layer within the recess, activating the non-continuous metal layer and a plurality of non-deposited regions within the recess, electrolessly depositing a seed layer on the activated non-continuous metal layer and the plurality of non-deposited regions within the recess, and electroplating a metal fill layer over the seed layer, to form a substantially void-free metal filled recess.

Description

    FIELD OF THE INVENTION
  • The present invention relates to the field of microelectronic processing, and more particularly to methods of forming continuous metal films in deep vias and structures formed thereby.
    • BACKGROUND OF THE INVENTION
  • In the manufacture of microelectronic devices, it is now the practice to fabricate recesses or vias to connect multiple levels of conductive (typically metal) layers in a substrate. The multiple metallization layers are employed in order to accommodate higher densities as device dimensions shrink well below one micron design rules. One type of metal film that is widely used as a material for via metallization is copper. Typically, a copper seed layer 12 (see FIG. 2) is sputtered into a via opening 14, and then the via opening 14 is filled by electroplating it with a copper fill layer (not shown). However, one serious disadvantage of sputtering the copper seed layer 12 into the via opening 14 is that the deposition rate of the copper seed layer 12 near the top corners 16 of the via opening 14 will be greater than near the sidewalls 18 and bottom 20 of the via opening 14. This results in an overhang 22 being formed at the top of the via opening 14 which shadows, (i.e., impairs) the copper deposition on the sidewalls 18 and bottom 20 of the via opening 14. This shadowing effect may cause voids 24, or areas of metal discontinuity, to form in the via opening 14, since additional sputter deposition cannot adequately reach the bottom 20 and sidewalls 18 of the via opening 14 due to the overhang 22 at the top of the via opening 14 which tends to block further sputter deposition into the via opening 14.
  • For high aspect ratio (i.e, greater than 3:1) vias in a microelectronic device, it is very difficult or impossible to sputter deposit a continuous seed layer on the sidewalls and bottom of a via due to the shadowing effect during the sputter deposition process. In other words, the sputtered seed layer will not be continuous within the via. This means that when a copper film is later electroplated to fill the via, the via will exhibit voids in the via fill metallization that can negatively effect the device reliability and performance. Accordingly, it is desirable to form a continuous seed layer upon which to plate a metal fill layer in order to prevent the formation of voids in a high aspect ratio via. The present invention provides such methods and their associated structures.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • While the specification concludes with claims particularly pointing out and distinctly claiming that which is regarded as the present invention, the advantages of this invention can be more readily ascertained from the following description of the invention when read in conjunction with the accompanying drawings in which:
  • FIGS. 1 a-1 i represent cross-sections of structures that may be formed when carrying out an embodiment of the method of the present invention.
  • FIG. 2 represents a cross section of a structure in the Prior Art.
    • DETAILED DESCRIPTION OF THE PRESENT INVENTION
  • In the following detailed description, reference is made to the accompanying drawings that show, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. It is to be understood that the various embodiments of the invention, although different, are not necessarily mutually exclusive. For example, a particular feature, structure, or characteristic described herein, in connection with one embodiment, may be implemented within other embodiments without departing from the spirit and scope of the invention. In addition, it is to be understood that the location or arrangement of individual elements within each disclosed embodiment may be modified without departing from the spirit and scope of the invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims, appropriately interpreted, along with the full range of equivalents to which the claims are entitled. In the drawings, like numerals refer to the same or similar functionality throughout the several views.
  • Methods of forming a copper film in a high aspect ratio recess and its associated structures are described. Those methods comprise forming a recess, forming a non-continuous metal layer within the recess, activating the non-continuous metal layer and a plurality of non-deposited regions within the recess, electrolessly plating a seed layer within the recess, and electroplating a metal fill layer over the seed layer, to form a substantially void-free, metal filled recess. The combination of sputtering a non-continuous metal layer followed by electrolessly plating a seed layer on the non-continuous metal layer enables the substantially void free, substantially 100% metal coverage over the bottom and inner sidewall of the recess.
  • FIGS. 1 a-1 f illustrate a method of fabricating a microelectronic structure. In one embodiment of the method of the present invention, FIG. 1 a illustrates a substrate 102, including but not limited to silicon, silicon dioxide, silicon nitride, silicon oxynitride, and the like. It is, of course, understood that the substrate 102 can occur anywhere within a microelectronic device. The substrate may also include the side opposite to the primary device side, i.e., the “backside” of a silicon wafer, as is well known in the art. The substrate 102 comprises a first surface 106.
  • As shown in FIG. 1 b, the substrate 102 is then patterned and etched, by methods well known in the art, to form a recess 104 (such as a trench or via) which extends from the first surface 106 of the substrate 102 into the substrate 102. The recess 104 comprises inner walls 108 and a bottom 110. The recess 104 may be a high aspect ratio recess, in which the ratio of the width 120 of the recess 104 to the height 122 of the recess 104 may be greater than 3:1, i.e., the recess 104 preferably comprises an aspect ratio greater than 3:1.
  • Because the recess 104 is a high aspect recess, a non-continuous metal layer 112 may be formed within the recess 104 due to the shadowing effects previously discussed herein. The non-continuous metal layer 112 may be formed by a sputter deposition process, or by other physical sputtering deposition processes, such as atomic layer deposition (ALD), or chemical depositon processes such as plasma enhanced chemical deposition, (PECVD) as is well known in the art. The temperature of the deposition may be about 100 to 200 degrees Celsius. The pressure may be from about 1 to about 10 milliTorr, and the power may be from 5 to about 10 KW. The materials used to form the non-continuous metal layer 112 may include but are not limited to tantalum, tantalum nitride, tantalum silicon nitride, tungsten, titanium, titanium tungsten, titanium nitride, titanium silicon nitride and combinations of these materials. The non-continuous metal layer 112 may provide a diffusion barrier to subsequently formed copper or copper alloy layers. The thickness of the non-continuous metal layer 112 may be from about 300 to about 500 Angstroms, and is preferably less than 500 Angstroms.
  • Because the recess 104 is preferably a high aspect ratio recess, the non-continuous metal layer 112 may not substantially form over, or entirely cover the inner walls 108 and bottom 110 of the recess 104. Non-deposited regions within the recess 104 may be formed due to the phenomenon of the sputter shadowing effect (previously described herein, see FIG. 2), wherein a thicker sputtered layer forms near the top of a high aspect recess, such as recess 104, than near the bottom of the recess, and the thicker layer near the top of the recess tends to block the complete metal coverage within the high aspect ratio recess. Consequently, there may be a plurality of non-deposited regions within the recess 104 that are not covered by the non-continuous metal layer 112, shown in FIG. 1 c as a non-deposited inner wall region 109 and a non-deposited bottom region 111. These non-deposited regions within the recess 104 do not have the non-continuous metal layer 112 disposed upon them.
  • As shown in FIG. 1 d, the non-continuous metal layer 112, the non-deposited inner wall region 109 and the non-deposited bottom region 111 within the recess 104 may be activated by forming an activation layer 114 on the non-continuous metal layer 112, on the non-deposited inner wall region 109 and on the non-deposited bottom region 111. The activation layer 114 may include, but is not limited to palladium or platinum, and may be contained in a solution comprising palladium chloride (PdCl2) or platinum chloride (Pt Cl2), for example.
  • The activation layer 114 may be formed on the non-continuous metal layer 112 by a contact displacement method, in which the non-continuous metal layer 112 is placed in a solution bath that may comprise Pd or Pt ions, a reducing agent (such as, but not limited to hypophosphite, dimethlyamine borane or hydrazine) a complexing agent (such as acetic acid or citric acid) and an acid (such as, but not limited to hydrofluoric acid, hydrochloric acid, or nitric acid) or a base (such as but not limited to tetramethylammonium hydroxide or potassium hydroxide). The activation layer 114 may be less than 300 Angstroms, and is typically about 100 Angstroms. The activation layer 114 activates, or prepares, the non-continuous metal layer 112, the non-deposited inner wall region 109 and the non-deposited bottom region 111 for an autocatalytic reaction, such as an electroless deposition reaction.
  • As shown in FIG. 1 e, a seed layer 116 may be formed on the activation layer 114 by electroless deposition. The seed layer 116 may comprise metallic materials including but not limited to copper. The seed layer 116 forms a substantially 100% continuous metal film coverage over the activation layer 114 (and therefore provides substantially 100% step coverage over the inner wall 108 and bottom 110 of the recess 104). The electrolessly plated seed layer 116 comprises a plurality of grains 117 that generally comprise a diameter 118 that is about 1 micron (see FIG. 1 f) or greater. As is well known in the art, the activation layer 114 may be substantially subsumed during the electroless deposition of the seed layer 116 (see FIG. 1 g) or may remain intact as depicted in FIG. 1 e.
  • One of a variety of known electroless deposition solutions can be utilized to electrolessly deposit the seed layer 116. The electroless solution of the preferred embodiment may comprise copper sulfate to supply the copper2+ cations, ethylenediaminetetraacetic acid (EDTA) as a complexing agent for the copper2+ cations, quaternary ammonium hydroxides to supply the hydroxide anions, formaldehyde (HCHO) or glyoxylic acid as a reducing agent, RHODAFAC RE 610™ or polyethylene glycols as a surfactant and wetting agent, and ammonium cyanide or 2,2″-dipyridyl as stabilizer and ductility promoter. After the electroless deposition of the seed layer 116, the substrate 102 may be rinsed in deionized water to remove the electroless deposition solution. It is appreciated that the formation of the seed layer 116 is timed so that it does not substantially fill the recess 104.
  • As shown in FIG. 1 h, a metal fill layer 120 may be formed on the seed layer 116. The metal fill layer 120 may comprise metallic materials including but not limited to copper. The metal fill layer 120 may be formed on the seed layer 116 by utilizing an electroplating process, as is well known in the art. The metal fill layer 120 forms on the seed layer 116 within the recess 104 such that the recess is substantially filled with the metal fill layer 120, with the absence of voids (such as are present in prior art recesses without an electroless seed layer 116 deposited over the non-continuous metal layer 112).
  • The electrolessly deposited seed layer 116 prevents the formation of voids in the metal fill layer 120, since the metal fill layer 120 can plate or form over a continuous electroplated seed layer film, such as the seed layer 116. Such a continuous seed layer would not be possible with the use of a sputtered seed layer deposited directly on the non-continuous metal layer 112 (such as is used in the prior art), since using a sputtered seed layer would not result in a continuous film within the recess due to the shadowing effects previously described herein. The metal fill layer 120 may be subsequently polished using a chemical mechanical polishing technique, for example, as is well known in the art (see FIG. 1 i).
  • As described above, the present invention provides methods and associated structures of forming a continuous seed layer in a high aspect recess that enables a substantially void free metal fill layer, thus greatly enhancing the reliability and performance of a microelectronic device fabricated according to the various embodiments of the present invention.
  • Although the foregoing description has specified certain steps and materials that may be used in the method of the present invention, those skilled in the art will appreciate that many modifications and substitutions may be made. Accordingly, it is intended that all such modifications, alterations, substitutions and additions be considered to fall within the spirit and scope of the invention as defined by the appended claims. In addition, it is appreciated that the fabrication of a multiple metal layer structure atop a substrate, such as a silicon substrate, to manufacture a microelectronic device is well known in the art. Therefore, it is appreciated that the Figures provided herein illustrate only portions of an exemplary microelectronic device that pertains to the practice of the present invention. Thus the present invention is not limited to the structures described herein.

Claims (21)

1. A method of forming a seed layer comprising:
forming a non-continuous metal layer within a recess in a substrate;
activating the non-continuous metal layer and at least one of a non-deposited region within the recess; and
electrolessly depositing a seed layer on the non-continuous metal layer and on the at least one non-deposited region within the recess.
2. The method of claim 1 wherein forming the recess comprises forming a high aspect recess comprising an aspect ratio greater than about 3:1.
3. The method of claim 1 wherein forming the non-continuous metal layer comprises forming a non-continuous layer of at least one of tantalum, tantalum nitride, tantalum silicon nitride, tungsten, titanium, titanium tungsten, titanium nitride, titanium silicon nitride or a combination thereof.
4. The method of claim 1 wherein activating the non-continuous metal layer and the at least one non-deposited region within the recess comprises forming an activation layer on the non-continuous metal layer and on the at least one non-deposited region within the recess.
5. The method of claim 4 wherein activating the non-continuous metal layer and the at least one non-deposited region within the recess comprises forming at least one of a palladium or platinum layer on the non-continuous metal layer and the at least one non-deposited region within the recess.
6. The method of claim 1 further comprising forming a metal fill layer on the seed layer.
7. The method of claim 6 further comprising polishing the metal fill layer by utilizing a chemical mechanical polishing process.
8. The method of claim 6 wherein forming the metal fill layer comprises forming a substantially void free metal fill layer.
9. A method of forming a microelectronic structure comprising:
forming a recess in a substrate;
forming a non-continuous metal layer within the recess;
activating the non-continuous metal layer and at least one non-deposited region within the recess;
electrolessly depositing a seed layer on the non-continuous metal layer and on the at least one non-deposited region within the recess; and
forming a metal fill layer over the seed layer.
10. The method of claim 9 wherein forming the recess comprises forming a high aspect recess comprising an aspect ratio greater than about 3:1.
11. The method of claim 9 wherein forming the non-continuous metal layer comprises forming a non-continuous layer of at least one of tantalum, tantalum nitride, tantalum silicon nitride, tungsten, titanium, titanium tungsten, titanium nitride, titanium silicon nitride or a combination thereof.
12. The method of claim 9 wherein electrolessly depositing the seed layer comprises electrolessly depositing a copper layer comprising a grain size of about 1 micron in diameter or greater.
13. The method of claim 9 wherein forming the metal fill layer comprises electroplating a metal fill layer.
14. The method of claim 9 wherein forming the metal fill layer comprises forming a substantially void free metal fill layer.
15. The method of claim 9 wherein forming the metal fill layer comprises electroplating a copper layer.
16. A microelectronic structure, comprising:
a recess in a substrate;
a non-continuous metal layer disposed within the recess;
a seed layer disposed on the non-continuous metal layer and on at least one non-deposited region within the recess; and
a metal fill layer disposed on the seed layer.
17. The structure of claim 16 wherein the seed layer comprises a grain size of about 1 micron in diameter or greater.
18. The structure of claim 16 wherein the non-continuous metal layer comprises at least one of titanium, tantalum, tantalum nitride, tantalum silicon nitride, tungsten, titanium, titanium tungsten, titanium nitride, titanium silicon nitride or a combination thereof.
19. The structure of claim 16 wherein the seed layer comprises copper.
20. The structure of claim 16 wherein the recess comprises a high aspect ratio recess, wherein the high aspect ratio comprises an aspect ratio greater than about 3:1.
21. The structure of claim 16 wherein the metal fill layer comprises a substantially void free metal fill layer.
US10/672,029 2003-09-25 2003-09-25 Deep via seed repair using electroless plating chemistry Abandoned US20050067295A1 (en)

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US10/672,029 US20050067295A1 (en) 2003-09-25 2003-09-25 Deep via seed repair using electroless plating chemistry
TW93114521A TWI241665B (en) 2003-09-25 2004-05-21 Deep via seed repair using electroless plating chemistry
JP2006528242A JP4563389B2 (en) 2003-09-25 2004-09-23 Deep via seed repair using electroless plating chemistry
PCT/US2004/031447 WO2005031834A1 (en) 2003-09-25 2004-09-23 Deep via seed repair using electroless plating chemistry
KR1020067005728A KR101242289B1 (en) 2003-09-25 2004-09-23 Deep via seed repair using electroless plating chemistry
DE200411001684 DE112004001684B4 (en) 2003-09-25 2004-09-23 Contact hole metallization and seed repair method deep vias (via) using electroless plating chemistry
CNB2004100806921A CN100442498C (en) 2003-09-25 2004-09-27 Deep via seed repair using electroless plating chemistry
US11/280,067 US7479687B2 (en) 2003-09-25 2005-11-15 Deep via seed repair using electroless plating chemistry

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US20060068181A1 (en) 2006-03-30
US7479687B2 (en) 2009-01-20
TWI241665B (en) 2005-10-11
CN1614777A (en) 2005-05-11
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KR20070017469A (en) 2007-02-12
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