US20040241914A1 - Mechanical support system for a thin package - Google Patents
Mechanical support system for a thin package Download PDFInfo
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- US20040241914A1 US20040241914A1 US10/884,654 US88465404A US2004241914A1 US 20040241914 A1 US20040241914 A1 US 20040241914A1 US 88465404 A US88465404 A US 88465404A US 2004241914 A1 US2004241914 A1 US 2004241914A1
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- Prior art keywords
- interposer
- pin carrier
- cavity
- die
- securing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/642—Capacitive arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/143—Digital devices
- H01L2924/1433—Application-specific integrated circuit [ASIC]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19106—Disposition of discrete passive components in a mirrored arrangement on two different side of a common die mounting substrate
Definitions
- the present invention relates generally to electronics packaging. More particularly, the present invention relates to an electronic package that includes a die packaged on a thin interposer, and to manufacturing methods related thereto.
- Integrated circuits have typically been assembled into electronic packages by physically and electrically coupling them to a substrate made of organic or ceramic material.
- IC packages can be physically and electrically coupled to a secondary substrate such as a printed circuit board (PCB) or motherboard to form an electronic assembly.
- PCB printed circuit board
- the electronic assembly can be part of an electronic system.
- An electronic system is broadly defined herein as any product comprising an electronic assembly.
- Examples of electronic systems include computers (e.g., desktop, laptop, hand-held, server, etc.), wireless communications devices (e.g., cellular phones, cordless phones, pagers, etc.), computer-related peripherals (e.g., printers, scanners, monitors, etc.), entertainment devices (e.g., televisions, radios, stereos, tape and compact disc players, video cassette recorders, MP3 (Motion Picture Experts Group, Audio Layer 3) players, etc.), and the like.
- computers e.g., desktop, laptop, hand-held, server, etc.
- wireless communications devices e.g., cellular phones, cordless phones, pagers, etc.
- computer-related peripherals e.g., printers, scanners, monitors, etc.
- entertainment devices e.g., televisions, radios, stereos, tape and compact disc players, video cassette recorders, MP3 (Motion Picture Experts Group, Audio Layer 3) players, etc.
- a typical package includes an IC, such as a die, that is mounted on an interposer which functionally connects the die through a hierarchy of electrically conductive paths to the other elements, such as other ICs, that make up the electronic system.
- SMT Surface mount technology
- One of the conventional methods for surface-mounting an IC on an interposer is called “controlled collapse chip connect” (C4).
- C4 controlled collapse chip connect
- the C4 joints are often used in combination with an underfill, such as an epoxy.
- the epoxy helps to hold the joint together when there is thermal expansion and contraction of the package during operation of the integrated circuit.
- Power delivery is an area of microprocessor development that will be crucial to improving future microprocessors.
- One of the major limitations associated with power delivery is the inductive path, or loop, between a die and one or more capacitors that provide power to the components in the die before another source, such as a voltage regulator, is able to provide a steady supply of power.
- This limitation is typically addressed by attaching the capacitors to the underside of a thin interposer that is positioned between the die and the capacitors in order to minimize the distance between the die and the capacitors. Reducing the distance between the capacitors and the die minimizes the inductive loop that is generated when supplying a voltage to the die.
- the thin interposer leads to another problem as the thin interposer is unable to handle the mechanical loads that are applied by the heat sinks which are typically used to cool the integrated circuit.
- FIG. 1 shows two different types of prior art packages.
- the package 10 illustrated in FIG. 1 includes a die 12 that is mounted onto an interposer 14 using a conventional C4 joint that is supplemented by a conventional underfill 15 .
- a pin carrier 16 is attached to the underside of the interposer 14 to support the interposer 14 along at least the entire area of the die 12 .
- the design of the package 10 in particular the pin carrier 16 , does not permit capacitors, or any other electronic component, to be mounted to the underside of the interposer 14 in that area of the interposer which is opposite to the die 12 . Therefore, the prior art package 10 shown in FIG. 1 suffers from an inductive path problem.
- FIG. 2 shows a prior art package 20 that overcomes the inductive path problem.
- the package 20 includes a die 22 that is mounted onto a thin interposer 24 .
- the die 22 is similarly mounted to the interposer 24 using a conventional C4 joint that is supplemented by a conventional underfill 25 .
- a pin carrier 26 that includes a cavity 27 is mounted to the underside of the thin interposer 24 .
- the cavity 27 in the pin carrier 26 is positioned underneath the die 22 such that capacitors 28 may be mounted to the underside of the interposer 24 opposite to the die 22 using conventional surface mount technology. Placing the capacitors 28 against the interposer 24 within the cavity 27 of the pin carrier 26 reduces the distance between the die 22 and capacitors 28 .
- the thin interposer 24 is incapable of withstanding the mechanical load that is applied to the package 20 by heat sinks and other thermal elements within the integrated circuit during operation of the electronic system where the package 20 is located.
- the mechanical load generates package deflection that results in multiple failure modes, including internal damage to the package circuitry and/or damage to the capacitor joints.
- FIG. 1 is a simplified diagram illustrating a prior art package.
- FIG. 2 is a simplified diagram similar to FIG. 1 illustrating another prior art package having a pin carrier with a cavity.
- FIG. 3 is a simplified diagram similar to FIGS. 1 and 2 illustrating an electronics package of the present invention.
- FIG. 4 is a block diagram of an electronic system incorporating at least one electronic assembly with an electronic package in accordance with the present invention.
- FIG. 3 shows an electronic package 30 of the present invention that overcomes the inductive path problem yet still has sufficient mechanical integrity.
- the package 30 includes a die 32 mounted onto an interposer 34 .
- the die 32 may be any type of IC, such as a processor, memory chip, chipset component, or the like.
- the die 32 is mounted to the interposer 34 using a conventional C4 joint that is supplemented by a common underfill 35 .
- a pin carrier 36 is mounted to the underside of the interposer 34 .
- the pin carrier 36 includes a cavity 37 positioned underneath the die 32 .
- the cavity 37 allows capacitors 38 , or some other electronic component, to be mounted to the underside of the interposer 34 opposite to the die 32 using conventional surface mount technology.
- the cavity 37 in the pin carrier 36 is filled with an encapsulant 39 to mechanically support the thin interposer 34 in the area of the cavity 37 .
- the thin interposer 34 reduces the distance between the die 32 and the capacitors 38 in order to minimize the inductive loop within the package 30 .
- the encapsulant 39 supports the thin interposer 34 in the area of the cavity 37 such that the package 30 is capable of withstanding the mechanical load that is applied to the package 30 by heat sinks and other thermal elements within the electronic assembly where the package 30 is located.
- the encapsulant 39 is preferably an epoxy that bonds with the pin carrier 36 when the epoxy is cured to a rigid state.
- the mechanical support provided by the encapsulant 39 within the package 30 minimizes package deflection during operation of a corresponding electronic system that includes the package 30 . Minimizing package deflection results in less damage to the package circuitry and/or the capacitor 38 joints and is therefore a key component in meeting reliability requirements in electronic packages with thin interposers.
- the epoxy encapsulant 39 and pin carrier 36 combination provide mechanical support while not limiting the ability to place electronic components, such as capacitors 38 , on the underside of the thin interposer 34 opposite to the die 32 .
- the interposer 34 may be formed in one or more layers and be made of metal and/or an organic material.
- the interposer 34 may also be formed in a thin, flexible, electrically insulating or conducting tape or film that are made from materials such as polyester, polyparabanic acid, epoxy, and fiberglass.
- the interposer 34 may also include a plurality of conductive traces that are formed using any suitable conductive material, such as copper, aluminum, silver, or the like.
- the interposer 34 preferably has a thickness of less than 1 mm. However, in other embodiments, a thicker or thinner interposer 34 may be used depending on what material the interposer 34 is made from.
- the interposer 34 is preferably secured to the pin carrier 36 via a ball grid array (BGA) of solder balls, although any joining technique that facilitates fabricating the package 30 may be used.
- BGA ball grid array
- the pin carrier 36 may be a printed circuit board (PCB) or card, a motherboard, or any other type of packaging element.
- the pin carrier 36 may be multi-layered or single-layered.
- the present invention is not to be construed as limited to any particular type of pin carrier or to any particular method of coupling the pin carrier 36 to the interposer 34 .
- pin carrier refers to pin or ball-type carriers.
- the cavity 37 in the pin carrier 36 includes an inner perimeter and the die 32 includes an outer perimeter.
- the perimeter of the die 32 is preferably smaller than the perimeter of the cavity while being substantially aligned with perimeter of the cavity 37 .
- the invention applies equally to embodiments where the cavity 37 is positioned anywhere opposite to the die 32 .
- the invention has been described such that a die 32 is mounted on the interposer 34 .
- the die 32 could also be a passive component such as a resistor, capacitor, or inductor, or any other type of electronic component, whether or not implemented as an IC, such as an oscillator, filter, sensor, variable resistor, fuse, coil, or the like.
- the present invention also relates to a method of fabricating an electronics package 30 .
- the method includes securing a die 32 to one side of an interposer 34 and securing a pin carrier 36 to an opposing side of the interposer 34 .
- the pin carrier 36 includes a cavity 37 that is positioned against the interposer 24 opposite to the die 32 such that capacitors 38 , or some other type of electronic component, are secured to the interposer 34 within the cavity 37 .
- the method further includes at least partially filling the cavity 37 in the pin carrier 36 with an encapsulant 39 to provide mechanical support to the interposer 34 during operation of the electronics package 30 .
- the pin carrier 36 and the capacitors 38 are preferably secured to the interposer 34 substantially simultaneously to decrease manufacturing costs.
- securing the die 32 the interposer 34 preferably includes forming a C4 joint between the die 32 and interposer 34 and underfilling the C4 joint with an epoxy.
- At least partially filling the cavity 37 in the pin carrier 36 with an encapsulant 39 may further include bonding the encapsulant 39 with the pin carrier 36 depending on the types of materials that are used for the encapsulant 39 and the pin carrier 36 .
- FIG. 4 is a block diagram of an electronic system 40 incorporating at least one electronic assembly 41 that includes an electronic package, such as electronic package 30 shown in FIG. 3.
- the electronic package in the electronic assembly 41 has minimal inductance loop yet maintains sufficient mechanical integrity.
- the illustrated electronic system 40 is merely one example of an electronic system in which the electronic package of the present invention may be used.
- the electronic system 40 comprises a data processing system that includes a system bus 42 which electrically couples the various components of the electronic system 40 together.
- the system bus 42 may be a single bus or any combination of busses.
- the electronic assembly 41 is coupled to the system bus 42 and may include any circuit or combination of circuits.
- the electronic assembly 41 includes a processor 46 which can be of any type.
- processor means any type of computational circuit such as, but not limited to, a microprocessor, a microcontroller, a graphics processor, a digital signal processor (DSP), or any other type of processor or processing circuit.
- DSP digital signal processor
- circuits that can be included in electronic assembly 41 are a custom circuit, an application-specific integrated circuit (ASIC), or the like, such as, for example, one or more circuits (such as a communications circuit 47 ) for use in wireless devices such as cellular telephones, pagers, portable computers, two-way radios, and similar electronic systems.
- ASIC application-specific integrated circuit
- the electronic system 40 may also include an external memory 50 , which in turn may include one or more memory elements suitable to the particular application, such as a main memory 52 in the form of random access memory (RAM), one or more hard drives 54 , and/or one or more drives that handle removable media 56 such as floppy diskettes, compact disks (CDs), digital video disk (DVD), and the like.
- a main memory 52 in the form of random access memory (RAM)
- hard drives 54 and/or one or more drives that handle removable media 56 such as floppy diskettes, compact disks (CDs), digital video disk (DVD), and the like.
- removable media 56 such as floppy diskettes, compact disks (CDs), digital video disk (DVD), and the like.
- the electronic system 40 may also include a display device 58 , a speaker 59 , and a keyboard and/or controller 60 such as a mouse, trackball, game controller, microphone, voice-recognition device, or any other device that permits a system user to input information into and receive information from the electronic system 40 .
- the present invention can be implemented in a number of different embodiments, including an electronic package, an electronic system, a data processing system, one or more methods of fabricating an electronic package, and one or more methods of fabricating an electronic assembly that includes the package.
- Other embodiments will be readily apparent to those of ordinary skill in the art.
- the elements, materials, geometries, dimensions, and sequence of operations can all be varied to suit particular packaging requirements.
- FIGS. 1-4 are merely representational and are not drawn to scale. Certain proportions thereof may be exaggerated, while others may be minimized.
- FIGS. 3 and 4 illustrate various implementations of the invention that can be understood and appropriately carried out by those of ordinary skill in the art.
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- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
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Abstract
An electronic package includes an IC, such as a die, mounted onto one side of a thin interposer and a pin carrier mounted to an opposing side of the interposer. The pin carrier includes a cavity underneath the die. The cavity allows capacitors, or other electronic components, to be mounted against the interposer beneath the die. The cavity in the pin carrier is filled with an encapsulant to mechanically support the thin interposer in the area of the cavity during operation of an electronic system that includes the package.
Description
- This application is a divisional of U.S. patent application Ser. No. 10/045,315, filed on Oct. 24, 2001, which is incorporated herein by reference.
- The present invention relates generally to electronics packaging. More particularly, the present invention relates to an electronic package that includes a die packaged on a thin interposer, and to manufacturing methods related thereto.
- Integrated circuits (ICs) have typically been assembled into electronic packages by physically and electrically coupling them to a substrate made of organic or ceramic material. One or more such IC packages can be physically and electrically coupled to a secondary substrate such as a printed circuit board (PCB) or motherboard to form an electronic assembly. The electronic assembly can be part of an electronic system. An electronic system is broadly defined herein as any product comprising an electronic assembly. Examples of electronic systems include computers (e.g., desktop, laptop, hand-held, server, etc.), wireless communications devices (e.g., cellular phones, cordless phones, pagers, etc.), computer-related peripherals (e.g., printers, scanners, monitors, etc.), entertainment devices (e.g., televisions, radios, stereos, tape and compact disc players, video cassette recorders, MP3 (Motion Picture Experts Group, Audio Layer 3) players, etc.), and the like.
- Manufacturers of electronic systems constantly try to improve product performance while reducing production costs. This is particularly true regarding the packaging of ICs, where each new generation of packaging must provide increased performance while generally being smaller or more compact in size. Therefore, manufacturers of high-end ICs, such as processors, continually develop IC packages that are thinner, lighter-weight, and/or more resilient because such packaging is useful for many applications.
- A typical package includes an IC, such as a die, that is mounted on an interposer which functionally connects the die through a hierarchy of electrically conductive paths to the other elements, such as other ICs, that make up the electronic system. Surface mount technology (SMT) is a widely known technique for coupling a die to an interposer. One of the conventional methods for surface-mounting an IC on an interposer is called “controlled collapse chip connect” (C4). In fabricating a C4 joint, the electrically conductive terminals or lands of an IC component are soldered directly to corresponding lands on the surface of the interposer using reflowable solder bumps or balls. The C4 process is widely used because of its robustness and simplicity.
- The C4 joints are often used in combination with an underfill, such as an epoxy. The epoxy helps to hold the joint together when there is thermal expansion and contraction of the package during operation of the integrated circuit.
- Power delivery is an area of microprocessor development that will be crucial to improving future microprocessors. One of the major limitations associated with power delivery is the inductive path, or loop, between a die and one or more capacitors that provide power to the components in the die before another source, such as a voltage regulator, is able to provide a steady supply of power. This limitation is typically addressed by attaching the capacitors to the underside of a thin interposer that is positioned between the die and the capacitors in order to minimize the distance between the die and the capacitors. Reducing the distance between the capacitors and the die minimizes the inductive loop that is generated when supplying a voltage to the die. However, the thin interposer leads to another problem as the thin interposer is unable to handle the mechanical loads that are applied by the heat sinks which are typically used to cool the integrated circuit.
- FIGS. 1 and 2 show two different types of prior art packages. The
package 10 illustrated in FIG. 1 includes adie 12 that is mounted onto aninterposer 14 using a conventional C4 joint that is supplemented by aconventional underfill 15. Apin carrier 16 is attached to the underside of theinterposer 14 to support theinterposer 14 along at least the entire area of the die 12. The design of thepackage 10, in particular thepin carrier 16, does not permit capacitors, or any other electronic component, to be mounted to the underside of theinterposer 14 in that area of the interposer which is opposite to thedie 12. Therefore, theprior art package 10 shown in FIG. 1 suffers from an inductive path problem. - FIG. 2 shows a prior art package20 that overcomes the inductive path problem. The package 20 includes a
die 22 that is mounted onto athin interposer 24. The die 22 is similarly mounted to theinterposer 24 using a conventional C4 joint that is supplemented by aconventional underfill 25. Apin carrier 26 that includes acavity 27 is mounted to the underside of thethin interposer 24. Thecavity 27 in thepin carrier 26 is positioned underneath the die 22 such thatcapacitors 28 may be mounted to the underside of theinterposer 24 opposite to the die 22 using conventional surface mount technology. Placing thecapacitors 28 against theinterposer 24 within thecavity 27 of thepin carrier 26 reduces the distance between the die 22 andcapacitors 28. This reduced distance minimizes the inductive loop problem. However, thethin interposer 24 is incapable of withstanding the mechanical load that is applied to the package 20 by heat sinks and other thermal elements within the integrated circuit during operation of the electronic system where the package 20 is located. The mechanical load generates package deflection that results in multiple failure modes, including internal damage to the package circuitry and/or damage to the capacitor joints. - As the internal circuitry of processors operates at higher and higher clock frequencies, and as processors operate at higher and higher power levels, the amount of loop inductance produced within processor packages often increases to unacceptable levels. Therefore, there is a significant need for a reliable electronics package, and methods of fabricating an electronics package, that generates minimal loop inductance within the package yet is mechanically stable.
- FIG. 1 is a simplified diagram illustrating a prior art package.
- FIG. 2 is a simplified diagram similar to FIG. 1 illustrating another prior art package having a pin carrier with a cavity.
- FIG. 3 is a simplified diagram similar to FIGS. 1 and 2 illustrating an electronics package of the present invention.
- FIG. 4 is a block diagram of an electronic system incorporating at least one electronic assembly with an electronic package in accordance with the present invention.
- In the following detailed description of embodiments of the invention, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific preferred embodiments in which the inventions may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other embodiments may be utilized and that mechanical, chemical, structural, electrical, and procedural changes may be made without departing from the spirit and scope of the present invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims.
- The present invention provides a solution to thickness, weight, and/or rigidity limitations in an electronic package, and to loop induction problems that are associated with prior art electronic packages. FIG. 3 shows an
electronic package 30 of the present invention that overcomes the inductive path problem yet still has sufficient mechanical integrity. Thepackage 30 includes a die 32 mounted onto aninterposer 34. The die 32 may be any type of IC, such as a processor, memory chip, chipset component, or the like. The die 32 is mounted to theinterposer 34 using a conventional C4 joint that is supplemented by acommon underfill 35. Apin carrier 36 is mounted to the underside of theinterposer 34. Thepin carrier 36 includes acavity 37 positioned underneath the die 32. Thecavity 37 allowscapacitors 38, or some other electronic component, to be mounted to the underside of theinterposer 34 opposite to the die 32 using conventional surface mount technology. Thecavity 37 in thepin carrier 36 is filled with anencapsulant 39 to mechanically support thethin interposer 34 in the area of thecavity 37. - The
thin interposer 34 reduces the distance between thedie 32 and thecapacitors 38 in order to minimize the inductive loop within thepackage 30. Theencapsulant 39 supports thethin interposer 34 in the area of thecavity 37 such that thepackage 30 is capable of withstanding the mechanical load that is applied to thepackage 30 by heat sinks and other thermal elements within the electronic assembly where thepackage 30 is located. Theencapsulant 39 is preferably an epoxy that bonds with thepin carrier 36 when the epoxy is cured to a rigid state. - The mechanical support provided by the
encapsulant 39 within thepackage 30 minimizes package deflection during operation of a corresponding electronic system that includes thepackage 30. Minimizing package deflection results in less damage to the package circuitry and/or thecapacitor 38 joints and is therefore a key component in meeting reliability requirements in electronic packages with thin interposers. In addition, theepoxy encapsulant 39 andpin carrier 36 combination provide mechanical support while not limiting the ability to place electronic components, such ascapacitors 38, on the underside of thethin interposer 34 opposite to thedie 32. - The
interposer 34 may be formed in one or more layers and be made of metal and/or an organic material. Theinterposer 34 may also be formed in a thin, flexible, electrically insulating or conducting tape or film that are made from materials such as polyester, polyparabanic acid, epoxy, and fiberglass. Theinterposer 34 may also include a plurality of conductive traces that are formed using any suitable conductive material, such as copper, aluminum, silver, or the like. Theinterposer 34 preferably has a thickness of less than 1 mm. However, in other embodiments, a thicker orthinner interposer 34 may be used depending on what material theinterposer 34 is made from. Theinterposer 34 is preferably secured to thepin carrier 36 via a ball grid array (BGA) of solder balls, although any joining technique that facilitates fabricating thepackage 30 may be used. - In alternative forms of the invention, the
pin carrier 36 may be a printed circuit board (PCB) or card, a motherboard, or any other type of packaging element. Thepin carrier 36 may be multi-layered or single-layered. The present invention is not to be construed as limited to any particular type of pin carrier or to any particular method of coupling thepin carrier 36 to theinterposer 34. As used herein, pin carrier refers to pin or ball-type carriers. - The
cavity 37 in thepin carrier 36 includes an inner perimeter and thedie 32 includes an outer perimeter. The perimeter of the die 32 is preferably smaller than the perimeter of the cavity while being substantially aligned with perimeter of thecavity 37. - While an embodiment of the
package 30 is shown in which thepin carrier 36 is positioned around the periphery of the die 32, the invention applies equally to embodiments where thecavity 37 is positioned anywhere opposite to thedie 32. The invention has been described such that adie 32 is mounted on theinterposer 34. However, thedie 32 could also be a passive component such as a resistor, capacitor, or inductor, or any other type of electronic component, whether or not implemented as an IC, such as an oscillator, filter, sensor, variable resistor, fuse, coil, or the like. - The present invention also relates to a method of fabricating an
electronics package 30. The method includes securing a die 32 to one side of aninterposer 34 and securing apin carrier 36 to an opposing side of theinterposer 34. Thepin carrier 36 includes acavity 37 that is positioned against theinterposer 24 opposite to the die 32 such thatcapacitors 38, or some other type of electronic component, are secured to theinterposer 34 within thecavity 37. The method further includes at least partially filling thecavity 37 in thepin carrier 36 with anencapsulant 39 to provide mechanical support to theinterposer 34 during operation of theelectronics package 30. - The
pin carrier 36 and thecapacitors 38 are preferably secured to theinterposer 34 substantially simultaneously to decrease manufacturing costs. In addition, securing the die 32 theinterposer 34 preferably includes forming a C4 joint between the die 32 andinterposer 34 and underfilling the C4 joint with an epoxy. At least partially filling thecavity 37 in thepin carrier 36 with anencapsulant 39 may further include bonding theencapsulant 39 with thepin carrier 36 depending on the types of materials that are used for theencapsulant 39 and thepin carrier 36. - The operations discussed above with respect to the described methods may be performed in a different order from those described herein. Also, it will be understood that the method of the present invention may be performed continuously.
- FIG. 4 is a block diagram of an
electronic system 40 incorporating at least oneelectronic assembly 41 that includes an electronic package, such aselectronic package 30 shown in FIG. 3. The electronic package in theelectronic assembly 41 has minimal inductance loop yet maintains sufficient mechanical integrity. - The illustrated
electronic system 40 is merely one example of an electronic system in which the electronic package of the present invention may be used. Theelectronic system 40 comprises a data processing system that includes asystem bus 42 which electrically couples the various components of theelectronic system 40 together. Thesystem bus 42 may be a single bus or any combination of busses. - The
electronic assembly 41 is coupled to thesystem bus 42 and may include any circuit or combination of circuits. In one embodiment, theelectronic assembly 41 includes aprocessor 46 which can be of any type. As used herein, processor means any type of computational circuit such as, but not limited to, a microprocessor, a microcontroller, a graphics processor, a digital signal processor (DSP), or any other type of processor or processing circuit. - Other types of circuits that can be included in
electronic assembly 41 are a custom circuit, an application-specific integrated circuit (ASIC), or the like, such as, for example, one or more circuits (such as a communications circuit 47) for use in wireless devices such as cellular telephones, pagers, portable computers, two-way radios, and similar electronic systems. - The
electronic system 40 may also include anexternal memory 50, which in turn may include one or more memory elements suitable to the particular application, such as amain memory 52 in the form of random access memory (RAM), one or morehard drives 54, and/or one or more drives that handleremovable media 56 such as floppy diskettes, compact disks (CDs), digital video disk (DVD), and the like. - The
electronic system 40 may also include adisplay device 58, aspeaker 59, and a keyboard and/orcontroller 60 such as a mouse, trackball, game controller, microphone, voice-recognition device, or any other device that permits a system user to input information into and receive information from theelectronic system 40. - As shown herein, the present invention can be implemented in a number of different embodiments, including an electronic package, an electronic system, a data processing system, one or more methods of fabricating an electronic package, and one or more methods of fabricating an electronic assembly that includes the package. Other embodiments will be readily apparent to those of ordinary skill in the art. The elements, materials, geometries, dimensions, and sequence of operations can all be varied to suit particular packaging requirements.
- FIGS. 1-4 are merely representational and are not drawn to scale. Certain proportions thereof may be exaggerated, while others may be minimized. FIGS. 3 and 4 illustrate various implementations of the invention that can be understood and appropriately carried out by those of ordinary skill in the art.
- Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement that is calculated to achieve the same purpose may be substituted for the specific embodiment shown. This application is intended to cover any adaptations or variations of the present invention. Therefore, it is manifestly intended that this invention be limited only by the claims and the equivalents thereof.
Claims (20)
1. A method of fabricating an electronics package, the method comprising:
securing a die to one side of an interposer, the interposer being a tape having a thickness less than 1 mm;
securing a pin carrier to an opposing side of the interposer, the pin carrier including a cavity positioned against the interposer opposite to the die;
securing an electronic component to the interposer such that the electronic component is positioned within the cavity in the pin carrier;
substantially filling the cavity in the pin carrier with an encapsulant while not overflowing the cavity with the encapsulant such that the interposer is capable of withstanding a mechanical load generated by thermal elements and is incapable of withstanding the mechanical load without the encapsulant.
2. The method of claim 1 , wherein securing the pin carrier to the interposer and securing the electronic component to the interposer are done substantially simultaneously.
3. The method of claim 1 , wherein securing a die to one side of an interposer includes forming a C4 joint between the die and interposer.
4. The method of claim 3 , wherein securing a die to one side of an interposer includes underfilling the C4 joint between the die and interposer with an epoxy.
5. The method of claim 1 , wherein substantially filling the cavity in the pin carrier with an encapsulant includes filling the entire cavity with an encapsulant.
6. The method of claim 1 , wherein substantially filling the cavity in the pin carrier with an encapsulant includes bonding the encapsulant to the pin carrier.
7. The method of claim 1 , wherein the electronic component is a capacitor such that securing an electronic component to the interposer includes securing the capacitor within the cavity in the pin carrier to minimize the inductive loop between the capacitor and the die.
8. The method of claim 1 , wherein securing a pin carrier to an opposing side of the interposer includes attaching the pin carrier to the interposer using a ball grid array of solder balls.
9. The method of claim 1 , wherein securing a pin carrier to an opposing side of the interposer includes substantially aligning a perimeter of the die with a perimeter of the cavity in the pin carrier.
10. The method of claim 9 , wherein substantially aligning a perimeter of the die with a perimeter of the cavity in the pin carrier includes placing the die and the pin carrier on the interposer such that the die is substantially concentric with the cavity in the pin carrier.
11. The method of claim 1 , wherein securing an electronic component to the interposer includes surface mounting the electronic component to the interposer.
12. The method of claim 11 , wherein surface mounting the electronic component to the interposer includes surface mounting a capacitor to the interposer.
13. A method of fabricating an electronics package, the method comprising:
securing a die to one side of an interposer;
securing a pin carrier to an opposing side of the interposer, the pin carrier including a cavity positioned against the interposer opposite to the die;
securing an electronic component to the interposer such that the electronic component is positioned within the cavity in the pin carrier;
substantially filling the cavity in the pin carrier with an encapsulant while not overflowing the cavity with the encapsulant such that the interposer is capable of withstanding a mechanical load generated by thermal elements.
14. The method of claim 13 , wherein the interposer is a tape having a thickness less than 1 mm such that the interposer is incapable of withstanding the mechanical load without the encapsulant.
15. The method of claim 13 , wherein substantially filling the cavity in the pin carrier with an encapsulant includes filling the entire cavity with an encapsulant.
16. The method of claim 13 , wherein the electronic component is a capacitor such that securing an electronic component to the interposer includes securing the capacitor within the cavity in the pin carrier to minimize the inductive loop between the capacitor and the die.
17. A method of fabricating an electronics package, the method comprising:
securing a die to one side of an interposer, the interposer being a tape having a thickness less than 1 mm;
securing a pin carrier to an opposing side of the interposer, the pin carrier including a cavity positioned against the interposer opposite to the die;
securing a capacitor to the interposer such that the capacitor is positioned within the cavity in the pin carrier to minimize the inductive loop between the capacitor and the die;
substantially filling the cavity in the pin carrier with an encapsulant while not overflowing the cavity with the encapsulant such that the interposer is capable of withstanding a mechanical load generated by thermal elements and is incapable of withstanding the mechanical load without the encapsulant.
18. The method of claim 17 , wherein securing a capacitor to the interposer includes surface mounting the capacitor to the interposer.
19. The method of claim 17 , wherein securing a pin carrier to an opposing side of the interposer includes attaching the pin carrier to the interposer using a ball grid array of solder balls.
20. The method of claim 17 , wherein the pin carrier and the capacitor are secured to the interposer substantially simultaneously.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/884,654 US20040241914A1 (en) | 2001-10-24 | 2004-07-02 | Mechanical support system for a thin package |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/045,315 US6777818B2 (en) | 2001-10-24 | 2001-10-24 | Mechanical support system for a thin package |
US10/884,654 US20040241914A1 (en) | 2001-10-24 | 2004-07-02 | Mechanical support system for a thin package |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/045,315 Division US6777818B2 (en) | 2001-10-24 | 2001-10-24 | Mechanical support system for a thin package |
Publications (1)
Publication Number | Publication Date |
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US20040241914A1 true US20040241914A1 (en) | 2004-12-02 |
Family
ID=21937175
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/045,315 Expired - Fee Related US6777818B2 (en) | 2001-10-24 | 2001-10-24 | Mechanical support system for a thin package |
US10/884,654 Abandoned US20040241914A1 (en) | 2001-10-24 | 2004-07-02 | Mechanical support system for a thin package |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
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US10/045,315 Expired - Fee Related US6777818B2 (en) | 2001-10-24 | 2001-10-24 | Mechanical support system for a thin package |
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US (2) | US6777818B2 (en) |
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US20080001310A1 (en) * | 2006-06-30 | 2008-01-03 | Sathe Ajit V | Multiple-dice packages with controlled underfill and methods of manufacture |
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US20130078745A1 (en) * | 2011-09-28 | 2013-03-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Production Flow and Reusable Testing Method |
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US20030122173A1 (en) * | 2001-12-28 | 2003-07-03 | Rabadam Eleanor P. | Package for a non-volatile memory device including integrated passive devices and method for making the same |
US7038305B1 (en) * | 2003-07-15 | 2006-05-02 | Altera Corp. | Package for integrated circuit die |
US7339263B2 (en) * | 2004-06-28 | 2008-03-04 | Intel Corporation | Integrated circuit packages, systems, and methods |
US7745912B2 (en) * | 2005-03-25 | 2010-06-29 | Intel Corporation | Stress absorption layer and cylinder solder joint method and apparatus |
US8264846B2 (en) * | 2006-12-14 | 2012-09-11 | Intel Corporation | Ceramic package substrate with recessed device |
JP2008171965A (en) * | 2007-01-11 | 2008-07-24 | Fuji Electric Device Technology Co Ltd | Microminiature power converter |
US20110050334A1 (en) * | 2009-09-02 | 2011-03-03 | Qualcomm Incorporated | Integrated Voltage Regulator with Embedded Passive Device(s) |
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Also Published As
Publication number | Publication date |
---|---|
US6777818B2 (en) | 2004-08-17 |
US20030075787A1 (en) | 2003-04-24 |
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