JP3586867B2 - Semiconductor device, method of manufacturing the same, method of mounting the same, and circuit board mounting the same - Google Patents

Semiconductor device, method of manufacturing the same, method of mounting the same, and circuit board mounting the same Download PDF

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JP3586867B2
JP3586867B2 JP53555498A JP53555498A JP3586867B2 JP 3586867 B2 JP3586867 B2 JP 3586867B2 JP 53555498 A JP53555498 A JP 53555498A JP 53555498 A JP53555498 A JP 53555498A JP 3586867 B2 JP3586867 B2 JP 3586867B2
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insulating film
wiring pattern
semiconductor device
holding plate
thermal expansion
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伸晃 橋元
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Seiko Epson Corp
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    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
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    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09909—Special local insulating pattern, e.g. as dam around component
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10734—Ball grid array [BGA]; Bump grid array
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/20—Details of printed circuits not provided for in H05K2201/01 - H05K2201/10
    • H05K2201/2036—Permanent spacer or stand-off in a printed circuit or printed circuit assembly
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Abstract

A surface-mounted type semiconductor device which can be easily mounted. The semiconductor device has a semiconductor element (16), an insulating film (12), a wiring pattern (20) which is formed on one face of the insulating film (12) and is connected to the semiconductor element (16), bumps (14) formed on a rear face of the wiring pattern (20) projected on the other face of the insulating film (12) via through holes (12a) in the insulating film (12), and a holding plate (24) which is so pasted on one face of the insulating film (12) as to cover the wiring pattern (20) to keep a flatness with a conductivity. The holding plate (24) is connected to a constant potential section of the wiring pattern (20).

Description

技術分野
本発明は、面実装型の半導体装置、その製造方法及びその実装方法並びにこれを実装した回路基板に関する。
背景技術
半導体装置の小型化を追求するとベアチップ実装が理想的であるが、品質の保証及び取り扱いが難しいため、パッケージ形態に加工することで対応してきた。そのパッケージ形態において、特に多端子化の要求に応じて近年BGA（ball grid array）型パッケージがでてきている。BGAパッケージは基板の基材により数種類にわけられるが、特に狭ピッチパッドの半導体素子を実装しなければならないニーズや、製造においてテープ状にして製造を行うことで連続性をもたせることが可能となるといった製造効率上の要求からフレキシブル（可撓性）基材を基板の基材として用いたフレキシブルテープ利用型のBGAパッケージが存在する。このBGAパッケージはフレキシブル基板に外部端子であるバンプをエリアアレイ状に配置し、面実装できるようにしたものである。
このBGAパッケージによれば、チップの電極からバンプまでを接続する配線パターンが、フレキシブル基板に露出して形成されており、回路基板への実装時に、配線パターンの品質を劣化させないように慎重に取り扱うことが必要であった。
しかも、BGAパッケージによれば、バンプと回路基板のパッドとの接続状態の確認及び検査ができないのみならず、接続不良があっても修復できないため、実装に高精度が要求されていた。
あるいは、BGAパッケージに使用されるフレキシブル基板は、その柔軟性から、反りが生じて実装しにくい場合があった。
このように、従来のBGAパッケージは、実装時に種々の問題を抱えるものであった。
本発明は、この問題点を解決するものであり、その目的は、容易な実装を可能にする面実装型の半導体装置、その製造方法及びその実装方法並びにこれを実装した回路基板を提供することにある。
発明の開示
本発明に係る半導体装置は、半導体素子と、
貫通孔を有する絶縁フィルムと、
前記絶縁フィルムの一方の面側において前記貫通孔上を通るように形成されるとともに前記半導体素子に接続される配線パターンと、
前記絶縁フィルムの他方の面側に設けられるとともに前記貫通孔を介して前記配線パターンと電気的な接続がなされている外部端子と、
導電性を有するとともに平面性を保つ部材からなり、前記配線パターンの前記絶縁フィルムが設けられた面の反対面側に前記配線パターンの少なくとも一部を覆うように設けられる保持板と、を有し、
前記保持板は、絶縁性の接着剤を介して前記絶縁フィルムに貼り付けられるとともに、前記配線パターンの一定電位部に接続されてなる。
この半導体装置は、絶縁フィルムを境として配線パターン形成面側とバンプ形成面側が異なるようになっていることから、配線パターン形成面側には配線パターン以外の障害物がない。従って、保持板は特殊加工（パターニング）せずそのまま用いられて配線パターンを覆うことができるので、製造作業が極めて容易になる。また、配線パターンの表面を保護できるだけでなく、平面性を保てる強度を有する保持板が絶縁フィルムを覆うので、可撓性を有する絶縁フィルムは歪むことがなくなり、バンプの平面安定性が向上し、回路基板への実装の歩留まりが向上する。
また、前記保持板は、導電性を有し、配線パターンの一定電位部と接続されている。ここで、一定電位部とは、半導体装置の動作中に変化しない電位となる部分である。また、絶縁性の接着剤によって、導電性の保持板と配線パターンとの短絡を防止できる。
こうして、保持板が一定の電位になると、保持板にて形成される面状の一定電位に沿って、配線パターンに信号が伝送されるので、理想的な伝送路となり、インピーダンス特にインダクタンスの小さい伝送が可能となる。そして、高周波信号の遅れやなまりを減少させて伝送特性を向上させ、信頼性の高い半導体装置を得ることができる。
前記保持板と前記配線パターンとの間に、前記配線パターンを覆う保護層が存在してもよい。
つまり、配線パターンの絶縁フィルムが設けられていない側の保持板が貼られる位置の全面にはあらかじめレジスト等の保護層が設けられていて、更にその上に接着剤を介して保持板が貼り付けられても良い。この場合も、配線パターンにおける外部端子の形成面とは反対面側に保護層を設けるので、レジストなどを塗布することが簡単である。また、保持板を設ける際に、保護層によって予め配線パターンが保護されているので、断線など配線パターンについての不良が生じなくなる。
一定電位部は、電源電位及びグランド電位のいずれか一方であってもよい。
前記配線パターンは、少なくとも一部に湾曲部を有し、前記湾曲部が前記保持板に接続されてもよい。
前記保持板は、ハンダ及び導電性接着剤のうち少なくともいずれか一方によって、前記配線パターンの一定電位部と接続されてもよい。
これらによっても、伝送特性を向上させられる。
本発明に係る半導体装置は、半導体素子と、絶縁フィルムと、前記絶縁フィルム上に形成されるとともに前記半導体素子に接続される配線パターンと、前記配線パターン上に形成される外部端子と、導電性を有するとともに平面性を保つ部材からなり前記絶縁フィルムの一部を保持する保持板と、を有し、
前記保持板は、前記配線パターンの一定電位部に接続されてなる。
本発明によれば、保持板を設けることで、柔軟性を有する絶縁フィルムの反りを防止することができ、確実な実装が可能になる。
また、前記保持板は、導電性を有し、配線パターンの一定電位部と接続されている。ここで、一定電位部とは、半導体装置の動作中に変化しない電位となる部分である。
こうして、保持板が一定の電位になると、保持板にて形成される面状の一定電位に沿って、配線パターンに信号が伝送されるので、理想的な伝送路となり、インピーダンス特にインダクタンスの小さい伝送が可能となる。そして、高周波信号の遅れやなまりを減少させて伝送特性を向上させ、信頼性の高い半導体装置を得ることができる。
前記保持板には、前記絶縁フィルムの熱膨張係数よりも大きい熱膨張係数を有する部材を用いてもよい。
上記半導体装置において、前記保持板は、スリット又は溝を有し、前記絶縁フィルムの端部は、前記スリット又は溝に挿入されて前記保持板に保持されてもよい。
上記半導体装置において、前記絶縁フィルムは、スリットを有し、前記保持板は、前記スリットを介して前記絶縁フィルムの反対側面に、端部が突出するように取り付けられてもよい。
本発明に係る半導体装置の製造方法は、絶縁フィルムに貫通孔を形成する工程と、
前記絶縁フィルムの一方の面側に前記貫通孔上を通る配線パターンを形成する工程と、
前記配線パターンにおける前記絶縁フィルム側の面に前記貫通孔を介して前記絶縁フィルムの他方の面側に突出する外部端子を形成する工程と、
半導体素子を前記配線パターンに接続して前記絶縁フィルムに設ける工程と、
前記配線パターンの前記絶縁フィルムが設けられた面の反射面側に、前記配線パターンの少なくとも一部を覆うように、導電性を有するとともに平面性を保つ部材からなる保持板を貼り付ける工程と、
前記配線パターンの一部を前記保持板に接続する工程と、
を含む。
この方法により製造された半導体装置は、配線パターンとは反対側からバンプが突出し、保持板が配線パターンを覆う。
この方法により製造された半導体装置によれば、保持板が、配線パターンの一部と同電位となり、保持板が面状であるため、インピーダンスの小さい電気的接続が可能となる。
上記半導体装置の製造方法において、
前記保持板を、絶縁性の接着剤を介して前記絶縁フィルムに貼り付けてもよい。
上記半導体装置の製造方法において、
前記絶縁フィルムは、前記配線パターンに対応する開口部を有し、
前記絶縁フィルムの前記他方の面から前記開口部を介して加圧治具を押し入れて、前記配線パターンの一部を、屈曲させて前記保持板に接続してもよい。
本発明に係る半導体装置の製造方法は、絶縁フィルムに配線パターンを形成する工程と、半導体素子を前記配線パターンに接続して前記絶縁フィルムに設ける工程と、前記絶縁フィルムの端部を保持する保持板を取り付ける工程と、前記配線パターンの一部を前記保持板に電気的に接続する工程と、を含む。
この方法により製造された半導体装置によれば、柔軟性を有する絶縁フィルムの反りを防止することができ、確実な実装が可能になる。また、配線パターンの一部が保持板に電気的に接続されているので、外部のノイズの影響を受けにくい構造の半導体装置を得ることができる。
本発明に係る回路基板は、上記半導体装置と、所望の導電パターンが形成された基板と、を有し、
前記半導体装置の前記外部端子が前記導電パターンに接続されてなる。
本発明によれば、保持板が一定電位となっているので、半導体装置は一定電位の平面上に配置されることになる。このことによって、半導体装置は、同軸ケーブルのように、外部のノイズの影響を受けにくい構造となる。
本発明に係る回路基板は、半導体素子と、絶縁フィルムと、前記絶縁フィルムに形成されて前記半導体素子に接続される配線パターンと、前記配線パターン上に形成されるバンプと、導電性を有するとともに平面性を保つ部材からなり前記配線パターンに電気的に接続される保持材と、を含む半導体装置と、
所望の導電パターンが形成され、前記絶縁フィルムの少なくとも端部と接着剤にて固定される基板と、
を有する。
この回路基板によれば、絶縁フィルムの少なくとも端部が固定されるので、その反りが防止される。また、配線パターンと保持板とが電気的に接続されているので、外部のノイズの影響を受けにくい構造が得られる。
本発明に係る半導体装置の実装方法は、ハンダバンプが形成された絶縁フィルムと、導電性を有するとともに平面性を保つ部材からなり前記配線パターンに電気的に接続される保持材と、を有する半導体装置の実装方法において、
前記絶縁フィルムの少なくとも端部に接着剤を塗布して回路基板に接着してから、ハンダバンプを溶融させて前記回路基板のパッドに接続する方法である。
本発明によれば、絶縁フィルムを接着剤で固定して絶縁フィルムの反りをなくしてから、ハンダによる電気的な接続を行うことができる。また、配線パターンと保持板とが電気的に接続されているので、外部のノイズの影響を受けにくい構造が得られる。
【図面の簡単な説明】
図１は、第１実施形態に係る半導体装置を示す図であり、図２は、第２実施形態に係る半導体装置を示す図であり、図3A及び図3Bは、第３実施形態及びその変形例に係る半導体装置を示す図であり、図４は、第４実施形態の他の変形例を示す図であり、図5A〜図5Cは、第５実施形態及びその変形例に係る半導体装置を示す図であり、図６は、第６実施形態に係る半導体装置を示す図であり、図７は、第７実施形態に係る半導体装置を示す図であり、図８は、第８実施形態に係る半導体装置を示す図であり、図９は、第９実施形態に係る半導体装置を示す図であり、図10は、第10実施形態に係る半導体装置を示す図であり、図11は、第11実施形態に係る回路基板を示す図であり、図12Aは、第12実施形態に係る回路基板を示す図であり、図12Bは、第12実施形態の変形例を示す図であり、図13は、本発明に係る方法を適用して製造された半導体装置を実装した回路基板を示す図であり、図14は、本発明に係る方法を適用して製造された半導体装置を実装した回路基板を備える電子機器を示す図である。
発明を実施するための最良の形態
以下、本発明の好適な実施の形態について図面を参照して説明する。
（第１実施形態）
図１は、第１実施形態に係る半導体装置を示す図である。この半導体装置10は、BGAパッケージを適用したものである。すなわち、同図において、絶縁フィルム12に多数のバンプ14が形成され、半導体チップ16の電極18とバンプ14とを接続する配線パターン20が形成されている。
絶縁フィルム12は、長尺のフィルムキャリアテープをパンチングして得られるもので、TAB（Tape Automated Bonding）技術が適用されている。この絶縁フィルム12には、貫通孔12aが形成されている。貫通孔12aは、絶縁フィルム12の一方の面に形成される配線パターン20の上に形成される。そして、この貫通孔12aを介して、バンプ14は、配線パターン20から絶縁フィルム12の他方の面に突出するように形成されている。すなわち、バンプ14は、配線パターン20とは反対側の面に突出する。こうすることで、バンプ14が形成される側には配線パターン20が露出しない構成となる。なお、バンプ14は、例えばハンダから形成されて上部はボール状に形成されている。貫通孔12a内までハンダを用いてバンプ14として一体形成されてもよいし、他の導電部材が少なくとも貫通孔12a内に設けられその上部にハンダが搭載されても良い。また、ハンダ以外に例えば銅等であってもよい。
また、絶縁フィルム12には、デバイスホール12bが形成されており、配線パターン20の端部がデバイスホール12bに突出する。デバイスホール12bは、配線パターン20と半導体チップ16の電極18とを接続するために使用される。すなわち、絶縁フィルム12における配線パターン20が形成される側の面であって、かつ、デバイスホール12bの内側に電極18が位置するように、半導体チップ16を配置して、配線パターン20と電極18とをボンディングする。
そして、半導体チップ16と絶縁フィルム12との接続領域が、エポキシ樹脂22のポッティングによって封止される。
さらに、本実施形態の特徴は、絶縁フィルム12に保持板24が設けられることにある。詳しくは、保持板24は、配線パターン20の上に、絶縁接着剤26を介して貼り付けられる。保持板24は、ステンレス鋼でもよいが、導電性の高い銅や銅係合金等で形成されることが好ましい。
こうすることで、配線パターン20が、絶縁接着剤26及び保持板24で覆われて保護される。特に、絶縁接着剤26は、ソルダレジストと同様な保護層となる。
絶縁接着剤26は、熱硬化性又は熱可塑性のフィルムとして形成し、予め保持板24に貼り付けておいてもよい。そして、保持板24を、絶縁フィルム12における配線パターン20を有する面に熱圧着することができる。
こうして、保持板24を設けることで、絶縁フィルム12の歪み、うねりがなくなり、バンプ14の高さが一定になって平面安定性が向上し、回路基板への実装歩留りが向上する。
この保持板24は、レジストを配線パターン20に設けてから、その上に絶縁接着剤を介して貼っても良い。こうすることで、不純物が入ったままで保持板24を貼り付けるのを防止することができる。
また、保持板24には突起24aが形成されており、この突起24aは配線パターン20の一定電位、例えばGND電位や電源電位の部分に接続されている。なお、突起24aは、図において１箇所にのみ示されているが、配線パターン20の一定電位となる全ての部分に設けてもよい。
この構成によれば、保持板24は、突起24aを介して接続される配線パターン20の電位と同電位となる。
そして、配線パターン20は、絶縁接着剤26を介して、保持板24にて形成される平面状の一定電位の上方に配置される。特に、一定電位がGND電位であれば、平面状のGND電位に沿って、配線パターン20に高周波信号を伝送することができるので、同軸ケーブルのように、理想的な伝送路となる。つまり、配線パターン20のインピーダンスやインダクタンスをコントロールできる。
なお、インピーダンスやインダクタンスは、接着剤やレジスト層（設ける場合）に起因するため、これらの厚みを変更することでコントロールできる。そして、コントロールできる結果として、高周波信号の遅れやなまりを減少させて伝送特性を向上させることができる。
本実施形態では、図１に示すように、絶縁フィルム12における保持板24側の面に配線パターン20を形成して、両者の間隔を小さくしてある。こうすることで、配線パターン20と保持板24との間隔が小さくなる。そして、電気容量をＣ、配線パターン20及び保持板24の対向する面積をＳ、配線パターン20と保持板24との間隔をｄ、真空での誘電率をε０、比誘電率をεとすると、
Ｃ＝εε0S/d
となることから分かるように、間隔ｄが小さくなると電気容量が大きくなって、理想的な伝送路が得られる。
GND電位の代わりに、配線パターン20の電源電位となる部分と保持板24とを突起24aによって接続してもよい。この場合でも、電源電位が一定電位であることから、配線パターン20に伝送される信号への影響を少なくすることができる。
なお、半導体素子との接合には、配線パターン側に突起が一体形成されたいわゆるＢ−TAB型のものを用いても良い。この点は、後述する全ての実施形態において共通である。
また、本実施形態は、半導体チップ16が絶縁フィルム12上の配線パターン20形成面と同じ側に実装された裏TAB型であるが、配線パターン20形成面の反対側に半導体チップ16を実装した表TAB型としてもよい。この場合には、半導体チップ16の裏面が、回路基板と接触することになるので、銀ペースト等の熱伝導接着部材を介して回路基板に接続すれば、半導体チップ16の放熱性を上げることができる。または、絶縁フィルム12に貫通孔12aを形成せず、配線パターン20にバンプを設け、このバンプを避けて配線パターン20側にソルダレジスト層を形成してもよい。これらの形成方法は、以下の実施形態の全てに共通である。また、半導体チップ16の厚みにより、絶縁フィルムと回路基板との間に一定の高さが得られることで、例えば隣り合うハンダバンプ間のショート防止にもなる。
（第２実施形態）
図２は、第２実施形態に係る半導体装置を示す図である。同図に示す半導体装置30は、配線パターン32と保持板34との電気的な接続の構造において、図１に示す半導体装置10と異なる。すなわち、図２において、配線パターン32の左端の延設部32aが、屈曲して保持板34に接続されている。接続の方法として、後述する第３実施形態に示されるものがある。延設部32aは、配線パターン32のGND電位となる部分に設けられている。なお、延設部32aは、図において端部の１箇所にのみ示されているが、配線パターン32のGND電位となる全ての部分に設けてもよく、端部でなくともそれ以外のどの位置に設けても良い。また、保持板34は、導電性が高くまた熱伝導性の良い銅などで構成されている。
この構成によれば、保持板34は、延設部32aを介して接続される配線パターン32の電位と同電位すなわちGND電位となる。そして、配線パターン32は、絶縁接着剤36を介して、保持板34にて形成される平面状のGND電位の上方に配置される。そうすると、平面状のGND電位に沿って、配線パターン32に高周波信号を伝送することができるので、同軸ケーブルのように、理想的な伝送路となる。つまり、配線パターン32のインピーダンスやインダクタンスをコントロールできる。なお、インピーダンスやインダクタンスは、接着剤やレジスト層（設ける場合）に起因するため、これらの厚みを変更することでコントロールできる。そして、コントロールできる結果として、高周波信号の遅れやなまりを減少させて伝送特性を向上させることができる。
あるいは、GND電位の代わりに、配線パターン32の電源電位となる部分と保持板34とを延設部32aによって接続してもよい。この場合でも、電源電位が一定電位であることから、配線パターン32に伝送される信号への影響を少なくすることができる。
（第３実施形態）
次に、図3A及び図3Bは、上記第２実施形態の接合手段からみた変形例を示す図である。
図3Aに示す半導体装置40は、配線パターン42の一部が屈曲して凸部42aを形成し、この凸部42aが保持板44に接続されるようになっている。なお、凸部42aは、配線パターン42のうち、GND電位又は電源電位等の一定電位となる部分に形成される。こうして、保持板44を一定電位にして、上記第２実施形態と同様の効果を得ることができる。
凸部42aは、絶縁フィルム46に形成された穴46aから加圧治具48を押圧して形成される。すなわち、配線パターン42のうち凸部42aを形成する部分に対応して、予め、絶縁フィルム46に穴46aを形成しておき、この穴46aから保持板44に向けて、配線パターン42を加圧治具48によって押圧して、凸部42aを形成して保持板44に接合する。
なお、凸部42aを形成する領域には、絶縁接着剤45を除去しておくことが好ましい。また、凸部42aを形成するときに、加圧治具48からは、熱又は超音波振動が加えられる。さらに、配線パターン42には金（Au）メッキが施されている。なお、配線パターン42としては金メッキ以外にも周知のスズメッキやハンダメッキを用いても良い。一方、保持板44にも金属メッキが施されていると、凸部42aと保持板44との接合が容易になる。
次に、図3Bに示す半導体装置50は、導電接着剤56によって配線パターン52及び保持板54が接続されたものである。このように接続するために、配線パターン52において保持板54に接続する部分に対応して、絶縁接着剤55を除去して導電接着剤56を設けて、保持板54を絶縁フィルム58に熱圧着する。
あるいは、導電接着剤56の代わりに、ハンダを用いても良い。その場合には、保持板54と絶縁フィルム58とを熱圧着するときに、ハンダの融点まで加熱する必要がある。
以上の変形例によっても、上記第２実施形態と同様の効果を達成することができる。
なお、半導体素子との接合には、配線パターン側に突起が一体成形されたいわゆるＢ−TAB型のものを用いても良い。
（第４実施形態）
次に、図４は、第３実施形態の他の変形例を示す図であり、前に挙げたいわゆる「Ｂ−TAB型」の例である。同図に示す半導体装置60の配線パターン62は、半導体チップ64の電極64aとの接続用の突起62aとともに、導電性の保持板66との接続用の突起62bを有する。なお、半導体チップ64は、樹脂65によってモールドされている。こうすることで、配線パターン62におけるGND電位又は電源電位と保持板66とを接続することができる。また、突起62bと保持板66とは、配線パターン62を有する絶縁フィルム68に保持板66を熱圧着して取り付けるときに、同時に接続される。なお、その他の構成は、図3Bに示す実施形態と同様であるため説明を省略する。
（第５実施形態）
図5A〜図5Cは、第５実施形態に係る半導体装置を示す図である。図5Aに示す半導体装置100は、絶縁フィルム104、配線パターン106、バンプ108及び半導体チップ109を有し、絶縁フィルム104及び配線パターン106の端部が保持板102によって保持されている。保持板102は、導電性の高い材質からなる。
詳しくは、保持板102に形成された溝102aに絶縁フィルム104の端部が挿入されることで、絶縁フィルム104の端部が保持されている。また、配線パターン106は、保持板102に保持されて電気的に接続されている。なお、保持板102に接続される配線パターン106の部分については、第１実施形態と同様であり、電気的な接続の効果についても同様であるため説明を省略する。
保持板102は、平面性を保つのに必要な強度を有する一方、絶縁フィルム104は柔軟性を有する。したがって、絶縁フィルム104の端部が保持板102に保持されることで、柔軟性のある絶縁フィルム104が平面性を保てるようになる。そして、絶縁フィルム104の反りを抑えて、確実な実装を行えるようになる。また、
保持板102の熱膨張係数＞絶縁フィルム104の熱膨張係数
とすることが好ましい。こうすることで、回路基板に半導体装置100を実装するときのリフロー工程で、保持板102によって絶縁フィルム104にテンションがかかり、絶縁フィルム104が張るようになり、その結果平坦性が得られるので、バンプ108を回路基板に確実に実装することができる。
なお、半導体素子との接合には、配線パターン側に突起が一体形成されたいわゆるＢ−TAB型のものを用いても良い。また、本実施形態では、保持板102と絶縁フィルム104との間に空間の存在する例が示されているが、空間が存在しないようにしても良い。
図5Bには、第５実施形態の変形例が示されている。同図に示す半導体装置110は、保持板112に形成されたスリット112aに、絶縁フィルム114及び配線パターン116の端部が挿入される点で、上記半導体装置100と相違する。
また、図5Cにも、第５実施形態の変形例が示されている。同図に示す半導体装置120は、絶縁フィルム124に形成されたスリット124aに、保持板122の端部が挿入されることで、絶縁フィルム124の端部が保持されている。詳しくは、絶縁フィルム124の一方の面から、スリット124aを介して他方の面に、保持板122の端部を弾性変形させて挿入し、保持板122の復元力によって絶縁フィルム124の平面性を保つようになっている。また、こうすることで、保持板122と配線パターン126とが電気的に接続される。
これらの半導体装置110、120であっても、上記半導体装置100と同様の効果を達成することができる。
なお、半導体素子との接合には、配線パターン側に突起が一体形成されたいわゆるＢ−TAB型のものを用いても良い。
（第６実施形態）
図６に示す半導体装置70は、保持板72と絶縁フィルム74とが接着剤73によって全面固定される点で、上記第４実施形態と異なる。ここで、
保持板72の熱膨張係数＞絶縁フィルム74の熱膨張係数
とすることが好ましい。こうすることで、回路基板に半導体装置70を実装するときのリフロー工程で、保持板72によって絶縁フィルム74にテンションがかかり、絶縁フィルム74が張るようになり、その結果平坦性が得られるので、ハンダボール75を回路基板に確実に実装することができる。なお、配線パターン71と保持板72との電気的な接続の構造は、図１に示す構図と同様であるので説明を省略する。
（第７実施形態）
図７に示す半導体装置76では、保持板78の端部78aが、絶縁フィルム80及び配線パターン81の端部に対して、矢印で示す方向にかしめられている。これによって、保持板78と絶縁フィルム80とが固定され、かつ、配線パターン81と保持板78との電気的な接続が図られている。本実施形態によれば、量産工程において、接着剤を用いずに安定して保持板78を取り付けることができる。
（第８実施形態）
図８に示す半導体装置82では、保持板84がピン等の突起84aを有し、絶縁フィルム86に穴86aが形成され、配線パターン87に穴87aが形成されている。突起84aと、穴86a及び穴87aとをはめ合わせて、保持板84が絶縁フィルム86に取り付けられている。また、穴86aよりも穴87aの直径がわずかに小さく形成されていおり、配線パターン87と保持板87との電気的な接続が確実に図られるようになっている。
なお、突起84aは、保持板84の端部を曲げて形成されてもよい。これによっても、量産工程において、接着剤を用いずに安定して保持板84を取り付けることができる。
（第９実施形態）
図９に示す半導体装置90は、図１に示す半導体装置10に放熱板（ヒートスプレッダ）91が取り付けられたものである。詳しくは、半導体チップ16の裏面（電極18とは反対側の面）と保持板24とに、接着剤92が塗布されて、放熱板91が接着されている。接着剤92は、銀などを含有して熱伝導性及び導電性が高く、放熱板91も熱伝導性及び導電性の高い材料から構成されている。こうすることで、放熱板91によって、半導体チップ16の熱の発散を促進するとともに、半導体チップ16の裏面も一定電位に接続することができる。そして、半導体チップ16の誤作動が防止されて信頼性が向上する。
（第10実施形態）
図10に示す半導体装置94は、図９に示す半導体装置90の保持板24及び放熱板91の代わりに、これらが一体化された形状の保持板93を有する。すなわち、保持板93は、絶縁フィルム12に貼り付けられる部分と、半導体チップ16の裏面に貼り付けられる部分と、が一体的になるように屈曲した形状をなしている。このような保持板93を使用しても、上記実施形態と同様の効果を得ることができる。
（第11実施形態）
図11は、第11施形態に係る回路基板を示す図である。図11に示す回路基板130は、半導体装置132が実装されている。半導体装置132は、絶縁フィルム134、配線パターン136、バンプ138及び半導体チップ139を有し、回路基板130には、バンプ138をボンディングするためのパッド130aが形成されている。絶縁フィルム134には保持板133が貼り付けられている。
また、半導体装置132は、絶縁フィルム134の端部及び中央部に設けられた接着剤128によって、回路基板130に接着されている。この接着は、リフロー工程前に行われる。すなわち、半導体装置132を、一時的に、接着剤128によって回路基板130に接着して、絶縁フィルム134の反りをなくしてから、バンプ138とパッド130aとを接合する。絶縁フィルム134の反りをなくすには、少なくとも、絶縁フィルム134の端部を接着剤128にて固定することが好ましい。また、接着剤128として、ハンダ溶融温度以下の温度で反応するものを用いて、先に接着剤128が半導体装置132を接続してその後ハンダが溶融することが好ましい。こうして、いわゆる仮り止めが行われる。
本実施形態によれば、接着剤128を用いて、絶縁フィルム134の反りをなくしたので、良好な実装が可能になる。
なお、半導体素子との接合には、配線パターン側に突起が一体形成されたいわゆるＢ−TAB型のものを用いても良い。また、本実施形態は、保持板133を有するが、保持板133を省略したものでも平坦性の維持が可能である。
（第12実施形態）
図12Aは、第12実施形態に係る回路基板を示す図である。同図に示す回路基板140には半導体装置142が実装されている。半導体基板142は、保持板144以外の点で、図１に示す半導体装置10と同様であるため説明を省略する。
そして、保持板144は、銅やスレンレス鋼や銅系合金などの導電性の高い材料で構成され、ネジ146を通す穴144aが形成されている。このネジ146も導電性を有する。一方、回路基板140にも、導電性のネジ146を通す穴140aが形成されており、一方の面において、この穴140aの周囲にリング状のパッド148が形成されている。パッド148は、回路基板140におけるGND電位又は電源電位等の一定電位に接続されている。そして、保持板144と回路基板140とが、それぞれの穴144a、140aに挿通されるネジ146及びナット149にて固定されている。
こうして、ネジ146を介して、面状の保持板144は、GND電位又は電源電位等の一定電位となる。こうすることで、半導体装置142において、面状の一定電位に沿って信号を伝送することができるので、高周波信号の伝送特性が向上する。
なお、ネジ146によるねじ止めは、ハンダ付け後に行うことが好ましい。また、本実施形態では、ネジ146が１箇所のみに用いられているが、複数箇所に設けられても良い。なお、対向位置にネジ146を設ける場合には、例えば四隅に設けることが好ましい。
また、図12Bは、第12実施形態の変形例を示す図である。同図において、回路基板150に形成されたパッド152と、保持板154とは、ワイヤ156にて接続されている。ここで、パッド152は、一定電位に接続されている。したがって、保持板154も一定電位となって、高周波信号の伝送特性が向上する。なお、ワイヤ156は、ハンダ付けを行ったり、通常のワイヤボンディング手法、例えば超音波にて設けられる。また、その後にワイヤを樹脂で保護してもよい。
なお、半導体素子との接合には、配線パターン側に突起が一体形成されたいわゆるＢ−TAB型のものを用いても良い。
図13には、本発明を適用した半導体装置1100を実装した回路基板1000が示されている。回路基板には例えばガラスエポキシ基板等の有機系基板を用いることが一般的である。回路基板には例えば銅からなる配線パターンが所望の回路となるように形成されていて、それらの配線パターンと半導体装置のバンプとを機械的に接続することでそれらの電気的導通を図る。この場合、上述の半導体装置に、外部との熱膨張差により生じる歪みを吸収する構造を設ければ、本半導体装置を回路基板に実装しても接続時及びそれ以降の信頼性を向上できる。また更に半導体装置の配線に対しても工夫が成されれば、接続時及び接続後の信頼性を向上させることができる。なお実装面積もベアチップにて実装した面積にまで小さくすることができる。このため、この回路基板を電子機器を用いれば電子機器自体の小型化が図れる。また、同一面積内においてはより実装スペースを確保することができ、高機能化を図ることも可能である。
そして、この回路基板1000を備える電子機器として、図14には、ノート型パーソナルコンピュータ1200が示されている。
なお、半導体装置と同様に多数のバンプを必要とする面実装用の電子部品であれば、能動部品か受動部品かを問わず、本発明を応用することができる。電子部品として、例えば、抵抗器、コンデンサ、コイル、発振器、フィルム、温度センサ、サーミスタ、バリスタ、ボリューム又はヒューズなどがある。Technical field
The present invention relates to a surface-mounted semiconductor device, a method of manufacturing the same, a method of mounting the same, and a circuit board on which the same is mounted.
Background art
In pursuit of miniaturization of semiconductor devices, bare chip mounting is ideal. However, since it is difficult to guarantee quality and handling, it has been dealt with by processing into a package form. In the package form, a BGA (ball grid array) type package has recently emerged in response to a demand for increasing the number of terminals. BGA packages can be divided into several types depending on the base material of the board, especially when it is necessary to mount semiconductor elements with narrow pitch pads, and it is possible to provide continuity by manufacturing in the form of tape in manufacturing Due to such demands on manufacturing efficiency, there is a BGA package using a flexible tape using a flexible (flexible) substrate as a substrate of the substrate. In this BGA package, bumps, which are external terminals, are arranged in an area array on a flexible substrate so that they can be surface-mounted.
According to this BGA package, the wiring pattern connecting the chip electrodes to the bumps is formed exposed on the flexible substrate, and is carefully handled so as not to deteriorate the quality of the wiring pattern when mounted on the circuit board. It was necessary.
In addition, according to the BGA package, not only the connection state between the bump and the pad of the circuit board cannot be confirmed and inspected, but also the connection cannot be repaired even if there is a connection failure, so that high precision is required for mounting.
Alternatively, the flexible substrate used for the BGA package may be warped due to its flexibility and difficult to mount.
As described above, the conventional BGA package has various problems during mounting.
An object of the present invention is to solve this problem, and an object of the present invention is to provide a surface-mount type semiconductor device which enables easy mounting, a method of manufacturing the same, a method of mounting the same, and a circuit board mounting the same. It is in.
Disclosure of the invention
A semiconductor device according to the present invention includes a semiconductor element,
An insulating film having a through hole,
A wiring pattern formed so as to pass over the through hole on one surface side of the insulating film and connected to the semiconductor element;
An external terminal provided on the other surface side of the insulating film and being electrically connected to the wiring pattern via the through hole,
A holding plate which is made of a member having conductivity and maintains planarity, and which is provided to cover at least a part of the wiring pattern on a surface of the wiring pattern opposite to a surface on which the insulating film is provided. ,
The holding plate is attached to the insulating film via an insulating adhesive, and is connected to a constant potential portion of the wiring pattern.
In this semiconductor device, since the wiring pattern forming surface side and the bump forming surface side are different from each other with the insulating film as a boundary, there are no obstacles other than the wiring pattern on the wiring pattern forming surface side. Therefore, since the holding plate can be used as it is without special processing (patterning) to cover the wiring pattern, the manufacturing operation becomes extremely easy. In addition, since the surface of the wiring pattern can be protected and the holding plate having the strength to maintain the flatness covers the insulating film, the flexible insulating film does not become distorted, and the planar stability of the bump is improved. The yield of mounting on a circuit board is improved.
Further, the holding plate has conductivity and is connected to a constant potential portion of the wiring pattern. Here, the constant potential portion is a portion having a potential which does not change during operation of the semiconductor device. In addition, a short circuit between the conductive holding plate and the wiring pattern can be prevented by the insulating adhesive.
In this way, when the holding plate has a constant potential, a signal is transmitted to the wiring pattern along the planar constant potential formed by the holding plate, so that the transmission line becomes an ideal transmission path, and transmission with low impedance, particularly low inductance. Becomes possible. Then, the delay and dullness of the high-frequency signal are reduced, the transmission characteristics are improved, and a highly reliable semiconductor device can be obtained.
A protective layer covering the wiring pattern may exist between the holding plate and the wiring pattern.
In other words, a protective layer such as a resist is provided in advance on the entire surface of the wiring pattern where the holding plate on the side where the insulating film is not provided is pasted, and the holding plate is further pasted thereon via an adhesive. You may be. Also in this case, since a protective layer is provided on the surface of the wiring pattern opposite to the surface on which the external terminals are formed, it is easy to apply a resist or the like. In addition, when the holding plate is provided, the wiring pattern is protected in advance by the protective layer, so that there is no occurrence of a defect in the wiring pattern such as disconnection.
The constant potential portion may be one of a power supply potential and a ground potential.
The wiring pattern may have a curved portion at least in part, and the curved portion may be connected to the holding plate.
The holding plate may be connected to a constant potential portion of the wiring pattern by at least one of a solder and a conductive adhesive.
These can also improve the transmission characteristics.
A semiconductor device according to the present invention includes a semiconductor element, an insulating film, a wiring pattern formed on the insulating film and connected to the semiconductor element, an external terminal formed on the wiring pattern, A holding plate made of a member having flatness and holding a part of the insulating film,
The holding plate is connected to a constant potential portion of the wiring pattern.
According to the present invention, by providing the holding plate, warpage of the flexible insulating film can be prevented, and reliable mounting becomes possible.
Further, the holding plate has conductivity and is connected to a constant potential portion of the wiring pattern. Here, the constant potential portion is a portion having a potential which does not change during operation of the semiconductor device.
In this way, when the holding plate has a constant potential, a signal is transmitted to the wiring pattern along the planar constant potential formed by the holding plate, so that the transmission line becomes an ideal transmission path, and transmission with low impedance, particularly low inductance. Becomes possible. Then, the delay and dullness of the high-frequency signal are reduced, the transmission characteristics are improved, and a highly reliable semiconductor device can be obtained.
For the holding plate, a member having a thermal expansion coefficient larger than that of the insulating film may be used.
In the semiconductor device, the holding plate may have a slit or a groove, and an end of the insulating film may be inserted into the slit or the groove and held by the holding plate.
In the above semiconductor device, the insulating film may have a slit, and the holding plate may be attached to an opposite side of the insulating film through the slit so that an end protrudes.
The method for manufacturing a semiconductor device according to the present invention includes a step of forming a through hole in the insulating film,
Forming a wiring pattern passing over the through hole on one surface side of the insulating film;
Forming an external terminal projecting to the other surface side of the insulating film through the through hole on the surface of the wiring pattern on the insulating film side,
Providing a semiconductor element on the insulating film by connecting to the wiring pattern;
Affixing a holding plate made of a member having conductivity and maintaining flatness on the reflection surface side of the surface of the wiring pattern on which the insulating film is provided, so as to cover at least a part of the wiring pattern,
Connecting a part of the wiring pattern to the holding plate;
including.
In the semiconductor device manufactured by this method, the bumps protrude from the side opposite to the wiring pattern, and the holding plate covers the wiring pattern.
According to the semiconductor device manufactured by this method, the holding plate has the same potential as a part of the wiring pattern, and the holding plate is planar, so that electrical connection with low impedance is possible.
In the method for manufacturing a semiconductor device,
The holding plate may be attached to the insulating film via an insulating adhesive.
In the method for manufacturing a semiconductor device,
The insulating film has an opening corresponding to the wiring pattern,
A part of the wiring pattern may be bent and connected to the holding plate by pushing a pressing jig from the other surface of the insulating film through the opening.
A method of manufacturing a semiconductor device according to the present invention includes a step of forming a wiring pattern on an insulating film, a step of connecting a semiconductor element to the wiring pattern and providing the semiconductor element on the insulating film, and a holding step for holding an end of the insulating film. Attaching a board, and electrically connecting a part of the wiring pattern to the holding plate.
According to the semiconductor device manufactured by this method, warpage of the flexible insulating film can be prevented, and reliable mounting becomes possible. Further, since a part of the wiring pattern is electrically connected to the holding plate, a semiconductor device having a structure that is hardly affected by external noise can be obtained.
A circuit board according to the present invention includes the semiconductor device and a substrate on which a desired conductive pattern is formed,
The external terminal of the semiconductor device is connected to the conductive pattern.
According to the present invention, since the holding plate has a constant potential, the semiconductor device is arranged on a plane having a constant potential. As a result, the semiconductor device has a structure that is less susceptible to external noise, such as a coaxial cable.
The circuit board according to the present invention has a semiconductor element, an insulating film, a wiring pattern formed on the insulating film and connected to the semiconductor element, a bump formed on the wiring pattern, and having conductivity. A semiconductor device including a holding member made of a member that maintains planarity and electrically connected to the wiring pattern,
A substrate on which a desired conductive pattern is formed and which is fixed with an adhesive at least at an end of the insulating film,
Having.
According to this circuit board, at least the end of the insulating film is fixed, so that warpage is prevented. Further, since the wiring pattern and the holding plate are electrically connected, a structure that is not easily affected by external noise can be obtained.
A method of mounting a semiconductor device according to the present invention is directed to a semiconductor device including: an insulating film on which solder bumps are formed; and a holding member made of a member having conductivity and maintaining flatness and electrically connected to the wiring pattern. In the implementation method of
A method in which an adhesive is applied to at least an end portion of the insulating film and adhered to a circuit board, and then the solder bump is melted and connected to a pad of the circuit board.
According to the present invention, after the insulating film is fixed with the adhesive to eliminate the warpage of the insulating film, it is possible to perform the electrical connection by the solder. Further, since the wiring pattern and the holding plate are electrically connected, a structure that is not easily affected by external noise can be obtained.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating a semiconductor device according to a first embodiment, FIG. 2 is a diagram illustrating a semiconductor device according to a second embodiment, and FIGS. 3A and 3B are diagrams illustrating the third embodiment and modifications thereof. FIG. 4 is a diagram illustrating a semiconductor device according to an example, FIG. 4 is a diagram illustrating another modification of the fourth embodiment, and FIGS. 5A to 5C are diagrams illustrating a semiconductor device according to the fifth embodiment and modifications thereof. FIG. 6 is a diagram illustrating a semiconductor device according to a sixth embodiment. FIG. 7 is a diagram illustrating a semiconductor device according to a seventh embodiment. FIG. 8 is a diagram illustrating a semiconductor device according to an eighth embodiment. FIG. 9 is a diagram illustrating the semiconductor device according to the ninth embodiment, FIG. 10 is a diagram illustrating the semiconductor device according to the tenth embodiment, and FIG. FIG. 12A is a diagram illustrating a circuit board according to an eleventh embodiment, FIG. 12A is a diagram illustrating a circuit board according to a twelfth embodiment, and FIG. FIG. 13 is a diagram showing a modification of the embodiment, FIG. 13 is a diagram showing a circuit board on which a semiconductor device manufactured by applying the method according to the present invention is mounted, and FIG. 1 is a diagram showing an electronic apparatus including a circuit board on which a semiconductor device manufactured by the above method is mounted.
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.
(1st Embodiment)
FIG. 1 is a diagram illustrating the semiconductor device according to the first embodiment. This semiconductor device 10 uses a BGA package. That is, in the drawing, a large number of bumps 14 are formed on the insulating film 12, and a wiring pattern 20 for connecting the electrodes 18 of the semiconductor chip 16 and the bumps 14 is formed.
The insulating film 12 is obtained by punching a long film carrier tape, and uses a TAB (Tape Automated Bonding) technique. The insulating film 12 has a through hole 12a. The through hole 12a is formed on the wiring pattern 20 formed on one surface of the insulating film 12. The bump 14 is formed so as to project from the wiring pattern 20 to the other surface of the insulating film 12 via the through hole 12a. That is, the bumps 14 protrude from the surface opposite to the wiring pattern 20. By doing so, the wiring pattern 20 is not exposed on the side where the bumps 14 are formed. The bumps 14 are formed of, for example, solder, and the upper portion is formed in a ball shape. The bump 14 may be formed integrally with the through hole 12a by using solder, or another conductive member may be provided at least in the through hole 12a and the solder may be mounted thereon. Further, other than solder, for example, copper or the like may be used.
Further, a device hole 12b is formed in the insulating film 12, and an end of the wiring pattern 20 projects into the device hole 12b. The device hole 12b is used for connecting the wiring pattern 20 and the electrode 18 of the semiconductor chip 16. That is, the semiconductor chip 16 is arranged such that the electrode 18 is located on the surface of the insulating film 12 on which the wiring pattern 20 is formed, and inside the device hole 12b, and the wiring pattern 20 and the electrode 18 And bonding.
Then, the connection region between the semiconductor chip 16 and the insulating film 12 is sealed by potting the epoxy resin 22.
Further, a feature of the present embodiment is that the holding plate 24 is provided on the insulating film 12. Specifically, the holding plate 24 is attached on the wiring pattern 20 via an insulating adhesive 26. The holding plate 24 may be made of stainless steel, but is preferably made of highly conductive copper or copper engaging gold.
By doing so, the wiring pattern 20 is covered and protected by the insulating adhesive 26 and the holding plate 24. In particular, the insulating adhesive 26 becomes a protective layer similar to the solder resist.
The insulating adhesive 26 may be formed as a thermosetting or thermoplastic film, and may be attached to the holding plate 24 in advance. Then, the holding plate 24 can be thermocompression-bonded to the surface of the insulating film 12 having the wiring pattern 20.
By providing the holding plate 24 in this manner, distortion and undulation of the insulating film 12 are eliminated, the height of the bumps 14 is made constant, the planar stability is improved, and the mounting yield on the circuit board is improved.
The holding plate 24 may be provided with a resist on the wiring pattern 20 and then pasted thereon via an insulating adhesive. By doing so, it is possible to prevent the holding plate 24 from being stuck with the impurities remaining therein.
Further, a projection 24a is formed on the holding plate 24, and the projection 24a is connected to a portion of the wiring pattern 20 at a constant potential, for example, a GND potential or a power supply potential. Although only one protrusion 24a is shown in the figure, the protrusion 24a may be provided on all portions of the wiring pattern 20 where the potential is constant.
According to this configuration, the holding plate 24 has the same potential as the potential of the wiring pattern 20 connected via the projection 24a.
Then, the wiring pattern 20 is disposed above a planar constant potential formed by the holding plate 24 via the insulating adhesive 26. In particular, if the fixed potential is the GND potential, a high-frequency signal can be transmitted to the wiring pattern 20 along the planar GND potential, so that an ideal transmission path like a coaxial cable is obtained. That is, the impedance and the inductance of the wiring pattern 20 can be controlled.
Since the impedance and the inductance are caused by the adhesive and the resist layer (when provided), they can be controlled by changing their thickness. As a result of being controllable, the transmission characteristics can be improved by reducing the delay and dullness of the high-frequency signal.
In the present embodiment, as shown in FIG. 1, a wiring pattern 20 is formed on the surface of the insulating film 12 on the side of the holding plate 24 to reduce the distance between the two. By doing so, the distance between the wiring pattern 20 and the holding plate 24 is reduced. The capacitance is C, the area of the wiring pattern 20 and the holding plate 24 facing each other is S, the distance between the wiring pattern 20 and the holding plate 24 is d, and the dielectric constant in vacuum is ε. 0 , And the relative permittivity is ε,
C = εε 0 S / d
As can be seen from the equation, when the distance d decreases, the electric capacity increases and an ideal transmission path can be obtained.
Instead of the GND potential, the portion of the wiring pattern 20 that becomes the power supply potential and the holding plate 24 may be connected by the projection 24a. Even in this case, since the power supply potential is constant, the influence on the signal transmitted to the wiring pattern 20 can be reduced.
Note that a so-called B-TAB type in which a projection is integrally formed on the wiring pattern side may be used for bonding with the semiconductor element. This point is common to all embodiments described later.
Further, the present embodiment is a back TAB type in which the semiconductor chip 16 is mounted on the same side as the wiring pattern 20 forming surface on the insulating film 12, but the semiconductor chip 16 is mounted on the opposite side of the wiring pattern 20 forming surface. It may be a table TAB type. In this case, since the back surface of the semiconductor chip 16 comes into contact with the circuit board, if the semiconductor chip 16 is connected to the circuit board via a heat conductive adhesive member such as silver paste, the heat dissipation of the semiconductor chip 16 can be improved. it can. Alternatively, a bump may be provided on the wiring pattern 20 without forming the through hole 12a in the insulating film 12, and a solder resist layer may be formed on the wiring pattern 20 side avoiding the bump. These forming methods are common to all of the following embodiments. In addition, since a certain height is obtained between the insulating film and the circuit board due to the thickness of the semiconductor chip 16, for example, short-circuit between adjacent solder bumps can be prevented.
(2nd Embodiment)
FIG. 2 is a diagram illustrating a semiconductor device according to the second embodiment. The semiconductor device 30 shown in FIG. 10 differs from the semiconductor device 10 shown in FIG. 1 in the structure of the electrical connection between the wiring pattern 32 and the holding plate 34. That is, in FIG. 2, the extended portion 32a at the left end of the wiring pattern 32 is bent and connected to the holding plate. As a connection method, there is a method described in a third embodiment described later. The extending portion 32a is provided at a portion of the wiring pattern 32 at which a GND potential is provided. Although the extended portion 32a is shown only at one end portion in the drawing, it may be provided at any portion of the wiring pattern 32 which is at the GND potential, and may be provided at any other position than the end portion. May be provided. The holding plate 34 is made of copper or the like having high conductivity and good heat conductivity.
According to this configuration, the holding plate 34 has the same potential as the potential of the wiring pattern 32 connected via the extension 32a, that is, the GND potential. The wiring pattern 32 is disposed above the planar GND potential formed by the holding plate 34 via the insulating adhesive 36. Then, since a high-frequency signal can be transmitted to the wiring pattern 32 along the planar GND potential, the transmission path becomes an ideal transmission path like a coaxial cable. That is, the impedance and the inductance of the wiring pattern 32 can be controlled. Since the impedance and the inductance are caused by the adhesive and the resist layer (when provided), they can be controlled by changing their thickness. As a result of being controllable, the transmission characteristics can be improved by reducing the delay and dullness of the high-frequency signal.
Alternatively, instead of the GND potential, the portion of the wiring pattern 32 that becomes the power supply potential and the holding plate 34 may be connected by the extension 32a. Even in this case, since the power supply potential is constant, the influence on the signal transmitted to the wiring pattern 32 can be reduced.
(Third embodiment)
Next, FIG. 3A and FIG. 3B are views showing a modified example as viewed from the joining means of the second embodiment.
In the semiconductor device 40 shown in FIG. 3A, a part of the wiring pattern 42 is bent to form a convex part 42a, and the convex part 42a is connected to the holding plate 44. The protrusion 42a is formed in a portion of the wiring pattern 42 where the potential becomes a constant potential such as a GND potential or a power supply potential. Thus, the same effect as in the second embodiment can be obtained by setting the holding plate 44 to a constant potential.
The convex portion 42a is formed by pressing a pressing jig 48 from a hole 46a formed in the insulating film 46. That is, a hole 46a is formed in the insulating film 46 in advance corresponding to a portion of the wiring pattern 42 where the projection 42a is formed, and the wiring pattern 42 is pressed from the hole 46a toward the holding plate 44. Pressing is performed by a jig 48 to form a convex portion 42a and join to the holding plate 44.
Note that it is preferable that the insulating adhesive 45 be removed from the region where the protrusion 42a is formed. Further, when forming the convex portion 42a, heat or ultrasonic vibration is applied from the pressing jig 48. Further, the wiring pattern 42 is plated with gold (Au). It should be noted that the wiring pattern 42 may be formed by well-known tin plating or solder plating other than gold plating. On the other hand, if the holding plate 44 is also metal-plated, the connection between the projection 42a and the holding plate 44 becomes easy.
Next, in the semiconductor device 50 shown in FIG. 3B, the wiring pattern 52 and the holding plate 54 are connected by the conductive adhesive 56. In order to connect in this manner, the insulating adhesive 55 is removed and the conductive adhesive 56 is provided corresponding to the portion of the wiring pattern 52 connected to the holding plate 54, and the holding plate 54 is thermocompression-bonded to the insulating film 58. I do.
Alternatively, solder may be used instead of the conductive adhesive 56. In that case, when the holding plate 54 and the insulating film 58 are thermocompression bonded, it is necessary to heat to the melting point of the solder.
According to the above modification, the same effect as in the second embodiment can be achieved.
Note that a so-called B-TAB type in which a projection is integrally formed on the wiring pattern side may be used for bonding with the semiconductor element.
(Fourth embodiment)
Next, FIG. 4 is a diagram showing another modification of the third embodiment, and is an example of the so-called “B-TAB type” described above. The wiring pattern 62 of the semiconductor device 60 shown in the figure has a projection 62a for connection with the electrode 64a of the semiconductor chip 64 and a projection 62b for connection with the conductive holding plate 66. The semiconductor chip 64 is molded with a resin 65. By doing so, the GND potential or the power supply potential of the wiring pattern 62 can be connected to the holding plate 66. The projection 62b and the holding plate 66 are simultaneously connected when the holding plate 66 is attached to the insulating film 68 having the wiring pattern 62 by thermocompression bonding. The other configuration is the same as that of the embodiment shown in FIG. 3B, and thus the description is omitted.
(Fifth embodiment)
5A to 5C are views showing a semiconductor device according to the fifth embodiment. The semiconductor device 100 shown in FIG. 5A includes an insulating film 104, a wiring pattern 106, a bump 108, and a semiconductor chip 109, and ends of the insulating film 104 and the wiring pattern 106 are held by a holding plate 102. The holding plate 102 is made of a highly conductive material.
Specifically, the end of the insulating film 104 is held by inserting the end of the insulating film 104 into the groove 102a formed in the holding plate 102. The wiring patterns 106 are held by the holding plate 102 and are electrically connected. Note that the portion of the wiring pattern 106 connected to the holding plate 102 is the same as in the first embodiment, and the effect of the electrical connection is also the same.
The holding plate 102 has strength necessary to maintain flatness, while the insulating film 104 has flexibility. Therefore, by holding the end portion of the insulating film 104 on the holding plate 102, the flexible insulating film 104 can maintain flatness. Then, the warpage of the insulating film 104 is suppressed, and the mounting can be performed reliably. Also,
Thermal expansion coefficient of holding plate 102> Thermal expansion coefficient of insulating film 104
It is preferable that By doing so, in the reflow step when the semiconductor device 100 is mounted on the circuit board, the insulating film 104 is tensioned by the holding plate 102, and the insulating film 104 is stretched.As a result, flatness is obtained. The bumps 108 can be reliably mounted on the circuit board.
Note that a so-called B-TAB type in which a projection is integrally formed on the wiring pattern side may be used for bonding with the semiconductor element. Further, in the present embodiment, an example is described in which a space exists between the holding plate 102 and the insulating film 104, but the space may not exist.
FIG. 5B shows a modification of the fifth embodiment. The semiconductor device 110 shown in the figure differs from the semiconductor device 100 in that the ends of the insulating film 114 and the wiring pattern 116 are inserted into the slits 112a formed in the holding plate 112.
FIG. 5C also shows a modification of the fifth embodiment. In the semiconductor device 120 shown in the figure, the end of the insulating film 124 is held by inserting the end of the holding plate 122 into the slit 124a formed in the insulating film 124. More specifically, the end of the holding plate 122 is elastically deformed and inserted from one surface of the insulating film 124 to the other surface via the slit 124a, and the flatness of the insulating film 124 is reduced by the restoring force of the holding plate 122. To keep it. Further, by doing so, the holding plate 122 and the wiring pattern 126 are electrically connected.
Even with these semiconductor devices 110 and 120, the same effects as those of the semiconductor device 100 can be achieved.
Note that a so-called B-TAB type in which a projection is integrally formed on the wiring pattern side may be used for bonding with the semiconductor element.
(Sixth embodiment)
The semiconductor device 70 shown in FIG. 6 is different from the fourth embodiment in that the holding plate 72 and the insulating film 74 are entirely fixed by an adhesive 73. here,
Thermal expansion coefficient of holding plate 72> Thermal expansion coefficient of insulating film 74
It is preferable that By doing so, in the reflow process when mounting the semiconductor device 70 on the circuit board, the tension is applied to the insulating film 74 by the holding plate 72, and the insulating film 74 is stretched.As a result, flatness is obtained. The solder balls 75 can be securely mounted on the circuit board. The structure of the electrical connection between the wiring pattern 71 and the holding plate 72 is the same as the composition shown in FIG.
(Seventh embodiment)
In the semiconductor device 76 shown in FIG. 7, the end 78a of the holding plate 78 is swaged in the direction shown by the arrow with respect to the end of the insulating film 80 and the end of the wiring pattern 81. As a result, the holding plate 78 and the insulating film 80 are fixed, and the electrical connection between the wiring pattern 81 and the holding plate 78 is achieved. According to the present embodiment, in the mass production process, the holding plate 78 can be stably mounted without using an adhesive.
(Eighth embodiment)
In a semiconductor device 82 shown in FIG. 8, a holding plate 84 has a projection 84a such as a pin, a hole 86a is formed in an insulating film 86, and a hole 87a is formed in a wiring pattern 87. The holding plate 84 is attached to the insulating film 86 by fitting the projection 84a with the hole 86a and the hole 87a. Further, the diameter of the hole 87a is formed slightly smaller than the diameter of the hole 86a, so that electrical connection between the wiring pattern 87 and the holding plate 87 can be ensured.
Note that the projection 84a may be formed by bending an end of the holding plate 84. This also allows the holding plate 84 to be stably mounted without using an adhesive in the mass production process.
(Ninth embodiment)
A semiconductor device 90 shown in FIG. 9 is obtained by attaching a heat sink (heat spreader) 91 to the semiconductor device 10 shown in FIG. Specifically, an adhesive 92 is applied to the back surface of the semiconductor chip 16 (the surface opposite to the electrodes 18) and the holding plate 24, and the heat radiation plate 91 is adhered. The adhesive 92 contains silver or the like and has high thermal conductivity and conductivity, and the radiator plate 91 is also made of a material having high thermal conductivity and conductivity. In this way, the heat dissipation plate 91 promotes the heat dissipation of the semiconductor chip 16 and also connects the back surface of the semiconductor chip 16 to a constant potential. Then, malfunction of the semiconductor chip 16 is prevented, and the reliability is improved.
(Tenth embodiment)
The semiconductor device 94 shown in FIG. 10 has a holding plate 93 in which these are integrated, instead of the holding plate 24 and the heat radiating plate 91 of the semiconductor device 90 shown in FIG. That is, the holding plate 93 has a bent shape such that a portion attached to the insulating film 12 and a portion attached to the back surface of the semiconductor chip 16 are integrated. Even when such a holding plate 93 is used, the same effect as in the above embodiment can be obtained.
(Eleventh embodiment)
FIG. 11 is a diagram showing a circuit board according to the eleventh embodiment. The semiconductor device 132 is mounted on the circuit board 130 shown in FIG. The semiconductor device 132 has an insulating film 134, a wiring pattern 136, bumps 138, and a semiconductor chip 139. On the circuit board 130, pads 130a for bonding the bumps 138 are formed. A holding plate 133 is attached to the insulating film 134.
Further, the semiconductor device 132 is bonded to the circuit board 130 by an adhesive 128 provided at the end and the center of the insulating film 134. This bonding is performed before the reflow process. That is, the semiconductor device 132 is temporarily bonded to the circuit board 130 with the adhesive 128 to eliminate the warpage of the insulating film 134, and then the bump 138 and the pad 130a are bonded. In order to eliminate the warpage of the insulating film 134, it is preferable to fix at least the ends of the insulating film 134 with the adhesive 128. Further, it is preferable that the adhesive 128 is used to react at a temperature equal to or lower than the solder melting temperature, the adhesive 128 is connected to the semiconductor device 132 first, and then the solder is melted. Thus, so-called temporary fixing is performed.
According to the present embodiment, since the warpage of the insulating film 134 is eliminated by using the adhesive 128, good mounting becomes possible.
Note that a so-called B-TAB type in which a projection is integrally formed on the wiring pattern side may be used for bonding with the semiconductor element. Although the present embodiment has the holding plate 133, the flatness can be maintained even if the holding plate 133 is omitted.
(Twelfth embodiment)
FIG. 12A is a diagram showing a circuit board according to a twelfth embodiment. A semiconductor device 142 is mounted on a circuit board 140 shown in FIG. The semiconductor substrate 142 is the same as the semiconductor device 10 shown in FIG.
The holding plate 144 is made of a highly conductive material such as copper, stainless steel, or a copper-based alloy, and has a hole 144a through which the screw 146 passes. This screw 146 also has conductivity. On the other hand, a hole 140a for passing the conductive screw 146 is also formed on the circuit board 140, and a ring-shaped pad 148 is formed around the hole 140a on one surface. The pad 148 is connected to a constant potential such as a GND potential or a power supply potential on the circuit board 140. The holding plate 144 and the circuit board 140 are fixed by screws 146 and nuts 149 inserted into the holes 144a, 140a.
Thus, the planar holding plate 144 is at a constant potential such as the GND potential or the power supply potential via the screw 146. In this manner, in the semiconductor device 142, a signal can be transmitted along a planar constant potential, so that transmission characteristics of a high-frequency signal are improved.
It is preferable that the screw 146 is used after the soldering. Further, in this embodiment, the screw 146 is used only at one place, but it may be provided at a plurality of places. When the screws 146 are provided at the opposed positions, it is preferable to provide the screws 146 at, for example, four corners.
FIG. 12B is a diagram showing a modification of the twelfth embodiment. In the figure, a pad 152 formed on a circuit board 150 and a holding plate 154 are connected by a wire 156. Here, the pad 152 is connected to a constant potential. Therefore, the holding plate 154 also has a constant potential, and the transmission characteristics of the high-frequency signal are improved. The wire 156 is provided by soldering or by a normal wire bonding method, for example, an ultrasonic wave. After that, the wire may be protected with a resin.
Note that a so-called B-TAB type in which a projection is integrally formed on the wiring pattern side may be used for bonding with the semiconductor element.
FIG. 13 shows a circuit board 1000 on which a semiconductor device 1100 to which the present invention is applied is mounted. Generally, an organic substrate such as a glass epoxy substrate is used as the circuit board. Wiring patterns made of, for example, copper are formed on a circuit board so as to form a desired circuit, and electrical connection between the wiring patterns and bumps of the semiconductor device is achieved by mechanical connection. In this case, if the semiconductor device described above is provided with a structure that absorbs a strain caused by a difference in thermal expansion with the outside, the reliability at the time of connection and thereafter can be improved even if the semiconductor device is mounted on a circuit board. In addition, if the wiring of the semiconductor device is devised, the reliability at the time of connection and after the connection can be improved. Note that the mounting area can be reduced to the area mounted with bare chips. Therefore, if an electronic device is used as the circuit board, the size of the electronic device itself can be reduced. In addition, more mounting space can be secured within the same area, and higher functionality can be achieved.
FIG. 14 shows a notebook personal computer 1200 as an electronic apparatus including the circuit board 1000.
Note that the present invention can be applied to any electronic component for surface mounting that requires a large number of bumps, regardless of whether it is an active component or a passive component like a semiconductor device. Examples of the electronic component include a resistor, a capacitor, a coil, an oscillator, a film, a temperature sensor, a thermistor, a varistor, a volume, and a fuse.

Claims (15)

半導体素子と、
貫通孔を有する絶縁フィルムと、
前記絶縁フィルムの一方の面側において前記貫通孔上を通るように形成されるとともに前記半導体素子に接続される配線パターンと、
前記絶縁フィルムの他方の面側に設けられるとともに前記貫通孔を介して前記配線パターンと電気的な接続がなされている外部端子と、
導電性を有するとともに平面性を保つ部材からなり、前記配線パターンの前記絶縁フィルムが設けられた面の反対面側に前記配線パターンの少なくとも一部を覆うように設けられる保持板と、を有し、
前記保持板は、絶縁性の接着剤を介して前記絶縁フィルムに貼り付けられるとともに、前記配線パターンの一定電位部に接続され、
前記保持板の熱膨張係数＞前記絶縁フィルムの熱膨張係数
の関係を有する半導体装置。A semiconductor element;
An insulating film having a through hole,
A wiring pattern formed so as to pass over the through hole on one surface side of the insulating film and connected to the semiconductor element;
An external terminal provided on the other surface side of the insulating film and being electrically connected to the wiring pattern via the through hole,
A holding plate which is made of a member having conductivity and maintains planarity, and which is provided to cover at least a part of the wiring pattern on a surface of the wiring pattern opposite to a surface on which the insulating film is provided. ,
The holding plate is attached to the insulating film via an insulating adhesive, and is connected to a constant potential portion of the wiring pattern,
A semiconductor device having a relationship of thermal expansion coefficient of the holding plate> thermal expansion coefficient of the insulating film. 請求項１記載の半導体装置において、
前記保持板と前記配線パターンとの間に、前記配線パターンを覆う保護層が存在する半導体装置。The semiconductor device according to claim 1,
A semiconductor device in which a protective layer that covers the wiring pattern exists between the holding plate and the wiring pattern. 請求項１記載の半導体装置において、
前記一定電位部は、電源電位及びグランド電位のいずれか一方である半導体装置。The semiconductor device according to claim 1,
The semiconductor device, wherein the constant potential portion is one of a power supply potential and a ground potential. 請求項１記載の半導体装置において、
前記配線パターンは、少なくとも一部に湾曲部を有し、前記湾曲部が前記保持板に接続される半導体装置。The semiconductor device according to claim 1,
The semiconductor device, wherein the wiring pattern has a curved portion at least in part, and the curved portion is connected to the holding plate. 請求項１記載の半導体装置において、
前記保持板は、ハンダ及び導電性接着剤のうち少なくともいずれか一方によって、前記配線パターンの前記一定電位部と接続される半導体装置。The semiconductor device according to claim 1,
The semiconductor device, wherein the holding plate is connected to the constant potential portion of the wiring pattern by at least one of a solder and a conductive adhesive. 半導体素子と、絶縁フィルムと、前記絶縁フィルム上に形成されるとともに前記半導体素子に接続される配線パターンと、前記配線パターン上に形成される外部端子と、導電性を有するとともに平面性を保つ部材からなり前記絶縁フィルムの一部を保持する保持板と、を有し、
前記保持板は、前記配線パターンの一定電位部に接続され、
前記保持板の熱膨張係数＞前記絶縁フィルムの熱膨張係数
の関係を有する半導体装置。A semiconductor element, an insulating film, a wiring pattern formed on the insulating film and connected to the semiconductor element, an external terminal formed on the wiring pattern, and a member having conductivity and maintaining flatness And a holding plate for holding a part of the insulating film,
The holding plate is connected to a constant potential portion of the wiring pattern,
A semiconductor device having a relationship of thermal expansion coefficient of the holding plate> thermal expansion coefficient of the insulating film. 請求項６記載の半導体装置において、
前記保持板は、スリット又は溝を有し、
前記絶縁フィルムの端部は、前記スリット又は溝に挿入されて前記保持板に保持される半導体装置。The semiconductor device according to claim 6,
The holding plate has a slit or a groove,
A semiconductor device in which an end of the insulating film is inserted into the slit or the groove and held by the holding plate. 請求項６記載の半導体装置において、
前記絶縁フィルムは、スリットを有し、
前記保持板は、前記スリットを介して前記絶縁フィルムの反対側面に、端部が突出するように取り付けられる半導体装置。The semiconductor device according to claim 6,
The insulating film has a slit,
The semiconductor device, wherein the holding plate is attached to an opposite side of the insulating film through the slit so that an end protrudes. 絶縁フィルムに貫通孔を形成する工程と、
前記絶縁フィルムの一方の面側に前記貫通孔上を通る配線パターンを形成する工程と、
前記配線パターンにおける前記絶縁フィルム側の面に前記貫通孔を介して前記絶縁フィルムの他方の面側に突出する外部端子を形成する工程と、
半導体素子を前記配線パターンに接続して前記絶縁フィルムに設ける工程と、
前記配線パターンの前記絶縁フィルムが設けられた面の反対面側に、前記配線パターンの少なくとも一部を覆うように、導電性を有するとともに平面性を保つ部材からなる保持板を貼り付ける工程と、
前記配線パターンの一部を前記保持板に接続する工程と、
を含み、
前記保持板の熱膨張係数＞前記絶縁フィルムの熱膨張係数
の関係を有する半導体装置の製造方法。Forming a through hole in the insulating film;
Forming a wiring pattern passing over the through hole on one surface side of the insulating film;
Forming an external terminal projecting to the other surface side of the insulating film through the through hole on the surface of the wiring pattern on the insulating film side,
Providing a semiconductor element on the insulating film by connecting to the wiring pattern;
On the opposite side of the surface of the wiring pattern provided with the insulating film, to cover at least a part of the wiring pattern, a step of attaching a holding plate made of a member having conductivity and maintaining flatness,
Connecting a part of the wiring pattern to the holding plate;
Including
A method of manufacturing a semiconductor device having a relationship of thermal expansion coefficient of the holding plate> thermal expansion coefficient of the insulating film. 請求項９記載の半導体装置の製造方法において、
前記保持板を、絶縁性の接着剤を介して前記絶縁フィルムに貼り付ける半導体装置の製造方法。The method of manufacturing a semiconductor device according to claim 9 ,
A method for manufacturing a semiconductor device, wherein the holding plate is attached to the insulating film via an insulating adhesive. 請求項10記載の半導体装置の製造方法において、
前記絶縁フィルムは、前記配線パターンに対応する開口部を有し、
前記絶縁フィルムの前記他方の面から前記開口部を介して加圧治具を押し入れて、前記配線パターンの一部を、屈曲させて前記保持板に接続する半導体装置の製造方法。In the method of manufacturing a semiconductor device according to claim 10 ,
The insulating film has an opening corresponding to the wiring pattern,
A method of manufacturing a semiconductor device, wherein a pressing jig is pushed in from the other surface of the insulating film through the opening, and a part of the wiring pattern is bent and connected to the holding plate. 絶縁フィルムに配線パターンを形成する工程と、半導体素子を前記配線パターンに接続して前記絶縁フィルムに設ける工程と、前記絶縁フィルムの端部を保持する保持板を取り付ける工程と、前記配線パターンの一部を前記保持板に電気的に接続する工程と、を含み、
前記保持板の熱膨張係数＞前記絶縁フィルムの熱膨張係数
の関係を有する半導体装置の製造方法。Forming a wiring pattern on the insulating film, connecting a semiconductor element to the wiring pattern and providing the insulating film on the insulating film, attaching a holding plate for holding an end of the insulating film, Electrically connecting a portion to the holding plate,
A method of manufacturing a semiconductor device having a relationship of thermal expansion coefficient of the holding plate> thermal expansion coefficient of the insulating film. 請求項１から請求項５のいずれかに記載の半導体装置、所望の導電パターンが形成された基板と、を有し、
前記半導体装置の前記外部端子が前記導電パターンに接続された回路基板。A semiconductor device according to any one of claims 1 to 5, comprising a substrate on which a desired conductive pattern is formed,
A circuit board in which the external terminals of the semiconductor device are connected to the conductive pattern. 半導体素子と、絶縁フィルムと、前記絶縁フィルムに形成されて前記半導体素子に接続される配線パターンと、前記配線パターン上に形成されるバンプと、導電性を有するとともに平面性を保つ部材からなり前記配線パターンに電気的に接続される保持材と、を含み、
前記保持板の熱膨張係数＞前記絶縁フィルムの熱膨張係数
の関係を有する半導体装置と、
所望の導電パターンが形成され、前記絶縁フィルムの少なくとも端部と接着剤にて固定される基板と、
を有する回路基板。A semiconductor element, an insulating film, a wiring pattern formed on the insulating film and connected to the semiconductor element, a bump formed on the wiring pattern, a member having conductivity and maintaining flatness, Holding material electrically connected to the wiring pattern,
A semiconductor device having a relationship of thermal expansion coefficient of the holding plate> thermal expansion coefficient of the insulating film;
A substrate on which a desired conductive pattern is formed and which is fixed with an adhesive at least at an end of the insulating film,
A circuit board having ハンダバンプが形成された絶縁フィルムと、導電性を有するとともに平面性を保つ部材からなり配線パターンに電気的に接続される保持材と、を有し、
前記保持板の熱膨張係数＞前記絶縁フィルムの熱膨張係数
の関係を有する半導体装置の実装方法において、
前記絶縁フィルムの少なくとも端部に接着剤を塗布して回路基板に接着してから、ハンダバンプを溶融させて前記回路基板のパッドに接続する半導体装置の実装方法。It has an insulating film which solder bumps are formed, a holding member that is electrically connected to a wiring pattern made of members to maintain the flatness and having a conductivity, a,
In a method for mounting a semiconductor device having a relationship of thermal expansion coefficient of the holding plate> thermal expansion coefficient of the insulating film,
A method of mounting a semiconductor device in which an adhesive is applied to at least an end portion of the insulating film and bonded to a circuit board, and then solder bumps are melted and connected to pads of the circuit board.
JP53555498A 1997-02-13 1998-01-28 Semiconductor device, method of manufacturing the same, method of mounting the same, and circuit board mounting the same Expired - Fee Related JP3586867B2 (en)

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