US20040007733A1 - Floating gate memory cell and forming method - Google Patents

Floating gate memory cell and forming method Download PDF

Info

Publication number
US20040007733A1
US20040007733A1 US10/180,168 US18016802A US2004007733A1 US 20040007733 A1 US20040007733 A1 US 20040007733A1 US 18016802 A US18016802 A US 18016802A US 2004007733 A1 US2004007733 A1 US 2004007733A1
Authority
US
United States
Prior art keywords
floating gate
carried out
gas
reaction gas
selecting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US10/180,168
Inventor
Tuung Luoh
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Macronix International Co Ltd
Original Assignee
Macronix International Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Macronix International Co Ltd filed Critical Macronix International Co Ltd
Priority to US10/180,168 priority Critical patent/US20040007733A1/en
Assigned to MACRONIX INTERNATIONAL CO., LTD. reassignment MACRONIX INTERNATIONAL CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: LOH, TUUNG
Publication of US20040007733A1 publication Critical patent/US20040007733A1/en
Priority to US11/013,089 priority patent/US7148105B2/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42324—Gate electrodes for transistors with a floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure

Definitions

  • EPROM eraseable programmable read-only memory
  • MOSFET N-channel metal oxide semiconductor field effect transistor
  • FIGS. 1 and 2 comprising a floating gate transistor 10 with two gates 12 , 14 made of polysilicon.
  • Polysilicon is commonly deposited by the thermal decomposition (pyrolysis) of silane (SiH4) or disilane (Si2H6) at about 520-700° C. using low-pressure chemical vapor deposition (LPCVD) techniques.
  • Gate 12 is a select or control gate while gate 14 is a floating gate.
  • Transistor 10 comprises a substrate 16 including a source 18 and a drain 20 separated from one another by a channel 22 .
  • Floating gate 14 is separated from channel 22 by a first insulation layer 24 , also called the gate oxide 24
  • control gate 12 is separated from floating gate 14 by a second insulation layer 26 .
  • FIG. 1 illustrates a conventional method for programming transistor 10 .
  • the arrow in FIG. 1 illustrates channel hot electron injection into floating gate 14 from channel 22 adjacent to drain 20 and through first insulation layer 24 causing a negative charge to be trapped within floating gate 14 .
  • the existence of the negative charge within floating gate 14 causes the threshold voltage of the programming transistor to the higher than prior to programming.
  • the programmed transistor retains its programmed state even when the power supply is turned off; it has been estimated that the programmed device will retain its programmed state for as long as 100 years.
  • FIG. 2 illustrates the erasing of transistor 10 .
  • the arrow in FIG. 2 suggests Fowler-Nordheim (FN) electron tunneling current through first insulation layer 24 and into source 18 (or along channel 22 ).
  • Transistor 10 is read by applying a voltage between high and low threshold values to control gate 12 . If transistor 10 is programmed, that is storing a 0, it will not conduct; if transistor 10 is not programmed, that is storing a 1, it will freely
  • the present invention is based on the recognition that the frequency of erratic erase may be decreased when the grain size of the polysilicon material constituting the floating gate is reduced.
  • a first aspect of the invention is directed to a floating gate memory cell of the type comprising a substrate with a drain and a source separated by a channel, a floating gate separated from the channel by a first insulation layer, and a control gate separated from the floating gate by a second insulation layer.
  • the floating gate is a microcrystalline polysilicon material having a grain size of between about 50-500 ⁇ .
  • the grain size may also be between about 50-300 ⁇ or 200-500 ⁇ .
  • a second aspect of the invention is directed to a method for forming a polysilicon floating gate during the manufacture of a floating gate memory cell using a deposition process.
  • the improved method comprises selecting a reaction gas and, optionally, a second gas for forming the floating gate during the deposition process, consisting essentially of a reaction gas SiX or Si2Y or an appropriate combination thereof, and, optionally, a second gas Z, where at least one of X, Y and Z comprises deuterium (D); and forming a microcrystalline polysilicon floating gate using said selected reaction gas/second gas.
  • X may comprise at least one of: H4, H2Cl2, HCl3, D4, D2Cl2, D3Cl.
  • Y may comprise at least one of: H6, H4Cl2, 2Cl4, D6, D4Cl2, D2Cl4.
  • Z is used primarily to reduce grain size and may comprise at least one of: D2, H2, D3.
  • the floating gate may be deposited with a desired microcrystalline polysilicon grain structure.
  • the floating gate may be deposited in an amorphous state and then treated to exhibit a desired microcrystalline polysilicon grain structure.
  • a third aspect of the invention is directed to a method for forming a polysilicon floating gate during the manufacture of a floating gate memory cell using a deposition process.
  • the method comprises selecting a reaction gas and, optionally, a second gas for forming the floating gate during the deposition process consisting essentially of a reaction gas SiX and, optionally, a second gas Y.
  • the selecting step is carried out with X comprising at least one of: H4, H2Cl2, HCl3, D4, D2Cl2, D3Cl and Y comprising at least one of: D2, H2, D3.
  • the method further comprises forming a microcrystalline polysilicon floating gate using said selected reaction gas/second gas.
  • the forming step may comprise depositing the amorphous silicon material for the floating gate and then treating the floating gate material to exhibit a desired microcrystalline polysilicon grain structure, such as about 200-500 ⁇ .
  • a fourth aspect of the invention is directed to a method for forming a polysilicon floating gate during the manufacture of a floating gate memory cell using a deposition process.
  • the method comprises selecting a reaction gas and, optionally, a second gas for forming the floating gate during the deposition process consisting essentially of a reaction gas Si2X and, optionally, a second gas Y.
  • the selecting step is carried out with X comprising at least one of: H6, H4Cl2, H2Cl4, D6, D4Cl2, D2Cl4 and Y comprising at least one of: D2, 2, D3.
  • the method further comprises forming a microcrystalline polysilicon floating gate using said selected reaction gas/second gas.
  • the forming step may comprise depositing the amorphous silicon material for the floating gate and then treating the floating gate material to exhibit a desired microcrystalline polysilicon grain structure, such as about 200-500 ⁇ .
  • a fifth aspect of the invention is directed to a method for forming a polysilicon floating gate during the manufacture of a floating gate memory cell using a deposition process, the floating gate memory cell of a type comprising a substrate with a drain and a source separated by a channel, a floating gate separated from the channel by a first insulation layer, and a control gate separated from the floating gate by a second insulation layer.
  • a deposition environment is chosen to include selecting a reaction gas, selecting a reaction gas flow rate, selecting a deposition pressure, and selecting a deposition time.
  • a microcrystalline polysilicon floating gate is formed with the selecting steps chosen so that the grain size of at least a portion of the floating gate opposite the first insulation layer is about 50-500 ⁇ .
  • the entire floating gate may have a grain size of about 50-500 ⁇ .
  • the selecting steps may also be carried out so that the grain size is between about 50-300 ⁇ .
  • the reaction gas selecting step may comprise selecting a reaction gas and, optionally, a second gas consisting essentially of a reaction gas SiX or Si2Y or an appropriate combination thereof, and, optionally, a second gas Z, where at least one of X, Y and Z comprises deuterium (D).
  • the reaction gas-selecting step may be carried out with X comprising at least one of: H4, H2Cl2, HCl3, D4, D2Cl2, D3Cl.
  • the reaction gas-selecting step may also be carried out with Y comprising at least one of: H6, H4Cl2, H2Cl4, D6, D4Cl2, D2Cl4.
  • the reaction gas-selecting step may be carried out with Z comprising at least one of: D2, H2, D3.
  • FIG. 1 illustrates a prior art floating gate transistor in a programming mode
  • FIG. 2 illustrates the floating gate transistor of FIG. 1 in an erase mode
  • FIG. 3 is an enlarged, simplified view of a portion of the transistor of FIG. 1;
  • FIG. 4 is a view, similar to that of FIG. 3, of a portion of a floating gate transistor made according to the invention illustrating the smaller grains of the floating gate.
  • Erratic floating gate transistors show an unstable and unpredictable behavior in erasing. Erratic erase can cause an over erase condition. An over erase condition can cause a memory cell to be stuck as a 1 so that it cannot be programmed.
  • the present invention is based on the concept that making at least the portion of the floating gate opposite the first insulation layer to be a microcrystalline polysilicon material with a controlled, small grain size will help eliminate erratic erase and lead to uniform erase speed.
  • FIG. 3 is an enlarged, simplified view of a portion of transistor 10 of FIG. 1 illustrating the relatively large grains 28 of the polysilicon material constituting that portion of floating gate 14 adjacent to first insulation layer 24 .
  • Conventional deposition processes create grains 28 having a grain size range from about 600-3000 ⁇ . Also illustrated is what is termed an oxide valley 30 in first insulation layer 24 at the intersection of adjacent grains 28 .
  • FIG. 4 is a view, similar view to that of FIG. 3, of a portion of a floating gate transistor made according to the invention.
  • a floating gate transistor made according to the invention is typically substantially identical to the conventional floating gate transistor 10 of FIGS. 1 - 3 , except that floating gate 14 A comprises much smaller grains 28 A and smaller oxide valleys 30 A than floating gate 14 .
  • a high density of phosphorous oxide region is designed as “oxide valley”.
  • Floating gate 14 A is a microcrystalline polysilicon material having a grain size of between about 50-500 ⁇ , and preferably between about 50-300 ⁇ . It is believed that having much smaller grains 28 A leads to smaller valleys 30 A. The smaller grain size helps to decrease the erratic erase problems and leads to a more uniform erase speed.
  • the barrier height or electron trapping will be reduced at the poly-Si/SiO2 interface due to the smaller oxide valley.
  • the provision of smaller grains 28 A, which as illustrated are somewhat randomly sized, can also help make transistor 10 resistant to trap generation by hot electron
  • the invention is typically carried out using an LPCVD deposition process.
  • One such LPCVD process known as the furnace process, is carried out at a temperature of about 500-700° C. and a pressure of about 0.1 mtorr-5 torr.
  • Another LPCVD process known as the single wafer process, is carried out at a temperature of about 580-800° C. and a pressure of about 10-500 torr.
  • the floating gate may be deposited with a desired microcrystalline polysilicon grain structure. However, when the deposition takes place at temperatures below about 580° C., the deposited floating gate material may be amorphous and will need to be treated, typically annealed, to achieve the desired microcrystalline polysilicon grain structure.
  • the resulting grain size is typically about 200-500 ⁇ .
  • the invention may be carried out using deposition processes other than LPCVD, such as PECVD (plasma enhance CVD), to achieve the desired grain structure.
  • PECVD plasma enhance CVD
  • the polysilicon floating gate 14 A is formed by first selecting a reaction gas and, optionally, a second gas for forming the floating gate during the deposition process.
  • the gas consists essentially of a reaction gas SiX or Si2Y or an appropriate combination thereof, and, optionally, a second gas Z.
  • At least one of X, Y and Z may comprise deuterium (D).
  • X comprises at least one of: H4, 2Cl2, HCl3, D4, D2Cl2, D3Cl.
  • Y comprises at least one of: H6, H4Cl2, H2Cl4, D6, 4Cl2, D2Cl4.
  • Z comprises at least one of: D2, H2, D3.
  • SiH4/H2, SiH4/D2, SiD4/H2, and SiD4/D2 the following has been found.
  • the test conditions included temperature: 640 ⁇ 770C, pressure: 200 ⁇ 400 torr, and SiH4 at 10 ⁇ 1000 sccm).
  • SiH4 (1) does not create a floating gate 14 A having a desired microcrystalline polysilicon grain structure, and (2) does not create a floating gate 14 A resistant to trap generation by hot electron impingement.
  • SiH4/H2 (1) does create a floating gate 14 A having a desired microcrystalline polysilicon grain structure, and (2) does not create a floating gate 14 A resistant to trap generation by hot electron impingement.
  • SiH4/D2 (1) does create a floating gate 14 A having a desired microcrystalline polysilicon grain structure, and (2) does create a floating gate 14 A resistant to trap generation by hot electron impingement.
  • SiD4/H2 (1) does create a floating gate 14 A having a desired microcrystalline polysilicon grain structure, and (2) does create a floating gate 14 A resistant to trap generation by hot electron impingement.
  • SiD4/D2 (1) does create a floating gate 14 A having a desired microcrystalline polysilicon grain structure, and (2) does create a floating gate 14 A resistant to trap generation by hot electron impingement. Of these compositions, SiD4/D2 appears to be the best.
  • H2 flow on grain size appears to be that grain size decreases as H2 flow increases.
  • testing was done at 720C, 275 torr, 24 sec deposition to 1000A thickness in a single-wafer POLYgen chamber using SiH4/H2.
  • a flow rate ratio for SiH4/H2 of 100 sccm/0 sccm resulted in a grain size of about 600-800 ⁇ .
  • a flow rate ratio for SiH4/d2 of 100 sccm/1000 sccm resulted in a grain size of about 200-400 ⁇ .
  • a flow rate ratio for SiH4/H2 of 100 sccm/2000 sccm resulted in a grain size of about 50-200 ⁇ .
  • testing was done in a single-wafer POLYgen chamber at 640C, 275 torr using SiH4/H2 for 38 sec deposition to 1000A thickness, and then RTP at 950C 30 sec in N2 ambient.
  • a flow rate ratio for SiH4/H2 of 200 sccm/0 sccm resulted in a grain size of about 800 ⁇ 1000 ⁇ .
  • a flow rate ratio for SiH4/H2 of 200 sccm/1000 sccm resulted in a grain size of about 400 ⁇ 600 ⁇ .
  • a flow rate ratio for SiH4/H2 of 200 sccm/2000 sccm resulted in a grain size of about 200 ⁇ 300 ⁇ .

Abstract

A floating gate memory cell comprises a substrate with a drain and a source separated by a channel, a floating gate separated from the channel by a first insulation layer, and a control gate separated from the floating gate by a second insulation layer. The deposition environment is chosen so that the grain size of at least a portion of the floating gate opposite the first insulation layer is about 50-500 Å.

Description

    BACKGROUND OF THE INVENTION
  • One type of integrated circuit (IC) memory is called eraseable programmable read-only memory (EPROM). This type of memory permits the user to program the memory and, if desired, erase and reprogram memory. One type of EPROM is an N-channel metal oxide semiconductor field effect transistor (MOSFET), one example of which is shown in FIGS. 1 and 2, comprising a [0001] floating gate transistor 10 with two gates 12, 14 made of polysilicon. Polysilicon is commonly deposited by the thermal decomposition (pyrolysis) of silane (SiH4) or disilane (Si2H6) at about 520-700° C. using low-pressure chemical vapor deposition (LPCVD) techniques. The deposition at lower temperatures, such as 520° C., results in the deposited polysilicon being amorphous; the amorphous polysilicon can be recrystallized by subsequent annealing procedures, such as at about 900-10000° C. Gate 12 is a select or control gate while gate 14 is a floating gate. Transistor 10 comprises a substrate 16 including a source 18 and a drain 20 separated from one another by a channel 22. Floating gate 14 is separated from channel 22 by a first insulation layer 24, also called the gate oxide 24, while control gate 12 is separated from floating gate 14 by a second insulation layer 26.
  • FIG. 1 illustrates a conventional method for [0002] programming transistor 10. The arrow in FIG. 1 illustrates channel hot electron injection into floating gate 14 from channel 22 adjacent to drain 20 and through first insulation layer 24 causing a negative charge to be trapped within floating gate 14. The existence of the negative charge within floating gate 14 causes the threshold voltage of the programming transistor to the higher than prior to programming. The programmed transistor retains its programmed state even when the power supply is turned off; it has been estimated that the programmed device will retain its programmed state for as long as 100 years. FIG. 2 illustrates the erasing of transistor 10. The arrow in FIG. 2 suggests Fowler-Nordheim (FN) electron tunneling current through first insulation layer 24 and into source 18 (or along channel 22). Transistor 10 is read by applying a voltage between high and low threshold values to control gate 12. If transistor 10 is programmed, that is storing a 0, it will not conduct; if transistor 10 is not programmed, that is storing a 1, it will freely conduct.
    • SUMMARY OF THE INVENTION
  • The present invention is based on the recognition that the frequency of erratic erase may be decreased when the grain size of the polysilicon material constituting the floating gate is reduced. [0003]
  • A first aspect of the invention is directed to a floating gate memory cell of the type comprising a substrate with a drain and a source separated by a channel, a floating gate separated from the channel by a first insulation layer, and a control gate separated from the floating gate by a second insulation layer. The floating gate is a microcrystalline polysilicon material having a grain size of between about 50-500 Å. The grain size may also be between about 50-300 Å or 200-500 Å. [0004]
  • A second aspect of the invention is directed to a method for forming a polysilicon floating gate during the manufacture of a floating gate memory cell using a deposition process. The improved method comprises selecting a reaction gas and, optionally, a second gas for forming the floating gate during the deposition process, consisting essentially of a reaction gas SiX or Si2Y or an appropriate combination thereof, and, optionally, a second gas Z, where at least one of X, Y and Z comprises deuterium (D); and forming a microcrystalline polysilicon floating gate using said selected reaction gas/second gas. X may comprise at least one of: H4, H2Cl2, HCl3, D4, D2Cl2, D3Cl. Y may comprise at least one of: H6, H4Cl2, 2Cl4, D6, D4Cl2, D2Cl4. Z is used primarily to reduce grain size and may comprise at least one of: D2, H2, D3. The floating gate may be deposited with a desired microcrystalline polysilicon grain structure. The floating gate may be deposited in an amorphous state and then treated to exhibit a desired microcrystalline polysilicon grain structure. [0005]
  • A third aspect of the invention is directed to a method for forming a polysilicon floating gate during the manufacture of a floating gate memory cell using a deposition process. The method comprises selecting a reaction gas and, optionally, a second gas for forming the floating gate during the deposition process consisting essentially of a reaction gas SiX and, optionally, a second gas Y. The selecting step is carried out with X comprising at least one of: H4, H2Cl2, HCl3, D4, D2Cl2, D3Cl and Y comprising at least one of: D2, H2, D3. The method further comprises forming a microcrystalline polysilicon floating gate using said selected reaction gas/second gas. The forming step may comprise depositing the amorphous silicon material for the floating gate and then treating the floating gate material to exhibit a desired microcrystalline polysilicon grain structure, such as about 200-500 Å. [0006]
  • A fourth aspect of the invention is directed to a method for forming a polysilicon floating gate during the manufacture of a floating gate memory cell using a deposition process. The method comprises selecting a reaction gas and, optionally, a second gas for forming the floating gate during the deposition process consisting essentially of a reaction gas Si2X and, optionally, a second gas Y. The selecting step is carried out with X comprising at least one of: H6, H4Cl2, H2Cl4, D6, D4Cl2, D2Cl4 and Y comprising at least one of: D2, 2, D3. The method further comprises forming a microcrystalline polysilicon floating gate using said selected reaction gas/second gas. The forming step may comprise depositing the amorphous silicon material for the floating gate and then treating the floating gate material to exhibit a desired microcrystalline polysilicon grain structure, such as about 200-500 Å. [0007]
  • A fifth aspect of the invention is directed to a method for forming a polysilicon floating gate during the manufacture of a floating gate memory cell using a deposition process, the floating gate memory cell of a type comprising a substrate with a drain and a source separated by a channel, a floating gate separated from the channel by a first insulation layer, and a control gate separated from the floating gate by a second insulation layer. A deposition environment is chosen to include selecting a reaction gas, selecting a reaction gas flow rate, selecting a deposition pressure, and selecting a deposition time. A microcrystalline polysilicon floating gate is formed with the selecting steps chosen so that the grain size of at least a portion of the floating gate opposite the first insulation layer is about 50-500 Å. The entire floating gate may have a grain size of about 50-500 Å. The selecting steps may also be carried out so that the grain size is between about 50-300 Å. The reaction gas selecting step may comprise selecting a reaction gas and, optionally, a second gas consisting essentially of a reaction gas SiX or Si2Y or an appropriate combination thereof, and, optionally, a second gas Z, where at least one of X, Y and Z comprises deuterium (D). The reaction gas-selecting step may be carried out with X comprising at least one of: H4, H2Cl2, HCl3, D4, D2Cl2, D3Cl. The reaction gas-selecting step may also be carried out with Y comprising at least one of: H6, H4Cl2, H2Cl4, D6, D4Cl2, D2Cl4. The reaction gas-selecting step may be carried out with Z comprising at least one of: D2, H2, D3. [0008]
  • Other features and advantages of the present invention will appear from the following description in which preferred embodiments are disclosed in detail in conjunction with the accompanying drawings.[0009]
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 illustrates a prior art floating gate transistor in a programming mode; [0010]
  • FIG. 2 illustrates the floating gate transistor of FIG. 1 in an erase mode; [0011]
  • FIG. 3 is an enlarged, simplified view of a portion of the transistor of FIG. 1; and [0012]
  • FIG. 4 is a view, similar to that of FIG. 3, of a portion of a floating gate transistor made according to the invention illustrating the smaller grains of the floating gate.[0013]
    • DETAILED DESCRIPTION OF THE INVENTION
  • One of the most common failure modes of an individual floating gate transistor within an integrated circuit memory is called erratic erase. Erratic floating gate transistors show an unstable and unpredictable behavior in erasing. Erratic erase can cause an over erase condition. An over erase condition can cause a memory cell to be stuck as a 1 so that it cannot be programmed. The present invention is based on the concept that making at least the portion of the floating gate opposite the first insulation layer to be a microcrystalline polysilicon material with a controlled, small grain size will help eliminate erratic erase and lead to uniform erase speed. [0014]
  • FIG. 3 is an enlarged, simplified view of a portion of [0015] transistor 10 of FIG. 1 illustrating the relatively large grains 28 of the polysilicon material constituting that portion of floating gate 14 adjacent to first insulation layer 24. Conventional deposition processes create grains 28 having a grain size range from about 600-3000 Å. Also illustrated is what is termed an oxide valley 30 in first insulation layer 24 at the intersection of adjacent grains 28.
  • FIG. 4 is a view, similar view to that of FIG. 3, of a portion of a floating gate transistor made according to the invention. A floating gate transistor made according to the invention is typically substantially identical to the conventional [0016] floating gate transistor 10 of FIGS. 1-3, except that floating gate 14A comprises much smaller grains 28A and smaller oxide valleys 30A than floating gate 14. A high density of phosphorous oxide region is designed as “oxide valley”. Floating gate 14A is a microcrystalline polysilicon material having a grain size of between about 50-500 Å, and preferably between about 50-300 Å. It is believed that having much smaller grains 28A leads to smaller valleys 30A. The smaller grain size helps to decrease the erratic erase problems and leads to a more uniform erase speed. The barrier height or electron trapping will be reduced at the poly-Si/SiO2 interface due to the smaller oxide valley. The provision of smaller grains 28A, which as illustrated are somewhat randomly sized, can also help make transistor 10 resistant to trap generation by hot electron impingement.
  • The invention is typically carried out using an LPCVD deposition process. One such LPCVD process, known as the furnace process, is carried out at a temperature of about 500-700° C. and a pressure of about 0.1 mtorr-5 torr. Another LPCVD process, known as the single wafer process, is carried out at a temperature of about 580-800° C. and a pressure of about 10-500 torr. The floating gate may be deposited with a desired microcrystalline polysilicon grain structure. However, when the deposition takes place at temperatures below about 580° C., the deposited floating gate material may be amorphous and will need to be treated, typically annealed, to achieve the desired microcrystalline polysilicon grain structure. When the floating gate is deposited in an amorphous state and then treated to exhibit a desired microcrystalline polysilicon grain structure, the resulting grain size is typically about 200-500 Å. The invention may be carried out using deposition processes other than LPCVD, such as PECVD (plasma enhance CVD), to achieve the desired grain structure. [0017]
  • Most of the steps in the formation of floating [0018] gate transistor 10 as part of an integrated circuit memory device are generally conventional. However, the polysilicon floating gate 14A is formed by first selecting a reaction gas and, optionally, a second gas for forming the floating gate during the deposition process. The gas consists essentially of a reaction gas SiX or Si2Y or an appropriate combination thereof, and, optionally, a second gas Z. At least one of X, Y and Z may comprise deuterium (D). X comprises at least one of: H4, 2Cl2, HCl3, D4, D2Cl2, D3Cl. Y comprises at least one of: H6, H4Cl2, H2Cl4, D6, 4Cl2, D2Cl4. Z comprises at least one of: D2, H2, D3.
  • In comparing the use of SiH4, SiH4/H2, SiH4/D2, SiD4/H2, and SiD4/D2, the following has been found. (The test conditions included temperature: 640˜770C, pressure: 200˜400 torr, and SiH4 at 10˜1000 sccm). SiH4 (1) does not create a floating [0019] gate 14A having a desired microcrystalline polysilicon grain structure, and (2) does not create a floating gate 14A resistant to trap generation by hot electron impingement. SiH4/H2 (1) does create a floating gate 14A having a desired microcrystalline polysilicon grain structure, and (2) does not create a floating gate 14A resistant to trap generation by hot electron impingement. SiH4/D2 (1) does create a floating gate 14A having a desired microcrystalline polysilicon grain structure, and (2) does create a floating gate 14A resistant to trap generation by hot electron impingement. SiD4/H2 (1) does create a floating gate 14A having a desired microcrystalline polysilicon grain structure, and (2) does create a floating gate 14A resistant to trap generation by hot electron impingement. SiD4/D2 (1) does create a floating gate 14A having a desired microcrystalline polysilicon grain structure, and (2) does create a floating gate 14A resistant to trap generation by hot electron impingement. Of these compositions, SiD4/D2 appears to be the best.
  • The effect of H2 flow on grain size appears to be that grain size decreases as H2 flow increases. For example, testing was done at 720C, 275 torr, 24 sec deposition to 1000A thickness in a single-wafer POLYgen chamber using SiH4/H2. A flow rate ratio for SiH4/H2 of 100 sccm/0 sccm resulted in a grain size of about 600-800 Å. A flow rate ratio for SiH4/d2 of 100 sccm/1000 sccm resulted in a grain size of about 200-400 Å. A flow rate ratio for SiH4/H2 of 100 sccm/2000 sccm resulted in a grain size of about 50-200 Å. In another example, testing was done in a single-wafer POLYgen chamber at 640C, 275 torr using SiH4/H2 for 38 sec deposition to 1000A thickness, and then RTP at [0020] 950C 30 sec in N2 ambient. A flow rate ratio for SiH4/H2 of 200 sccm/0 sccm resulted in a grain size of about 800˜1000 Å. A flow rate ratio for SiH4/H2 of 200 sccm/1000 sccm resulted in a grain size of about 400˜600 Å. A flow rate ratio for SiH4/H2 of 200 sccm/2000 sccm resulted in a grain size of about 200˜300 Å.
  • Modification and variation can be made to be disclosed embodiments without the departing from the subject of the invention as defined in the following claims. [0021]
  • Any and all patents, patent applications and printed publications referred to above are incorporated by reference. [0022]

Claims (44)

What is claimed is:
1. A floating gate memory cell of a type comprising a substrate with a drain and a source separated by a channel, a floating gate separated from the channel by a first insulation layer, and a control gate separated from the floating gate by a second insulation layer, an improvement comprising:
at least the portion of the floating gate opposite the first insulation layer being a microcrystalline polysilicon material having a grain size of between about 50-500 Å.
2. The floating gate memory cell according to claim 1 wherein the entire floating gate is a microcrystalline polysilicon material having a grain size of between about 50-500 Å.
3. The floating gate memory cell according to claim 1 wherein the grain size is between about 50-300 Å.
4. The floating gate memory cell according to claim 1 wherein the grain size is between about 200-500 Å.
5. The floating gate memory cell according to claim 1 wherein the microcrystalline polysilicon material is an undoped material.
6. The floating gate memory cell according to claim 1 wherein the microcrystalline polysilicon material is an in-situ doped-process doped material.
7. The floating gate memory cell according to claim 1 wherein the microcrystalline polysilicon material is an undoped process with implant.
8. A method for forming a polysilicon floating gate during the manufacture of a floating gate memory cell using a deposition process, comprising:
selecting a reaction gas and, optionally, a second gas for forming the floating gate during the deposition process consisting essentially of a reaction gas SiX or Si2Y or an appropriate combination thereof, and, optionally, a second gas Z, where at least one of X, Y and Z comprises deuterium (D); and
forming a microcrystalline polysilicon floating gate using said selected reaction gas/second gas.
9. The method according to claim 8 wherein the selecting step is carried out with X comprising at least one of. H4, H2Cl2, HCl3, D4, D2Cl2, D3Cl.
10. The method according to claim 8 wherein the selecting step is carried out with Y comprising at least one of. H6, H4Cl2, H2Cl4, D6, D4Cl2, D2Cl4.
11. The method according to claim 8 wherein the selecting step is carried out with Z comprising at least one of. D2, H2, D3.
12. The method according to claim 8 wherein the selecting step is carried out with the reaction gas/second gas being SiD4/D2.
13. The method according to claim 8 wherein the selecting step is carried out with the reaction gas/second gas being Si2D6/D2.
14. The method according to claim 8 wherein the selecting step is carried out with the reaction gas/second gas comprising at least one of the following: SiD4/D2, SiD4/H2, SiH4/D2.
15. The method according to claim 8 wherein the selecting step is carried out with the reaction gas/second gas comprising at least one of the following: Si2D6/D2, Si2D6/H2, Si2H6/D.
16. The method according to claim 8 wherein the forming step comprises:
depositing an amorphous silicon material for the floating gate; and then
treating the amorphous silicon floating gate material to exhibit a desired microcrystalline polysilicon grain structure.
17. The method according to claim 16 wherein the treating step is carried out so that the microcrystalline polysilicon floating gate has a grain size of about 200-500 Å.
18. The method according to claim 16 wherein the treating step is carried out by subjecting the amorphous silicon floating gate material to a temperature above about 600° C.
19. The method according to claim 8 wherein the forming step takes place with the polysilicon material being deposited with a desired microcrystalline polysilicon grain structure.
20. The method according to claim 8 wherein the selecting and forming steps are carried out during an LPCVD procedure.
21. The method according to claim 20 wherein the LPCVD process comprises a chosen one of the following processes: furnace, single wafer.
22. The method according to claim 8 wherein the LPCVD process comprises a furnace process carried out at a pressure from about 0.1 milliTorr to about 5 Torr and at a temperature of about 5000° C. to about 7000° C.
23. The method according to claim 8 wherein the LPCVD process comprises a single wafer process carried out at a pressure from about 10 Torr to about 500 Torr and at a temperature of about 580° C. to about 800° C.
24. The method according to claim 8 wherein the forming step is carried out so that the microcrystalline polysilicon floating gate has a grain size of about 50-500 Å.
25. The method according to claim 8 wherein the forming step is carried out so that the microcrystalline polysilicon floating gate has a grain size of about 50-300 Å.
26. A floating gate memory cell made according to the method of claim 8.
27. A method for forming a polysilicon floating gate during the manufacture of a floating gate memory cell using a deposition process, comprising:
selecting a reaction gas and, optionally, a second gas for forming the floating gate during the deposition process consisting essentially of a reaction gas SiX and, optionally, a second gas Y;
the selecting step being carried out with X comprising at least one of: H4, H2Cl2, HCl3, D4, D2Cl2, D3Cl and Y comprising at least one of: D2, H2, D3; and
forming a microcrystalline polysilicon floating gate using said selected reaction gas/second gas.
28. The method according to claim 27 wherein the forming step comprises:
depositing an amorphous silicon material for the floating gate; and then
treating the amorphous silicon floating gate material to exhibit a desired microcrystalline polysilicon grain structure.
29. The method according to claim 28 wherein the treating step is carried out so that the microcrystalline polysilicon floating gate has a grain size of about 200-500 Å.
30. The method according to claim 27 wherein the forming step takes place with the polysilicon material being deposited with a grain size of about 50-300 Å.
31. The method according to claim 27 wherein at least one of X and Y comprises deuterium (D).
32. A floating gate memory cell made according to the method of claim 27.
33. A method for forming a polysilicon floating gate during the manufacture of a floating gate memory cell using a deposition process, comprising:
selecting a reaction gas and, optionally, a second gas for forming the floating gate during the deposition process consisting essentially of a reaction gas Si2X and, optionally, a second gas Y;
the selecting step being carried out with X comprising at least one of: H6, H4Cl2, 2Cl4, D6, D4Cl2, D2Cl4 and Y comprising at least one of: D2, H2, D3; and forming a microcrystalline polysilicon floating gate using said selected reaction gas/second gas.
34. The method according to claim 33 wherein the forming step comprises:
depositing an amorphous silicon material for the floating gate; and then
treating the amorphous silicon floating gate material to exhibit a desired microcrystalline polysilicon grain structure.
35. The method according to claim 34 wherein the treating step is carried out so that the microcrystalline polysilicon floating gate has a grain size of about 200-500 Å.
36. The method according to claim 33 wherein the forming step takes place with the polysilicon material being deposited with a grain size of about 50-300 Å.
37. The method according to claim 33 wherein at least one of X and Y comprises deuterium (D).
38. A floating gate memory cell made according to the method of 33.
39. A method for forming a polysilicon floating gate during the manufacture of a floating gate memory cell using a deposition process, the floating gate memory cell of a type comprising a substrate with a drain and a source separated by a channel, a floating gate separated from the channel by a first insulation layer, and a control gate separated from the floating gate by a second insulation layer, comprising:
choosing a deposition environment comprising:
selecting a reaction gas;
selecting a reaction gas flow rate;
selecting a deposition pressure; and
selecting a deposition time;
forming a microcrystalline polysilicon floating gate; and
said the selecting steps chosen so that the grain size of at least a portion of the floating gate opposite the first insulation layer is about 50-500 Å.
40. The method according to claim 39 wherein the selecting steps are carried out so that the grain size is between about 50-300 Å.
41. The method according to claim 39 wherein the reaction gas selecting step comprises:
selecting a reaction gas and, optionally, a second gas consisting essentially of a reaction gas SiX or Si2Y or an appropriate combination thereof, and, optionally, a second gas Z, where at least one of X, Y and Z comprises deuterium (D).
42. The method according to claim 41 wherein the reaction gas selecting step is carried out with X comprising at least one of: H4, H2Cl2, HCl3, D4, D2Cl2, D3Cl.
43. The method according to claim 41 wherein the reaction gas selecting step is carried out with Y comprising at least one of: H6, H4Cl2, H2Cl4, D6, D4Cl2, D2Cl4.
44. The method according to claim 41 wherein the reaction gas selecting step is carried out with Z comprising at least one of: D2, H2, D3.
US10/180,168 2002-06-26 2002-06-26 Floating gate memory cell and forming method Abandoned US20040007733A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US10/180,168 US20040007733A1 (en) 2002-06-26 2002-06-26 Floating gate memory cell and forming method
US11/013,089 US7148105B2 (en) 2002-06-26 2004-12-15 Method for forming polysilicon floating gate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/180,168 US20040007733A1 (en) 2002-06-26 2002-06-26 Floating gate memory cell and forming method

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US11/013,089 Division US7148105B2 (en) 2002-06-26 2004-12-15 Method for forming polysilicon floating gate

Publications (1)

Publication Number Publication Date
US20040007733A1 true US20040007733A1 (en) 2004-01-15

Family

ID=30113940

Family Applications (2)

Application Number Title Priority Date Filing Date
US10/180,168 Abandoned US20040007733A1 (en) 2002-06-26 2002-06-26 Floating gate memory cell and forming method
US11/013,089 Expired - Lifetime US7148105B2 (en) 2002-06-26 2004-12-15 Method for forming polysilicon floating gate

Family Applications After (1)

Application Number Title Priority Date Filing Date
US11/013,089 Expired - Lifetime US7148105B2 (en) 2002-06-26 2004-12-15 Method for forming polysilicon floating gate

Country Status (1)

Country Link
US (2) US20040007733A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050158976A1 (en) * 2002-06-26 2005-07-21 Macronix International Co., Ltd. Floating gate memory cell and forming method

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110101442A1 (en) * 2009-11-02 2011-05-05 Applied Materials, Inc. Multi-Layer Charge Trap Silicon Nitride/Oxynitride Layer Engineering with Interface Region Control
CN106571287A (en) * 2015-10-12 2017-04-19 上海新昇半导体科技有限公司 Method for forming epitaxial layer
KR20220023613A (en) * 2020-08-21 2022-03-02 에스케이하이닉스 주식회사 Semiconductor device and manufacturing method of semiconductor device

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5017308A (en) * 1980-10-15 1991-05-21 Toa Nenryo Kogyo K.K. Silicon thin film and method of producing the same
US5147813A (en) * 1990-08-15 1992-09-15 Intel Corporation Erase performance improvement via dual floating gate processing
US5445982A (en) * 1994-02-23 1995-08-29 Goldstar Electron Co., Ltd. Method of fabricating nonvolatile semiconductor memory device
US5972765A (en) * 1997-07-16 1999-10-26 International Business Machines Corporation Use of deuterated materials in semiconductor processing
US6114722A (en) * 1995-09-29 2000-09-05 Intel Corporation Microcrystalline silicon structure and fabrication process
US6218246B1 (en) * 1998-12-31 2001-04-17 Hyundai Electronics Industries Co., Ltd. Fabrication method of triple polysilicon flash eeprom arrays
US6221705B1 (en) * 1997-07-28 2001-04-24 Texas Instruments Incorporated Method for improving performance and reliability of MOS technologies and data retention characteristics of flash memory cells
US6252270B1 (en) * 1997-04-28 2001-06-26 Agere Systems Guardian Corp. Increased cycle specification for floating-gate and method of manufacture thereof
US6670241B1 (en) * 2002-04-22 2003-12-30 Advanced Micro Devices, Inc. Semiconductor memory with deuterated materials

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4748133A (en) * 1987-06-26 1988-05-31 Motorola Inc. Deposition of amorphous silicon for the formation of interlevel dielectrics in semiconductor memory devices
US5017980A (en) * 1988-07-15 1991-05-21 Texas Instruments Incorporated Electrically-erasable, electrically-programmable read-only memory cell
US4945393A (en) * 1988-06-21 1990-07-31 At&T Bell Laboratories Floating gate memory circuit and apparatus
US4963506A (en) * 1989-04-24 1990-10-16 Motorola Inc. Selective deposition of amorphous and polycrystalline silicon
EP0909985A1 (en) * 1990-09-26 1999-04-21 Canon Kabushiki Kaisha Photolithographic processing method and apparatus
US5614257A (en) * 1991-08-09 1997-03-25 Applied Materials, Inc Low temperature, high pressure silicon deposition method
US5753134A (en) * 1994-01-04 1998-05-19 Siemens Aktiengesellschaft Method for producing a layer with reduced mechanical stresses
JP3069509B2 (en) * 1995-04-10 2000-07-24 株式会社日立製作所 Non-aqueous secondary battery and method for producing graphite powder
EP0830684B1 (en) * 1995-06-07 2004-08-25 Macronix International Co., Ltd. Automatic programming algorithm for page mode flash memory with variable programming pulse height and pulse width
US5711998A (en) * 1996-05-31 1998-01-27 Lam Research Corporation Method of polycrystalline silicon hydrogenation
US6023093A (en) * 1997-04-28 2000-02-08 Lucent Technologies Inc. Deuterated direlectric and polysilicon film-based semiconductor devices and method of manufacture thereof
US6013551A (en) * 1997-09-26 2000-01-11 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacture of self-aligned floating gate, flash memory cell and device manufactured thereby
US6143632A (en) * 1997-12-18 2000-11-07 Advanced Micro Devices, Inc. Deuterium doping for hot carrier reliability improvement
US6373092B1 (en) * 1998-09-29 2002-04-16 Texas Instruments Incorporated Staggered-edge capacitor electrode
US6268068B1 (en) * 1998-10-06 2001-07-31 Case Western Reserve University Low stress polysilicon film and method for producing same
US6218245B1 (en) 1998-11-24 2001-04-17 Advanced Micro Devices, Inc. Method for fabricating a high-density and high-reliability EEPROM device
US6509217B1 (en) * 1999-10-22 2003-01-21 Damoder Reddy Inexpensive, reliable, planar RFID tag structure and method for making same
US20040007733A1 (en) * 2002-06-26 2004-01-15 Macronix International Co., Ltd. Floating gate memory cell and forming method
US6861339B2 (en) * 2002-10-21 2005-03-01 Taiwan Semiconductor Manufacturing Co., Ltd Method for fabricating laminated silicon gate electrode

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5017308A (en) * 1980-10-15 1991-05-21 Toa Nenryo Kogyo K.K. Silicon thin film and method of producing the same
US5147813A (en) * 1990-08-15 1992-09-15 Intel Corporation Erase performance improvement via dual floating gate processing
US5445982A (en) * 1994-02-23 1995-08-29 Goldstar Electron Co., Ltd. Method of fabricating nonvolatile semiconductor memory device
US6114722A (en) * 1995-09-29 2000-09-05 Intel Corporation Microcrystalline silicon structure and fabrication process
US6252270B1 (en) * 1997-04-28 2001-06-26 Agere Systems Guardian Corp. Increased cycle specification for floating-gate and method of manufacture thereof
US5972765A (en) * 1997-07-16 1999-10-26 International Business Machines Corporation Use of deuterated materials in semiconductor processing
US6221705B1 (en) * 1997-07-28 2001-04-24 Texas Instruments Incorporated Method for improving performance and reliability of MOS technologies and data retention characteristics of flash memory cells
US6218246B1 (en) * 1998-12-31 2001-04-17 Hyundai Electronics Industries Co., Ltd. Fabrication method of triple polysilicon flash eeprom arrays
US6670241B1 (en) * 2002-04-22 2003-12-30 Advanced Micro Devices, Inc. Semiconductor memory with deuterated materials

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050158976A1 (en) * 2002-06-26 2005-07-21 Macronix International Co., Ltd. Floating gate memory cell and forming method
US7148105B2 (en) 2002-06-26 2006-12-12 Macronix International Co., Ltd. Method for forming polysilicon floating gate

Also Published As

Publication number Publication date
US20050158976A1 (en) 2005-07-21
US7148105B2 (en) 2006-12-12

Similar Documents

Publication Publication Date Title
US6998675B2 (en) Nucleation for improved flash erase characteristics
US6445030B1 (en) Flash memory erase speed by fluorine implant or fluorination
US6319775B1 (en) Nitridation process for fabricating an ONO floating-gate electrode in a two-bit EEPROM device
EP1234324B1 (en) Ono-deposition for 2-bit eeprom devices
KR101219067B1 (en) Non-volatile nanocrystal memory and method therefor
US5836772A (en) Interpoly dielectric process
US6248628B1 (en) Method of fabricating an ONO dielectric by nitridation for MNOS memory cells
US7517747B2 (en) Nanocrystal non-volatile memory cell and method therefor
US7001810B2 (en) Floating gate nitridation
US20060246665A1 (en) Manufacturing process of an interpoly dielectric structure for non-volatile semiconductor integrated memories
JP4617574B2 (en) Nonvolatile semiconductor memory device and manufacturing method thereof
US6458677B1 (en) Process for fabricating an ONO structure
US8044454B2 (en) Non-volatile memory device
US6180538B1 (en) Process for fabricating an ONO floating-gate electrode in a two-bit EEPROM device using rapid-thermal-chemical-vapor-deposition
KR20090052682A (en) Non-volatile memory device, and memory card and system including the same
US6218227B1 (en) Method to generate a MONOS type flash cell using polycrystalline silicon as an ONO top layer
US7098505B1 (en) Memory device with multiple memory layers of local charge storage
US20040007733A1 (en) Floating gate memory cell and forming method
US9425325B2 (en) Electrically programmable and eraseable memory device
KR100534210B1 (en) Method for forming dielectric layer structure for use in non-volatile memory cell
JP2002261175A (en) Nonvolatile semiconductor memory and its manufacturing method
US20070249121A1 (en) Method of fabricating non-volatile memory
US20060108610A1 (en) Method of manufacturing a thin dielectric layer using a heat treatment and a semiconductor device formed using the method
JP2004103902A (en) Nonvolatile semiconductor storage device and its manufacturing method
KR100678295B1 (en) Method for manufacturing of semiconductor device

Legal Events

Date Code Title Description
AS Assignment

Owner name: MACRONIX INTERNATIONAL CO., LTD., TAIWAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:LOH, TUUNG;REEL/FRAME:014835/0599

Effective date: 20030904

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION