US20030214050A1 - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
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- US20030214050A1 US20030214050A1 US10/298,927 US29892702A US2003214050A1 US 20030214050 A1 US20030214050 A1 US 20030214050A1 US 29892702 A US29892702 A US 29892702A US 2003214050 A1 US2003214050 A1 US 2003214050A1
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- semiconductor device
- semiconductor chip
- semiconductor
- terminal surface
- die pad
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
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Definitions
- the present invention generally relates to a semiconductor device, and more specifically, it relates to a semiconductor device having a semiconductor chip fixed to a die pad.
- a semiconductor device mounted with a plurality of semiconductor chips is referred to as an MCP (multi chip package).
- MCP multi chip package
- the semiconductor chips must be densely mounted on the same package, in order to implement miniaturization or high-speed operability.
- Japanese Patent Laying-Open No. 2001-127244 discloses such a multi chip semiconductor device.
- FIG. 14 is a plan view showing the multi chip semiconductor device disclosed in Japanese Patent Laying-Open No. 2001-127244.
- FIG. 15 is a sectional view of the multi chip semiconductor device taken along the line XV-XV in FIG. 14.
- the multi chip semiconductor device 101 comprises a plurality of inner leads 103 extending from the outer periphery toward the center and an island 102 formed at the center. Suspended leads 102 a extending from four corners for supporting the island 102 and the suspended leads 102 a and the inner leads 103 are integrated with each other on the outer periphery to form a frame part (not shown). The island 102 , the suspended leads 102 a , the inner leads 103 and the frame part form a lead frame. An opening 107 is formed at the center of the island 102 .
- An upper chip 106 is provided to bridge the opening 107 .
- a lower chip 105 is provided to be stored in the opening 107 .
- the upper and lower chips 106 and 105 are so provided as to set active element surfaces 106 a and 105 a thereof in the same direction. Bonding wires 104 electrically connect the active element surfaces 106 a and 105 a of the upper and lower chips 106 and 105 and the inner leads 103 with each other.
- the upper chip 106 widely covers the active element surface 105 a of the lower chip 105 .
- the active element surface 105 a of the lower chip 105 therefore, only regions 105 b not overlapping with the upper chip 106 can be connected with the inner leads 103 through the bonding wires 104 . Bonding of the multi chip semiconductor device 101 cannot be freely designed but interconnection of the bonding wires 104 may be complicated due to such limitation.
- the upper and lower chips 106 and 105 In order to mount semiconductor chips on the multi chip semiconductor device 101 , the upper and lower chips 106 and 105 must be so shaped or superposed as to leave the regions 105 b not overlapping with the upper chip 106 on the active element surface 105 a of the lower chip 105 .
- the upper and lower chips 106 and 105 are formed to have rectangular surfaces and so provided on the island 102 that the long sides of the rectangular surfaces are orthogonal to each other.
- design of the semiconductor device 101 is remarkably limited.
- an object of the present invention is to provide a semiconductor device, having a high degree of freedom in design, mounted with semiconductor chips in high density.
- the semiconductor device comprises a die pad having an opening, a first semiconductor chip located in the opening and a second semiconductor chip.
- the first semiconductor chip has a first surface forming a terminal surface and a second surface positioned opposite to the first surface.
- the second semiconductor chip has a third surface facing the second surface and the die pad and a fourth surface, positioned opposite to the third surface, forming a terminal surface.
- the first and second semiconductor chips are so provided on the die pad as to direct the first and fourth surfaces forming terminal surfaces opposite to each other, whereby the terminal surfaces do not overlap with the first or second semiconductor chip. Therefore, the first and second semiconductor chips can be bonded to each other along the overall first and fourth surfaces forming terminal surfaces.
- the terminal surfaces not overlapping with the first or second semiconductor chip are not narrowed to restrict the bonding design.
- the first and the second semiconductor chips can be shaped or combined with no limitation resulting from provision of the terminal surfaces.
- the die pad has the opening for locating the first semiconductor chip therein, whereby the total height of the semiconductor device can be reduced due to the overlap of the thicknesses of the opening of the die pad and the first semiconductor chip.
- the semiconductor device further comprises a bonding wire connected to the first and fourth surfaces, a lead terminal connected to the bonding wire and a resin member provided to cover the first and second semiconductor chips, part of the lead terminal, the bonding wire and the die pad.
- the first and second semiconductor chips are provided on the die pad and the bonding wire is connected to the lead terminal formed independently of the die pad, whereby heat generated in a bonding step can be efficiently radiated from the semiconductor chips.
- the first and second semiconductor chips mounted on the die pad are improved in torsional strength in mounting.
- the bonding wire employed for connecting the first or second semiconductor chip and the lead terminal with each other can absorb an error in the fixed position of the semiconductor chip. Therefore, the degree of freedom in design of the fixed position of the semiconductor chip can be improved.
- FIG. 1 is a sectional view showing a semiconductor device according to a first embodiment of the present invention
- FIGS. 2, 8 and 9 are perspective views and FIGS. 3 to 7 are sectional views showing steps of a method of fabricating the semiconductor device shown in FIG. 1 respectively;
- FIG. 10 is a sectional view showing a semiconductor device according to a second embodiment of the present invention.
- FIG. 11 is a sectional view showing a semiconductor device according to a third embodiment of the present invention.
- FIG. 12 is a sectional view showing a semiconductor device according to a fourth embodiment of the present invention.
- FIG. 13 is a sectional view showing a semiconductor device according to a fifth embodiment of the present invention.
- FIG. 14 is a plan view showing a multi chip semiconductor device disclosed in Japanese Patent Laying-Open No. 2001-127244.
- FIG. 15 is a sectional view of the multi chip semiconductor device taken along the line XV-XV in FIG. 14.
- FIGS. 1 to 13 Embodiments of the present invention are now described with reference to FIGS. 1 to 13 .
- a semiconductor device 1 according to a first embodiment of the present invention comprises a die pad 5 , semiconductor chips 21 and 31 , lead terminals 3 , bonding wires 41 and a sealing resin member 51 .
- the die pad 5 and the lead terminals 3 are formed at prescribed spaces.
- An opening 6 is formed at the center of the die pad 5 .
- the opening 6 having a rectangular sectional shape, is sized to be capable of storing the semiconductor chip 21 .
- the opening 6 may have a square or polygonal sectional shape in response to the sectional shape of the semiconductor chip 21 .
- the semiconductor chip 31 has a terminal surface 31 b and a non-terminal surface 31 a formed opposite thereto.
- the semiconductor chip 31 is provided through a bonding agent 22 so that the non-terminal surface 31 a faces a first surface of the die pad 5 .
- the semiconductor chip 21 has a terminal surface 21 a and a non-terminal surface 21 b formed opposite thereto.
- the semiconductor chip 21 is provided through the bonding agent 22 so that the non-terminal surface 21 b faces the non-terminal surface 31 a of the semiconductor chip 31 .
- the semiconductor chip 21 is located in the opening 6 formed in the die pad 5 .
- the semiconductor chip 21 is a flash memory, for example, and the semiconductor chip 31 is a CPU (central processing unit), for example.
- the bonding agent 22 is prepared from a bonding film or bonding paste.
- a plurality of bonding wires 41 electrically connect the terminal surface 21 a of the semiconductor chip 21 and first surfaces of the lead terminals 3 with each other.
- a plurality of bonding wires 41 electrically connect the terminal surface 31 b of the semiconductor chip 31 and second surfaces of the lead terminals 3 with each other.
- the sealing resin member 51 is provided to cover the semiconductor chips 21 and 31 , the die pad 5 , the bonding wires 41 and parts of the lead terminals 3 .
- the parts of the lead terminals 3 covered with the sealing resin member 51 include all portions bonded to the bonding wires 41 .
- the sealing resin member 51 is prepared by blending epoxy resin, silicone resin or silicone-epoxy hybrid resin with an additive such as a hardener or filler at need.
- novolac epoxy resin, novolac phenol resin or the like is representatively employed as the epoxy resin.
- the silicone-epoxy hybrid resin is prepared by hybridizing epoxy resin and silicone resin with each other at a prescribed ratio.
- the die pad 5 and the lead terminals 3 are formed with prescribed steps.
- steps between the terminal surface 21 a and the first surfaces of the lead terminals 3 and those between the terminal surface 31 b and the second surfaces of the lead terminals 3 are equal to each other.
- the sealing resin member 51 can have a uniform thickness with reference to the first and second surfaces of the lead terminals 3 .
- steps arbitrarily decided in response to the shape of the bent lead terminals 3 or the thicknesses of the semiconductor chips 21 and 31 , are not restricted to those shown in FIG. 1. The steps may not be provided regardless of the object thereof.
- the semiconductor device 1 comprises the die pad 5 having the opening 6 , the semiconductor chip 21 serving as the first semiconductor chip located in the opening 6 and the semiconductor chip 31 serving as the second semiconductor chip.
- the semiconductor chip 21 has the terminal surface 21 a serving as the first surface forming a terminal surface and the non-terminal surface 21 b serving as the second surface positioned opposite to the terminal surface 21 a .
- the semiconductor chip 31 has the non-terminal surface 31 a serving as the third surface facing the non-terminal surface 21 b and the die pad 5 and the terminal surface 31 b serving as the fourth surface, positioned opposite to the non-terminal surface 31 a , forming a terminal surface.
- the semiconductor device 1 further comprises the bonding wires 41 connected to the terminal surfaces 21 a and 31 b , the lead terminals 3 connected to the bonding wires 41 and the sealing resin member 51 .
- the sealing resin member 51 is provided to cover the semiconductor chips 21 and 31 , parts of the lead terminals 3 , the bonding wires 41 and the die pad 5 .
- the sealing resin member 51 contains at least single resin selected from a group consisting of epoxy resin, silicone resin and silicone-epoxy hybrid resin.
- a plate 7 of an iron-nickel (Fe-Ni) alloy or a copper (Cu) alloy is prepared.
- the alloy plate 7 is pressed or etched and worked into a prescribed shape.
- the worked alloy plate 7 comprises a lead frame 4 , formed by a frame 2 and the lead terminals 3 , and the die pad 5 .
- Die pad support portions 5 a extending from four corners of the frame 2 support the die pad 5 .
- the opening 6 having the rectangular sectional shape is formed at the center of the die pad 5 .
- the opening 6 is sized to be capable of storing the semiconductor chip 21 .
- the plurality of lead terminals 3 are formed to extend from the frame 2 toward the peripheral portions of the die pad 5 .
- FIG. 3 is a sectional view taken along the line III-III in FIG. 2. Referring to FIG. 3, the die pad 5 and the lead terminals 3 are formed at spaces with the prescribed steps.
- the bonding agent 22 is applied to the non-terminal surface 31 a of the semiconductor chip 31 .
- the semiconductor chip 31 is fixed to the die pad 5 to bridge the opening 6 formed in the die pad 5 .
- the bonding agent 22 is applied also to the non-terminal surface 21 b of the semiconductor chip 21 .
- the semiconductor chip 21 is fixed to the non-terminal surface 31 a of the semiconductor chip 31 to be located in the opening 6 .
- the bonding agent 22 is prepared from a bonding film, the semiconductor chip 21 can be fixed to the semiconductor chip 31 without applying the bonding agent 22 to the non-terminal surface 21 b of the semiconductor chip 21 .
- the bonding wires 41 electrically connect the terminal surface 21 a of the semiconductor chip 21 and the first surfaces of the lead terminals 3 with each other by ultrasonic bonding or the like.
- the bonding wires 41 are prepared from gold (Au) wires.
- the bonding wires 41 electrically connect the terminal surface 31 b of the semiconductor chip 31 and the second surfaces of the lead terminals 3 with each other.
- the semiconductor chips 21 and 31 , the die pad 5 , the bonding wires 41 and parts of the lead terminals 3 are covered with the sealing resin member 51 .
- the sheath is plated with tin (Sn).
- the lead terminals 3 are improved in oxidation resistance and corrosion resistance due to the plating.
- FIG. 1 is a sectional view taken along the line I-I in FIG. 9. The semiconductor device 1 is completed through the aforementioned steps.
- the terminal surfaces 21 a and 31 b not overlapping with the semiconductor chip 21 and 31 are not narrowed to restrict wire-bondable regions. Therefore, bonding design is not restricted, and the bonding wires 41 can be prevented from complicated interconnection. Further, the semiconductor chips 21 and 31 can be shaped or superposed with no limitation resulting from provision of the terminal surfaces 21 a and 31 b.
- the semiconductor chip 21 is located in the opening 6 formed in the die pad 5 , whereby the total height of the semiconductor device 1 can be reduced due to the thickness of the portion where the semiconductor chip 21 and the die pad 5 overlap with each other.
- PDA personal digital assistant
- the thickness of a built-in semiconductor device must be reduced.
- simple reduction of the thickness of each component of a semiconductor chip or the like leads to limitation in fabrication.
- a die pad is provided to fix semiconductor chips in intermediate steps of fabricating a semiconductor device. Therefore, non-terminal surfaces of the semiconductor chips may not be entirely fixed to the die pad but the former may be partially fixed to the latter. According to the first embodiment, therefore, the opening 6 is formed in the die pad 5 for locating the semiconductor chip 21 therein, thereby reducing the thickness of the semiconductor device 1 .
- the bonding agent 22 may not be re-applied to the semiconductor chip 21 for fixing the same, whereby the fabrication steps can be simplified and the quantity of the bonding agent 22 can be reduced.
- the semiconductor chips 21 and 31 are fixed to the die pad 5 separated from the lead terminals 3 , whereby heat generated in the step of connecting the semiconductor chips 21 and 31 with the lead terminals 3 with the bonding wires 41 can be efficiently radiated.
- the semiconductor chips 21 and 31 can be prevented from damage resulting from heat.
- the bonding wires 41 employed for connecting the semiconductor chips 21 and 31 with the lead terminals 3 can absorb position errors of the semiconductor chips 21 and 31 . Therefore, the semiconductor chips 21 and 31 can be prevented from damage caused in the bonding step due to fabrication errors.
- the resin such as epoxy resin contained in the sealing resin member 51 having excellent electric insulation, adhesiveness, chemical resistance or heat resistance can prevent the semiconductor chips 21 and 31 covered therewith from physical or chemical contact with an external device.
- a semiconductor device 60 according to a second embodiment of the present invention further comprises a passive element 61 in addition to components similar to those of the semiconductor device 1 according to the first embodiment.
- This passive element 61 is provided on a terminal surface 21 a of a semiconductor chip 21 .
- the passive element 61 is a resistive element, a capacitive element or an inductive element.
- the semiconductor device 60 according to the second embodiment of the present invention further comprises the passive element 61 provided on the terminal surface 21 a.
- the semiconductor device 60 having the aforementioned structure can attain effects similar to those of the semiconductor device 1 according to the first embodiment.
- a prescribed circuit structure can be obtained by connecting the passive element 61 to the terminal surface 21 a of the semiconductor chip 21 while setting the resistance, capacitance or inductance thereof to a prescribed value.
- a semiconductor device 70 according to a third embodiment of the present invention further comprises a transistor 71 in addition to components similar to those of the semiconductor device 1 according to the first embodiment.
- the transistor 71 is provided on a terminal surface 21 a of a semiconductor chip 21 .
- a bonding wire 72 electrically connects a lead terminal 71 a of the transistor 71 with a lead terminal 3 .
- the semiconductor device 70 according to the third embodiment of the present invention further comprises the transistor 71 provided on the terminal surface 21 a and electrically connected with the lead terminal 3 .
- the semiconductor device 70 having the aforementioned structure can compensate for insufficient output current of the semiconductor chip 21 in addition to effects similar to those of the semiconductor device 1 according to the first embodiment.
- a semiconductor device 80 according to a fourth embodiment of the present invention further comprises a semiconductor chip 81 in addition to components similar to those of the semiconductor device 1 according to the first embodiment.
- the semiconductor chip 81 is provided on a terminal surface 21 a of a semiconductor chip 21 through a metal bump 82 .
- the semiconductor chip 81 has a non-terminal surface 81 a formed opposite to a terminal surface 81 b .
- the semiconductor chip 81 is so provided that the terminal surface 81 b faces the terminal surface 21 a of the semiconductor chip 21 .
- a sealing resin member 51 is provided to cover the semiconductor chips 21 , 31 and 81 , a die pad 5 , bonding wires 41 and parts of lead terminals 3 .
- the semiconductor device 80 further comprises the semiconductor chip 81 serving as the third semiconductor chip mounted on the terminal surface 21 a.
- the semiconductor chips 21 , 31 and 81 can be further densely mounted in the same package, in addition to effects similar to those of the semiconductor device 1 according to the first embodiment, and miniaturization or high-speed operability of the semiconductor device 80 can be implemented.
- a semiconductor device 90 according to a fifth embodiment of the present invention is different from the semiconductor device 80 according to the fourth embodiment in the mode of a sealing resin member 51 .
- a semiconductor chip 81 is provided on a terminal surface 21 a of a semiconductor chip 21 through a metal bump 82 .
- the sealing resin member 51 covers portions of the semiconductor chip 81 other than an exposed non-terminal surface 81 a , the semiconductor chip 21 , a semiconductor chip 31 , a die pad 5 , bonding wires 41 and parts of lead terminals 3 .
- the semiconductor device 90 comprises the bonding wires 41 connected to the terminal surface 21 a and a terminal surface 31 b , the lead terminals 3 connected to the bonding wires 41 and the sealing resin member 51 provided to cover the semiconductor chips 21 and 31 , the portions of the semiconductor chip 81 , the parts of the lead terminals 3 , the bonding wires 41 and the die pad 5 .
- the semiconductor chip 81 includes a terminal surface 81 b facing the terminal surface 21 a and the non-terminal surface 81 a , formed with no terminal, provided independently of the terminal surface 81 b .
- the non-terminal surface 81 a of the semiconductor chip 81 is exposed from the sealing resin member 51 .
- the semiconductor device 90 having the aforementioned structure can attain effects similar to those of the semiconductor device 80 according to the fourth embodiment.
- the non-terminal surface 81 a of the semiconductor chip 81 is exposed from the sealing resin member 51 , whereby the total height of the semiconductor device 90 can be further reduced.
Abstract
Description
- 1. Field of the Invention
- The present invention generally relates to a semiconductor device, and more specifically, it relates to a semiconductor device having a semiconductor chip fixed to a die pad.
- 2. Description of the Background Art
- A semiconductor device mounted with a plurality of semiconductor chips is referred to as an MCP (multi chip package). In the MCP, the semiconductor chips must be densely mounted on the same package, in order to implement miniaturization or high-speed operability. Japanese Patent Laying-Open No. 2001-127244 discloses such a multi chip semiconductor device.
- FIG. 14 is a plan view showing the multi chip semiconductor device disclosed in Japanese Patent Laying-Open No. 2001-127244. FIG. 15 is a sectional view of the multi chip semiconductor device taken along the line XV-XV in FIG. 14.
- Referring to FIGS. 14 and 15, the multi
chip semiconductor device 101 comprises a plurality ofinner leads 103 extending from the outer periphery toward the center and anisland 102 formed at the center. Suspendedleads 102 a extending from four corners for supporting theisland 102 and the suspended leads 102 a and theinner leads 103 are integrated with each other on the outer periphery to form a frame part (not shown). Theisland 102, the suspended leads 102 a, the inner leads 103 and the frame part form a lead frame. Anopening 107 is formed at the center of theisland 102. - An
upper chip 106 is provided to bridge theopening 107. Alower chip 105 is provided to be stored in theopening 107. The upper andlower chips active element surfaces Bonding wires 104 electrically connect theactive element surfaces lower chips inner leads 103 with each other. - In the aforementioned multi
chip semiconductor device 101, theupper chip 106 widely covers theactive element surface 105 a of thelower chip 105. In theactive element surface 105 a of thelower chip 105, therefore, onlyregions 105 b not overlapping with theupper chip 106 can be connected with theinner leads 103 through thebonding wires 104. Bonding of the multichip semiconductor device 101 cannot be freely designed but interconnection of thebonding wires 104 may be complicated due to such limitation. - In order to mount semiconductor chips on the multi
chip semiconductor device 101, the upper andlower chips regions 105 b not overlapping with theupper chip 106 on theactive element surface 105 a of thelower chip 105. In the multichip semiconductor device 101, therefore, the upper andlower chips island 102 that the long sides of the rectangular surfaces are orthogonal to each other. When the upper andlower chips semiconductor device 101 is remarkably limited. - In order to solve the aforementioned problem, an object of the present invention is to provide a semiconductor device, having a high degree of freedom in design, mounted with semiconductor chips in high density.
- The semiconductor device according to the present invention comprises a die pad having an opening, a first semiconductor chip located in the opening and a second semiconductor chip. The first semiconductor chip has a first surface forming a terminal surface and a second surface positioned opposite to the first surface. The second semiconductor chip has a third surface facing the second surface and the die pad and a fourth surface, positioned opposite to the third surface, forming a terminal surface.
- According to the semiconductor device having the aforementioned structure, the first and second semiconductor chips are so provided on the die pad as to direct the first and fourth surfaces forming terminal surfaces opposite to each other, whereby the terminal surfaces do not overlap with the first or second semiconductor chip. Therefore, the first and second semiconductor chips can be bonded to each other along the overall first and fourth surfaces forming terminal surfaces. The terminal surfaces not overlapping with the first or second semiconductor chip are not narrowed to restrict the bonding design. Further, the first and the second semiconductor chips can be shaped or combined with no limitation resulting from provision of the terminal surfaces. In addition, the die pad has the opening for locating the first semiconductor chip therein, whereby the total height of the semiconductor device can be reduced due to the overlap of the thicknesses of the opening of the die pad and the first semiconductor chip.
- Preferably, the semiconductor device further comprises a bonding wire connected to the first and fourth surfaces, a lead terminal connected to the bonding wire and a resin member provided to cover the first and second semiconductor chips, part of the lead terminal, the bonding wire and the die pad. According to the semiconductor device having this structure, the first and second semiconductor chips are provided on the die pad and the bonding wire is connected to the lead terminal formed independently of the die pad, whereby heat generated in a bonding step can be efficiently radiated from the semiconductor chips. Further, the first and second semiconductor chips mounted on the die pad are improved in torsional strength in mounting. In addition, the bonding wire employed for connecting the first or second semiconductor chip and the lead terminal with each other can absorb an error in the fixed position of the semiconductor chip. Therefore, the degree of freedom in design of the fixed position of the semiconductor chip can be improved.
- The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
- FIG. 1 is a sectional view showing a semiconductor device according to a first embodiment of the present invention;
- FIGS. 2, 8 and9 are perspective views and FIGS. 3 to 7 are sectional views showing steps of a method of fabricating the semiconductor device shown in FIG. 1 respectively;
- FIG. 10 is a sectional view showing a semiconductor device according to a second embodiment of the present invention;
- FIG. 11 is a sectional view showing a semiconductor device according to a third embodiment of the present invention;
- FIG. 12 is a sectional view showing a semiconductor device according to a fourth embodiment of the present invention;
- FIG. 13 is a sectional view showing a semiconductor device according to a fifth embodiment of the present invention;
- FIG. 14 is a plan view showing a multi chip semiconductor device disclosed in Japanese Patent Laying-Open No. 2001-127244; and
- FIG. 15 is a sectional view of the multi chip semiconductor device taken along the line XV-XV in FIG. 14.
- Embodiments of the present invention are now described with reference to FIGS.1 to 13.
- (First Embodiment)
- Referring to FIG. 1, a
semiconductor device 1 according to a first embodiment of the present invention comprises adie pad 5,semiconductor chips lead terminals 3,bonding wires 41 and asealing resin member 51. The diepad 5 and thelead terminals 3 are formed at prescribed spaces. Anopening 6 is formed at the center of the diepad 5. The opening 6, having a rectangular sectional shape, is sized to be capable of storing thesemiconductor chip 21. Alternatively, the opening 6 may have a square or polygonal sectional shape in response to the sectional shape of thesemiconductor chip 21. Thesemiconductor chip 31 has aterminal surface 31 b and anon-terminal surface 31 a formed opposite thereto. Thesemiconductor chip 31 is provided through abonding agent 22 so that thenon-terminal surface 31 a faces a first surface of thedie pad 5. Thesemiconductor chip 21 has aterminal surface 21 a and anon-terminal surface 21 b formed opposite thereto. Thesemiconductor chip 21 is provided through thebonding agent 22 so that thenon-terminal surface 21 b faces thenon-terminal surface 31 a of thesemiconductor chip 31. Thesemiconductor chip 21 is located in theopening 6 formed in thedie pad 5. Thesemiconductor chip 21 is a flash memory, for example, and thesemiconductor chip 31 is a CPU (central processing unit), for example. Thebonding agent 22 is prepared from a bonding film or bonding paste. - A plurality of
bonding wires 41 electrically connect theterminal surface 21 a of thesemiconductor chip 21 and first surfaces of thelead terminals 3 with each other. A plurality ofbonding wires 41 electrically connect theterminal surface 31 b of thesemiconductor chip 31 and second surfaces of thelead terminals 3 with each other. The sealingresin member 51 is provided to cover the semiconductor chips 21 and 31, thedie pad 5, thebonding wires 41 and parts of thelead terminals 3. The parts of thelead terminals 3 covered with the sealingresin member 51 include all portions bonded to thebonding wires 41. The sealingresin member 51 is prepared by blending epoxy resin, silicone resin or silicone-epoxy hybrid resin with an additive such as a hardener or filler at need. For example, novolac epoxy resin, novolac phenol resin or the like is representatively employed as the epoxy resin. The silicone-epoxy hybrid resin is prepared by hybridizing epoxy resin and silicone resin with each other at a prescribed ratio. - The
die pad 5 and thelead terminals 3 are formed with prescribed steps. When the semiconductor chips 21 and 31 are fixed to thedie pad 5, therefore, steps between theterminal surface 21 a and the first surfaces of thelead terminals 3 and those between theterminal surface 31 b and the second surfaces of thelead terminals 3 are equal to each other. Thus, the sealingresin member 51 can have a uniform thickness with reference to the first and second surfaces of thelead terminals 3. However, these steps, arbitrarily decided in response to the shape of thebent lead terminals 3 or the thicknesses of the semiconductor chips 21 and 31, are not restricted to those shown in FIG. 1. The steps may not be provided regardless of the object thereof. - The
semiconductor device 1 according to the first embodiment of the present invention comprises thedie pad 5 having theopening 6, thesemiconductor chip 21 serving as the first semiconductor chip located in theopening 6 and thesemiconductor chip 31 serving as the second semiconductor chip. Thesemiconductor chip 21 has theterminal surface 21 a serving as the first surface forming a terminal surface and thenon-terminal surface 21 b serving as the second surface positioned opposite to theterminal surface 21 a. Thesemiconductor chip 31 has thenon-terminal surface 31 a serving as the third surface facing thenon-terminal surface 21 b and thedie pad 5 and theterminal surface 31 b serving as the fourth surface, positioned opposite to thenon-terminal surface 31 a, forming a terminal surface. - The
semiconductor device 1 further comprises thebonding wires 41 connected to the terminal surfaces 21 a and 31 b, thelead terminals 3 connected to thebonding wires 41 and the sealingresin member 51. The sealingresin member 51 is provided to cover the semiconductor chips 21 and 31, parts of thelead terminals 3, thebonding wires 41 and thedie pad 5. - The sealing
resin member 51 contains at least single resin selected from a group consisting of epoxy resin, silicone resin and silicone-epoxy hybrid resin. - A method of fabricating the
semiconductor device 1 is now described. - Referring to FIG. 2, a plate7 of an iron-nickel (Fe-Ni) alloy or a copper (Cu) alloy is prepared. The alloy plate 7 is pressed or etched and worked into a prescribed shape. The worked alloy plate 7 comprises a
lead frame 4, formed by aframe 2 and thelead terminals 3, and thedie pad 5. Diepad support portions 5 a extending from four corners of theframe 2 support thedie pad 5. Theopening 6 having the rectangular sectional shape is formed at the center of thedie pad 5. Theopening 6 is sized to be capable of storing thesemiconductor chip 21. The plurality oflead terminals 3 are formed to extend from theframe 2 toward the peripheral portions of thedie pad 5. - FIG. 3 is a sectional view taken along the line III-III in FIG. 2. Referring to FIG. 3, the
die pad 5 and thelead terminals 3 are formed at spaces with the prescribed steps. - Referring to FIG. 4, the
bonding agent 22 is applied to thenon-terminal surface 31 a of thesemiconductor chip 31. Thesemiconductor chip 31 is fixed to thedie pad 5 to bridge theopening 6 formed in thedie pad 5. - Referring to FIG. 5, the
bonding agent 22 is applied also to thenon-terminal surface 21 b of thesemiconductor chip 21. Thesemiconductor chip 21 is fixed to thenon-terminal surface 31 a of thesemiconductor chip 31 to be located in theopening 6. When thebonding agent 22 is prepared from a bonding film, thesemiconductor chip 21 can be fixed to thesemiconductor chip 31 without applying thebonding agent 22 to thenon-terminal surface 21 b of thesemiconductor chip 21. - Referring to FIG. 6, the
bonding wires 41 electrically connect theterminal surface 21 a of thesemiconductor chip 21 and the first surfaces of thelead terminals 3 with each other by ultrasonic bonding or the like. Thebonding wires 41 are prepared from gold (Au) wires. Similarly, thebonding wires 41 electrically connect theterminal surface 31 b of thesemiconductor chip 31 and the second surfaces of thelead terminals 3 with each other. - Referring to FIG. 7, the semiconductor chips21 and 31, the
die pad 5, thebonding wires 41 and parts of thelead terminals 3 are covered with the sealingresin member 51. - Referring to FIG. 8, the sheath is plated with tin (Sn). The
lead terminals 3 are improved in oxidation resistance and corrosion resistance due to the plating. - Referring to FIG. 9, the
lead terminals 3 are cut out from theframe 2. The diepad support portions 5 a provided on the four corners are cut out from theframe 2. Thelead terminals 3 are bent in prescribed directions. FIG. 1 is a sectional view taken along the line I-I in FIG. 9. Thesemiconductor device 1 is completed through the aforementioned steps. - According to the
semiconductor device 1 having the aforementioned structure, the terminal surfaces 21 a and 31 b not overlapping with thesemiconductor chip bonding wires 41 can be prevented from complicated interconnection. Further, the semiconductor chips 21 and 31 can be shaped or superposed with no limitation resulting from provision of the terminal surfaces 21 a and 31 b. - The
semiconductor chip 21 is located in theopening 6 formed in thedie pad 5, whereby the total height of thesemiconductor device 1 can be reduced due to the thickness of the portion where thesemiconductor chip 21 and thedie pad 5 overlap with each other. Particularly in the field of a portable telephone, a personal digital assistant (PDA) or a notebook computer, the thickness of a built-in semiconductor device must be reduced. However, simple reduction of the thickness of each component of a semiconductor chip or the like leads to limitation in fabrication. A die pad is provided to fix semiconductor chips in intermediate steps of fabricating a semiconductor device. Therefore, non-terminal surfaces of the semiconductor chips may not be entirely fixed to the die pad but the former may be partially fixed to the latter. According to the first embodiment, therefore, theopening 6 is formed in thedie pad 5 for locating thesemiconductor chip 21 therein, thereby reducing the thickness of thesemiconductor device 1. - When prepared from a bonding film, the
bonding agent 22 may not be re-applied to thesemiconductor chip 21 for fixing the same, whereby the fabrication steps can be simplified and the quantity of thebonding agent 22 can be reduced. - Further, the semiconductor chips21 and 31 are fixed to the
die pad 5 separated from thelead terminals 3, whereby heat generated in the step of connecting the semiconductor chips 21 and 31 with thelead terminals 3 with thebonding wires 41 can be efficiently radiated. Thus, the semiconductor chips 21 and 31 can be prevented from damage resulting from heat. In addition, thebonding wires 41 employed for connecting the semiconductor chips 21 and 31 with thelead terminals 3 can absorb position errors of the semiconductor chips 21 and 31. Therefore, the semiconductor chips 21 and 31 can be prevented from damage caused in the bonding step due to fabrication errors. - Further, the resin such as epoxy resin contained in the sealing
resin member 51 having excellent electric insulation, adhesiveness, chemical resistance or heat resistance can prevent the semiconductor chips 21 and 31 covered therewith from physical or chemical contact with an external device. - (Second Embodiment)
- Referring to FIG. 10, a
semiconductor device 60 according to a second embodiment of the present invention further comprises apassive element 61 in addition to components similar to those of thesemiconductor device 1 according to the first embodiment. Thispassive element 61 is provided on aterminal surface 21 a of asemiconductor chip 21. Thepassive element 61 is a resistive element, a capacitive element or an inductive element. - The
semiconductor device 60 according to the second embodiment of the present invention further comprises thepassive element 61 provided on theterminal surface 21 a. - The
semiconductor device 60 having the aforementioned structure can attain effects similar to those of thesemiconductor device 1 according to the first embodiment. A prescribed circuit structure can be obtained by connecting thepassive element 61 to theterminal surface 21 a of thesemiconductor chip 21 while setting the resistance, capacitance or inductance thereof to a prescribed value. - (Third Embodiment)
- Referring to FIG. 11, a
semiconductor device 70 according to a third embodiment of the present invention further comprises atransistor 71 in addition to components similar to those of thesemiconductor device 1 according to the first embodiment. Thetransistor 71 is provided on aterminal surface 21 a of asemiconductor chip 21. Abonding wire 72 electrically connects a lead terminal 71 a of thetransistor 71 with alead terminal 3. - The
semiconductor device 70 according to the third embodiment of the present invention further comprises thetransistor 71 provided on theterminal surface 21 a and electrically connected with thelead terminal 3. - The
semiconductor device 70 having the aforementioned structure can compensate for insufficient output current of thesemiconductor chip 21 in addition to effects similar to those of thesemiconductor device 1 according to the first embodiment. - (Fourth Embodiment)
- Referring to FIG. 12, a
semiconductor device 80 according to a fourth embodiment of the present invention further comprises asemiconductor chip 81 in addition to components similar to those of thesemiconductor device 1 according to the first embodiment. Thesemiconductor chip 81 is provided on aterminal surface 21 a of asemiconductor chip 21 through ametal bump 82. Thesemiconductor chip 81 has anon-terminal surface 81 a formed opposite to aterminal surface 81 b. Thesemiconductor chip 81 is so provided that theterminal surface 81 b faces theterminal surface 21 a of thesemiconductor chip 21. A sealingresin member 51 is provided to cover the semiconductor chips 21, 31 and 81, adie pad 5,bonding wires 41 and parts oflead terminals 3. - The
semiconductor device 80 according to the fourth embodiment of the present invention further comprises thesemiconductor chip 81 serving as the third semiconductor chip mounted on theterminal surface 21 a. - According to the
semiconductor device 80 having the aforementioned structure, the semiconductor chips 21, 31 and 81 can be further densely mounted in the same package, in addition to effects similar to those of thesemiconductor device 1 according to the first embodiment, and miniaturization or high-speed operability of thesemiconductor device 80 can be implemented. - (Fifth Embodiment)
- Referring to FIG. 13, a
semiconductor device 90 according to a fifth embodiment of the present invention is different from thesemiconductor device 80 according to the fourth embodiment in the mode of a sealingresin member 51. - A
semiconductor chip 81 is provided on aterminal surface 21 a of asemiconductor chip 21 through ametal bump 82. The sealingresin member 51 covers portions of thesemiconductor chip 81 other than an exposednon-terminal surface 81 a, thesemiconductor chip 21, asemiconductor chip 31, adie pad 5,bonding wires 41 and parts oflead terminals 3. - The
semiconductor device 90 according to the fifth embodiment of the present invention comprises thebonding wires 41 connected to theterminal surface 21 a and aterminal surface 31 b, thelead terminals 3 connected to thebonding wires 41 and the sealingresin member 51 provided to cover the semiconductor chips 21 and 31, the portions of thesemiconductor chip 81, the parts of thelead terminals 3, thebonding wires 41 and thedie pad 5. Thesemiconductor chip 81 includes aterminal surface 81 b facing theterminal surface 21 a and thenon-terminal surface 81 a, formed with no terminal, provided independently of theterminal surface 81 b. Thenon-terminal surface 81 a of thesemiconductor chip 81 is exposed from the sealingresin member 51. - The
semiconductor device 90 having the aforementioned structure can attain effects similar to those of thesemiconductor device 80 according to the fourth embodiment. Thenon-terminal surface 81 a of thesemiconductor chip 81 is exposed from the sealingresin member 51, whereby the total height of thesemiconductor device 90 can be further reduced. - Although the present invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the spirit and scope of the present invention being limited only by the terms of the appended claims.
Claims (8)
Applications Claiming Priority (3)
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JP2002-142739(P) | 2002-05-17 | ||
JP2002142739A JP2003332522A (en) | 2002-05-17 | 2002-05-17 | Semiconductor device |
JP2002-142739 | 2002-05-17 |
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US20030214050A1 true US20030214050A1 (en) | 2003-11-20 |
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US20100276806A1 (en) * | 2003-04-11 | 2010-11-04 | Dai Nippon Printing Co., Ltd. | Plastic package and method of fabricating the same |
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US7307502B2 (en) | 2003-07-16 | 2007-12-11 | Marvell World Trade Ltd. | Power inductor with reduced DC current saturation |
US7023313B2 (en) | 2003-07-16 | 2006-04-04 | Marvell World Trade Ltd. | Power inductor with reduced DC current saturation |
US7489219B2 (en) | 2003-07-16 | 2009-02-10 | Marvell World Trade Ltd. | Power inductor with reduced DC current saturation |
US8324872B2 (en) | 2004-03-26 | 2012-12-04 | Marvell World Trade, Ltd. | Voltage regulator with coupled inductors having high coefficient of coupling |
JP4668729B2 (en) * | 2005-08-17 | 2011-04-13 | ルネサスエレクトロニクス株式会社 | Manufacturing method of semiconductor device |
US20070200210A1 (en) * | 2006-02-28 | 2007-08-30 | Broadcom Corporation | Methods and apparatus for improved thermal performance and electromagnetic interference (EMI) shielding in integrated circuit (IC) packages |
US7535110B2 (en) * | 2006-06-15 | 2009-05-19 | Marvell World Trade Ltd. | Stack die packages |
JP2009252815A (en) * | 2008-04-02 | 2009-10-29 | Toppan Printing Co Ltd | Composite lead frame structure and semiconductor device |
WO2009143492A1 (en) * | 2008-05-23 | 2009-11-26 | Statek Corporation | Piezoelectric resonator |
CN103489792B (en) * | 2013-08-06 | 2016-02-03 | 江苏长电科技股份有限公司 | First be honored as a queen and lose three-dimensional systematic flip chip encapsulation structure and process |
CN103390563B (en) * | 2013-08-06 | 2016-03-30 | 江苏长电科技股份有限公司 | Erosion flip-chip of being first honored as a queen three-dimensional systematic metal circuit board structure &processes method |
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JP3266815B2 (en) * | 1996-11-26 | 2002-03-18 | シャープ株式会社 | Method for manufacturing semiconductor integrated circuit device |
US6441495B1 (en) * | 1997-10-06 | 2002-08-27 | Rohm Co., Ltd. | Semiconductor device of stacked chips |
JPH11330347A (en) | 1998-05-20 | 1999-11-30 | Rohm Co Ltd | Semiconductor ic |
KR100277438B1 (en) * | 1998-05-28 | 2001-02-01 | 윤종용 | Multi Chip Package |
JP3235589B2 (en) | 1999-03-16 | 2001-12-04 | 日本電気株式会社 | Semiconductor device |
JP2001127244A (en) | 1999-11-01 | 2001-05-11 | Nec Corp | Multichip semiconductor device and method of manufacturing the same |
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2002
- 2002-05-17 JP JP2002142739A patent/JP2003332522A/en active Pending
- 2002-10-21 TW TW091124208A patent/TW563240B/en active
- 2002-11-19 US US10/298,927 patent/US6661091B1/en not_active Expired - Fee Related
- 2002-12-31 DE DE10261462A patent/DE10261462A1/en not_active Ceased
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- 2003-01-24 KR KR10-2003-0004734A patent/KR20030089411A/en not_active Application Discontinuation
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20100276806A1 (en) * | 2003-04-11 | 2010-11-04 | Dai Nippon Printing Co., Ltd. | Plastic package and method of fabricating the same |
US8653647B2 (en) * | 2003-04-11 | 2014-02-18 | Dai Nippon Printing Co., Ltd. | Plastic package and method of fabricating the same |
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US6661091B1 (en) | 2003-12-09 |
DE10261462A1 (en) | 2003-11-27 |
KR20030089411A (en) | 2003-11-21 |
JP2003332522A (en) | 2003-11-21 |
CN1459857A (en) | 2003-12-03 |
TW563240B (en) | 2003-11-21 |
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