TWI234865B - Electrically insulating heat sink and semiconductor package with the heat sink - Google Patents

Electrically insulating heat sink and semiconductor package with the heat sink Download PDF

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Publication number
TWI234865B
TWI234865B TW092116503A TW92116503A TWI234865B TW I234865 B TWI234865 B TW I234865B TW 092116503 A TW092116503 A TW 092116503A TW 92116503 A TW92116503 A TW 92116503A TW I234865 B TWI234865 B TW I234865B
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Taiwan
Prior art keywords
heat
semiconductor package
patent application
dissipating
scope
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TW092116503A
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Chinese (zh)
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TW200501361A (en
Inventor
Chien-Chiah Chen
Chung-Pao Wang
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Siliconware Precision Industries Co Ltd
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Priority to TW092116503A priority Critical patent/TWI234865B/en
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Publication of TWI234865B publication Critical patent/TWI234865B/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

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  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

An electrically insulating heat sink and a semiconductor package with the heat sink are provided. Prior to a molding process, an anti-oxidation layer is formed on a surface of the heat sink primarily made of copper, and then the heat sink is stamped to form a desire shape. A black oxidation process is performed to deposit a non-conductive oxidation layer on a surface, opposite to the surface having the anti-oxidation layer, of the heat sink. After that, an epoxide layer is applied over the non-conductive oxidation layer to form an electrically insulating layer. Besides heat dissipation, the above heat sink, as being incorporated with the semiconductor package, can protect its copper surface from exposure and being oxidized, and eliminate undesirable short circuit with passive components or bonding wires mounted in the semiconductor package, thereby not having to pre-encapsulate the passive components or bonding wires by means of an insulating adhesive used in the prior art, and thus reducing the fabrication costs of the semiconductor package.

Description

1234865 五、發明說明（1) 【發明所屬之技術領域】 本發明係關於一種防止導電之散熱件及具有該散熱件 之半導體封裝結構，更詳而言之，係有關於一種提供半導 體封裝結構可獲得極佳之散熱效果、避免外露表面氧化.且 同時防止被動元件或銲線接觸散熱件而短路之散熱件及具 有該散熱件之半導體封裝結構。 【先前技術】 目前各種形式的封裝產品中，球柵陣列式（B a 1 1 Grid Array; BGA)半導體封裝結構係其中之一，其特徵 在於基板底面上植佈多數以陣列方式排列之銲球，使得相 同單位面積内設有較多之輸入/輸出連接端（I / 0 Connection)，以因應具有高密度電子元件（Electronic Component)及電子電路（Electronic Circuit)之半導 體晶片所需，以符合電子產品對於電性功能與處理速度之 需求。此外，由於可供輸入/輸出連接端使用的面積較 大，使得縮小產品的同時復得保持較大的連接間距 (Interconnection Pitch)，再加上銲球回銲作業時具 有自動對位之能力，相對的在表面黏著對封裝件放置的位 置精度要求較不嚴格，同時又因銲球的共面度要求較寬， 且銲球的接著強度亦較傳統的金屬導線架外引腳為強，故 可導致產品良率提昇。另一方面，因BGA產品所具有之低 電阻、低電感、低渦電電容極低熱阻抗等優良之電氣特 性，使球栅陣列封裝在現今I C產品朝高記憶容量、應答高 速化、低電壓需求、外觀小型化及外引腳高密度化發展之1234865 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a heat-dissipating member for preventing conduction and a semiconductor package structure having the heat-dissipating member. More specifically, it relates to a method for providing a semiconductor package structure. A heat sink with excellent heat dissipation effect, avoiding exposed surface oxidation, and simultaneously preventing a passive component or a bonding wire from contacting the heat sink and short-circuiting, and a semiconductor package structure having the heat sink. [Previous technology] Among the various forms of packaging products, ball grid array (B a 1 1 Grid Array; BGA) semiconductor packaging structure is one of them, which is characterized in that most of the solder balls arranged in an array are arranged on the bottom surface of the substrate. , So that there are more input / output connections (I / 0 Connection) in the same unit area, in order to meet the needs of semiconductor chips with high-density electronic components (Electronic Component) and electronic circuits (Electronic Circuit) to meet the electronics Product requirements for electrical functionality and processing speed. In addition, due to the large area available for the input / output connection, the product can be reduced while maintaining a large connection pitch (Interconnection Pitch), plus the ability of automatic alignment during solder ball reflow operations, Relatively, the accuracy of the position of the package placed on the surface is less stringent. At the same time, the coplanarity of the solder ball is wider, and the bonding strength of the solder ball is stronger than the outer lead of the traditional metal lead frame. Can lead to improved product yield. On the other hand, due to the excellent electrical characteristics of BGA products such as low resistance, low inductance, low eddy capacitance, and extremely low thermal impedance, ball grid array packages are now being used in IC products toward high memory capacity, high speed response, and low voltage. Demand, appearance miniaturization, and high-density development of external pins

17294 矽品.ptd 第7頁 1234865 五、發明說明 趨勢下， 惟半 下，迅速 題。請參 使該球柵 於封裝結 空氣直接 以銅（Cl 熱效率， 外界空氣 外，為解 般係 0 ， 膠體 包含 部分 裝膠 惟， 導電 而仍 然而 露表 封裝 造成 界一 (N 封裝 亦即 外露 如封 性。 有不 薄， 之外 11與 現象 ⑵ 遂成為封裝產品之主流。 導體封裝產品在面臨高性能與小型化的發展趨勢 而有效的散熱管理遂成為當前所亟需解決之課 閱第1圖所示之習知球柵陣列封裝結構1，通常為 陣列封裝結構1具有較佳且有效之散熱途徑，多 構中設置有可部分外露出封裝膠體2外而與外界 接觸之外露形散熱件1 0，此種外露型散熱件1 0多 I)為主要材料，俾利用其熱阻低的特性達到高導 此外，該散熱件1 0之外露部分可將熱直接散發至 中，使散熱途徑縮短，並有效提昇散熱效率。此 決該散熱件1 0之外露表面易產生氧化之問題，業 將該散熱件1 0施予表面處理，亦即鍍上一層鎳 以避免氧化現象發生，且為顧及該散熱件10與該 2間之附著性，通常僅在該散熱件1 0之上表面， 有外露部分之表面11鍍上鎳層1 2。並於相對於該 之另一表面1 3施以黑化處理之黑化層1 4，俾提昇 體等封裝化合物（Molding Compound)之附著 前述經過黑化處理之散熱件1 0，其黑化層1 4雖具 之特性，但卻受限於該黑化層1 4本身之厚度過 會有導電短路之現象。 前述單面鍍鎳之封裝結構1，由於除其鍍有鎳層 面外，皆被包覆於封裝膠體2之中，而其鍍鎳層 膠體2之接合界面由於附著性不佳，易產生脫層 產品良率之問題。遂發展出一種選擇性鍍鎳之方17294 Silicon. PTD Page 7 1234865 V. Description of the invention Under the trend, only half of the problem is quick. Please refer to the ball grid in the package junction air directly with copper (Cl thermal efficiency, outside air, the solution is 0, the gel contains a part of the glue, but conductive and still exposed surface of the package to cause a boundary (N package is exposed Such as tightness. There is no thinness. Outside 11 and phenomena have become the mainstream of packaging products. Conductive packaging products are facing the development trend of high performance and miniaturization, and effective thermal management has become the current urgently needed solution. The conventional ball grid array package structure 1 shown in FIG. 1 is generally an array package structure 1 with a better and effective heat dissipation method. A multi-structure is provided with an exposed heat sink 1 that can partially expose the outside of the packaging gel 2 and contact the outside. 0, this type of exposed heat sink is more than 10. I) is the main material, and it uses its low thermal resistance to achieve high conductivity. In addition, the exposed part of the heat sink 10 can directly radiate heat to the middle, shortening the heat dissipation path. And effectively improve the heat dissipation efficiency. This determines the problem that the exposed surface of the heat sink 10 is prone to oxidation. Therefore, the heat sink 10 is subjected to surface treatment, that is, plated with nickel to No oxidation occurs, and in order to take into account the adhesion between the heat sink 10 and the two, usually only the upper surface of the heat sink 10, and the surface 11 with an exposed portion is plated with a nickel layer 12. The other surface 1 3 is provided with a blackened layer 1 4 and a sealing compound such as a lifting compound (Molding Compound) is adhered to the heat-treated member 10 that has undergone the blackening treatment. Characteristics, but it is limited by the phenomenon that the thickness of the blackened layer 14 itself will be conductive short circuit. The aforementioned single-sided nickel-plated packaging structure 1 is covered by the encapsulation except for the nickel-plated layer. 2, and the joint interface of the nickel-plated colloid 2 has poor adhesion, which is prone to the problem of yield of the delaminated product. Therefore, a selective nickel plating method has been developed.

II

17294矽品.ptd 第8頁 1234865 五、發明說明（3) 式。其係於一銅製胚料之上下表面皆塗敷上絕緣層，接著 選擇性地在散熱件上欲外露於封裝膠體表面之位置上進行 去除塗敷層之步驟，並施予鍍鎳之製程，使該已去除塗敷 層之表面鍍上鎳層，其後將所有絕緣層去除，再沖製成所 須之形狀。透過前述之製程步驟亦得保有避免氧化現象發 生之問題。 前述兩種外露式散熱件雖能夠達到散熱並且防止散熱 件本身氧化之目的，然而卻至少必須歷經絕緣層之塗敷， 鍍鎳處理、去絕緣層處理及沖製成形等步驟始能完成。製 成的繁複意味製造成本的增加。為解決此一問題，另一種 f 外露型散熱件製造方法係置備一以銅為主要材料之胚料 2 1，如第2 A圖所示，接著將該胚料2 1之上下表面直接鍍上 鈀層2 2 ，如第2 B圖所示，最後再依據所需的形狀加以沖 製，即成第2 C圖所示之散熱件成品2 3。 無論其功效或製程之繁簡，前述各該散熱件之特色在 於其形成有一平坦部，並延伸有一支撐部，而支撐部復延 伸有一接觸部，俾形成一圍限空間，容納晶片及銲線，藉 以避免該等晶片及銲線碰觸該散熱件進而造成短路現象。17294 silicon product. Ptd page 8 1234865 V. Description of invention (3). It is coated with an insulating layer on the upper and lower surfaces of a copper blank, and then selectively removes the coating layer on the position of the heat sink to be exposed on the surface of the packaging colloid, and applies a nickel plating process. The surface of the removed coating layer is plated with a nickel layer, and then all insulating layers are removed, and then punched into a desired shape. Through the aforementioned process steps, the problem of avoiding the occurrence of oxidation phenomenon can also be kept. Although the aforementioned two types of exposed heat sinks can achieve heat dissipation and prevent the heat sinks from oxidizing, they must at least undergo the coating of an insulating layer, nickel plating, deinsulating layer processing, and stamping. The complexity involved means increased manufacturing costs. In order to solve this problem, another f-exposed heat sink manufacturing method is to prepare a blank 21 with copper as the main material, as shown in Figure 2A, and then directly plate the top and bottom surfaces of the blank 21 As shown in FIG. 2B, the palladium layer 2 2 is finally punched according to the required shape to form a finished heat sink 23 as shown in FIG. 2C. Regardless of its effectiveness or the complexity of the manufacturing process, each of the aforementioned heat sinks is characterized in that it is formed with a flat portion and extends with a support portion, and the support portion further extends with a contact portion, forming a confined space to accommodate the chip and the bonding wire. In order to avoid the chips and bonding wires from touching the heat sink and causing a short circuit.

惟現今的半導體產品為達到高性能化，常設有如電阻、電 容等被動元件於基板上，為避免該被動元件碰觸到散熱件 胃I 而造成該被動元件因短路而失效，習知係以絕緣膠包覆於 該被動元件之外層，然此舉不但造成製程複雜且浪費成 本。此外，具有導電性之散熱件亦常因銲線弧高過高而導 致短路現象之發生。However, in order to achieve high performance in today's semiconductor products, passive components such as resistors and capacitors are always on the substrate. In order to prevent the passive components from contacting the heat sink's stomach and causing the passive components to fail due to short circuits, it is known to use insulation. The rubber is coated on the outer layer of the passive component, but this not only causes a complicated process and wastes costs. In addition, conductive heat sinks often cause short circuits due to the high arc height of the wire.

17294矽品.ptd 第9頁 1234865 五、發明說明（4) 另外，前述經過黑化處理之散熱件1 0，其黑化層1 4雖 具有不導電之特性，但卻受限於該黑化層1 4本身之厚度過 薄，而仍會有導電短路之現象，故其並無法有效的解決銲 線弧高過高所導致的短路問題，自亦無法取代被動元件上 的絕緣膠，以做為該散熱件1 0與被動元件間絕緣之用。 綜上所述，如何能提供一種製程簡單、具有高散熱效 果、得防止氧化且得防止被動元件與銲線短路之散熱件， 以及具有該散熱件之半導體封裝結構，乃目前所亟需解決 之課題。 【發明内容】 為解決以上所述習知技術之缺點，本發明之主要目的 在於提供一種防止導電之散熱件以及具有該散熱件之半導 體封裝結構，透過於該散熱件之表面形成一鍍層，並於相 對該鐘層之另一表面形成一絕緣層，除得使該散熱件外露 於封裝構造的部分無氧化之虞外，同時得避免封裝產品之 被動元件與銲線因碰觸該散熱件，進而造成短路之現象發 生。 本發明之另一目的在於提供一種防止導電之散熱件以 及具有該散熱件之半導體封裝結構，透過以形成一絕緣層 於該散熱件外露於該封裝構造外表面之相對表面上之方 式，代替習知以絕緣膠包覆封裝構造中被動元件之封裝技 術，俾達到減少製程成本之目的。 本發明之另一目的在於提供一種防止導電之散熱件以 及具有該散熱件之半導體封裝結構，透過以形成一絕緣層17294 硅 品 .ptd Page 9 1234865 V. Description of the Invention (4) In addition, the blackened heat sink 10, whose blackened layer 1 4 is non-conductive, is limited by the blackened The thickness of layer 1 4 itself is too thin, and there will still be a conductive short circuit, so it cannot effectively solve the short circuit caused by the arc height of the welding wire is too high, and it can not replace the insulating glue on the passive components to do For the purpose of insulation between the heat sink 10 and the passive element. In summary, how to provide a heat sink with a simple process, high heat dissipation effect, oxidation prevention and short circuit between passive components and bonding wires, and a semiconductor package structure with the heat sink are currently urgently needed to be solved. Topic. [Summary of the Invention] In order to solve the shortcomings of the conventional techniques described above, the main object of the present invention is to provide a heat-dissipating member that prevents conduction and a semiconductor packaging structure having the heat-dissipating member. A plating layer is formed on the surface of the heat-dissipating member, and An insulating layer is formed on the other surface opposite to the clock layer, in addition to avoiding the risk of oxidation of the part of the heat sink exposed to the packaging structure, and avoiding the passive components and bonding wires of the packaged product from touching the heat sink. This will cause a short circuit. Another object of the present invention is to provide a heat-dissipating member for preventing conduction and a semiconductor package structure having the heat-dissipating member. The method of forming an insulating layer on the opposite surface of the heat-dissipating member exposed on the outer surface of the package structure by forming an insulating layer instead of the conventional It is known that the packaging technology of passive components in the packaging structure with insulating glue can reduce the process cost. Another object of the present invention is to provide a heat-dissipating member for preventing conduction and a semiconductor package structure having the heat-dissipating member, which can pass through to form an insulating layer.

17294矽品.ptd 第10頁 1234865 五、發明說明（5) 於該散熱件外露於該封裝構造外表面之相對表面上之方 式，代替習知以絕緣膠包覆封裝構造中被動元件之封裝技 術，俾達到增加半導體封裝良率之目的。 為達成以上所述的目的，本發明之防止導電之散熱件 其係於封裝製程前，於主要材料為銅之散熱件胚材的一表 面形成一抗氧化層後，將該胚材沖製成所需形狀。其次， 於該散熱件相對於該形成有抗氧化層之另一表面上進行黑 化或棕化處理，俾令該相對表面形成一不導電之氧化層； 再塗敷一環氧化物於該不導電之氧化層之表面，俾令該相 對表面形成一絕緣層。 依據前述之防止導電之散熱件，則本發明之具有該散 熱件之半導體封裝結構至少包括：至少一晶片及/或被動 元件、一上表面接合有該晶片及/或被動元件之基板 (substrate)、銲接於該基板下表面上之銲球（solder bal 1)、形成於該基板上並包覆住該晶片及/或被動元件 之封裝膠體、以及前述之該防止導電之散熱件。 相較於習知的散熱件以及具有該散熱件之半導體封裝 結構，本發明之防止導電之散熱件以及具有該散熱件之半 導體封裝結構，得使該散熱件外露於封裝構造的部分無氧 化之虞外，同時得取代以絕緣膠包覆被動元件之高成本製 造方式，進而達到避免封裝產品之被動元件與銲線因碰觸 該散熱件所造成之短路現象發生。 【實施方式】 第一實施例17294 silicon product.ptd page 10 1234865 V. Description of the invention (5) The way in which the heat sink is exposed on the opposite surface of the outer surface of the packaging structure, instead of the conventional packaging technology of passive components in the packaging structure covered with insulating glue , To achieve the purpose of increasing the yield of semiconductor packaging. In order to achieve the above-mentioned object, the heat-dissipating heat-preventing member of the present invention is formed by forming an anti-oxidation layer on a surface of the heat-dissipating member base material whose main material is copper before the encapsulation process. Desired shape. Secondly, a blackening or browning process is performed on the other surface of the heat-dissipating member opposite to the anti-oxidation layer, so that a non-conductive oxide layer is formed on the opposite surface; and an epoxy is coated on the non-conductive The surface of the oxide layer causes the opposite surface to form an insulating layer. According to the foregoing heat-dissipating heat-dissipating member, the semiconductor package structure with the heat-dissipating member of the present invention at least includes: at least one chip and / or passive element, and a substrate on which the chip and / or passive element are bonded on the upper surface. Solder balls (solder bal 1) soldered on the lower surface of the substrate, packaging gels formed on the substrate and covering the chip and / or passive components, and the aforementioned heat-dissipating heat-dissipating member. Compared with the conventional heat sink and the semiconductor package structure having the heat sink, the conductive heat sink and the semiconductor package structure with the heat sink of the present invention can make the part of the heat sink that is exposed to the packaging structure free of oxidation. At the same time, it is necessary to replace the high-cost manufacturing method of covering the passive components with insulating glue, so as to avoid the short-circuit phenomenon caused by the passive components and bonding wires of the packaged products touching the heat sink. [Embodiment] First embodiment

17294矽品.ptd 第11頁 1234865 五、發明說明（6) 於本實施例中，本發明之防止導電之散熱件3 0係如第 3A置3D圖所示之方式加以製成。首先，置備一主要材料為 銅之散熱件胚材3 1，如第3 A圖所示。惟該胚材3 1除得為銅 以外，復得為銅合金或類似具良好導熱性之金屬材料製 成。 其次，於該胚材之上表面3 2形成一抗氧化層3 3，如第 3 B圖所示。須特別說明者，係該抗氧化層3 3得為一鍍鎳 (Ni)、鍍鉻（Cr)或鍍鈀（Pd)層等任何達到防止該散 熱件3 0之外露部分產生氧化作用之物質。 接著，如第3C圖所示，將該胚材3 1沖製成所需形狀。 於本實施例中，該胚材3 1係形成有一平坦部310，並延仲 有一支撐部3 1 1，而該支撐部3 1 1復延伸有一接觸部3 1 2， 俾形成一圍限空間，容納晶片暨銲線及/或如電容、電阻 或電感等被動元件。 再者，如第3 D圖所示，於該胚材3 1相對於該形成有抗 氧化層3 3的上表面3 2之一下表面3 4進行黑化（C u p r i c Oxide)或棕化（Cuprous Oxide)處理，俾令該下表面34 形成一不導電之氧化銅（CuO)或氧化亞銅（Cu20)之黑 (或棕）化層3 5，接著於此黑化層3 5上塗敷一環氧化物 (epoxy)或其他類似具有絕緣特性之高分子材料，俾形 成該具有絕緣效果之絕緣層3 6。藉以避免前述之該等晶片 暨銲線及/或如電容、電阻或電感等被動元件碰觸該散熱 件3 0進而造成短路現象。 請參閱第4圖，承前所述，依此種方式所製成之散熱17294 silicon product. Ptd page 11 1234865 V. Description of the invention (6) In this embodiment, the conductive heat sink 30 of the present invention is made as shown in the 3D and 3D drawings. First, a heat sink blank 31 whose main material is copper is prepared, as shown in FIG. 3A. However, in addition to the copper material 31, it can be made of a copper alloy or a similar metal material with good thermal conductivity. Next, an anti-oxidation layer 3 3 is formed on the upper surface 32 of the green material, as shown in FIG. 3B. It should be particularly noted that the anti-oxidation layer 33 may be a nickel (Ni), chromium (Cr) or palladium (Pd) plating layer, etc., which can prevent any oxidation of the exposed part of the heat sink 30. Next, as shown in FIG. 3C, the blank 31 is punched into a desired shape. In this embodiment, the blank material 31 is formed with a flat portion 310, and a support portion 3 1 1 is extended, and the support portion 3 1 1 is further extended with a contact portion 3 1 2 to form a confined space. , To accommodate chips and bonding wires and / or passive components such as capacitors, resistors or inductors. Furthermore, as shown in FIG. 3D, the green material 31 is blackened (Cupric Oxide) or browned (Cuprous) with respect to one of the upper surface 32 and the lower surface 34 of the anti-oxidation layer 33. Oxide) treatment, so that a black (or brown) layer 3 5 of non-conductive copper oxide (CuO) or cuprous oxide (Cu20) is formed on the lower surface 34, and then an epoxidation is applied on the blackened layer 35. Materials (epoxy) or other similar high-molecular materials with insulating properties, to form the insulating layer 36 having the insulating effect. In order to avoid the aforementioned chips and bonding wires and / or passive components such as capacitors, resistors or inductors from touching the heat sink 30 and causing short circuit. Please refer to Figure 4 for the heat dissipation made in this way.

17294矽品.ptd 第12頁 1234865 五、發明說明（7) 件3 0即得直接運用於本發明之具有該散熱件3 0之半導體封 裝結構40’其主要係由一上表面411導電地接合有半導體 晶片4 2 0及/或被動元件4 3 0之印刷電路基板4 1 0 ;焊接於該 基板4 1 0之下表面4 1 2上之銲球4 4 0 ;形成於該基板4 1 〇上並 包覆住該半導體晶片4 2 0及/或該被動元件4 3 0之封裝膠體 4 5 0，以及接至於該基板4 1 0之上表面4 1 1上之該散熱件3 〇 等所構成。 其中，該散熱件3 0係以中央***之部分外露出該封裝 膠體4 5 0，側邊部分以與該基板4 1 0相接的方式被包覆於該 封裝膠體4 5 0内，俾將產生於該半導體晶片4 2 0及/或該被 動元件43 0之熱量，經由熱傳導的方式傳導至其中央外露 部分，再直接散逸至外界空氣中而達到良好而有效之散熱 效果，並因該散熱件3 0的上表面3 2鍍有鎳、鉻或鈀之抗氧 化層3 3，使得該散熱件3 0外露於該封裝膠體4 5 0之部分不 致氧化。此外，由於該散熱件3 0下表面3 4之黑化層3 5外， 塗敷有一不導電之絕緣層3 6，藉以避免前述之該等晶片暨 銲線4 5 1及/或如電容、電阻或電感等被動元件碰觸該散熱 件3 0進而造成短路現象。 綜上所述，本發明之防止導電之散熱件以及具有該散 熱件之半導體封裝結構，除得使該散熱件外露於封裝構造 的部分無氧化之虞外，同時得取代以絕緣膠包覆被動元件 之高成本製造方式，進而達到避免封裝產品之被動元件與 銲線因碰觸該散熱件所造成之短路現象發生。17294 silicon product.ptd Page 12 1234865 V. Description of the invention (7) Piece 30 can be directly applied to the semiconductor package structure 40 'with the heat sink 30 of the present invention, which is mainly connected by an upper surface 411 conductively A printed circuit board 4 1 0 having a semiconductor wafer 4 2 0 and / or a passive element 4 3 0; a solder ball 4 4 0 soldered on the lower surface 4 1 2 of the substrate 4 10; formed on the substrate 4 1 〇 And encapsulating the semiconductor wafer 4 2 0 and / or the encapsulation gel 4 50 of the passive component 4 3 0 and the heat sink 3 0 and the like connected to the upper surface 4 1 1 of the substrate 4 1 0 Make up. Wherein, the heat sink 30 is exposed to the packaging gel 4 50 with a central bulging portion, and the side portion is covered with the packaging gel 4 50 in a manner of being in contact with the substrate 4 10. The heat generated in the semiconductor wafer 4 2 0 and / or the passive element 43 0 is conducted to the central exposed portion through heat conduction, and then directly dissipated into the outside air to achieve a good and effective heat dissipation effect, and due to the heat dissipation The upper surface 32 of the component 30 is plated with an anti-oxidation layer 3 3 of nickel, chromium or palladium, so that the part of the heat dissipation component 30 exposed to the encapsulant 4 50 does not oxidize. In addition, since the blackened layer 35 of the lower surface 34 of the heat sink 30 is coated with a non-conductive insulating layer 36, in order to avoid the aforementioned wafers and bonding wires 4 51 and / or such as capacitors, Passive components such as resistance or inductance touch the heat sink 30 and cause a short circuit. To sum up, the heat-dissipating heat-dissipating member and the semiconductor packaging structure having the heat-dissipating member of the present invention can not only avoid the risk of oxidation when the heat-dissipating member is exposed to the packaging structure, but also replace the passive coating The high-cost manufacturing method of the components can avoid short circuit caused by the passive components and bonding wires of the packaged products due to contact with the heat sink.

17294 矽品.ptd 第13頁 1234865 圖式簡單說明 【圖式簡單說明】 第1圖為習知球栅陣列封裝結構之局部剖視圖； 第2 A至第2 C圖為習知單面度鎳之散熱件之製作過程示 意圖； 第3A至第3D圖為本發明之防止導電之散熱件之製作過 程示意圖；以及 第4圖為本發明之具有防止導電之散熱件之半導體封 裝結構之局部剖視圖。 1 球 柵 陣列封裝結構 2 封 裝 膠 體 10 散 熱 件 11 表 面 12 鎳 層 13 表 面 14 化 層 21 胚 料 22 4巴 層 23 散 熱 件 成 品 30 散 熱 件 31 散 敎 件 胚 材 32 上 表 面 33 抗 氧 化 層 34 下 表 面 35 黑 化 層 36 絕 緣 層 40 半 導 體 封 裝 結構 310 平 坦 部 31 1 支 撐 部 312 接 觸 部 410 印 刷 電 路 基 板 411 上 表 面 412 下 表 面 420 半 導 體晶片 430 被 動 元 件 440 銲 球 450 封 裝 膠 體 451 銲 線17294 Silicon product.ptd Page 13 1234865 Brief description of the drawings [Simplified description of the drawings] Figure 1 is a partial cross-sectional view of a conventional ball grid array package structure; Figures 2 A to 2 C are conventional heat sinks of single-sided nickel Schematic diagrams of the manufacturing process; Figures 3A to 3D are schematic diagrams of the manufacturing process of the conductive heat-dissipating heat sink of the present invention; and Figure 4 is a partial cross-sectional view of the semiconductor package structure with the conductive heat-dissipating heat sink of the present invention. 1 Ball grid array package structure 2 Packaging gel 10 Heat sink 11 Surface 12 Nickel layer 13 Surface 14 Chemical layer 21 Blank 22 Bar layer 23 Heat sink finished product 30 Heat sink 31 Bulk material 32 Upper surface 33 Antioxidant layer 34 Lower surface 35 Blackened layer 36 Insulating layer 40 Semiconductor package structure 310 Flat portion 31 1 Support portion 312 Contact portion 410 Printed circuit board 411 Upper surface 412 Lower surface 420 Semiconductor wafer 430 Passive component 440 Solder ball 450 Encapsulated gel 451 Solder wire

]7294矽品.ptd 第14頁] 7294 硅 品 .ptd Page 14

Claims (1)

1234865 六、申請專利範圍 1. 一種防止導電之散熱件，係應用於半導體封裝結構 中，其包括： 一散熱本體； 一抗氧化層，其係形成於該散熱本體之上表面， 俾防止該散熱件外露於該半導體封裝結構之部分發生 氧化現象； 一不導電氧化層，其係形成於該散熱本體之下表 面上；以及 一絕緣層，其係形成於該不導電氧化層之下表面 上，俾防止該半導體封裝結構中之電子組件因觸碰該 散熱件進而發生短路現象。 2. 如申請專利範圍第1項之防止導電之散熱件，其中，該 散熱本體係由一導熱性良好的金屬胚材沖製而成。 3. 如申請專利範圍第2項之防止導電之散熱件，其中，該 散熱本體係沖製成具有一平坦部，並延伸有一支撐 部，而該支撐部復延伸有一接觸部，俾形成一用以容 納該電子組件之圍限空間。 4. 如申請專利範圍第2或3項之防止導電之散熱件，其 中，該金屬胚材可為銅及銅合金其中任一者。 5. 如申請專利範圍第3項之防止導電之散熱件，其中，該 散熱本體係於沖製成型後，在於其上表面鍍上該抗氧 化層。 6. 如申請專利範圍第3項之防止導電之散熱件，其中，該 抗氧化層係先形成於該散熱本體之上表面，再沖製成1234865 VI. Scope of patent application 1. A heat-dissipating member for preventing conduction, which is used in a semiconductor package structure, includes: a heat-dissipating body; an anti-oxidation layer formed on the upper surface of the heat-dissipating body to prevent the heat dissipation An oxidation phenomenon occurs in a part exposed on the semiconductor package structure; a non-conductive oxide layer is formed on the lower surface of the heat-dissipating body; and an insulating layer is formed on the lower surface of the non-conductive oxide layer.俾 Prevent the electronic components in the semiconductor package structure from short-circuiting due to touching the heat sink. 2. For example, a conductive heat-dissipating heat sink according to item 1 of the patent application scope, wherein the heat-dissipating system is made of a metal blank with good thermal conductivity. 3. For example, the conductive heat-dissipating heat sink of item 2 of the patent application scope, wherein the heat-dissipating system is punched to have a flat portion, and a support portion is extended, and the support portion is further extended to have a contact portion, so as to form a purpose. To contain the confined space of the electronic component. 4. For the conductive heat-dissipating heat sink of item 2 or 3 of the patent application, the metal blank can be any one of copper and copper alloy. 5. For example, the conductive heat-dissipating heat sink according to item 3 of the patent application scope, wherein the heat-dissipating system is stamped with an anti-oxidation layer on the upper surface. 6. For example, the conductive heat-dissipating heat-dissipating member in item 3 of the scope of patent application, wherein the anti-oxidation layer is first formed on the upper surface of the heat-dissipating body, and then punched out. 17294矽品.ptd 第15頁 1234865 六、申請專利範圍 型。 7. 如申請專利範圍第1項之防止導電之散熱件，其中，該 抗氧化層可為一鑛鎳層、鍵鉻層及鍍把層其中任一 者。 8. 如申請專利範圍第1項之防止導電之散熱件，其中，該 不導電氧化層係藉由形成一氧化銅及氧化亞銅其中任 一者所形成者。 9. 如申請專利範圍第1項之防止導電之散熱件，其中，該 絕緣層係藉由塗敷一環氧化物所形成者。 1 0 .如申請專利範圍第8或9項之防止導電之散熱件，其 中，該絕緣層係本體係於沖製成型後所形成者。 1 1.如申請專利範圍第1項之防止導電之散熱件，其中，該 電子組件可為晶片、銲線及被動元件其中任一者。 1 2 .如申請專利範圍第1項之防止導電之散熱件，其中，該 被動元件可為電阻、電容及電感其中任一者。 1 3. —種具有防止導電之散熱件之半導體封裝結構，其包 括： 至少一電子組件； 一基板，其具有一可導電地接合有該電子組件之 上表面及一下表面； 複數個導電元件，其係用以銲接於該基板之下表 面上 ； 一防止導電之散熱件，其係接置於該基板上表面 上之外露型散熱件，並形成有一用以使該電子組件位17294 silicon products. Ptd page 15 1234865 6. Application for patent scope. 7. For example, the conductive heat-dissipating heat sink of the scope of application for patent, wherein the anti-oxidation layer may be any one of a nickel ore layer, a bond chrome layer, and a plating layer. 8. The conductive heat-dissipating member according to item 1 of the patent application scope, wherein the non-conductive oxide layer is formed by forming any one of copper oxide and cuprous oxide. 9. The heat-dissipating member for preventing conduction according to item 1 of the patent application scope, wherein the insulating layer is formed by coating an epoxy. 10. The conductive heat-dissipating heat-dissipating member according to item 8 or 9 of the scope of patent application, wherein the insulating layer is formed after the system is punched. 1 1. The conductive heat-dissipating component according to item 1 of the patent application scope, wherein the electronic component may be any one of a chip, a wire and a passive component. 1 2. If the conductive heat sink is provided in item 1 of the patent application scope, wherein the passive element may be any one of a resistor, a capacitor and an inductor. 1 3. A semiconductor package structure having a heat-dissipating member for preventing conduction, comprising: at least one electronic component; a substrate having an upper surface and a lower surface of the electronic component that are conductively joined; a plurality of conductive elements, It is used for soldering to the lower surface of the substrate; a heat-dissipating member for preventing conduction is connected to an exposed heat-dissipating member placed on the upper surface of the substrate, and is formed with a position for the electronic component 17294矽品.ptd 第16頁 1234865 六、申請專利範圍 於該散熱件與該基板間之圍限空間；以及 一封裝膠體’其係形成於該基板上並包覆住該電 子組件與該散熱件，其中，該散熱件係部分外露於該 封裝膠體表面。 1 4 .如申請專利範圍第1 3項之防止導電之半導體封裝結 構，其中，該防止導電之散熱件係包括： 一散熱本體； 一抗氧化層，其係形成於該散熱本體之上表面， 俾防止該散熱件外露於該半導體封裝結構之部分發生 氧化現象； 一不導電氧化層，其係形成於該散熱本體之下表 面上；以及 一絕緣層，其係形成於該不導電氧化層之下表面 上，俾防止該半導體封裝結構中之電子組件因觸碰該 散熱件進而發生短路現象。 1 5 .如申請專利範圍第1 4項之半導體封裝結構，其中，該 散熱本體係由一導熱性良好的金屬胚材沖製而成。 1 6 .如申請專利範圍第1 5項之半導體封裝結構，其中，該 散熱本體係沖製成具有一平坦部，並延伸有一支撐 部，而該支撐部復延伸有一接觸部，俾形成一用以容 納該電子組件之圍限空間。 1 7 .如申請專利範圍第1 5或1 6項之半導體封裝結構，其 中，該金屬胚材可為銅及銅合金其中任一者。 1 8 .如申請專利範圍第1 6項之半導體封裝結構，其中，該17294 silicon product. Ptd page 16 1234865 6. The scope of the patent application is in the confined space between the heat sink and the substrate; and a packaging gel is formed on the substrate and covers the electronic component and the heat sink. Wherein, the heat sink is partially exposed on the surface of the encapsulating gel. 14. The conductive semiconductor package structure according to item 13 of the scope of patent application, wherein the conductive heat-radiating member includes: a heat-dissipating body; an anti-oxidation layer formed on the upper surface of the heat-dissipating body,俾 Prevent the oxidation of the heat-dissipating part exposed on the semiconductor package structure; a non-conductive oxide layer formed on the lower surface of the heat-dissipating body; and an insulating layer formed on the non-conductive oxide layer On the lower surface, the electronic components in the semiconductor package structure are prevented from short-circuiting due to touching the heat sink. 15. The semiconductor package structure according to item 14 of the scope of patent application, wherein the heat dissipation system is punched from a metal base material with good thermal conductivity. 16. The semiconductor package structure according to item 15 of the scope of patent application, wherein the heat dissipation system is punched out to have a flat portion, and a support portion is extended, and the support portion is further extended with a contact portion, and is used for To contain the confined space of the electronic component. 17. The semiconductor package structure according to item 15 or 16 of the scope of patent application, wherein the metal blank can be any one of copper and copper alloy. 18. The semiconductor package structure according to item 16 of the scope of patent application, wherein the 17294石夕品.ptd 第17頁 1234865 六、申請專利範圍 散熱本體係於沖製成型後，在於其上表面鍍上該氧化 層。 1 9 .如申請專利範圍第1 6項之半導體封裝結構，其中，該 抗氧化層係先形成於該散熱本體之上表面，再沖製成 型 〇 2 0 .如申請專利範圍第1 4項之半導體封裝結構，其中，該 抗氧化層可為一鍍鎳層、鍍鉻層及鍍鈀層其中任一 者。 2 1.如申請專利範圍第1 4項之半導體封裝結構，其中，該 不導電氧化層係藉由形成一氧化銅及氧化亞銅其中任 一者所形成者。 2 2 .如申請專利範圍第1 4項之半導體封裝結構，其中，該 絕緣層係藉由塗敷一環氧化物所形成者。 2 3 .如申請專利範圍第2 1或2 2項之半導體封裝結構，其 中，該絕緣層係本體係於沖製成型後所形成者。 2 4.如申請專利範圍第1 3項之半導體封裝結構，其中，該 電子組件可為晶片、銲線及被動元件其中任一者。 2 5 .如申請專利範圍第1 3項之半導體封裝結構，其中，該 被動元件可為電阻、電容及電感其中任一者。 2 6 .如申請專利範圍第1 3項之半導體封裝結構，其中，該 複數個導電元件係為銲球。17294 Shi Xipin. Ptd Page 17 1234865 VI. Scope of Patent Application After cooling, the system is coated with the oxide layer on the upper surface. 19. The semiconductor package structure according to item 16 of the scope of patent application, wherein the anti-oxidation layer is first formed on the upper surface of the heat sink body, and then punched into a shape. 0. 2 In the semiconductor package structure, the anti-oxidation layer may be any one of a nickel-plated layer, a chromium-plated layer, and a palladium-plated layer. 2 1. The semiconductor package structure according to item 14 of the scope of patent application, wherein the non-conductive oxide layer is formed by forming any one of copper monoxide and cuprous oxide. 22. The semiconductor package structure according to item 14 of the scope of patent application, wherein the insulating layer is formed by coating an epoxy. 2 3. The semiconductor package structure according to the scope of application for patent No. 21 or 22, wherein the insulation layer is formed after the system is punched into a shape. 2 4. The semiconductor package structure according to item 13 of the patent application scope, wherein the electronic component can be any one of a chip, a wire and a passive component. 25. The semiconductor package structure according to item 13 of the patent application scope, wherein the passive element may be any one of a resistor, a capacitor and an inductor. 26. The semiconductor package structure according to item 13 of the patent application scope, wherein the plurality of conductive elements are solder balls. 17294 矽品.ptd 第18頁17294 Silicone.ptd Page 18
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