US20030011009A1 - Grooved channel schottky mosfet - Google Patents
Grooved channel schottky mosfet Download PDFInfo
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- US20030011009A1 US20030011009A1 US09/884,345 US88434501A US2003011009A1 US 20030011009 A1 US20030011009 A1 US 20030011009A1 US 88434501 A US88434501 A US 88434501A US 2003011009 A1 US2003011009 A1 US 2003011009A1
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66643—Lateral single gate silicon transistors with source or drain regions formed by a Schottky barrier or a conductor-insulator-semiconductor structure
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
- H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7834—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a non-planar structure, e.g. the gate or the source or the drain being non-planar
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7839—Field effect transistors with field effect produced by an insulated gate with Schottky drain or source contact
Definitions
- a Schottky contacted MOSFET has been proposed to eliminate the scaling issues of conventional CMOS.
- a Schottky contacted MOSFET uses Schottky junctions to replace the conventional heavily-doped p-n homojunctions within the source and drain regions.
- Metal silicides are used to form natural Schottky barriers to silicon substrates that confine the carriers, reducing or eliminating the need for dopant impurities in the channel to prevent current flow in the “off” condition.
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- Computer Hardware Design (AREA)
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- Manufacturing & Machinery (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
- The present invention relates to integrated circuits and more particularly to a grooved channel Schottky contacted MOSFET and a method for making a grooved channel Schottky contacted MOSFET.
- In order to more highly integrate electronic circuits, a great deal of research has been focused on small geometry transistors. A Schottky contacted MOSFET has been proposed to eliminate the scaling issues of conventional CMOS. A Schottky contacted MOSFET uses Schottky junctions to replace the conventional heavily-doped p-n homojunctions within the source and drain regions. Metal silicides are used to form natural Schottky barriers to silicon substrates that confine the carriers, reducing or eliminating the need for dopant impurities in the channel to prevent current flow in the “off” condition.
- Such Schottky contacted MOSFETs are turned on by large gate-induced electric fields at the top of the source region that result in narrowing of the Schottky barrier width and then enhancing the carrier tunneling into the silicon channel. Schottky contacted MOSFETs have the advantage that there is no punch-through because the source barrier is determined by the Schottky barrier itself. Further, random dopant location issues have been eliminated and the external resistance components in the source and drain regions can be reduced because metal silicides directly contact the silicon channel. Therefore, the fabrication of Schottky contacted MOSFETs is more simple than conventional CMOS structures.
- Such Schottky contacted MOSFETs still have some drawbacks that prevent their application in logic VLSI and analog circuits. The most important drawback is that the off-state current, which is more than 10−8 A/μm, is too large to be used in conventional circuits. Unfortunately, optimizing the design parameters, such as barrier height and background doping, cannot eliminate this drawback.
- Another drawback of the Schottky contacted MOSFETs is that they cannot be scaled to less than 30 nm due to severe short-channel effects. As the gate length of a planar Schottky MOSFET is reduced to less than 0.05 μm, the short-channel effects become quite severe. Referring to FIG. 11, a graph of drain current versus gate voltage of a planar Schottky MOSFET having a gate length of 20 nm is shown.
Curves - It is an object of the present invention to provide a Schottky contacted MOSFET suitable for VLSI and analog circuit applications.
- In order to provide a Schottky contacted MOSFET that is suitable for VLSI and analog circuit applications, the present invention provides a grooved channel Schottky contacted MOSFET with a metal gate and asymmetric Schottky contacted source and drain regions.
- In a first embodiment, the invention provides a semiconductor device including a silicon substrate having a grooved channel formed in a first surface thereof. A first metal silicide material is formed on the first surface on a first side of the grooved channel, which defines a source region. A second metal silicide material is formed on the first surface on a second side of the grooved channel, which defines a drain region. A metal gate is formed in the grooved channel.
- In accordance with the invention, a N-channel grooved Schottky MOSFET includes an undoped silicon or P-doped silicon substrate having a background doping concentration of less than about 1017 cm−3. A grooved channel is formed in a first surface of the substrate. A PtSi layer is formed on the first surface on a first side of the grooved channel, which defines a source region. An ErSi layer is formed on the first surface on a second side of the grooved channel, which defines a drain region. A gate made of TiSi2 is formed in the grooved channel. The gate has a length of about 0.03 um or less. An off-state current of the MOSFET is less than about 50 pA/um and an on-state current is greater than about 200 uA/um.
- The invention further provides a P-channel grooved Schottky MOSFET including an undoped silicon or N-doped silicon substrate having a background doping concentration of less than about 1017 cm−3. A grooved channel is formed in a first surface of the substrate. An ErSi layer is formed on the first surface on a first side of the grooved channel, which defines a source region and a PtSi layer is formed on the first surface on a second side of the grooved channel, which defines a drain region. A metal gate is formed in the grooved channel. The gate is made of a metal having a work function of about 5.0 eV and a gate length of less than about 0.03 um. An off-state current of the MOSFET is less than about 50 pA/um and an on-state current is greater than about 200 uA/um.
- The present invention also provides a method of fabricating a grooved channel Schottky contacted MOSFET including the steps of:
- providing an undoped silicon substrate having a background doping concentration of less than 1017 cm−3;
- forming an isolation trench in a first surface of the substrate;
- depositing a thin oxide film on the first surface of the substrate;
- depositing a thin nitride film over the thin oxide film;
- forming first and second grooved channels in the first surface of the substrate wherein the first and second grooved channels are formed on opposing sides of the isolation trench;
- forming a first metal gate in the first grooved channel and a second metal gate in the second grooved channel;
- depositing a first metal on the first surface of the substrate on first sides of the first and second channels, the first sides being located between the isolation trench and the first and second channels, respectively, and annealing the first metal to form a first metal silicide, thereby defining a drain of a p-channel device and a source of a n-channel device; and
- depositing a second metal on the first surface of the substrate on second sides of the first and second channels, the second sides opposing the first sides, and annealing the second metal to form a second metal silicide, thereby defining a source of the p-channel device and a drain of the n-channel device.
- FIG. 1 is an enlarged cross-sectional view of a grooved channel Schottky MOSFET in accordance with the present invention;
- FIGS.2-6 illustrate different stages of the fabrication process of a grooved channel Schottky MOSFET in accordance with the present invention;
- FIGS.7-10 are graphs illustrating drain current versus gate voltage of various sized devices of the present invention; and
- FIG. 11 is a graph of drain voltage versus threshold voltage of a prior art planar Schottky contacted MOSFET.
- Those skilled in the art will appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale.
- The detailed description set forth below in connection with the appended drawings is intended as a description of the embodiments of the invention, and is not intended to represent the only forms in which the present invention may be practiced. It is to be understood that the same or equivalent functions may be accomplished by different embodiments that are intended to be encompassed within the spirit and scope of the invention. In the drawings, like numerals are used to indicate like elements throughout.
- Referring now to FIG. 1, an enlarged, cross-sectional view of a grooved
channel CMOS device 100 with asymmetric source and drain Schottky contacts is shown. Thedevice 100 has a doped or undopedsilicon substrate 102 having afirst surface 104. That is, the background doping of thesilicon substrate 102 should be less than about 1017 cm−3. Anisolation trench 106 is formed in thesubstrate 102 and separates a P-channel device 108 and an N-channel device 110. The background dopant of the P-channel device 108 is preferably Phosphorous and the background dopant of the N-channel device 110 is preferably Boron. Theisolation trench 106 is formed in a conventional manner. Those of ordinary skill in the art understand substrate background doping and isolation channel formation. - A grooved
channel 112 is formed in thefirst surface 104 of thesubstrate 102. For the P-channel device 108, a firstmetal silicide material 114 is formed on thefirst surface 104 on a first side of thegrooved channel 112. The firstmetal silicide material 114 forms a source region of the P-channel device 108. A secondmetal silicide material 116 is formed on thefirst surface 104 on a second side of thegrooved channel 112. The secondmetal silicide material 116 forms a drain region of the P-channel device 108. - For the N-
channel device 110, the firstmetal silicide material 114 is formed on thefirst surface 104 on a first side of thegrooved channel 112 and in this instance, forms a drain region of the N-channel device 110. The secondmetal silicide material 116 is formed on thefirst surface 104 on a second side of thegrooved channel 112 and forms a source region of the N-channel device 110. - In this embodiment, the first
metal silicide material 114 comprises ErSi and the secondmetal silicide material 116 comprises PtSi. Thus, the drain of the N-channel device 110 and the source of the P-channel device 108 are formed of ErSi while the source of the N-channel device 110 and the drain of the P-channel device 108 are formed of PtSi. - A
metal gate 118 is formed in thegrooved channel 112. A high K dielectric 120 is located between thegate 118 and thesubstrate 102. In this embodiment, the high K dielectric 120 is an oxide layer. The high K dielectric 120 substantially surrounds themetal gate 118 and separates themetal gate 118 from thesubstrate 102 and the first and secondmetal silicides materials device grooved channel 112 has a depth of about 5.0 nm below an interface of thesubstrate 102 and themetal silicide materials metal silicide material substrate 102 is located about 5.0 nm above the interface of the high K dielectric 120 and thesubstrate 102. - The
metal gates 118 of the P-channel and N-channel devices metal gates 118 preferably comprise metal materials that have a work function within about 0.3 to 0.4 eV from the conduction band or above a mid-gap for the N-channel device 110 and about 0.3 to 0.4 eV from the valence band or below the mid-gap for the P-channel device 108. For example, themetal gate 118 of the N-channel device 110 is preferably a metal material having a work function of about 4.1 eV, such as TiSi2, which has a work function of 4.245 eV, while themetal gate 118 of the P-channel device 108 preferably comprises a metal material having a work function of about 5.045 eV, such as tungsten nitride (WNx). For the N-channel device 110, other preferred metal materials have a work function within about 0.2 eV from the conduction band (4.1 eV), such as TaN and Mo. For the P-channel device 108, other preferred metal materials have a work function within about 0.2 ev from the valence band, such as Pt and Ir. - A
sidewall layer 122 is formed on the sides of themetal gates 118. The thickness of thesidewall layer 122 is controlled to allow lateral extension of themetal silicide high K dielectric 120. The sidewall layer is preferably formed of Si3N4. - The Schottky contacted MOSFETs are turned on by a large gate induced electrical field at the source contact, which induces internal field emission via Fowler-Nordheim tunneling through the sources Schottky barrier to the
grooved channel 112 with a tunneling barrier width of about 5.0 nm. A groove depth of about 5.0 nm effectively screens the effect of the electric field from the drain to the source, which eliminates short-channel effects. Although the physical channel length of the grooved MOSFET is the planar gate length plus two times the depth of thegroove 112, the effective gate length is equal to the planar gate length if the depth of the groove is less than 5.0 nm, which is close to the tunneling barrier width in the source, assuming Vgs=Vdd and Vds=Vdd. This does not degrade the drive current significantly. Simulation results of this device structure show that the gate delay (CV/I) of theNMOS device 110 is about 2.4 ps and the gate delay of thePMOS device 108 is about 4.6 ps. - The off-state current includes electron current and hole current. Therefore, large Schottky barrier heights to electrons and holes are needed in order to achieve a very low off-state current. Thus asymmetric source/drain contacts are preferred. PtSi and ErSi yield about a 0.9 V of barrier height to electrons and to holes, respectively. Another advantage of asymmetric source/drain contacts is to let the drain effectively sink channel current for increasing on-state current. For example, ErSi (PtSi) in the drain of the NMOS device110 (PMOS device 108) has only 0.25 V of barrier height for electrons (holes).
- Referring now to FIGS.7-10, these graphs show the characteristics of a semiconductor device in accordance with the present invention. FIG. 7 shows the transfer characteristics for three different drain voltages.
Curves Curves - Further, there is a saturation region in the output characteristics. The proposed Schottky MOSFET structure can reduce the off-state current to less 50 pA/μm, while the on-state current exceeds more 200 μA/μm. FIG. 9 shows the transfer characteristics of a grooved channel Schottky MOSFET in accordance with the present invention.
Curves 314, 316 and 318 illustrate drain currents for devices having gate lengths Lg of 0.03 μm, 0.02 μm and 0.01 μm, respectively. The characteristics of these three devices are very close, which implies that the Schottky MOSFET structure of the present invention can be scaled down to 0.01 μm. FIG. 10 shows the transfer characteristics for a device having a gate length of 10 nm (Lg=0.01 μm).Curves TABLE 1 N-channel MOSFET P-channel MOSFET Gate TiSi2 WNx (work func. = 4.245 eV) (work func. = 5.045 eV) Source PtSi ErSi Drain ErSi PtSi Substrate <1017 cm−3 <1017 cm−3 - In the grooved channel device architecture of the present invention, the difference between NMOS and PMOS devices is in the substrate and the metal gate. There is no difference in source/drain, as the two metal silicides are just exchanged. The grooved channel structure has the advantage of allowing the off-state current to be reduced to less than 50 pA/μm. Further, the device feature size can be scaled down to about 10 nm without strong short-channel effects (DIBL<0.063). In addition, the gate delay (CV/I) is reduced to about 2.4 ps. The device structure of the present invention can be used in high-speed logic VLSI and analog integrated circuits.
- Referring now to FIGS.2-6, a method of preparing a semiconductor integrated circuit is shown. An integrated circuit, such as a CMOS device, according to the present invention can be manufactured using only five masks. The first mask is used to pattern the shallow trench isolation and the active region. The second mask is used to etch silicon forming the grooved N-channel and to deposit the gate dielectric and metal. The third mask is used to etch silicon forming the grooved P-channel and deposit the gate dielectric and metal. The same silicides can be used for both n- and p- channel devices, facilitating integration. Then, a sidewall layer is deposited. The fourth mask is used to define the silicide for the source of the NMOS device and the drain of the PMOS device. Finally, the fifth mask is used to define the silicide for the drain of the NMOS device and the source of the PMOS device.
- Referring particularly to FIG. 2, a MOSFET device is formed using a doped or an
undoped silicon substrate 210 having afirst surface 212. As discussed above, a doped silicon substrate having a background doping concentration of less than about 1017 cm−3 can also be used. One ormore isolation trenches 214 are formed in thefirst surface 212 of thesubstrate 210 and separate P-channel areas 216 from N-channel areas 218. The P-channel area 216 is preferably doped with Phosphorous and the N-channel area 218 is preferably doped with Boron. However, other dopants known to those of skill in the art could be used. Theisolation trenches 214 are formed in a conventional manner. - A
thin oxide film 220 is deposited on thefirst surface 212 of thesubstrate 210 and athin nitride film 222 is deposited over thethin oxide film 220, as shown in FIG. 3. Theoxide film 220 preferably has a thickness of about 12 nm and thenitride film 222 preferably has a thickness of about 100 nm. The oxide andnitride films substrate 210 is etched using the oxide andnitride films grooved channels 224 are formed in thesubstrate 210. Thegrooved channels 224 preferably extend about 0.05 um or more below thefirst surface 212 of thesubstrate 210. Thus, a grooved channel device, as opposed to a planar device, will be formed. Thechannels 224 are formed on opposing sides of theisolation trenches 214. - Referring now to FIG. 4, a high K
dielectric material 226 and agate dielectrode material 228 are grown or deposited in thegrooved channels 224. In this embodiment, the high Kdielectric material 226 is an oxide layer having a thickness of about 0.01 um. As discussed above, preferably thegate dielectrode material 228 of the P-channel and N-channel devices are made of different metals. For example, thegate dielectrode material 228 of the N-channel device is preferably TiSi2 and thegate dielectrode material 228 of the P-channel device is preferably WNx. The gate dielectric anddielectrode materials - After the metal gates (dielectrode material228) are formed, the
nitride film 222 is etched using anisotropic etch stop on theoxide film 220 to form a nitride spacer. The thickness of sidewall layers 236 (FIG. 5) is strictly controlled to allow lateral extension of silicide to reach thegate dielectric 226 when a silicide annealing process is performed, while preventing damage to thegate dielectrode material 228. Another option to form a thinner nitride spacer is to remove thenitride 222 by using either dry or wet etching, depending on the gate dielectric andgate electrode materials oxide film 220 remains, such as to a thickness of about 10 nm as shown in FIG. 5. Then a thinner layer of nitride is deposited using the anisotropic etch to form a narrower nitride spacer. The drain of the P-channel device and the source of the N-channel device are then defined by patterning. The thin oxide is removed by dry etch or wet etch. - Referring now to FIG. 6, after stripping the photo resist, a first metal is deposited on the
first surface 212 of thesubstrate 210. The drain of the P-channel device is located between one of theisolation trenches 214 and one of thegrooved channels 224 at the P-channel area 216. Similarly, the source of the N-channel device is located between one of theisolation trenches 214 and one of thegrooved channels 224 at the N-channel area 218. The first metal is then annealed to form afirst metal silicide 232, which forms a drain of the P-channel device and a source of the N-channel device. Any unreacted first metal is removed, such as by selective wet etching. A second thermal anneal for silicide may be used to reduce resistance. - The
oxide film 220 is removed by wet etching. Then, after the etching of theoxide film 220, a second metal is deposited on thefirst surface 212 of thesubstrate 210. More specifically, the second metal is deposited on opposing sides of thechannels 224 as the first metal was deposited. The second metal is then annealed to form asecond metal silicide 234, which forms a source of the P-channel device and a drain of the N-channel device. Any unreacted second metal is removed, such as by etching. A second thermal anneal might be needed to reduce the resistance of the silicide layer. - In this embodiment, the first metal comprises Pt and the second metal comprises Er, so that the first metal silicide is PtSi and the second metal silicide is ErSi. It is possible to use one metal, such as Pt, instead of two different metals, when forming the source and drain regions, however, using the same metal material affects the device offset current. That is, using different metals, such as Pt and Er, provides a lower offset current.
- As is apparent, the present invention provides a grooved Schottky MOSFET structure and a method of fabricating a device with such a structure. As will be appreciated, other metals and materials having properties similar to those described with reference to the preferred embodiment may be used. Thus, the present invention is not limited to using PtSi, ErSi, WNx and TiSi2. It is understood, therefore, that this invention is not limited to the particular embodiments disclosed, but covers modifications within the spirit and scope of the present invention as defined by the appended claims.
Claims (25)
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