US20010024862A1

US20010024862A1 - Method for forming a lower electrode by using an electroplating method

Info

Publication number: US20010024862A1
Application number: US09/735,528
Authority: US
Inventors: Kwon Hong; Heung-Sik Kwak; Chung-Tae Kim; Hyung-Bok Choi
Original assignee: Hyundai Electronics Industries Co Ltd
Current assignee: SK Hynix Inc
Priority date: 1999-12-27
Filing date: 2000-12-14
Publication date: 2001-09-27
Anticipated expiration: 2020-12-14
Also published as: DE10065350A1; JP2001210806A; US6451666B2; DE10065350B4

Abstract

A method for manufacturing a semiconductor device can form a thick lower electrode made of Pt. The method begins with the preparation of an active matrix provided with at least one transistor, a plurality of conductive plugs electrically connected to the transistors and an insulating layer formed around the conductive plugs. Thereafter, a seed layer is formed on top of the active matrix and a dummy oxide layer is formed on top of the seed layer. And then, the dummy oxide layer is patterned into a predetermined configuration, thereby exposing portions of the seed layer which are located on top of the conductive plugs. The exposed portions are filled with a conductive material to a predetermined thickness. And, the dummy oxide layer and portions of the seed layer which are not covered with the conductive material are removed, thereby obtaining lower electrodes. A capacitor dielectric layer is on the lower electrodes. Finally, an upper electrode layer is formed on the capacitor dielectric layer.

Description

FIELD OF THE INVENTION

The present invention relates to a semiconductor device; and, more particularly, to a method for forming a lower electrode for use in a semiconductor device by using an electroplating method.

DESCRIPTION OF THE PRIOR ART

As is well known, a dynamic random access memory (DRAM) with at least one memory cell comprised of a transistor and a capacitor has a higher degree of integration mainly by downsizing through micronization. However, there is still a demand for downsizing the area of the memory cell.

To meet the demand, there have been proposed several structures for the capacitor, such as a trench type or a stack type capacitor, which are arranged three-dimensionally in a memory device to reduce the cell area available to the capacitor. However, the process of manufacturing three-dimensionally arranged capacitor is a long and tedious one and consequently involves high manufacturing cost. Therefore, there is a strong demand for a new memory device that can reduce the cell area with securing a requisite volume of information without requiring complex manufacturing steps.

Since capacitance is a function of dielectric area and the dielectric constant of the dielectric material, there have been introduced a high K dielectric, e.g., barium strontium titanate (BST) or the like, as a capacitor thin film in place of conventional silicon oxide film or silicon nitride film to increase capacitance in a given area. However, the use of high dielectric constant materials presents a problem when using a conventional material like ruthenium (Ru) as an electrode. The Ru electrode creates leakage current in the capacitance device.

Therefore, platinum (Pt) is suitable for use as electrodes in this situation. However, Pt is very difficult to be patterned by a conventional process such as a reactive ion etching (RIE), vertically, which, in turn, gives sloped sidewalls to a patterned thick Pt layer.

Thus, there remains a need for a method of forming an electrode compatible with a high K capacitor dielectric without representing the above-described problems.

SUMMARY OF THE INVENTION

It is, therefore, an object of the present invention to provide a semiconductor device incorporating therein lower electrodes which are formed by using an electroplating method.

In accordance with one aspect of the present invention, there is provided a method for manufacturing a semiconductor device for use in a memory cell, the method comprising the steps of: a) preparing an active matrix provided with at least one transistor, a plurality of conductive plugs electrically connected to the transistors and an insulating layer formed around the conductive plugs; b) forming a seed layer on top of the active matrix; c) forming a dummy oxide layer on top of the seed layer; d) patterning the dummy oxide layer into a predetermined configuration, thereby exposing portions of the seed layer which are located on top of the conductive plugs; e) filling the exposed portions with a first conductive material to a predetermined thickness; f) removing the dummy oxide layer; g) removing portions of the seed layer which are not covered with the conductive material, thereby obtaining lower electrodes; h) forming a capacitor dielectric layer on the lower electrodes; and i) forming a second conductive layer on the capacitor dielectric layer.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects and features of the present invention will become apparent from the following description of the preferred embodiments given in conjunction with the accompanying drawings, in which: [0009]
FIGS. 1A to [0010] 1H are schematic cross sectional views setting forth a method for the manufacture of the semiconductor memory device in accordance with the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

There are provided in FIGS. 1A to [0011] 1H cross sectional views setting forth a method for manufacturing a semiconductor device incorporating therein a lower electrode which is formed by using an electroplating method in accordance with preferred embodiments of the present invention.
FIGS. 1A to [0012] 1H are schematic cross sectional views setting forth the method for manufacture of a capacitor structure 150 for use in a semiconductor memory device 100 in accordance with the present invention.
The process for manufacturing the semiconductor device [0013] 100 begins with the preparation of an active matrix 110 including a silicon substrate 102, an isolation region 104, diffusion regions 106, gate oxides 108, gate lines 112, a sidewall 114, a bit line 118, poly plugs 116, barrier metals 126, anti-reflection coating (ARC) films 124 and an insulating layer 122, as shown in FIG. 1A. The bit line 118 is electrically connected to one of the diffusion regions 106 to apply an electric potential. Each of the poly plugs 116 is electrically connected to the other diffusion regions 106, respectively. Although the bit line 118 actually extends in right and left directions bypassing the poly plugs 116, the drawing does not show these parts of the bit line 118. The capacitor structures 140 can be connected to a plate line (not shown) to apply thereto a common constant potential. The insulating layer 122 is made of a material, e.g., boron-phosphor-silicate glass (BPSG).
In the preferred embodiment, the [0014] barrier metals 126 are formed on top of the poly plugs 116 and the ARC films 124 are formed on portions of the active matrix 110 which are not covered with the barrier metals 126. It is preferable that the barrier metals 126 are made of a material selected from a group consisting of TiN, TiSiN, TiAlN, TaSiN, TaAlN or the like. And also, the ARC films 124 are formed with a material having a high etch selectivity with respect to a dummy oxide layer to be formed thereon in a thickness ranging from approximately 300 Å to approximately 1,000 Å. In order to reduce contact resistance between the poly plugs 116 and the barrier metals 126, films 125, e.g., made of TiS_x, can be formed between the poly plugs 116 and the barrier metals 126 in a thickness ranging from approximately 100 Å to approximately 300 Å. After the formation of the barrier metals 126, a chemical mechanical polishing (CMP) can be carried out to make their top surface flatted.
In an ensuing step, a [0015] seed layer 130 is formed by using a chemical vapor deposition (CVD) method on top of the ARC films 124 and the barrier metals 126, as shown in FIG. 1B. The seed layer 130 can be made of a material selected from a group consisting of Pt, Ru, Ir, Os, W, Mo, Co, Ni, Au, Ag or the like. It is preferable that if Pt is selected as the seed layer 130, the seed layer 130 has a thickness ranging from approximately 50 Å to approximately 1,000 Å.
In a following step, a dummy oxide layer is formed on top of the [0016] seed layer 130 by using a method such as CVD. The dummy oxide layer can be made of PSG or USG. Preferably, the dummy oxide has a thickness ranging from approximately 5,000 Å to approximately 20,000 Å. Thereafter, the dummy oxide layer is patterned into a predetermined configuration in such a way that portions of the seed layer 130 located on top of the poly plugs 116 are exposed, thereby forming a patterned dummy oxide 132, as shown in FIG. 1C.
Optionally, the [0017] active matrix 110 is dipped into a solution selected from a 90% H₂SO₄solution, H₂SO₄/H₂O₂solution, HF/H₂O solution, HF/HN₄F solution during 2-3600 seconds in order to remove particles or foreign material remaining on the exposed seed layer 130.
In a next step, the exposed portions of the [0018] seed layer 130 are electroplated with a material selected from a group consisting of consisting of Pt, Ru, Ir, Os, W, Mo, Co, Ni, Au, Ag or the like, as shown in FIG. 1D. It is preferable that an electroplating material 134 corresponds to that of the seed layer 130. If the electroplating material is Pt, a thickness of the electroplating material 134 has a thickness ranging from approximately 3,000 Å to approximately 10,000 Å. In this case, the electroplating process is carried out with a current density ranging from approximately 0.1 mA/cm²to approximately 10 mA/cm². 20. Alternatively, it is possible to deposit a conductive material on top of the exposed positions of the seed layer 130 by using a CVD.
Thereafter, the patterned [0019] dummy oxide 132 is removed by using a method such as a wet etching, as shown in FIG. 1E.
And then, the portions of the [0020] seed layer 130 which are not covered by the electroplating material 134 are etched-back by using a method such as a dry etching, thereby forming lower electrodes 137, wherein each of the lower electrodes includes a electroplating material 134 and an etched seed layer 136, as shown in FIG. 1F.
In a subsequent step, a capacitor [0021] dielectric layer 138, e.g., made of barium strontium titanate (BST), are formed on the lower electrodes 137 and the ARC film 124 by using a CVD method at a temperature ranging from approximately 400° C. to approximately 600° C. in a thickness ranging from approximately 150 Å to approximately 500 Å, as shown in FIG. 1G. It is possible that the capacitor dielectric layer 138 are crystallized by using a rapid thermal process (RTP) at a temperature ranging from approximately 500° C. to approximately 700° C. in the presence of N₂for 30-180 seconds.
Finally, an [0022] upper electrode layer 140 is formed on the capacitor dielectric layer 138 by using a method such as a CVD, thereby forming capacitor structures 150, as shown in FIG. 1H.
While the present invention has been described with respect to the particular embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the scope of the invention as defined in the following claims. [0023]

Claims

What is claimed is:

1. A method for manufacturing a semiconductor device, the method comprising the steps of:

a) preparing an active matrix provided with at least one transistor, a plurality of conductive plugs electrically connected to the transistors and an insulating layer formed around the conductive plugs;

b) forming a seed layer on top of the active matrix;

c) forming a dummy oxide layer on the seed layer;

d) patterning the dummy oxide layer into a predetermined configuration, thereby exposing portions of the seed layer which are located on top of the conductive plugs;

e) filling the exposed portions with a conductive material to a predetermined thickness;

f) removing the dummy oxide layer;

g) removing portions of the seed layer which are not covered with the conductive material, thereby obtaining lower electrodes;

h) forming a capacitor dielectric on the lower electrodes; and

i) forming an upper electrode layer on the capacitor dielectric layer.

2. The method of

claim 1

, wherein the capacitor dielectric layer includes barium strontium titanate (BST).

3. The method of

claim 2

, before the step b), further comprising the step of forming barrier metals on top of the conductive plugs.

4. The method of

claim 3

, wherein the barrier metals includes a material selected from a group consisting of TiN, TiSiN, TiAlN, TaSiN, TaAlN or the like.

5. The method of

claim 3

, before the formation of the barrier metals, further comprising the step of forming a layer of TiS_xin a thickness ranging from approximately 100 Å to approximately 300 Å to reduce contact resistance between the conductive plugs and the barrier metals.

6. The method of

claim 2

, before the step b), further comprising the step of forming anti-reflection coating (ARC) films on portions of the active matrix which are not covered with the diffusion barriers.

7. The method of

claim 6

, wherein the ARC films includes a material having a high etch selectivity with respect to the dummy oxide layer and formed in a thickness ranging from approximately 300 Å to approximately 1,000 Å.

8. The method of

claim 7

, wherein the ARC films includes SiON.

9. The method of

claim 1

, wherein the seed layer includes a material selected from a group consisting of Pt, Ru, Ir, Os, W, Mo, Co, Ni, Au, Ag or the like.

10. The method of

claim 9

, wherein the step e) is carried out by electroplating the exposed portions with a conductive material corresponding to that of the seed layer.

11. The method of

claim 10

, wherein if the seed layer is made of Pt, the seed layer has a thickness ranging from approximately 50 Å to approximately 1,000 Å.

12. The method of

claim 10

, wherein the electroplating process is carried out with a current density ranging from approximately 0.1 mA/cm²to approximately 10 mA/cm².

13. The method of

claim 1

, wherein the dummy oxide layer includes PSG and has a thickness ranging from approximately 5,000 Å to approximately 20,000 Å.

14. The method of

claim 1

, wherein the dummy oxide layer includes USG and has a thickness ranging from approximately 5,000 Å to approximately 10,000 Å.

15. The method of

claim 14

, wherein a thickness of Pt ranges from approximately 3,000 Å to approximately 10,000 Å.

16. The method of

claim 1

, wherein the step g) is carried out by using a dry etch back.

17. The method of

claim 2

, wherein the capacitor dielectric layer is formed by using a chemical vapor deposition (CVD) at a temperature ranging from approximately 400° C. to approximately 600° C. in a thickness ranging from approximately 150 Å to approximately 500 Å.

18. The method of

claim 2

, further comprising the step of crystallizing the capacitor dielectric layer by using a rapid thermal process (RTP) at a temperature ranging from approximately 500° C. to approximately 700° C. in the presence of N₂for 30-180 seconds.

19. The method of

claim 1

, wherein the step e) is carried out by using a CVD.

20. The method of

claim 1

, between the steps d) and e), further comprising the step of dipping the exposed portions of seed layer into a solution selected from a group consisting of a 90% H₂SO₄solution, H₂SO₄/H₂O₂solution, HF/H₂O solution, HF/HN₄F solution during 2-3600 seconds to remove particles or foreign material remaining thereon.