US20010009804A1 - Manufacturing process of a semiconductor device - Google Patents
Manufacturing process of a semiconductor device Download PDFInfo
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- US20010009804A1 US20010009804A1 US08/916,708 US91670897A US2001009804A1 US 20010009804 A1 US20010009804 A1 US 20010009804A1 US 91670897 A US91670897 A US 91670897A US 2001009804 A1 US2001009804 A1 US 2001009804A1
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- groove
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- semiconductor device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76882—Reflowing or applying of pressure to better fill the contact hole
Definitions
- the present invention relates to a manufacturing method of a semiconductor device, and more particularly to a method of forming electrode wires on an insulating layer of the semiconductor device.
- a size of a connection hole formed in an insulating layer for electrical connection, between first and second conductive layers is also micronized.
- the electrical connection is between a first conductive layer, which is a conductive diffused layer on a principal plane of a semiconductor substrate or a metal film on a semiconductor element, etc., and a second conductive layer, which is a metal film, etc. located on an upper side of the insulating layer.
- connection hole With such a micronization of a connection hole, an aspect ratio of a connection hole (ratio of height to diameter of a connection hole) is increased.
- an attempt has been proposed to achieve an electrical connection between the first conductive layer and second conductive layer, in which the second conductive layer is formed by sputtering and a space in the connection hole is closed by the second conductive layer and is then buried under an atmosphere of high temperature and high pressure.
- the Japanese Laid-Open Patent Publication (unexamined) Toku-Hyou-Hei 7-503106 discloses a manufacturing process of a semiconductor device including the steps of closing an upper part of a space in the internal part of a connection hole with a second conductive layer formed by sputtering while leaving the internal space, and burying the second conductive layer into the connection hole, whereby an electrical connection between the first conductive layer and the second conductive layer is achieved.
- This prior manufacturing process is hereinafter discussed more specifically with reference to FIG. 10 to FIG. 14.
- a first conductive layer 11 is formed on the upper part of a semiconductor element 10 , an insulating layer 12 is further formed thereon, and a connection hole 13 is formed in the insulating layer 12 .
- a second conductive layer 14 is deposited by sputtering on the insulating layer 12 and in the internal part of the connection hole 13 .
- a thickness of the second conductive layer 14 deposited on the side wall 13 a and on the bottom face 13 b of the connection hole 13 is small as compared with that of the second conductive layer 14 coating the surface of the insulating layer 12 .
- a gap 15 of the second conductive layer 14 on the connection hole 13 is narrowed.
- the second conductive layer 14 is buried into the connection hole 13 until a state illustrated in FIG. 13 is achieved.
- a conductive wire 17 is formed by etching the second conductive layer 14 .
- the upper part of the hollow space 16 is closed with the second conductive layer 14 formed by sputtering while leaving the hollow space 16 in the internal part of the connection hole. Thereafter, the second conductive layer 14 is buried into the connection hole 13 by applying a high temperature and a high pressure, by which an electrical connection can be established between the first conductive layer 11 and the second conductive layer 14 through the connection hole 13 .
- the present invention was made to solve the above-stated problems and it is an object of the present invention to provide a novel manufacturing process of a semiconductor device having connecting electrode wires with less defects and with a high yield.
- An aspect of the present invention is a manufacturing process of a semiconductor device which includes a step of forming an insulating layer on a semiconductor substrate or on a semiconductor element formed on the semiconductor substrate. A groove having a connection hole at a bottom part thereof is formed, if required, in the insulating layer. An electrical conductor is formed along the surface of the groove and on the insulating layer. The conductor is buried into the groove by applying a high temperature and a high pressure to the conductor and an electrode wire is formed of the conductor by removing a part of the conductor by the CMP method.
- Another aspect of the present invention is a manufacturing process of a semiconductor device which includes a step of forming an insulating layer on a semiconductor substrate or on a semiconductor element formed on the semiconductor substrate.
- a groove having a connection hole is formed at a bottom part thereof, if required, in the insulating layer.
- An electrical conductor is formed along the surface of the groove and the insulating layer. The conductor is buried into the groove by applying a temperature of 300 to 850° C. and a pressure of 500 to 900 bar to the conductor and an electrode wire is formed of the conductor by removing a part of the conductor by the CMP method.
- FIGS. 1 and 2 a through 8 are sectional views of parts of a semiconductor device in an order of the manufacturing process of the present invention
- FIGS. 2 b and 2 c are further views of the device as shown in FIG. 2 a;
- FIG. 9 is a sectional view of parts of a semiconductor device in another embodiment of the manufacturing process of the present invention.
- FIGS. 10 through 14 are sectional views of essential parts of a semiconductor device in the order of the manufacturing process in the background art.
- FIG. 1 to FIG. 9 A first embodiment of the present invention is hereinafter described with reference to FIG. 1 to FIG. 9, each illustrating a semiconductor device in an order of manufacturing steps.
- a semiconductor substrate 1 made of a silicon for example, is provided, and a semiconductor element 2 , which is composed of a silicon oxide film or the like and a wired layer composed of Al-0.5 wt % Cu alloy for example, is formed on the semiconductor substrate 1 .
- an insulating layer 3 which is made of a silicon oxide film formed by plasma CVD, normal pressure CVD or the like employing TEOS or silane, for example, combined with organic SOG or inorganic SOG, is formed on the semiconductor element 2 .
- FIG. 2 a At least one groove 4 having a connection hole 40 at the bottom part thereof, if required, is formed utilizing a photomechanical process on the insulating layer 3 .
- a plan view of this construction is shown in FIG. 2 b and a cross sectional view along a groove 41 is shown in FIG. 2 c .
- a groove 41 runs along a main surface of the insulating layer 3 and the connecting hole 40 extends downwards to underlying semiconductor substrate 1 or semiconductor element 2 .
- the groove 41 and the connecting hole 40 are formed by a photomechanical process technology, and then the grooves 41 are formed corresponding to the wiring pattern.
- the width of the groove 41 is usually around 1 ⁇ m ranging from 0.1 ⁇ m to 50 ⁇ m.
- the diameter of the connecting hole is generally from 0.1 to 1 ⁇ m. It may happen that the width of the groove 41 is equal to the diameter of the connecting hole 40 .
- degassing After forming the groove 4 , materials such as water, nitrogen, hydrogen or other organic matters, etc., stuck to the surface of the semiconductor device under manufacture are removed by heating (hereinafter referred to as degassing). More specifically, the degassing is performed by heating at a temperature of 250 to 500° C. for 60 to 300 seconds under an atmosphere of inert gas such as Ar of 1 to 2 Torr.
- a natural oxide film 4 a is removed by sputtering or etching maintaining a high vacuum condition of 10-5 Torr (this state is hereinafter referred to as a continuous vacuum).
- the natural oxide film 4 a is formed on a part of the surface of the semiconductor element 2 at a bottom face of the mentioned connection hole 40 . More specifically, the natural oxide film 4 a of 50 to 300 ⁇ in terms of Si oxide film is removed using a low damage etching by ICP (Inductive Coupled Plasma) on conditions of 0.5 to 1.5 mTorr in Ar atmosphere, 300 to 500 W in ICP power, and 100 to 450 V in bias voltage.
- ICP Inductive Coupled Plasma
- a barrier layer 5 is formed on the bottom face of the groove 4 , which is a part of the surface of the semiconductor element 2 , and on the surface of the insulating layer 3 by sputtering under the continuous vacuum.
- the barrier layer 5 is formed of a barrier metal layer composed of TiN/Ti:1000 ⁇ /150 ⁇ , TiN/Ti:1000 ⁇ /200 ⁇ , TiN/Ti:500 ⁇ /150 ⁇ , or TiN/Ti:500 ⁇ /200 ⁇ .
- the temperature for heating the semiconductor substrate 1 at the time of the film formation may be 50 to 500° C., for example.
- a Ti layer is formed downside, that is in contact with the insulating layer and a TiN layer is formed upside. This barrier layer works to slide in a conductor layer in the later stage.
- a film thickness of the conductor 6 is more than 1.2 times as large as the diameter of the connection hole 40 and less than 3 ⁇ m.
- the conductor 6 more than 1.2 times thick covers the upper part of the groove 4 and a thickness of 3 ⁇ m is enough.
- a hollow space 7 may be formed in the groove 4 at this time, it does not matter herein.
- the hollow space 7 disappears by maintaining the conductor 6 under a high temperature and a high pressure in the continuous vacuum, and the groove 4 is filled with the conductor 6 . More specifically, the conductor 6 is maintained for 1 to 20 minutes at a temperature of 350 to 750° C. and a pressure of 650 to 900 bar under an atmosphere of inert gas such as Ar.
- polishing by the CMP method is performed so that the conductor 6 is left only in the groove 4 , whereby electrode wires 8 comprised of the conductor 6 are formed.
- propionic acid and H 2 0 2 are employed as an etchant for CMP, for example.
- an anti-reflection film 9 composed of Ti, for example, is formed on the electrode wires 8 and the insulating layer 3 , as illustrated in FIG. 7, and then the anti-reflection film 9 is left only on the electrode wires 8 by the conventional photomechanical process, see FIG. 8.
- This anti-reflection film 9 works to decrease reflecting light when another layer is formed thereon in the later stage.
- the groove 4 is formed in the insulating layer 3 located on the semiconductor element 2 , which is formed on the semiconductor substrate 1 , in the embodiment above, it is also possible that the insulating layer 3 is formed immediately on the semiconductor substrate 1 , and the groove 4 is formed in such an insulating layer 3 .
- an interval between one step and another i.e., between any two steps of degassing, removal of the natural oxide film 4 a, formation of the barrier layer 5 , and formation of the conductor 6 , is kept in the continuous vacuum state without cooling. It is, however, also possible that the semiconductor substrate 1 is cooled to 25 to 200° C. in the continuous vacuum state in the interval between a respective two steps. In a case of employing such a cooling between a respective two steps before the formation step of the barrier layer 5 , the barrier layer formation is performed at 25 to 200° C., while the barrier layer formation is performed at 300 to 600° C. in a case of employing no cooling.
- the conductor formation is performed at 25 to 200° C., while the conductor formation is performed at 300 to 600° C. in a case of employing no cooling.
- the same advantages as the foregoing arrangement are also achieved in this modification.
- the degassing is performed by heating at a temperature of 250 to 500° C. for 60 to 300 seconds under an atmosphere of inert gas such as Ar of 1 to 2 Torr in the foregoing embodiment, it is also possible that the degassing is performed by heating at a temperature of 200 to 600° C. for 30 to 600 seconds under an atmosphere of inert gas such as Ar of 1 to 10 Torr.
- inert gas such as Ar of 1 to 2 Torr
- the natural oxide film 4 a correspondingly to 50 to 300 ⁇ in terms of Si oxide film is removed in the foregoing embodiment on conditions of 0.5 to 1.5 mTorr in Ar atmosphere, 300 to 500 W in ICP power, and 100 to 450 V in bias voltage
- the natural oxide film 4 a corresponding to 30 to 400 ⁇ in terms of Si oxide film is removed on conditions of 0.1 to 5 mTorr in Ar atmosphere, 100 to 600 W in ICP power, and 50 to 600 V in bias voltage.
- the barrier layer 5 is formed of any of Tin/Ti:1000 ⁇ /150 ⁇ , TiN/Ti:1000 ⁇ /200 ⁇ , TiN/Ti:500 ⁇ /150 ⁇ or TiN/Ti:500 ⁇ /200 ⁇ in this embodiment, it is also possible that the barrier layer 5 is formed of a material composed of TiN/Ti:100 to 1000 ⁇ /20 to 500 ⁇ . The same advantages as the foregoing embodiment are also achieved in this modification.
- the barrier layer 5 is formed into the TiN/Ti structure in the foregoing embodiment, it is also possible that the barrier layer 5 is formed in a Ti or Ti/TiN/Ti structure. More specifically, it is possible to employ a structure of Ti/TiN/Ti:20 to 500 ⁇ /100 to 1500 ⁇ /20 to 500 ⁇ . Likewise, it is possible to employ Ti, W, Ta or TiW or nitride of any of them, or employ a composite film formed by stacking them.
- collimation sputtering low pressure sputtering or long range sputtering as a sputtering for forming the barrier layer 5 .
- a pressure is 1 to 8 mTorr
- a power is 8 to 20 kW
- a flow ratio of N 2 /N 2 +Ar is 0.2 to 0.9 in gas atmosphere
- a diameter of the opening of collimator:length thereof is 1:1 to 1:1.75 in an aspect ratio of the collimator.
- a pressure is 0.2 to 5 mTorr
- a power is 1 to 20 kW
- a flow ratio of N 2 /N 2 +Ar is 0.1 to 0.9 in gas atmosphere.
- conditions are established such that a pressure is 0.2 to 8 mTorr, a power is 8 to 20 kW, a flow ratio of N 2 /N 2 +Ar is 0.1 to 0.9 in gas atmosphere, and a distance between the semiconductor substrate 1 and a sputtering target is 40 to 400 nm.
- barrier layer 5 may be a composite film made of a film formed by sputtering and a film formed by the CVD method. Further, in a case of forming the barrier layer 5 by the CVD method, it is also possible that the semiconductor device under manufacture is once aerated (i.e., exposed to outside air) for degassing, and a barrier layer is further stacked on the barrier layer 5 by sputtering. The same advantages as the foregoing embodiment are also achieved in these modifications.
- barrier layer 5 is formed in the foregoing embodiment, it is not always necessary to form the barrier layer 5 .
- the same advantages as the foregoing embodiment are also achieved in this modification.
- the Cu serving as the conductor 6 is formed by the CVD method.
- Cu(HFA)TMVS is used as a raw material gas, and the substrate is heated at a temperature of 100 to 300° C. The same advantages as the foregoing embodiment are also achieved in this modification.
- a thickness of the conductor 6 is 1.2 times as large as a diameter of the connection hole 40 or more and 3 ⁇ m or less in the foregoing embodiment, it is also preferable that the thickness is 0.8 times as large as the diameter of the connection hole 40 or more and 5 ⁇ m or less. The same advantages as the foregoing embodiment are also achieved in this modification.
- a pure Cu is employed as the conductor 6 in the foregoing embodiment, it is also possible to employ a material which contains 0.01 to 2% Al, Ti, Sc, Pd, Si, Ta, Mn, Mg, Nb, Cr, Co, Ni, Ag, Pt, W, Au or V with respect to Cu. It is also possible to employ a material which contains not less than two of these mentioned elements at 0.1 to 2% each with respect to Cu. Further, the principal component of the conductor 6 may be Al, Ag, or Pt. The conductor 6 may be formed of pure Al, pure Ag or pure Pt.
- the Al may be formed by the CVD method, and in which case, for example, DMAH may be employed as raw material gas and the substrate may be heated at a temperature of 200 to 300° C. Further in this case, any additive element other than Al may be added by mixing a gas containing such an element at the time of formation by the CVD method. It is also possible that only film formation of the additive element is performed by sputtering and, then, Al is formed by the CVD method and is subject to a reaction by annealing. The same advantages as the foregoing embodiment are also achieved in these modifications.
- the conductor 6 is buried in the groove 4 under a high temperature and a high pressure in the foregoing embodiment, it is also possible to hold the conductor 6 under specific conditions of 300 to 850° C. in temperature and 50 M to 90 MPa in pressure for 1 to 40 minutes.
- an atmosphere of inert gas such as Ar is employed at the time of applying the high temperature and high pressure, it is also possible that, when the conductor 6 is made of pure copper or an alloy principally composed of Cu, an oxidizing atmosphere containing 2 to 30% oxygen other than the inert gas, a reducing atmosphere containing 2 to 30% hydrogen other than the inert gas, or an oxygen and reducing atmosphere containing both oxygen and nitrogen is employed.
- an atmosphere of inert gas such as Ar
- the anti-reflection film 9 is made of Ti in the foregoing embodiment, it is also possible to employ an oxide, nitride or oxide-nitride of Si, or Ti, Ta, W, TiW, Mo, C or an oxide or nitride of these elements. Further, it is also possible that the anti-reflection film 9 is formed into a shape shown in FIG. 8 by selectively forming it on the electrode wires by the CVD method.
- the anti-reflection film 9 made of the mentioned oxide, nitride or oxide-nitride of Si, it is also possible to advance to the next process with the anti-reflection film 9 stacked on the insulating layer 3 , without reforming the anti-reflection film 9 to leave only on the electrode wire 8 after forming the anti-reflection film 9 as illustrated in FIG. 7.
- the same advantages as the foregoing embodiment are also achieved in this modification.
- wires of a single layer are formed in the embodiment, it is also possible that, as illustrated in FIG. 9, wires of multiple layers are formed by employing the same wire formation method for forming the respective wires as shown in the first embodiment.
- the semiconductor device includes a lower insulating layer 31 having grooves 41 , in which lower electrode wires 81 are formed, and an upper insulating layer 32 having grooves 42 , in which upper electrode wires 82 are formed.
- the same advantages as the foregoing embodiment are also achieved in this modification.
- the manufacturing process of a semiconductor device in accordance with the present invention exhibits an effect that electrode wires of less defects and greater yield can be manufactured.
Abstract
An insulating layer is formed on a semiconductor element fabricated in a semiconductor substrate. A groove, with a connecting hole at the bottom part thereof when required, is formed in the insulating layer. A barrier layer is formed on the inner surface of the groove, and the connecting hole, and on the insulating layer. A conductive layer is formed in the groove and on the insulating layer, and is buried into the groove by applying high temperature and high pressure. Then, the conductive layer on the insulating layer is polished to leave the conductive layer in the groove by a CMP method to form an electrodes wire composed of the conductive layer material.
Description
- 1. Field of the Invention
- The present invention relates to a manufacturing method of a semiconductor device, and more particularly to a method of forming electrode wires on an insulating layer of the semiconductor device.
- 2. Description of the Background Art
- In recent years, with micronization of semiconductor devices, a size of a connection hole formed in an insulating layer for electrical connection, between first and second conductive layers, is also micronized. The electrical connection is between a first conductive layer, which is a conductive diffused layer on a principal plane of a semiconductor substrate or a metal film on a semiconductor element, etc., and a second conductive layer, which is a metal film, etc. located on an upper side of the insulating layer.
- With such a micronization of a connection hole, an aspect ratio of a connection hole (ratio of height to diameter of a connection hole) is increased. To meet this situation, an attempt has been proposed to achieve an electrical connection between the first conductive layer and second conductive layer, in which the second conductive layer is formed by sputtering and a space in the connection hole is closed by the second conductive layer and is then buried under an atmosphere of high temperature and high pressure.
- For example, the Japanese Laid-Open Patent Publication (unexamined) Toku-Hyou-Hei 7-503106 discloses a manufacturing process of a semiconductor device including the steps of closing an upper part of a space in the internal part of a connection hole with a second conductive layer formed by sputtering while leaving the internal space, and burying the second conductive layer into the connection hole, whereby an electrical connection between the first conductive layer and the second conductive layer is achieved. This prior manufacturing process is hereinafter discussed more specifically with reference to FIG. 10 to FIG. 14.
- First, as illustrated in FIG. 10, a first
conductive layer 11 is formed on the upper part of asemiconductor element 10, aninsulating layer 12 is further formed thereon, and aconnection hole 13 is formed in theinsulating layer 12. - Then, as illustrated in FIG. 11, a second
conductive layer 14 is deposited by sputtering on theinsulating layer 12 and in the internal part of theconnection hole 13. At this time, as illustrated in FIG. 11, a thickness of the secondconductive layer 14 deposited on theside wall 13 a and on the bottom face 13 b of theconnection hole 13 is small as compared with that of the secondconductive layer 14 coating the surface of theinsulating layer 12. While continuing the deposition of the secondconductive layer 14, agap 15 of the secondconductive layer 14 on theconnection hole 13 is narrowed. - When further continuing the deposition of the second
conductive layer 14 by sputtering, as illustrated in FIG. 12, thegap 15 of the second conductive layer on theconnection hole 13 comes to be closed while ahollow space 16 being left in the internal part of theconnection hole 13 comes to be closed while ahollow space 16 is left in the internal part of theconnection hole 13. - Then, on maintaining the semiconductor device in an atmosphere of high pressure, the second
conductive layer 14 is buried into theconnection hole 13 until a state illustrated in FIG. 13 is achieved. - Further, as illustrated in FIG. 14, a
conductive wire 17 is formed by etching the secondconductive layer 14. - In the above-mentioned manufacturing process of a semiconductor device, the upper part of the
hollow space 16 is closed with the secondconductive layer 14 formed by sputtering while leaving thehollow space 16 in the internal part of the connection hole. Thereafter, the secondconductive layer 14 is buried into theconnection hole 13 by applying a high temperature and a high pressure, by which an electrical connection can be established between the firstconductive layer 11 and the secondconductive layer 14 through theconnection hole 13. - However, in the mentioned manufacturing process of a semiconductor device, a problem exists in that etching is required to form the
conductive wire 17 formed from thesecond conductor 14, and theconductive wire 17 formed by etching may be defective and is of a low yield. - The present invention was made to solve the above-stated problems and it is an object of the present invention to provide a novel manufacturing process of a semiconductor device having connecting electrode wires with less defects and with a high yield.
- An aspect of the present invention is a manufacturing process of a semiconductor device which includes a step of forming an insulating layer on a semiconductor substrate or on a semiconductor element formed on the semiconductor substrate. A groove having a connection hole at a bottom part thereof is formed, if required, in the insulating layer. An electrical conductor is formed along the surface of the groove and on the insulating layer. The conductor is buried into the groove by applying a high temperature and a high pressure to the conductor and an electrode wire is formed of the conductor by removing a part of the conductor by the CMP method.
- Another aspect of the present invention is a manufacturing process of a semiconductor device which includes a step of forming an insulating layer on a semiconductor substrate or on a semiconductor element formed on the semiconductor substrate. A groove having a connection hole is formed at a bottom part thereof, if required, in the insulating layer. An electrical conductor is formed along the surface of the groove and the insulating layer. The conductor is buried into the groove by applying a temperature of 300 to 850° C. and a pressure of 500 to 900 bar to the conductor and an electrode wire is formed of the conductor by removing a part of the conductor by the CMP method.
- A more complete appreciation of the present invention and many of the attendant advantages thereof will be readily obtained as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings, wherein:
- FIGS. 1 and 2a through 8 are sectional views of parts of a semiconductor device in an order of the manufacturing process of the present invention;
- FIGS. 2b and 2 c are further views of the device as shown in FIG. 2a;
- FIG. 9 is a sectional view of parts of a semiconductor device in another embodiment of the manufacturing process of the present invention; and
- FIGS. 10 through 14 are sectional views of essential parts of a semiconductor device in the order of the manufacturing process in the background art.
- A first embodiment of the present invention is hereinafter described with reference to FIG. 1 to FIG. 9, each illustrating a semiconductor device in an order of manufacturing steps.
- First, as illustrated in FIG. 1, a
semiconductor substrate 1, made of a silicon for example, is provided, and asemiconductor element 2, which is composed of a silicon oxide film or the like and a wired layer composed of Al-0.5 wt % Cu alloy for example, is formed on thesemiconductor substrate 1. Further, aninsulating layer 3, which is made of a silicon oxide film formed by plasma CVD, normal pressure CVD or the like employing TEOS or silane, for example, combined with organic SOG or inorganic SOG, is formed on thesemiconductor element 2. - Then, as illustrated in FIG. 2a, at least one groove 4 having a
connection hole 40 at the bottom part thereof, if required, is formed utilizing a photomechanical process on theinsulating layer 3. A plan view of this construction is shown in FIG. 2b and a cross sectional view along agroove 41 is shown in FIG. 2c. As seen in these drawings, agroove 41 runs along a main surface of theinsulating layer 3 and the connectinghole 40 extends downwards to underlyingsemiconductor substrate 1 orsemiconductor element 2. Thegroove 41 and the connectinghole 40 are formed by a photomechanical process technology, and then thegrooves 41 are formed corresponding to the wiring pattern. The width of thegroove 41 is usually around 1 μm ranging from 0.1 μm to 50 μm. The diameter of the connecting hole is generally from 0.1 to 1 μm. It may happen that the width of thegroove 41 is equal to the diameter of the connectinghole 40. - After forming the groove4, materials such as water, nitrogen, hydrogen or other organic matters, etc., stuck to the surface of the semiconductor device under manufacture are removed by heating (hereinafter referred to as degassing). More specifically, the degassing is performed by heating at a temperature of 250 to 500° C. for 60 to 300 seconds under an atmosphere of inert gas such as Ar of 1 to 2 Torr.
- In this step, if required, a natural oxide film4 a is removed by sputtering or etching maintaining a high vacuum condition of 10-5 Torr (this state is hereinafter referred to as a continuous vacuum). The natural oxide film 4 a is formed on a part of the surface of the
semiconductor element 2 at a bottom face of the mentionedconnection hole 40. More specifically, the natural oxide film 4 a of 50 to 300 Å in terms of Si oxide film is removed using a low damage etching by ICP (Inductive Coupled Plasma) on conditions of 0.5 to 1.5 mTorr in Ar atmosphere, 300 to 500 W in ICP power, and 100 to 450 V in bias voltage. - Then, as illustrated in FIG. 3, a barrier layer5 is formed on the bottom face of the groove 4, which is a part of the surface of the
semiconductor element 2, and on the surface of theinsulating layer 3 by sputtering under the continuous vacuum. The barrier layer 5 is formed of a barrier metal layer composed of TiN/Ti:1000 Å/150 Å, TiN/Ti:1000 Å/200 Å, TiN/Ti:500 Å/150 Å, or TiN/Ti:500 Å/200 Å. The temperature for heating thesemiconductor substrate 1 at the time of the film formation may be 50 to 500° C., for example. A Ti layer is formed downside, that is in contact with the insulating layer and a TiN layer is formed upside. This barrier layer works to slide in a conductor layer in the later stage. - Then, as illustrated in FIG. 4, a conductor6 composed of pure Cu, for example, is formed in the groove 4 and on the
insulating layer 3 under the continuous vacuum. More specifically, first, a film of 50 to 200 nm is formed by sputtering under Ar atmosphere of 1 to 10 mTorr, with an ICP power of 5 to 20 kW and at a heating temperature of 25 to 150° C. Then, a film of desired thickness is formed by sputtering at a heating temperature of 300 to 450° C. The thickness of the formed film ranges from 300 nm to 2 μm. In this regard, the maximum temperature of thesemiconductor substrate 1 is limited to 600° C. - A film thickness of the conductor6 is more than 1.2 times as large as the diameter of the
connection hole 40 and less than 3 μm. The conductor 6 more than 1.2 times thick covers the upper part of the groove 4 and a thickness of 3 μm is enough. Although ahollow space 7 may be formed in the groove 4 at this time, it does not matter herein. - The reason why the conductor6 is heated at a relatively low temperature in the initial stage of the film formation for forming the conductor 6 is described hereinbelow.
- When the
semiconductor substrate 1 is exposed to the plasma atmosphere at the time of film formation, an actual temperature of thesemiconductor substrate 1 rises higher than the heating temperature and a gas is produced from the side wall of the groove 4 or from the barrier layer 5, whereby the conductor 6 is oxidized or nitrified by the gas, resulting in deterioration of burying characteristic. - Therefore, first, 50 to 200 nm of the conductor6 is formed at a low temperature, thereby coating the side wall of the groove 4 and the barrier layer 5 with the conductor 6 to restrain the production of gas, and then the conductor 6 of satisfactory crystallization is formed by heating the
semiconductor substrate 1. - Then, as illustrated in FIG. 5, the
hollow space 7 disappears by maintaining the conductor 6 under a high temperature and a high pressure in the continuous vacuum, and the groove 4 is filled with the conductor 6. More specifically, the conductor 6 is maintained for 1 to 20 minutes at a temperature of 350 to 750° C. and a pressure of 650 to 900 bar under an atmosphere of inert gas such as Ar. - Then, as illustrated in FIG. 6, polishing by the CMP method is performed so that the conductor6 is left only in the groove 4, whereby
electrode wires 8 comprised of the conductor 6 are formed. In this step, propionic acid and H2 0 2 are employed as an etchant for CMP, for example. - If required, after the polishing by the CMP, an
anti-reflection film 9 composed of Ti, for example, is formed on theelectrode wires 8 and the insulatinglayer 3, as illustrated in FIG. 7, and then theanti-reflection film 9 is left only on theelectrode wires 8 by the conventional photomechanical process, see FIG. 8. Thisanti-reflection film 9 works to decrease reflecting light when another layer is formed thereon in the later stage. - In the manufacturing process of a semiconductor device as stated above, since the conductor6 is buried in the groove 4 under a high temperature and a high pressure,
electrode wires 8 of a large grain of conductor material and of less defects such as void can be formed with a high yield. Further, the polishing is performed by the CMP method to leave the conductor 6 only in the groove 4 so that theelectrode wires 8 of a plane surface can be formed. - Although the groove4 is formed in the insulating
layer 3 located on thesemiconductor element 2, which is formed on thesemiconductor substrate 1, in the embodiment above, it is also possible that the insulatinglayer 3 is formed immediately on thesemiconductor substrate 1, and the groove 4 is formed in such aninsulating layer 3. - Further, in this embodiment, an interval between one step and another, i.e., between any two steps of degassing, removal of the natural oxide film4 a, formation of the barrier layer 5, and formation of the conductor 6, is kept in the continuous vacuum state without cooling. It is, however, also possible that the
semiconductor substrate 1 is cooled to 25 to 200° C. in the continuous vacuum state in the interval between a respective two steps. In a case of employing such a cooling between a respective two steps before the formation step of the barrier layer 5, the barrier layer formation is performed at 25 to 200° C., while the barrier layer formation is performed at 300 to 600° C. in a case of employing no cooling. Furthermore, when in a case of performing such a cooling between a respective two steps before the formation step of the conductor 6, the conductor formation is performed at 25 to 200° C., while the conductor formation is performed at 300 to 600° C. in a case of employing no cooling. The same advantages as the foregoing arrangement are also achieved in this modification. - Although the degassing is performed by heating at a temperature of 250 to 500° C. for 60 to 300 seconds under an atmosphere of inert gas such as Ar of 1 to 2 Torr in the foregoing embodiment, it is also possible that the degassing is performed by heating at a temperature of 200 to 600° C. for 30 to 600 seconds under an atmosphere of inert gas such as Ar of 1 to 10 Torr. The same advantages as the foregoing embodiment are also achieved in this modification.
- Although a portion of the natural oxide film4 a correspondingly to 50 to 300 Å in terms of Si oxide film is removed in the foregoing embodiment on conditions of 0.5 to 1.5 mTorr in Ar atmosphere, 300 to 500 W in ICP power, and 100 to 450 V in bias voltage, it is also possible that the natural oxide film 4 a corresponding to 30 to 400 Å in terms of Si oxide film is removed on conditions of 0.1 to 5 mTorr in Ar atmosphere, 100 to 600 W in ICP power, and 50 to 600 V in bias voltage.
- Further, it is also possible to omit the step of removing the natural oxide film4 a as long as there is no problem in the electrical connection between the
semiconductor element 2 and theelectrode wires 8. The same advantages as the foregoing embodiment are also achieved in this modification. - Although the barrier layer5 is formed of any of Tin/Ti:1000 Å/150 Å, TiN/Ti:1000 Å/200 Å, TiN/Ti:500 Å/150 Å or TiN/Ti:500 Å/200 Å in this embodiment, it is also possible that the barrier layer 5 is formed of a material composed of TiN/Ti:100 to 1000 Å/20 to 500 Å. The same advantages as the foregoing embodiment are also achieved in this modification.
- Although the barrier layer5 is formed into the TiN/Ti structure in the foregoing embodiment, it is also possible that the barrier layer 5 is formed in a Ti or Ti/TiN/Ti structure. More specifically, it is possible to employ a structure of Ti/TiN/Ti:20 to 500 Å/100 to 1500 Å/20 to 500 Å. Likewise, it is possible to employ Ti, W, Ta or TiW or nitride of any of them, or employ a composite film formed by stacking them.
- From the viewpoint of improvement in coverage, it is also possible to employ collimation sputtering, low pressure sputtering or long range sputtering as a sputtering for forming the barrier layer5. More specifically, in a case of employing the collimation sputtering, for example, at the time of sputtering, conditions are established such that a pressure is 1 to 8 mTorr, a power is 8 to 20 kW, a flow ratio of N2/N2+Ar is 0.2 to 0.9 in gas atmosphere, and a diameter of the opening of collimator:length thereof is 1:1 to 1:1.75 in an aspect ratio of the collimator. In a case of employing the low pressure sputtering, for example, at the time of sputtering, conditions are established such that a pressure is 0.2 to 5 mTorr, a power is 1 to 20 kW, and a flow ratio of N2/N2+Ar is 0.1 to 0.9 in gas atmosphere. In a case of employing the long range sputtering, for example, at the time of sputtering, conditions are established such that a pressure is 0.2 to 8 mTorr, a power is 8 to 20 kW, a flow ratio of N2/N2+Ar is 0.1 to 0.9 in gas atmosphere, and a distance between the
semiconductor substrate 1 and a sputtering target is 40 to 400 nm. The same advantages as the foregoing embodiment are also achieved in these modifications. - Although sputtering is employed as a formation process of the barrier layer5 in the foregoing embodiment, it is also possible to employ a CVD method using an organic gas including TiCl4 or Ti as a raw material gas. The barrier layer 5 may be a composite film made of a film formed by sputtering and a film formed by the CVD method. Further, in a case of forming the barrier layer 5 by the CVD method, it is also possible that the semiconductor device under manufacture is once aerated (i.e., exposed to outside air) for degassing, and a barrier layer is further stacked on the barrier layer 5 by sputtering. The same advantages as the foregoing embodiment are also achieved in these modifications.
- Although the barrier layer5 is formed in the foregoing embodiment, it is not always necessary to form the barrier layer 5. The same advantages as the foregoing embodiment are also achieved in this modification.
- Although sputtering is employed as a formation of the Cu serving as the conductor6 in the foregoing embodiment, it is also possible that the Cu is formed by the CVD method. In this case, Cu(HFA)TMVS is used as a raw material gas, and the substrate is heated at a temperature of 100 to 300° C. The same advantages as the foregoing embodiment are also achieved in this modification.
- Although a thickness of the conductor6 is 1.2 times as large as a diameter of the
connection hole 40 or more and 3 μm or less in the foregoing embodiment, it is also preferable that the thickness is 0.8 times as large as the diameter of theconnection hole 40 or more and 5 μm or less. The same advantages as the foregoing embodiment are also achieved in this modification. - Although a pure Cu is employed as the conductor6 in the foregoing embodiment, it is also possible to employ a material which contains 0.01 to 2% Al, Ti, Sc, Pd, Si, Ta, Mn, Mg, Nb, Cr, Co, Ni, Ag, Pt, W, Au or V with respect to Cu. It is also possible to employ a material which contains not less than two of these mentioned elements at 0.1 to 2% each with respect to Cu. Further, the principal component of the conductor 6 may be Al, Ag, or Pt. The conductor 6 may be formed of pure Al, pure Ag or pure Pt.
- In a case of employing Al as the principal component of the conductor6, the Al may be formed by the CVD method, and in which case, for example, DMAH may be employed as raw material gas and the substrate may be heated at a temperature of 200 to 300° C. Further in this case, any additive element other than Al may be added by mixing a gas containing such an element at the time of formation by the CVD method. It is also possible that only film formation of the additive element is performed by sputtering and, then, Al is formed by the CVD method and is subject to a reaction by annealing. The same advantages as the foregoing embodiment are also achieved in these modifications.
- Although the conductor6 is buried in the groove 4 under a high temperature and a high pressure in the foregoing embodiment, it is also possible to hold the conductor 6 under specific conditions of 300 to 850° C. in temperature and 50 M to 90 MPa in pressure for 1 to 40 minutes. Further, although an atmosphere of inert gas such as Ar is employed at the time of applying the high temperature and high pressure, it is also possible that, when the conductor 6 is made of pure copper or an alloy principally composed of Cu, an oxidizing atmosphere containing 2 to 30% oxygen other than the inert gas, a reducing atmosphere containing 2 to 30% hydrogen other than the inert gas, or an oxygen and reducing atmosphere containing both oxygen and nitrogen is employed. The same advantages as the foregoing embodiment are also achieved in these modifications.
- In the foregoing embodiment, it is also possible to employ as an etchant for the CMP method, a mixture of acetic acid and hydrogen peroxide water (acetic acid: water: hydrogen peroxide water=0.3 to0.6:10:0.01 to 0.1), acetic acid (acetic acid : water=0.3 to 0.6:10), a mixture of nitric acid and hydrogen peroxide water (nitric acid water:hydrogen peroxide water=0.1 to 10:120:0.01 to 1), or a mixture of ammonium persulfate and hydrogen peroxide water (ammonium persulfate water : hydrogen peroxide=0.1 to 5:350:0.01 to 0.1). The same advantages as the foregoing embodiment are also achieved in these modifications.
- Although the
anti-reflection film 9 is made of Ti in the foregoing embodiment, it is also possible to employ an oxide, nitride or oxide-nitride of Si, or Ti, Ta, W, TiW, Mo, C or an oxide or nitride of these elements. Further, it is also possible that theanti-reflection film 9 is formed into a shape shown in FIG. 8 by selectively forming it on the electrode wires by the CVD method. Furthermore, in a case of theanti-reflection film 9 made of the mentioned oxide, nitride or oxide-nitride of Si, it is also possible to advance to the next process with theanti-reflection film 9 stacked on the insulatinglayer 3, without reforming theanti-reflection film 9 to leave only on theelectrode wire 8 after forming theanti-reflection film 9 as illustrated in FIG. 7. The same advantages as the foregoing embodiment are also achieved in this modification. - Although wires of a single layer are formed in the embodiment, it is also possible that, as illustrated in FIG. 9, wires of multiple layers are formed by employing the same wire formation method for forming the respective wires as shown in the first embodiment. In the construction as shown in FIG. 9, the semiconductor device includes a lower insulating
layer 31 havinggrooves 41, in which lower electrode wires 81 are formed, and an upper insulatinglayer 32 havinggrooves 42, in whichupper electrode wires 82 are formed. The same advantages as the foregoing embodiment are also achieved in this modification. - As described above, the manufacturing process of a semiconductor device in accordance with the present invention exhibits an effect that electrode wires of less defects and greater yield can be manufactured.
- Obviously, numerous additional modifications and variations of the present invention are possible in light of the above teachings. It is therefore to be understood that within the scope of the appended claims, the present invention may be practiced otherwise than as specifically described herein.
Claims (20)
1. A process for manufacturing a semiconductor device comprising the steps of:
forming an insulating layer on a semiconductor substrate or on a semiconductor element formed on the semiconductor substrate;
forming a groove on said insulating layer;
forming a conductur on a surface of said groove and on said insulating layer burying said conductor into said groove by applying a high temperature and a high pressure to said conductor; and
forming electrode wires comprised of said conductor by removing a part of said conductor by a CMP method.
2. A process for manufacturing a semiconductor device as defined in , wherein said conductor contains an alloy principally composed of a material selected from the group consisting of Cu, Al, Ag and Pt or contains a metal selected from the group consisting of pure Cu, pure Al, pure Ag and pure Pt.
claim 1
3. A process for manufacturing a semiconductor device as defined in , wherein said conductor is formed at a low temperature in a first stage of the forming step thereof and at a high temperature in a second subsequent stage of the forming step thereof.
claim 1
4. A process for manufacturing a semiconductor device as defined in , wherein said conductor is formed first at a temperature of 25 to 150° C. by 50 to 200 nm and is then formed at a higher temperature to a desired thickness.
claim 1
5. A process for manufacturing a semiconductor device as defined in , wherein a temperature and a pressure applied for burying said conductor into said groove are respectively 300 to 850° C. and 650 to 900 bar.
claim 1
6. A process for manufacturing a semiconductor device as defined in , wherein a temperature and a pressure applied for burying said conductor into said groove are respectively 350 to 750° C. and 650 to 900 bar.
claim 1
7. A process for manufacturing a semiconductor device as defined in , further comprising a step of forming an anti-reflection film on said electrode wires.
claim 1
8. A process for manufacturing a semiconductor device comprising the steps of:
forming an insulating layer on a semiconductor substrate or on a semiconductor element formed on the semiconductor substrate;
forming a groove on said insulating layer;
forming a barrier layer on a surface of said groove;
forming a conductor on said barrier layer and said insulating layer;
burying said conductor into said groove by applying a high temperature and a high pressure to said conductor; and
forming electrode wires comprised of said conductor by removing a part of said conductor by a CMP method.
9. A process for manufacturing a semiconductor device as defined in , wherein said barrier layer is composed of a material selected from the group consisting of TiN/Ti,Ti and Ti/TiN/Ti.
claim 8
10. A process for manufacturing a semiconductor device comprising the steps of:
forming an insulating layer on a semiconductor substrate or on a semiconductor element formed on the semiconductor substrate;
forming a groove on said insulating layer;
forming a connection hole at a bottom of the groove;
forming a conductor on surfaces of said groove and said connecting hole and on said insulating layer;
burying said conductor into said groove and said connecting hole by applying a high temperature and a high pressure to said conductor; and
forming electrode wires comprised of said conductor by removing a part of said conductor by a CMP method.
11. A process for manufacturing a semiconductor device as defined in , wherein said conductor contains an alloy principally composed of a material selected from the group consisting of Cu, Al, Ag and Pt or contains a metal selected from the group consisting of pure Cu, pure Al, pure Ag and pure Pt.
claim 10
12. A process for manufacturing a semiconductor device as defined in , wherein a thickness of said conductor layer is more than 0.8 times of a diameter of said connection hole and less than 5 μm
claim 10
13. A process for manufacturing a semiconductor device as defined in , wherein a thickness of said conductor layer is more than 1.2 times of a diameter of said connection hole and less than 3 μm.
claim 10
14. A process for manufacturing a semiconductor device as defined in claims 10, wherein said conductor is formed at a low temperature in a first stage of the forming step thereof and at a high temperature in a second subsequent stage of the forming step thereof.
15. A process for manufacturing a semiconductor device as defined in , wherein said conductor is formed first at a temperature of 25 to 150° C. by 50 to 200 nm and is then formed at a higher temperature to a desired thickness.
claim 10
16. A process for manufacturing a semiconductor device as defined in , wherein a temperature and a pressure applied for burying said conductor into said groove are respectively 300 to 850° C. and 50 M to 90 Mpa.
claim 10
17. A process for manufacturing a semiconductor device as defined in , wherein a temperature and a pressure applied for burying said conductor into said groove are respectively 350 to 750° C. and 65 M to 90 MPa.
claim 10
18. A process for manufacturing a semiconductor device as defined in , further comprising a step of forming an anti-reflection film on said electrode wires.
claim 10
19. A process for manufacturing a semiconductor device comprising the steps of:
forming an insulating layer on a semiconductor substrate or on a semiconductor element formed on the semiconductor substrate;
forming a groove on said insulating layer;
forming a connection hole at a bottom of said groove;
forming a barrier layer surfaces of said groove and said connecting hole;
forming a conductor on surfaces of said groove and said connecting hole and on said insulating layer;
burying said conductor into said groove and said connecting hole by applying a high temperature and a high pressure to said conductor; and
forming electrode wires comprised of said conductor by removing a part of said conductor by a CMP method.
20. A process for manufacturing a semiconductor device as defined in , wherein said barrier layer is composed of a metal selected from the group consisting of TiN/Ti,Ti and Ti/TiN/Ti.
claim 19
Priority Applications (1)
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US08/916,708 US6329284B2 (en) | 1995-10-17 | 1997-08-25 | Manufacturing process of a semiconductor device |
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JP7268160A JPH09115866A (en) | 1995-10-17 | 1995-10-17 | Semiconductor device manufacturing method |
JP7-268160 | 1995-10-17 | ||
US63693496A | 1996-04-24 | 1996-04-24 | |
US08/916,708 US6329284B2 (en) | 1995-10-17 | 1997-08-25 | Manufacturing process of a semiconductor device |
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US63693496A Continuation | 1995-10-17 | 1996-04-24 |
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JP (1) | JPH09115866A (en) |
KR (1) | KR100240128B1 (en) |
DE (1) | DE19629886A1 (en) |
TW (1) | TW445621B (en) |
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US6909191B2 (en) * | 2000-03-27 | 2005-06-21 | Kabushiki Kaisha Toshiba | Semiconductor device |
US20090308636A1 (en) * | 2008-06-12 | 2009-12-17 | International Business Machines Corporation | In-situ silicon cap for metal gate electrode |
CN109196634A (en) * | 2016-06-10 | 2019-01-11 | 应用材料公司 | In the seam restorative procedure crossed in atmospheric pressure technique in promoting diffusional environment |
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KR100230392B1 (en) * | 1996-12-05 | 1999-11-15 | 윤종용 | The method of forming contact plug in semiconductor device |
US5854140A (en) * | 1996-12-13 | 1998-12-29 | Siemens Aktiengesellschaft | Method of making an aluminum contact |
US6140234A (en) * | 1998-01-20 | 2000-10-31 | International Business Machines Corporation | Method to selectively fill recesses with conductive metal |
US7338908B1 (en) * | 2003-10-20 | 2008-03-04 | Novellus Systems, Inc. | Method for fabrication of semiconductor interconnect structure with reduced capacitance, leakage current, and improved breakdown voltage |
JP2001148367A (en) * | 1999-11-22 | 2001-05-29 | Nec Corp | Processing method and apparatus for semiconductor device |
US6461225B1 (en) * | 2000-04-11 | 2002-10-08 | Agere Systems Guardian Corp. | Local area alloying for preventing dishing of copper during chemical-mechanical polishing (CMP) |
JP2002353245A (en) * | 2001-03-23 | 2002-12-06 | Seiko Epson Corp | Electro-optic substrate device, its manufacturing method, electro-optic device, electronic apparatus, and method for manufacturing substrate device |
US6627550B2 (en) * | 2001-03-27 | 2003-09-30 | Micron Technology, Inc. | Post-planarization clean-up |
KR100446316B1 (en) * | 2002-03-30 | 2004-09-01 | 주식회사 하이닉스반도체 | Method for forming a contact plug in semiconductor device |
US7972970B2 (en) | 2003-10-20 | 2011-07-05 | Novellus Systems, Inc. | Fabrication of semiconductor interconnect structure |
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US8372757B2 (en) | 2003-10-20 | 2013-02-12 | Novellus Systems, Inc. | Wet etching methods for copper removal and planarization in semiconductor processing |
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DE102004002464B4 (en) * | 2004-01-16 | 2005-12-08 | Infineon Technologies Ag | Method for filling contact holes |
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-
1995
- 1995-10-17 JP JP7268160A patent/JPH09115866A/en active Pending
-
1996
- 1996-02-07 TW TW085101604A patent/TW445621B/en not_active IP Right Cessation
- 1996-07-24 DE DE19629886A patent/DE19629886A1/en not_active Withdrawn
- 1996-08-23 KR KR1019960035059A patent/KR100240128B1/en not_active IP Right Cessation
-
1997
- 1997-08-25 US US08/916,708 patent/US6329284B2/en not_active Expired - Fee Related
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US6909191B2 (en) * | 2000-03-27 | 2005-06-21 | Kabushiki Kaisha Toshiba | Semiconductor device |
US20090308636A1 (en) * | 2008-06-12 | 2009-12-17 | International Business Machines Corporation | In-situ silicon cap for metal gate electrode |
US8138041B2 (en) * | 2008-06-12 | 2012-03-20 | International Business Machines Corporation | In-situ silicon cap for metal gate electrode |
CN109196634A (en) * | 2016-06-10 | 2019-01-11 | 应用材料公司 | In the seam restorative procedure crossed in atmospheric pressure technique in promoting diffusional environment |
Also Published As
Publication number | Publication date |
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TW445621B (en) | 2001-07-11 |
US6329284B2 (en) | 2001-12-11 |
JPH09115866A (en) | 1997-05-02 |
DE19629886A1 (en) | 1997-04-24 |
KR100240128B1 (en) | 2000-01-15 |
KR970023743A (en) | 1997-05-30 |
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