US20010003657A1 - Method for manufacturing a thin-film transistor - Google Patents

Method for manufacturing a thin-film transistor Download PDF

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US20010003657A1
US20010003657A1 US09/731,693 US73169300A US2001003657A1 US 20010003657 A1 US20010003657 A1 US 20010003657A1 US 73169300 A US73169300 A US 73169300A US 2001003657 A1 US2001003657 A1 US 2001003657A1
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insulating layer
doping
channel region
layer
ions
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US6451630B2 (en
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Jeong-No Lee
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Samsung Display Co Ltd
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Samsung SDI Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile

Definitions

  • the present invention relates to a thin-film transistor (TFT) and, more particularly, to a method for manufacturing a TFT that can reduce the number of photolithography processes, that can easily adjust a width of an lightly doped drain region and planarize the film surface.
  • TFT thin-film transistor
  • TFTs are widely used as a switching element for turning On/Off pixels of a flat panel display such as an active matrix liquid crystal display, because they can contain CMOS on the substrate.
  • the TFT should be able to withstand a high voltage and to provide a high ratio of On currents to Off current.
  • such a TFT is manufactured through a number of photolithography processes, each comprising a plurality of steps such as a photoresist step, a light-exposing step, and an etching step. As the number of processes increases, the overall productivity is lowered and the quality of the TFT is deteriorated.
  • the present invention provides a method for manufacturing a thin film transistor comprising the steps of forming a channel region on a surface of a substrate, depositing an insulating layer on the surface of the substrate while covering the channel region and patterning the insulating layer such that a portion of the channel region is exposed, depositing a silicon layer on the insulating layer, depositing a metal layer on the silicon layer and etching the silicon and metal layers to define source, drain and gate electrode sections, doping positive ions on a portion corresponding to a MOS circuit portion, depositing an intermediate insulating layer on the metal layer while covering the source, drain and gate electrode sections and patterning the intermediate insulating layer to form a plurality of contact holes, and depositing an electrode material on the intermediate insulating layer and patterning the electrode material to define a pixel electrode section and a wire section.
  • the method may further comprise the step of doping negative ions to define an LDD region at an exposed portion of the channel region before doping the positive ions.
  • the step of doping the positive ions comprises the step of doping n+ ions on an NMOS circuit section.
  • the step of doping the positive ions Ad comprises the step of doping p+ ions on a PMOS circuit section.
  • FIGS. 1 a through 1 g illustrate cross-sectional views of a portion of a TFT as it undergoes sequential processing steps according to a preferred embodiment of the present invention.
  • a CMOS TFT includes a pixel section, a wire section, a PMOS circuit section, and an NMOS circuit section.
  • FIGS. 1 a to 1 g are cross-sectional views of a portion of a CMOS TFT as it undergoes sequential processing steps.
  • a buffer layer 22 is first deposited on a substrate 20 , then a pattern of a channel region 24 is formed on the buffer layer 22 .
  • an active layer is first deposited on the buffer layer 22 using an amorphous silicon, then crystallized by an eximer laser, and patterned through a photolithography process.
  • the buffer layer 22 may be omitted.
  • an insulating layer is deposited on the buffer layer 22 while covering the channel region 24 , then patterned such that the channel region 24 is exposed except for its edges and middle portion as shown in FIG. 1 b.
  • an n+ or p+ silicon layer 28 is deposited on the insulating layer 26 and the channel region 24 , and a metal layer 33 is deposited on the n+ or p+ silicon layer 28 . Then, the silicon and metal layers 28 and 33 are simultaneously etched to define drain, source and gate electrode regions 30 , 32 and 34 .
  • the silicon layer 28 is used for ohmic contacts between the channel region 24 and each of the drain and source electrode regions 30 and 32 .
  • the silicon layer 28 formed under the gate electrode 34 of an NMOS circuit section is the n+ silicon layer
  • the silicon layer 28 formed under the gate electrode of a PMOS circuit section is the p+ silicon layer.
  • n ⁇ or p ⁇ ions are doped on the channel region 24 using the gate electrode region 34 as a mask such that an exposed portion of the channel region 24 become an LDD region.
  • n+ ions are doped on a portion corresponding to the NMOS circuit, and as shown in FIG. 1 e , p+ ions are doped on a portion of the PMOS circuit. If a TFT IX is formed having only the NMOS circuits or PMOS circuits, only the corresponding ions are doped.
  • an intermediate insulating layer 36 is deposited, then patterned such that a plurality of contact holes 38 are formed as shown in FIG. 1 f.
  • an electrode material is deposited on the intermediate insulating layer 36 and patterned using a mask such that a pixel electrode 40 and a wire section 42 , which respectively contact the electrodes 30 and 32 , can be defined on the intermediate insulating layer 36 .

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

A method for manufacturing a thin film transistor is disclosed. Afterforming a channel region on a surface of a substrate, an insulating layer is deposited on the surface of the substrate to cover the channel region. The insulating layer is pataterned such that a portion of the channel region is exposed. Then, a silicon layer and a metal layer are sequentially deposited on the insulating layer. The silicon and metal layers are etched to define source, drain and gate electrode sections. After doping positive ions on a portion corresponding to a MOS circuit portion, an intermediate insulating layer is deposited on the metal layer while covering the source, drain and gate electrode sections. The intermediate insulating layer is patterned to form a plurality of contact holes. An electrode material is deposited on the intermediate insulating layer and patterned to define a pixel electrode section and a wire section.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention [0001]
  • The present invention relates to a thin-film transistor (TFT) and, more particularly, to a method for manufacturing a TFT that can reduce the number of photolithography processes, that can easily adjust a width of an lightly doped drain region and planarize the film surface. [0002]
  • 2. Description of the Related Art [0003]
  • Generally, TFTs are widely used as a switching element for turning On/Off pixels of a flat panel display such as an active matrix liquid crystal display, because they can contain CMOS on the substrate. To use the TFT as a switching element, the TFT should be able to withstand a high voltage and to provide a high ratio of On currents to Off current. [0004]
  • As is well known, such a TFT is manufactured through a number of photolithography processes, each comprising a plurality of steps such as a photoresist step, a light-exposing step, and an etching step. As the number of processes increases, the overall productivity is lowered and the quality of the TFT is deteriorated. [0005]
  • In addition, in the conventional TFT, since source and drain electrodes and a gate electrode are formed in a different step, it is difficult to adjust the width of an lightly doped drain (LDD) region, while increasing the number of layers that are stacked and the number of photolithography processes. The more number of layers stacked makes a surface of the TFT uneven, costing the reflecting efficiency in a reflective-type LCD. [0006]
    • SUMMARY OF THE INVENTION
  • Therefore, the present invention has been made in an effort to solve the above described problems. [0007]
  • It is an objective of the present invention to provide a method for manufacturing a TFT that can reduce the number of photolithography processes, that can easily adjust the width of an LDD region and planarize the TFT surface. [0008]
  • To achieve the above objective, the present invention provides a method for manufacturing a thin film transistor comprising the steps of forming a channel region on a surface of a substrate, depositing an insulating layer on the surface of the substrate while covering the channel region and patterning the insulating layer such that a portion of the channel region is exposed, depositing a silicon layer on the insulating layer, depositing a metal layer on the silicon layer and etching the silicon and metal layers to define source, drain and gate electrode sections, doping positive ions on a portion corresponding to a MOS circuit portion, depositing an intermediate insulating layer on the metal layer while covering the source, drain and gate electrode sections and patterning the intermediate insulating layer to form a plurality of contact holes, and depositing an electrode material on the intermediate insulating layer and patterning the electrode material to define a pixel electrode section and a wire section. [0009]
  • The method may further comprise the step of doping negative ions to define an LDD region at an exposed portion of the channel region before doping the positive ions. [0010]
  • The step of doping the positive ions comprises the step of doping n+ ions on an NMOS circuit section. Alternatively, the step of doping the positive ions Ad comprises the step of doping p+ ions on a PMOS circuit section. [0011]
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate an embodiment of the invention, and, together with the description, serve to explain the principles of the invention: [0012]
  • FIGS. 1[0013] a through 1 g illustrate cross-sectional views of a portion of a TFT as it undergoes sequential processing steps according to a preferred embodiment of the present invention.
    • DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
  • Reference will now be made in detail to the present preferred embodiment of the invention, an example of which is illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts. [0014]
  • In the following embodiment, a CMOS TFT includes a pixel section, a wire section, a PMOS circuit section, and an NMOS circuit section. [0015]
  • FIGS. 1[0016] a to 1 g are cross-sectional views of a portion of a CMOS TFT as it undergoes sequential processing steps. Referring first to FIG. 1a, a buffer layer 22 is first deposited on a substrate 20, then a pattern of a channel region 24 is formed on the buffer layer 22. To form the pattern of the channel region 24, an active layer is first deposited on the buffer layer 22 using an amorphous silicon, then crystallized by an eximer laser, and patterned through a photolithography process. The buffer layer 22 may be omitted.
  • After forming the [0017] channel region 24, an insulating layer is deposited on the buffer layer 22 while covering the channel region 24, then patterned such that the channel region 24 is exposed except for its edges and middle portion as shown in FIG. 1b.
  • Next, an n+ or [0018] p+ silicon layer 28 is deposited on the insulating layer 26 and the channel region 24, and a metal layer 33 is deposited on the n+ or p+ silicon layer 28. Then, the silicon and metal layers 28 and 33 are simultaneously etched to define drain, source and gate electrode regions 30, 32 and 34. Here, the silicon layer 28 is used for ohmic contacts between the channel region 24 and each of the drain and source electrode regions 30 and 32.
  • At this point, the [0019] silicon layer 28 formed under the gate electrode 34 of an NMOS circuit section is the n+ silicon layer, and the silicon layer 28 formed under the gate electrode of a PMOS circuit section is the p+ silicon layer.
  • Next, n− or p− ions are doped on the [0020] channel region 24 using the gate electrode region 34 as a mask such that an exposed portion of the channel region 24 become an LDD region.
  • Then, through a photolithography process using a [0021] mask 35, as shown in FIG. 1d, n+ ions are doped on a portion corresponding to the NMOS circuit, and as shown in FIG. 1e, p+ ions are doped on a portion of the PMOS circuit. If a TFT IX is formed having only the NMOS circuits or PMOS circuits, only the corresponding ions are doped.
  • After the circuits are doped, an intermediate [0022] insulating layer 36 is deposited, then patterned such that a plurality of contact holes 38 are formed as shown in FIG. 1f.
  • Next, an electrode material is deposited on the intermediate insulating [0023] layer 36 and patterned using a mask such that a pixel electrode 40 and a wire section 42, which respectively contact the electrodes 30 and 32, can be defined on the intermediate insulating layer 36.
  • As described above, since the source and drain electrodes, and the gate electrode are simultaneously formed, the number of photolithography processes for manufacturing the TFT can be reduced, improving productivity and yield. [0024]
  • In addition, since gaps between the source, drain, and gate electrodes can be adjusted on the mask, it is easy to adjust the LDD region and reduce the thickness of the TFT. Furthermore, since a silicon layer is formed under the gate electrode, the characteristics of the gate electrode and the channel region does not become much different, lowering the threshold voltage. [0025]
  • While this invention has been described in connection with what is presently considered to be the most practical and preferred embodiment, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims. [0026]

Claims (5)

What is claimed is:
1. A method for manufacturing a thin film transistor, comprising the steps of:
forming a channel region on a surface of a substrate;
depositing an insulating layer on the surface of the substrate to cover the channel region;
patterning the insulating layer such that a portion of the channel region is exposed;
depositing a silicon layer on the insulating layer;
depositing a metal layer on the silicon layer;
etching the silicon layer and the metal layer at the same time to define a source electrode, a drain electrode and a gate electrode;
doping positive ions on a portion corresponding to a MOS circuit;
depositing an intermediate insulating layer on the metal layer to cover the source electrode, the drain electrode and the gate electrode;
patterning the intermediate insulating layer to form a plurality of contact holes; and
depositing an electrode material on the intermediate insulating layer; and
patterning the electrode material to define a pixel electrode section and a wire section.
2. A method of
claim 1
, further comprising the step of doping negative ions to define an LDD region at exposed portion of the channel region before doping the positive ions.
3. A method of
claim 1
, wherein the step of doping the positive ions comprises the step of doping n+ ions on an NMOS circuit section.
4. A method of
claim 1
, wherein the step of doping the positive ions comprises the step of doping p+ ions on a PMOS circuit section.
5. A method of
claim 1
, wherein the step of doping the positive ions comprises the steps of doping n+ ions on an NMOS circuit section and doping p+ ions on a PMOS circuit section.
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US6451630B2 (en) 2002-09-17
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