KR101500867B1 - Fabrication methods of low-temperature polycrystalline thin film transistor - Google Patents
Fabrication methods of low-temperature polycrystalline thin film transistor Download PDFInfo
- Publication number
- KR101500867B1 KR101500867B1 KR20130127209A KR20130127209A KR101500867B1 KR 101500867 B1 KR101500867 B1 KR 101500867B1 KR 20130127209 A KR20130127209 A KR 20130127209A KR 20130127209 A KR20130127209 A KR 20130127209A KR 101500867 B1 KR101500867 B1 KR 101500867B1
- Authority
- KR
- South Korea
- Prior art keywords
- thin film
- polycrystalline silicon
- film transistor
- low
- temperature
- Prior art date
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- 239000010409 thin film Substances 0.000 title claims abstract description 43
- 238000000034 method Methods 0.000 title claims abstract description 35
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 40
- 229910008479 TiSi2 Inorganic materials 0.000 claims abstract description 12
- DFJQEGUNXWZVAH-UHFFFAOYSA-N bis($l^{2}-silanylidene)titanium Chemical compound [Si]=[Ti]=[Si] DFJQEGUNXWZVAH-UHFFFAOYSA-N 0.000 claims abstract description 12
- 239000012535 impurity Substances 0.000 claims abstract description 10
- 238000005468 ion implantation Methods 0.000 claims description 8
- 238000010438 heat treatment Methods 0.000 claims description 5
- 238000004904 shortening Methods 0.000 claims description 2
- 238000000151 deposition Methods 0.000 abstract 1
- 239000000758 substrate Substances 0.000 description 8
- 239000002184 metal Substances 0.000 description 6
- 239000010408 film Substances 0.000 description 5
- 229910021417 amorphous silicon Inorganic materials 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 230000007547 defect Effects 0.000 description 2
- 230000003993 interaction Effects 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- GPRLSGONYQIRFK-UHFFFAOYSA-N hydron Chemical compound [H+] GPRLSGONYQIRFK-UHFFFAOYSA-N 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000007790 solid phase Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000000427 thin-film deposition Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thin Film Transistor (AREA)
Abstract
In the method of fabricating a low-temperature polycrystalline silicon thin film transistor having the n-channel MOSFET characteristics of the present invention, when the source and drain of the transistor are formed by using the TiSi2 thin film and the conventional n + polycrystalline silicon source and drain regions are formed, (TEPSI) process for depositing a TiSi2 thin film at a temperature higher than room temperature in order to activate the process and ion implanted impurities at a low temperature, Temperature process polycrystalline silicon thin film transistor using a TiSi2 thin film having n-channel MOSFET characteristics as a source and a drain.
Description
The present invention relates to a method of manufacturing a thin film transistor that operates as a switch in a low temperature process polycrystalline silicon thin film transistor liquid crystal display (TFT-LCD) panel, and more particularly, to a method of manufacturing an n-channel low temperature process polycrystalline silicon thin film transistor will be.
The n-channel low-temperature process polycrystalline silicon thin film transistor is used as an active rod in image sensors, various display devices and high-speed static random access memory (SRAM). In an active matrix liquid crystal display (AMLCD) driven by an active addressing method, a high performance low temperature polycrystalline silicon thin film transistor having far greater field effect mobility than an amorphous silicon thin film transistor has been actively studied in various fields. As a result of the above efforts, the characteristics of the polycrystalline silicon thin film itself have been greatly improved. However, the n + polycrystalline silicon source and drain of the n-channel low-temperature polycrystalline silicon thin film transistor are mostly implanted with a high concentration n-type impurity, Polycrystalline silicon containing an n-type impurity is deposited to form an n + polycrystalline silicon source and drain. In forming n + polycrystalline silicon source and drain regions of conventional n-channel low-temperature polycrystalline silicon thin film transistors, ion implantation problems in a large-area display and long-time heat treatment processes are required to activate ion implanted impurities at a low temperature This can be a factor in the decrease in productivity.
In order to improve the performance of the n-channel low-temperature polycrystalline silicon thin film transistor (TFT), a technique of increasing the grain size of the silicon thin film or a process such as hydrogen plasma or hydrogen ion implantation is used to remove defects. As a result of the above efforts, the characteristics of the polycrystalline silicon thin film itself have been greatly improved. However, when forming the n + polycrystalline silicon source and drain regions of the n-channel low-temperature polycrystalline silicon thin film transistor, And a polycrystalline silicon containing an impurity is deposited to form source and drain of the n-channel low-temperature process polycrystalline silicon thin film transistor. Conventional low-temperature process to form source and drain regions of n-channel low-temperature polycrystalline silicon thin-film transistor In order to activate ion implantation in a large-area display and ion implanted impurities at a low temperature, a long- This is a factor that deteriorates the characteristics of the polycrystalline silicon thin film transistor of the n-channel low temperature process due to not only a decrease in the productivity but also various defects occurring during the ion implantation.
In the low-temperature process polycrystalline silicon thin film transistor fabrication,
forming source and drain structures of an n-channel low-temperature process polycrystalline silicon thin film transistor; Forming a source and a drain of the n-channel low-temperature process polycrystalline silicon thin film transistor using only a TiSi2
According to the present invention, when source and drain of an n-channel low-temperature process polycrystalline silicon thin film transistor are formed by ion implantation of a high concentration n-type impurity in a conventional n + polycrystalline silicon source and drain region, By forming a TiSi2 thin film by applying a thermally enhanced plasma-surface interaction (TEPSI) process in which a substrate temperature is higher than room temperature during thin film deposition, a long time is required to activate the ion implantation process and the implanted impurities at a low temperature It is possible to omit the heat treatment step of the heat treatment step and improve the productivity.
1A to 1D are sectional views of a device for explaining a method of manufacturing a low temperature process polycrystalline silicon thin film transistor device according to an embodiment of the present invention.
Hereinafter, embodiments of the present invention will be described in more detail with reference to the accompanying drawings, Figs. 1A to 1D. The n-channel low temperature process polycrystalline silicon thin film transistor manufacturing method according to the present invention is applicable to various modules for manufacturing thin film transistors in a low temperature process.
1A to 1D show a method of manufacturing a semiconductor device according to an embodiment of the present invention in accordance with a process order.
1A, a TiSi2
Next, referring to FIG. 1B, a channel
Next, referring to FIG. 1C, a
Next, referring to FIG. 1D, a wiring metal 7 is deposited on the entire surface of the substrate to form a wiring metal. Then, the wiring metal layer 7 is patterned using a predetermined photoresist pattern as a mask, and the metal of the exposed substrate portion is etched to form a wiring metal pattern 7.
Description of the Related Art
1: substrate
2: TiSi2 thin film
3: channel amorphous silicon
4: gate oxide film
5: Gate polycrystalline silicon
6: Device protection film
7: Wiring metal
Claims (2)
forming source and drain structures of an n-channel low-temperature process polycrystalline silicon thin film transistor; Forming a source and a drain of the n-channel low-temperature process polycrystalline silicon thin film transistor as a TiSi2 thin film 2 without an n + polycrystalline silicon layer; Wherein the TiSi2 thin film (2) is formed by a low-temperature TEPSI process so that the n-type impurity ion implantation and the long heat treatment process can be omitted, thereby shortening the manufacturing process and improving the productivity.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR20130127209A KR101500867B1 (en) | 2013-10-24 | 2013-10-24 | Fabrication methods of low-temperature polycrystalline thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR20130127209A KR101500867B1 (en) | 2013-10-24 | 2013-10-24 | Fabrication methods of low-temperature polycrystalline thin film transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR101500867B1 true KR101500867B1 (en) | 2015-03-12 |
Family
ID=53026995
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR20130127209A KR101500867B1 (en) | 2013-10-24 | 2013-10-24 | Fabrication methods of low-temperature polycrystalline thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR101500867B1 (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000286423A (en) * | 1998-05-26 | 2000-10-13 | Matsushita Electric Ind Co Ltd | Thin-film transistor and its manufacture |
| KR100307456B1 (en) * | 1999-12-08 | 2001-10-17 | 김순택 | Method for manufacturing Thin Film Transistor |
-
2013
- 2013-10-24 KR KR20130127209A patent/KR101500867B1/en not_active IP Right Cessation
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000286423A (en) * | 1998-05-26 | 2000-10-13 | Matsushita Electric Ind Co Ltd | Thin-film transistor and its manufacture |
| KR100307456B1 (en) * | 1999-12-08 | 2001-10-17 | 김순택 | Method for manufacturing Thin Film Transistor |
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