US11056579B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

Info

Publication number
US11056579B2
US11056579B2 US16/704,127 US201916704127A US11056579B2 US 11056579 B2 US11056579 B2 US 11056579B2 US 201916704127 A US201916704127 A US 201916704127A US 11056579 B2 US11056579 B2 US 11056579B2
Authority
US
United States
Prior art keywords
material layer
trench
source
layer
drain
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
US16/704,127
Other versions
US20200111899A1 (en
Inventor
Hai Yang ZHANG
Zhuo Fan CHEN
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
Original Assignee
Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Manufacturing International Shanghai Corp, Semiconductor Manufacturing International Beijing Corp filed Critical Semiconductor Manufacturing International Shanghai Corp
Priority to US16/704,127 priority Critical patent/US11056579B2/en
Publication of US20200111899A1 publication Critical patent/US20200111899A1/en
Application granted granted Critical
Publication of US11056579B2 publication Critical patent/US11056579B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/66818—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the channel being thinned after patterning, e.g. sacrificial oxidation on fin
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location
    • H01L27/11556—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41791—Source or drain electrodes for field effect devices for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7856—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with an non-uniform gate, e.g. varying doping structure, shape or composition on different sides of the fin, or different gate insulator thickness or composition on opposing fin sides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78681—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising AIIIBV or AIIBVI or AIVBVI semiconductor materials, or Se or Te
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

Definitions

  • the present disclosure generally relates to the field of semiconductor technology and, more particularly, relates to semiconductor devices and fabrication methods of the semiconductor devices.
  • the MOS (metal-oxide-semiconductor) transistor is one of the most important elements in modern integrated circuits.
  • the basic structure of the MOS transistor includes a semiconductor substrate, and a gate structure located on the surface of the semiconductor substrate.
  • the gate structure includes: a gate dielectric layer located on the surface of the semiconductor substrate; a gate electrode layer located on the surface of the gate dielectric layer; and a source and drain doped region located in the semiconductor substrate at the two sidewalls of the gate structure.
  • the fin field effect transistor is an emerging multi-gate device
  • the semiconductor substrate generally includes a fin structure which protrudes out of the surface of the semiconductor substrate, a gate structure covering the top surface and the sidewalls of the fin, and a source and drain doped region located in the fin portions on the two sides of the gate structure.
  • the disclosed devices and methods are directed to at least partially alleviate one or more problems set forth above and to solve other problems in the art.
  • One aspect of the present disclosure provides a method for forming a semiconductor device.
  • the method includes: providing a substrate; forming a source and drain material layer over the substrate; forming a mask layer on the source and drain material layer, and the mask layer includes a first trench and the first trench exposes a portion of the source and drain material layer; forming a protective layer on sidewalls of the first trench; forming a second trench in the source and drain material layer by etching the source and drain material layer at a bottom of the first trench using the mask layer and the protective layer as a mask; removing the protective layer after the second trench is formed; forming a channel material layer and a gate structure on the channel material layer after the protective layer is removed, and the channel material layer is on the sidewalls and the bottom of the first trench and on sidewalls and bottom of the second trench; and removing the mask layer after the channel material layer and the gate structure are formed.
  • the semiconductor device includes: a substrate; a source and drain material layer formed on the substrate, the source and drain material layer containing a first trench there-through; a mask layer formed on the source and drain material layer containing a second trench there-through, the second trench having a cross-section area larger than the first trench and covers the first trench; a channel material layer conformally formed on a bottom and sidewalls of each of the first trench and the second trench; and a gate structure conformally formed on the channel material layer, on the bottom and the sidewalls of each of the first trench and the second trench.
  • FIG. 1 and FIG. 2 are schematic structural diagrams illustrating a process of forming a semiconductor device
  • FIG. 3 illustrates an exemplary method for forming a semiconductor device according to the disclosed embodiments.
  • FIGS. 4-13 illustrate semiconductor structures corresponding to certain stages of an exemplary fabrication process of a transistor consistent with the disclosed embodiments.
  • FIG. 1 and FIG. 2 are schematic structural diagrams illustrating a process of forming a semiconductor device.
  • a substrate 100 is provided, and an oxide layer 110 is formed on the substrate 100 .
  • a source and drain material layer 120 is formed on the oxide layer 110 , and the source and drain material layer 120 is provided with a trench 130 passing through the source-drain material layer 120 .
  • a channel material film (not shown) is formed on the two sidewalls and the bottom portions of trench 130 (refer to FIG. 1 ), the source drain material layer 120 , and the substrate 100 .
  • the material of the channel material film may be MoS 2 .
  • a gate structure material layer may be formed on the surface of the channel material film.
  • a patterned gate structure material layer and the channel material film form a channel material layer 140 and a gate structure 150 on the top of channel material layer 140 .
  • the gate structure 150 corresponds to the gate structure material layer.
  • the method further includes the following step: the source and drain ions are doped in the source and drain material layer 120 on the two sides of the gate structure 150 ; and a source and drain doped region is formed in the source and drain material layer 120 on the two sides of the gate structure 150 .
  • the channel material layer 140 is located not only on the sidewalls and the bottom of the trench 130 , but also on the source and drain material layer 120 on the two sides of the trench 130 . As a result, the effective length of the channel material layer 140 is relatively large, and distance between the source and drain doped regions on the two sides of the gate structure 150 is also relatively large.
  • the method for forming the patterned gate structure material layer and the channel material film includes: forming a patterned photoresist layer on the gate structure material layer, and the photoresist layer only covers the gate structure material layer in the trench 130 and the portion of gate structure material layer located on the source and drain material layer 120 on the two sides of the trench 130 ; and etching the gate structure material layer and the channel material film by using the patterned photoresist layer as a mask until the source and drain material layer 120 is exposed.
  • the trench 130 may have a first sidewall and a second sidewall, facing each other.
  • the first sidewall and the second sidewall of the trench 130 are respectively on the source and drain material layer 120 .
  • the position of the projection of the center of the gate structure 150 on the surface of the substrate 100 may be offset from the position of the projection of the center of the trench 130 on the surface of the substrate 100 .
  • the position of the projection of the center of the channel material layer 140 on the surface of the substrate 100 may also be offset from the position of the projection of the center of the trench 130 on the surface of the substrate 100 .
  • the size difference between the channel material layer 140 on the first side of the trench 130 and the second side of the trench 130 is relative large, and the gate structure 150 on the first side of the trench 130 and the gate structure 150 on the second side of the trench 130 are also different in size.
  • the size of the source and drain doped region formed in the source and drain material layer 120 are very different from each other on the two sides of the trench, and the parameters of the current and the process design in the source-drain doped region. As a result, the stability of the electrical properties of the semiconductor device may be lowered.
  • the present disclosure provides a semiconductor device and a method for forming the semiconductor device.
  • the method includes: providing a substrate; forming a source and drain material layer over the substrate; forming a mask layer on the source and drain material layer, and the mask layer includes a first trench and the first trench exposes a portion of the source and drain material layer; forming a protective layer on sidewalls of the first trench; forming a second trench in the source and drain material layer by etching the source and drain material layer at a bottom of the first trench using the mask layer and the protective layer as a mask; removing the protective layer after the second trench is formed; forming a channel material layer and a gate structure on the channel material layer after the protective layer is removed, and the channel material layer is on the sidewalls and the bottom of the first trench and on sidewalls and bottom of the second trench; and removing the mask layer after the channel material layer and the gate structure are formed.
  • the sizes of the source drain material layers on the two sides of the gate structure are consistent, and the stability of the electrical performance of the semiconductor device may be improved.
  • FIG. 3 is a flowchart illustrating a method for forming a semiconductor device.
  • a substrate is provided.
  • a source and drain material layer is formed on the substrate at step S 102 .
  • a mask layer which includes a first trench and the first trench exposes a portion of the source and drain material layer, is formed on the source and drain material layer.
  • a protective layer is formed on sidewalls of the first trench at step S 104 .
  • a second trench passing through the source and drain material layer is formed by etching the source and drain material layer at a bottom of the first trench using the mask layer and the protective layer as a mask.
  • the protective layer is removed after the second trench at step S 106 .
  • a channel material layer and a gate structure are formed on the channel material layer after the protective layer is removed, and the channel material layer is located on the sidewalls and the bottom of the first trench and the second trench.
  • the mask layer is removed after the channel material layer and the gate structure are formed.
  • FIGS. 4-13 illustrate semiconductor structures corresponding to certain stages of an exemplary fabrication process of a transistor consistent with the disclosed embodiments.
  • a substrate 200 is provided.
  • the substrate 200 may be a bulk silicon substrate, a bulk germanium substrate, a glass substrate, a silicon-on-insulator substrate, or a germanium-on-insulator substrate. In one embodiment, the substrate 200 may be a bulk silicon substrate.
  • an interface layer 210 may be formed on the surface of the substrate 200 .
  • the material of the interface layer 210 may be silicon oxide.
  • the interface layer 210 may isolate the substrate 200 from a subsequently formed source and drain material layer.
  • a source and drain material layer 220 may be formed on the substrate 200 and a mask layer 230 may be formed on the source and drain material layer 220 , the mask layer 230 may include a first trench 231 , and a portion of the source and drain material layer 220 may be exposed in the first trench 231 .
  • the interface layer 210 may be formed on the surface of the substrate 200 before the source and drain material layer 220 is formed.
  • the material of the source and drain material layer 220 may be, for example, polycrystalline silicon.
  • the process for forming the source and drain material layer 220 may be a deposition process, such as a plasma chemical vapor deposition process, a low-pressure chemical vapor deposition process, or a sub-atmospheric pressure chemical vapor deposition process.
  • the method for forming a mask layer 230 includes: forming a mask material layer on the source and drain material layer 220 ; and forming the mask layer 230 by patterning the mask material layer.
  • the mask layer 230 may include the first trench 231 passing through the mask layer 230 .
  • the mask layer 230 may be made of, for example, silicon oxide.
  • a protective layer 240 may be formed on the sidewalls of the first trench 231 .
  • the mask layer 230 and the protective layer 240 are used jointly to define the position of a subsequent formed second trench.
  • the protective layer 240 may be formed by, for example, forming a protective material layer (not illustrated) on the sidewalls and the bottom of the first trench 231 and on the top surface of the mask layer 230 ; and forming the protective layer 240 by etching back the protective material layer until the top surface of the mask layer 230 and the top surface of the source and drain material layer 220 are exposed.
  • the process for forming the protective material layer may be a deposition process, such as an atomic layer deposition process, a plasma chemical vapor deposition process, a low-pressure chemical vapor deposition process, or a sub-atmospheric chemical vapor deposition process.
  • a deposition process such as an atomic layer deposition process, a plasma chemical vapor deposition process, a low-pressure chemical vapor deposition process, or a sub-atmospheric chemical vapor deposition process.
  • the material of the protective layer 240 and the material of the mask layer 230 are different.
  • the protective layer 240 and the source and drain material layer 220 may also be made of different materials.
  • the protective material layer may have a relatively high etching selection ratio value comparing to the source and drain material layer 220 .
  • the protective material layer may have a higher etching selection ratio comparing to the mask layer 230 .
  • the protective layer 240 may have a higher etching selection ratio comparing to the source and drain material layer 220 .
  • the protective layer 240 may be made of silicon nitride.
  • the mask layer 230 and the protective layer 240 are used as a mask to etch the source and drain material layer 220 on the bottom of the first trench 231 , and the source and drain material layer 220 may include a second trench 222 passing through the source and drain material layer 220 .
  • the process of etching the source and drain material layer 220 on the bottom of the first trench 231 may be an anisotropic dry etching process.
  • the process of etching the source and drain material layer 220 on the bottom of the first trench 231 may use the interface layer 210 as an etching stop layer.
  • the interface layer 210 may be optionally formed on the surface of the substrate 200 before the source and drain material layer 220 is formed. Therefore, the interface layer 210 may be exposed on the bottom of the second trench 222 .
  • the distances from the center of the second trench 222 to the two sidewalls of the first trench 231 are consistent with each other.
  • the first trench 231 may cover the second trench 222 .
  • the first trench 231 may have a cross-section area larger than the second trench 222 .
  • projections of centers of the first and second trenches on a surface the substrate may be substantially overlapped.
  • the protective layer 240 may be removed after the second trench 222 is formed.
  • the process for removing the protective layer 240 may be an etching process, such as a dry etching process or a wet etching process.
  • the ratio of the etching rate between the protective layer 240 and the mask layer 230 may be in a range from 3 to 10.
  • the ratio of the etching rate between the protective layer 240 and the mask layer 220 may be in a range from 3 to 10.
  • a channel material layer and a gate structure on the channel material layer are formed after the protective layer 240 is removed.
  • the channel material layer may be located on the sidewalls and the bottom of the first trench 231 and the sidewalls and the bottom of the second trench 222 .
  • the source and drain material layer 220 which is located on the two sides of the second trench 222 and on the bottom of the first trench 231 , may be exposed. And the sizes of the source and drain material layer 220 , located on the two sides of the second trench 222 and on the bottom of the first trench 231 , are consistent with each other.
  • the method of forming the channel material layer and the gate structure is described below with reference to FIG. 9 and FIG. 10 .
  • a channel material film 250 may be formed on the sidewalls and the bottom portion of the first trench 231 , on the sidewalls and the bottom the second trench 222 , and on the mask layer 230 .
  • the channel material film 250 may further be formed on the surface of the interface layer 210 .
  • the channel material film 250 may be used to form a channel material layer.
  • the material of the channel material film 250 may be MoS 2 , and the process for forming the channel material film 250 may be a solid source chemical vapor deposition process.
  • the material of the subsequently formed channel material layer may be a crystalline material.
  • the electrical conductivity of the crystalline state material may be high, and the channel material layer may have a good conductive property.
  • the material of the channel material film 250 may be MoS 2 , and the channel material film 250 may be formed on the bottom of the second trench 222 by using a solid source chemical vapor deposition process.
  • the channel material film 250 on the bottom of the second trench 222 may be used as a channel material layer on the bottom of the second trench 222 .
  • the channel material film 250 may be ultra-thin.
  • the solid source chemical vapor deposition process includes: taking a solid as a generating source; evaporating and sublimating the solid source; and forming a channel material film 250 with decomposition reactions in the atmosphere of the carrier gas.
  • the parameters of the solid source chemical vapor deposition process may include: a solid source including MoO 3 and S; a carrier gas including Ar; and a temperature in a range of approximately 600° C.-900° C., such as 755° C.
  • the thickness of the channel material film 250 may be in a range of approximately 5 nm-10 nm, such as about 7 nm. Thickness of the subsequently formed channel material layer may be in a range of approximately 5 nm-10 nm.
  • the present method may be used to form a semiconductor device with an ultra-thin channel.
  • the thickness of the channel material film 250 may be in a range from 5 nm to 10 nm. If the channel material film 250 is thinner than 5 nm, it will be too difficult to control the process; and if the channel material film 250 is thicker than 10 nm, the subsequently formed channel material layer may be too thick, and it will be too hard to improve the control capability of the gate structure on the channel.
  • a gate structure material layer 260 may be formed on the surface of the channel material film 250 .
  • the gate structure material layer 260 may include: a gate dielectric material layer (not shown) on the surface of the channel material film 250 ; and a gate electrode material layer (not shown) on the surface of gate dielectric material layer.
  • the material of the gate dielectric material layer may be a high-k (k may be greater than 3.9) dielectric material.
  • the gate electrode material layer may be made of metal, such as copper and/or tungsten.
  • the process for forming the gate dielectric material layer may be a deposition process, such as an atomic layer deposition process, a plasma chemical vapor deposition process, a low-pressure chemical vapor deposition process, or a sub-atmospheric chemical vapor deposition process.
  • the process for forming the gate electrode material layer may be a deposition process, such as a sputtering process or a plasma chemical vapor deposition process.
  • a filling layer 270 may be formed to fill in the first trench 231 (see FIG. 9 ) and the second trench 222 (see FIG. 9 ) after the gate structure material layer 260 is formed.
  • the material of the filling layer 270 may be made of silicon oxide or a bottom anti-reflective coating (B ARC) material.
  • the process for forming the filling layer 270 may include a spin coating process.
  • the gate structure material layer 260 and the channel material film 250 are planarized until the top surface of the mask layer 230 and the top surface of the filling layer 270 are exposed. Then the channel material film 250 forms a channel material layer 251 , and the gate structure material layer 260 forms a gate structure 261 .
  • the process for planarizing the gate structure material layer 260 and the channel material film 250 may be a chemical mechanical grinding process.
  • the channel material layer 251 may be made of MoS 2 .
  • the channel material layer 251 may be located not only on the sidewalls and the bottom of the second trench 222 , but also on the bottom of the first trench 231 . As a result, the effective length of the channel material layer 251 may be relatively big, and the distance between the source and drain doped regions on the two sides of the subsequent gate structure may be relatively big correspondingly. And the short channel effect of the semiconductor device may be improved.
  • the channel material layer 251 may be made of MoS 2 .
  • the advantages of using MoS 2 may include that the semiconductor device may be provided with an ultra-thin channel and the channel material layer 251 may be formed on the surface of the interface layer 210 .
  • the thickness of the channel material layer 251 may be in a range of approximately 5 nm-10 nm.
  • the gate structure 261 may include a gate dielectric layer located on the channel material layer 251 and a gate electrode layer on the gate dielectric layer.
  • the gate dielectric layer corresponds to the gate dielectric material layer
  • the gate electrode layer corresponds to the gate electrode material layer
  • the filling layer 270 may be removed.
  • the method may further include removing the mask layer 230 (see FIG. 11 ) after forming a channel material layer 251 and a gate structure 261 .
  • the mask layer 230 may be removed in the process of removing the filler layer 270 .
  • the filling layer 270 and the mask layer 230 may be removed separately, in another embodiment.
  • the filling layer 270 and the mask layer 230 may be removed by an etching process.
  • a source and drain doped region 280 may be formed on the two sides of the gate structure 261 in the source and drain material layer 220 .
  • source and drain ions may be injected into the source and drain material layer 220 on the two sides of the gate structure 261 by adopting an ion implantation process and a source and drain doped region 280 may be formed on the two sides of the gate structure 261 in the source and drain material layer 220 .
  • the size of the channel material layer 251 on the source and drain material layer 220 on one side of the second trench 222 may be consistent with that of the channel material layer 251 on the other side of the second trench 222 .
  • the size of the gate structure 261 on the source and drain material layer 220 on one side of the second trench 222 may also be consistent with the size of the gate structure 261 on the other side of the second trench 222 . Therefore, the sizes of the source and drain material layer 220 on the two sides of the gate structure 261 are consistent with each other, and the size of the source and drain doped region 280 may also be consistent.
  • the self-aligned metal gate with channel substantially reduces the size difference of the source and drain material layer on the two sides of the gate structure 261 . Therefore, the stability of the electrical performance of the semiconductor device may be improved.
  • the source region and the drain region are formed in the source and drain material layer respectively on sides of the channel material layer.
  • projections of centers of the gate structure and the channel material layer on a surface the substrate may be substantially overlapped.
  • the embodiment further provides a semiconductor device formed by the above discussed method.
  • the present disclosure has the following advantages.
  • the channel material layer is formed along the sidewalls and the bottom of the first trench and of the second trench, and an ultra-thin channel material layer is formed.
  • the ultra-thin channel material layer limits the channel size of the semiconductor device, and the semiconductor device is provided with an ultra-thin channel.
  • the channel material layer is located not only on the sidewalls and the bottom of the second trench, but also on the bottom of the first trench. Therefore, the effective length of the channel material layer is relatively large, and the short channel effect of the semiconductor device is further improved.
  • a source and drain doped region is formed on the two sides of the gate structure in the source and drain material layer.
  • a protective layer is formed on the sidewall of the first trench, and then the mask layer and the protective layer are used jointly to define the position of the second trench.
  • the mask layer and the protective layer are used as a mask to etch the source and drain material layer on the bottom of the first trench, and the distances from the center of the second trench to the two sidewalls of the first trench are consistent with each other.
  • the source and drain material layer which is located on the two sides of the second trench and on the bottom of the first trench, is exposed after the protective layer is removed.
  • the size of the source and drain material layer located on the two sides of the second trench and on the bottom of the first trench is also consistent with each other.
  • the size of the channel material layer on the source/drain material layer on one side of the second trench is consistent with that of the channel material layer on the other side of the second trench.
  • the size of the gate structure on the source/drain material layer on one side of the second trench is consistent with that of the gate structure on the other side of the second trench. Therefore, the sizes of the source and drain material layer on the two sides of the gate structure are consistent with each other, and the stability of the electrical performance of the semiconductor device is improved.

Abstract

Semiconductor devices and fabrication methods are provided. A semiconductor device includes a substrate, a source and drain material layer formed on the substrate. The source and drain material layer contains a first trench there-through. The semiconductor device further includes a mask layer formed on the source and drain material layer containing a second trench there-through. The second trench has a cross-section area larger than the first trench and covers the first trench. The semiconductor device further includes a channel material layer conformally formed on a bottom and sidewalls of each of the first trench and the second trench and a gate structure conformally formed on the channel material layer, on the bottom and the sidewalls of each of the first trench and the second trench. The gate structure has a recess and the recess has a symmetrical step structure.

Description

CROSS-REFERENCES TO RELATED APPLICATION
This application is a continuation application of U.S. patent application Ser. No. 15/964,738, filed on Apr. 27, 2018, which claims the priority of Chinese Patent Application No. 201710310410.X, filed on May 5, 2017, the content of which is incorporated by reference in its entirety.
TECHNICAL FIELD
The present disclosure generally relates to the field of semiconductor technology and, more particularly, relates to semiconductor devices and fabrication methods of the semiconductor devices.
BACKGROUND
The MOS (metal-oxide-semiconductor) transistor is one of the most important elements in modern integrated circuits. The basic structure of the MOS transistor includes a semiconductor substrate, and a gate structure located on the surface of the semiconductor substrate. And the gate structure includes: a gate dielectric layer located on the surface of the semiconductor substrate; a gate electrode layer located on the surface of the gate dielectric layer; and a source and drain doped region located in the semiconductor substrate at the two sidewalls of the gate structure.
With the development of semiconductor technology, the control capability of the traditional planar MOS transistor on the channel current is weakened, and serious leakage current is produced as a result. The fin field effect transistor is an emerging multi-gate device, the semiconductor substrate generally includes a fin structure which protrudes out of the surface of the semiconductor substrate, a gate structure covering the top surface and the sidewalls of the fin, and a source and drain doped region located in the fin portions on the two sides of the gate structure.
With the further development of the semiconductor technology, there are higher requirements for control capability of the channel current for not only the planar MOS transistor but also the fin field effect transistor. For this reason, a semiconductor device with an ultra-thin channel was used. However, the performance of conventional semiconductor devices having an ultra-thin channel still needs to be improved. The disclosed devices and methods are directed to at least partially alleviate one or more problems set forth above and to solve other problems in the art.
SUMMARY
One aspect of the present disclosure provides a method for forming a semiconductor device. The method includes: providing a substrate; forming a source and drain material layer over the substrate; forming a mask layer on the source and drain material layer, and the mask layer includes a first trench and the first trench exposes a portion of the source and drain material layer; forming a protective layer on sidewalls of the first trench; forming a second trench in the source and drain material layer by etching the source and drain material layer at a bottom of the first trench using the mask layer and the protective layer as a mask; removing the protective layer after the second trench is formed; forming a channel material layer and a gate structure on the channel material layer after the protective layer is removed, and the channel material layer is on the sidewalls and the bottom of the first trench and on sidewalls and bottom of the second trench; and removing the mask layer after the channel material layer and the gate structure are formed.
Another aspect of the present disclosure provides a semiconductor device. The semiconductor device includes: a substrate; a source and drain material layer formed on the substrate, the source and drain material layer containing a first trench there-through; a mask layer formed on the source and drain material layer containing a second trench there-through, the second trench having a cross-section area larger than the first trench and covers the first trench; a channel material layer conformally formed on a bottom and sidewalls of each of the first trench and the second trench; and a gate structure conformally formed on the channel material layer, on the bottom and the sidewalls of each of the first trench and the second trench.
Other aspects or embodiments of the present disclosure can be understood by those skilled in the art in light of the description, the claims, and the drawings of the present disclosure.
BRIEF DESCRIPTION OF THE DRAWINGS
The following drawings are merely examples for illustrative purposes according to various disclosed embodiments and are not intended to limit the scope of the present disclosure.
FIG. 1 and FIG. 2 are schematic structural diagrams illustrating a process of forming a semiconductor device;
FIG. 3 illustrates an exemplary method for forming a semiconductor device according to the disclosed embodiments; and
FIGS. 4-13 illustrate semiconductor structures corresponding to certain stages of an exemplary fabrication process of a transistor consistent with the disclosed embodiments.
 DETAILED DESCRIPTION
Reference will now be made in detail to exemplary embodiments of the disclosure, which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts.
FIG. 1 and FIG. 2 are schematic structural diagrams illustrating a process of forming a semiconductor device.
In FIG. 1, a substrate 100 is provided, and an oxide layer 110 is formed on the substrate 100. A source and drain material layer 120 is formed on the oxide layer 110, and the source and drain material layer 120 is provided with a trench 130 passing through the source-drain material layer 120.
In FIG. 2, a channel material film (not shown) is formed on the two sidewalls and the bottom portions of trench 130 (refer to FIG. 1), the source drain material layer 120, and the substrate 100. The material of the channel material film may be MoS2. A gate structure material layer may be formed on the surface of the channel material film. A patterned gate structure material layer and the channel material film form a channel material layer 140 and a gate structure 150 on the top of channel material layer 140. The gate structure 150 corresponds to the gate structure material layer.
After the channel material layer 140 and the gate structure 150 are formed, the method further includes the following step: the source and drain ions are doped in the source and drain material layer 120 on the two sides of the gate structure 150; and a source and drain doped region is formed in the source and drain material layer 120 on the two sides of the gate structure 150.
However, the performance of the semiconductor device formed by the above method needs to be improved. The channel material layer 140 is located not only on the sidewalls and the bottom of the trench 130, but also on the source and drain material layer 120 on the two sides of the trench 130. As a result, the effective length of the channel material layer 140 is relatively large, and distance between the source and drain doped regions on the two sides of the gate structure 150 is also relatively large.
The method for forming the patterned gate structure material layer and the channel material film includes: forming a patterned photoresist layer on the gate structure material layer, and the photoresist layer only covers the gate structure material layer in the trench 130 and the portion of gate structure material layer located on the source and drain material layer 120 on the two sides of the trench 130; and etching the gate structure material layer and the channel material film by using the patterned photoresist layer as a mask until the source and drain material layer 120 is exposed.
The trench 130 may have a first sidewall and a second sidewall, facing each other. The first sidewall and the second sidewall of the trench 130 are respectively on the source and drain material layer 120.
Due to the influence of the photo etching alignment deviation, the position of the projection of the center of the gate structure 150 on the surface of the substrate 100 may be offset from the position of the projection of the center of the trench 130 on the surface of the substrate 100. The position of the projection of the center of the channel material layer 140 on the surface of the substrate 100 may also be offset from the position of the projection of the center of the trench 130 on the surface of the substrate 100. The size difference between the channel material layer 140 on the first side of the trench 130 and the second side of the trench 130 is relative large, and the gate structure 150 on the first side of the trench 130 and the gate structure 150 on the second side of the trench 130 are also different in size. Thus, the size of the source and drain doped region formed in the source and drain material layer 120 are very different from each other on the two sides of the trench, and the parameters of the current and the process design in the source-drain doped region. As a result, the stability of the electrical properties of the semiconductor device may be lowered.
The present disclosure provides a semiconductor device and a method for forming the semiconductor device. The method includes: providing a substrate; forming a source and drain material layer over the substrate; forming a mask layer on the source and drain material layer, and the mask layer includes a first trench and the first trench exposes a portion of the source and drain material layer; forming a protective layer on sidewalls of the first trench; forming a second trench in the source and drain material layer by etching the source and drain material layer at a bottom of the first trench using the mask layer and the protective layer as a mask; removing the protective layer after the second trench is formed; forming a channel material layer and a gate structure on the channel material layer after the protective layer is removed, and the channel material layer is on the sidewalls and the bottom of the first trench and on sidewalls and bottom of the second trench; and removing the mask layer after the channel material layer and the gate structure are formed.
With this method, the sizes of the source drain material layers on the two sides of the gate structure are consistent, and the stability of the electrical performance of the semiconductor device may be improved.
In accordance with some embodiments of the present disclosure, FIG. 3 is a flowchart illustrating a method for forming a semiconductor device. At step S101, a substrate is provided. A source and drain material layer is formed on the substrate at step S102. At step S103, a mask layer, which includes a first trench and the first trench exposes a portion of the source and drain material layer, is formed on the source and drain material layer. A protective layer is formed on sidewalls of the first trench at step S104. At step S105, a second trench passing through the source and drain material layer is formed by etching the source and drain material layer at a bottom of the first trench using the mask layer and the protective layer as a mask. The protective layer is removed after the second trench at step S106. At step S107, a channel material layer and a gate structure are formed on the channel material layer after the protective layer is removed, and the channel material layer is located on the sidewalls and the bottom of the first trench and the second trench. And at step 108, the mask layer is removed after the channel material layer and the gate structure are formed.
FIGS. 4-13 illustrate semiconductor structures corresponding to certain stages of an exemplary fabrication process of a transistor consistent with the disclosed embodiments.
As shown in FIG. 4, a substrate 200 is provided.
The substrate 200 may be a bulk silicon substrate, a bulk germanium substrate, a glass substrate, a silicon-on-insulator substrate, or a germanium-on-insulator substrate. In one embodiment, the substrate 200 may be a bulk silicon substrate.
In one embodiment, an interface layer 210 may be formed on the surface of the substrate 200.
The material of the interface layer 210 may be silicon oxide.
The interface layer 210 may isolate the substrate 200 from a subsequently formed source and drain material layer.
In FIG. 5, a source and drain material layer 220 may be formed on the substrate 200 and a mask layer 230 may be formed on the source and drain material layer 220, the mask layer 230 may include a first trench 231, and a portion of the source and drain material layer 220 may be exposed in the first trench 231.
In one embodiment, the interface layer 210 may be formed on the surface of the substrate 200 before the source and drain material layer 220 is formed.
The material of the source and drain material layer 220 may be, for example, polycrystalline silicon.
The process for forming the source and drain material layer 220 may be a deposition process, such as a plasma chemical vapor deposition process, a low-pressure chemical vapor deposition process, or a sub-atmospheric pressure chemical vapor deposition process.
The method for forming a mask layer 230 includes: forming a mask material layer on the source and drain material layer 220; and forming the mask layer 230 by patterning the mask material layer. The mask layer 230 may include the first trench 231 passing through the mask layer 230.
The mask layer 230 may be made of, for example, silicon oxide.
In FIG. 6, a protective layer 240 may be formed on the sidewalls of the first trench 231.
The mask layer 230 and the protective layer 240 are used jointly to define the position of a subsequent formed second trench.
The protective layer 240 may be formed by, for example, forming a protective material layer (not illustrated) on the sidewalls and the bottom of the first trench 231 and on the top surface of the mask layer 230; and forming the protective layer 240 by etching back the protective material layer until the top surface of the mask layer 230 and the top surface of the source and drain material layer 220 are exposed.
The process for forming the protective material layer may be a deposition process, such as an atomic layer deposition process, a plasma chemical vapor deposition process, a low-pressure chemical vapor deposition process, or a sub-atmospheric chemical vapor deposition process.
The material of the protective layer 240 and the material of the mask layer 230 are different. The protective layer 240 and the source and drain material layer 220 may also be made of different materials.
In the process of etching back the protective material layer, the protective material layer may have a relatively high etching selection ratio value comparing to the source and drain material layer 220. The protective material layer may have a higher etching selection ratio comparing to the mask layer 230. In the subsequent process of removing the protective layer 240, the protective layer 240 may have a higher etching selection ratio comparing to the source and drain material layer 220.
In one embodiment, the protective layer 240 may be made of silicon nitride.
As shown in FIG. 7, the mask layer 230 and the protective layer 240 are used as a mask to etch the source and drain material layer 220 on the bottom of the first trench 231, and the source and drain material layer 220 may include a second trench 222 passing through the source and drain material layer 220.
Using the mask layer 230 and the protective layer 240 as a mask, the process of etching the source and drain material layer 220 on the bottom of the first trench 231 may be an anisotropic dry etching process.
In one embodiment, the process of etching the source and drain material layer 220 on the bottom of the first trench 231 may use the interface layer 210 as an etching stop layer.
It should be noted that in one embodiment, the interface layer 210 may be optionally formed on the surface of the substrate 200 before the source and drain material layer 220 is formed. Therefore, the interface layer 210 may be exposed on the bottom of the second trench 222.
By using the mask layer 230 and the protective layer 240 as a mask to etch the source and drain material layer 220 on the bottom of the first trench 231, the distances from the center of the second trench 222 to the two sidewalls of the first trench 231 are consistent with each other.
The first trench 231 may cover the second trench 222. The first trench 231 may have a cross-section area larger than the second trench 222. In one embodiment, projections of centers of the first and second trenches on a surface the substrate may be substantially overlapped.
In FIG. 8, the protective layer 240 (see FIG. 7) may be removed after the second trench 222 is formed.
The process for removing the protective layer 240 may be an etching process, such as a dry etching process or a wet etching process.
In the process of removing the protective layer 240, the ratio of the etching rate between the protective layer 240 and the mask layer 230 may be in a range from 3 to 10.
In the process of removing the protective layer 240, the ratio of the etching rate between the protective layer 240 and the mask layer 220 may be in a range from 3 to 10.
A channel material layer and a gate structure on the channel material layer are formed after the protective layer 240 is removed. The channel material layer may be located on the sidewalls and the bottom of the first trench 231 and the sidewalls and the bottom of the second trench 222.
After the protective layer 240 is removed, the source and drain material layer 220, which is located on the two sides of the second trench 222 and on the bottom of the first trench 231, may be exposed. And the sizes of the source and drain material layer 220, located on the two sides of the second trench 222 and on the bottom of the first trench 231, are consistent with each other.
The method of forming the channel material layer and the gate structure is described below with reference to FIG. 9 and FIG. 10.
In FIG. 9, a channel material film 250 may be formed on the sidewalls and the bottom portion of the first trench 231, on the sidewalls and the bottom the second trench 222, and on the mask layer 230.
The channel material film 250 may further be formed on the surface of the interface layer 210.
The channel material film 250 may be used to form a channel material layer.
The material of the channel material film 250 may be MoS2, and the process for forming the channel material film 250 may be a solid source chemical vapor deposition process.
The material of the subsequently formed channel material layer may be a crystalline material. The electrical conductivity of the crystalline state material may be high, and the channel material layer may have a good conductive property.
The material of the channel material film 250 may be MoS2, and the channel material film 250 may be formed on the bottom of the second trench 222 by using a solid source chemical vapor deposition process. The channel material film 250 on the bottom of the second trench 222 may be used as a channel material layer on the bottom of the second trench 222.
In addition, when using MoS2 as the material for the channel material film 250, the channel material film 250 may be ultra-thin.
The solid source chemical vapor deposition process includes: taking a solid as a generating source; evaporating and sublimating the solid source; and forming a channel material film 250 with decomposition reactions in the atmosphere of the carrier gas.
When the channel material film 250 is made of MoS2, the parameters of the solid source chemical vapor deposition process may include: a solid source including MoO3 and S; a carrier gas including Ar; and a temperature in a range of approximately 600° C.-900° C., such as 755° C.
The thickness of the channel material film 250 may be in a range of approximately 5 nm-10 nm, such as about 7 nm. Thickness of the subsequently formed channel material layer may be in a range of approximately 5 nm-10 nm. The present method may be used to form a semiconductor device with an ultra-thin channel.
The thickness of the channel material film 250 may be in a range from 5 nm to 10 nm. If the channel material film 250 is thinner than 5 nm, it will be too difficult to control the process; and if the channel material film 250 is thicker than 10 nm, the subsequently formed channel material layer may be too thick, and it will be too hard to improve the control capability of the gate structure on the channel.
As illustrated in FIG. 9, a gate structure material layer 260 may be formed on the surface of the channel material film 250.
The gate structure material layer 260 may include: a gate dielectric material layer (not shown) on the surface of the channel material film 250; and a gate electrode material layer (not shown) on the surface of gate dielectric material layer.
The material of the gate dielectric material layer may be a high-k (k may be greater than 3.9) dielectric material.
The gate electrode material layer may be made of metal, such as copper and/or tungsten.
The process for forming the gate dielectric material layer may be a deposition process, such as an atomic layer deposition process, a plasma chemical vapor deposition process, a low-pressure chemical vapor deposition process, or a sub-atmospheric chemical vapor deposition process.
The process for forming the gate electrode material layer may be a deposition process, such as a sputtering process or a plasma chemical vapor deposition process.
In FIG. 10, a filling layer 270 may be formed to fill in the first trench 231 (see FIG. 9) and the second trench 222 (see FIG. 9) after the gate structure material layer 260 is formed.
The material of the filling layer 270 may be made of silicon oxide or a bottom anti-reflective coating (B ARC) material.
The process for forming the filling layer 270 may include a spin coating process.
As shown in FIG. 11, the gate structure material layer 260 and the channel material film 250 are planarized until the top surface of the mask layer 230 and the top surface of the filling layer 270 are exposed. Then the channel material film 250 forms a channel material layer 251, and the gate structure material layer 260 forms a gate structure 261.
The process for planarizing the gate structure material layer 260 and the channel material film 250 may be a chemical mechanical grinding process.
The channel material layer 251 may be made of MoS2.
The channel material layer 251 may be located not only on the sidewalls and the bottom of the second trench 222, but also on the bottom of the first trench 231. As a result, the effective length of the channel material layer 251 may be relatively big, and the distance between the source and drain doped regions on the two sides of the subsequent gate structure may be relatively big correspondingly. And the short channel effect of the semiconductor device may be improved.
The channel material layer 251 may be made of MoS2. The advantages of using MoS2 may include that the semiconductor device may be provided with an ultra-thin channel and the channel material layer 251 may be formed on the surface of the interface layer 210.
The thickness of the channel material layer 251 may be in a range of approximately 5 nm-10 nm.
The gate structure 261 may include a gate dielectric layer located on the channel material layer 251 and a gate electrode layer on the gate dielectric layer.
The gate dielectric layer corresponds to the gate dielectric material layer, and the gate electrode layer corresponds to the gate electrode material layer.
In FIG. 12, after the gate structure material layer 260 and the channel material film 250 are planarized, the filling layer 270 (see FIG. 11) may be removed.
In one embodiment, the method may further include removing the mask layer 230 (see FIG. 11) after forming a channel material layer 251 and a gate structure 261.
In one embodiment, the mask layer 230 may be removed in the process of removing the filler layer 270. The filling layer 270 and the mask layer 230 may be removed separately, in another embodiment.
In one embodiment, the filling layer 270 and the mask layer 230 may be removed by an etching process.
As shown in FIG. 13, after the mask layer 230 is removed, a source and drain doped region 280 may be formed on the two sides of the gate structure 261 in the source and drain material layer 220.
For example, source and drain ions may be injected into the source and drain material layer 220 on the two sides of the gate structure 261 by adopting an ion implantation process and a source and drain doped region 280 may be formed on the two sides of the gate structure 261 in the source and drain material layer 220.
After the channel material layer 251 and the gate structure 261 are formed, the size of the channel material layer 251 on the source and drain material layer 220 on one side of the second trench 222 may be consistent with that of the channel material layer 251 on the other side of the second trench 222. And the size of the gate structure 261 on the source and drain material layer 220 on one side of the second trench 222 may also be consistent with the size of the gate structure 261 on the other side of the second trench 222. Therefore, the sizes of the source and drain material layer 220 on the two sides of the gate structure 261 are consistent with each other, and the size of the source and drain doped region 280 may also be consistent. The self-aligned metal gate with channel substantially reduces the size difference of the source and drain material layer on the two sides of the gate structure 261. Therefore, the stability of the electrical performance of the semiconductor device may be improved.
As such, the source region and the drain region are formed in the source and drain material layer respectively on sides of the channel material layer. In one embodiment, projections of centers of the gate structure and the channel material layer on a surface the substrate may be substantially overlapped.
Correspondingly, the embodiment further provides a semiconductor device formed by the above discussed method. Comparing with the conventional techniques, the present disclosure has the following advantages. According to the forming method of the semiconductor device provided by present disclosure, the channel material layer is formed along the sidewalls and the bottom of the first trench and of the second trench, and an ultra-thin channel material layer is formed. The ultra-thin channel material layer limits the channel size of the semiconductor device, and the semiconductor device is provided with an ultra-thin channel. The channel material layer is located not only on the sidewalls and the bottom of the second trench, but also on the bottom of the first trench. Therefore, the effective length of the channel material layer is relatively large, and the short channel effect of the semiconductor device is further improved. Then a source and drain doped region is formed on the two sides of the gate structure in the source and drain material layer. A protective layer is formed on the sidewall of the first trench, and then the mask layer and the protective layer are used jointly to define the position of the second trench. The mask layer and the protective layer are used as a mask to etch the source and drain material layer on the bottom of the first trench, and the distances from the center of the second trench to the two sidewalls of the first trench are consistent with each other. The source and drain material layer, which is located on the two sides of the second trench and on the bottom of the first trench, is exposed after the protective layer is removed. The size of the source and drain material layer located on the two sides of the second trench and on the bottom of the first trench is also consistent with each other. After the channel material layer and the gate structure are formed, and the size of the channel material layer on the source/drain material layer on one side of the second trench is consistent with that of the channel material layer on the other side of the second trench. Similarly, the size of the gate structure on the source/drain material layer on one side of the second trench is consistent with that of the gate structure on the other side of the second trench. Therefore, the sizes of the source and drain material layer on the two sides of the gate structure are consistent with each other, and the stability of the electrical performance of the semiconductor device is improved.
The embodiments disclosed herein are exemplary only. Other applications, advantages, alternations, modifications, or equivalents to the disclosed embodiments are obvious to those skilled in the art and are intended to be encompassed within the scope of the present disclosure.

Claims (8)

What is claimed is:
1. A semiconductor device, comprising: a substrate; a source and drain material layer formed on the substrate, wherein the source and drain material layer contains a first trench extending there-through; a channel material layer, including a U-shape portion conformally formed on a bottom and sidewalls of the first trench and two L-shape portions formed on a top surface of the source and drain material layer, wherein the two L-shape portions connects with two ends of the U-shape portion, respectively, and the two L-shape portions form a second trench, and each of the two L-shape portions of the channel material layer includes: a first planar portion levelled on the top surface of the source and drain material layer, and a second planar portion directly on the top surface of the source and drain material layer, perpendicular to the first planar portion, and extending in a direction perpendicular to the top surface of the source and drain material layer; a source region and a drain region formed in the source and drain material layer respectively on sides of the channel material layer, wherein the second planar portion has a planar surface coplanar with a side surface of the source region and the drain region, and an undoped portion of the source and drain material layer is located between the source region and the channel material layer and another undoped portion of the source and drain material layer is located between the drain region and the channel material layer; and a gate structure conformally formed on the channel material layer, on the bottom and the sidewalls of each of the first trench and the second trench, wherein the gate structure has a recess and the recess has a symmetrical step structure.
2. The semiconductor device according to claim 1, wherein:
projections of centers of the gate structure and the channel material layer on a surface the substrate are substantially overlapped.
3. The semiconductor device according to claim 1, further including:
an interface layer formed between a surface of the substrate and the source and drain material layer, and
the first trench exposes a surface portion of the interface layer.
4. The semiconductor device according to claim 1, wherein:
the channel material layer is made of a material comprising MoS2.
5. The semiconductor device according to claim 1, wherein:
a thickness of the channel material layer is in a range of approximately 5 nm-10 nm.
6. The semiconductor device according to claim 1, wherein the gate structure layer comprises:
a gate dielectric layer on the channel material layer; and
a gate electrode layer on the gate dielectric layer.
7. The semiconductor device according to claim 1, further including:
an interface layer on a surface of the substrate.
8. The semiconductor device according to claim 7, wherein:
the source and drain material layer is on a top surface of the interface layer, and
the first trench exposes a portion of the top surface of the interface layer and the interface layer closes off the first trench at the top surface of the interface layer.
US16/704,127 2017-05-05 2019-12-05 Semiconductor device Active US11056579B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US16/704,127 US11056579B2 (en) 2017-05-05 2019-12-05 Semiconductor device

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
CN201710310410.X 2017-05-05
CN201710310410.XA CN108807177B (en) 2017-05-05 2017-05-05 Semiconductor device and method of forming the same
US15/964,738 US10535759B2 (en) 2017-05-05 2018-04-27 Semiconductor device and fabrication method thereof
US16/704,127 US11056579B2 (en) 2017-05-05 2019-12-05 Semiconductor device

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US15/964,738 Continuation US10535759B2 (en) 2017-05-05 2018-04-27 Semiconductor device and fabrication method thereof

Publications (2)

Publication Number Publication Date
US20200111899A1 US20200111899A1 (en) 2020-04-09
US11056579B2 true US11056579B2 (en) 2021-07-06

Family

ID=64015488

Family Applications (2)

Application Number Title Priority Date Filing Date
US15/964,738 Active US10535759B2 (en) 2017-05-05 2018-04-27 Semiconductor device and fabrication method thereof
US16/704,127 Active US11056579B2 (en) 2017-05-05 2019-12-05 Semiconductor device

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US15/964,738 Active US10535759B2 (en) 2017-05-05 2018-04-27 Semiconductor device and fabrication method thereof

Country Status (2)

Country Link
US (2) US10535759B2 (en)
CN (1) CN108807177B (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111640665B (en) * 2019-03-01 2023-05-26 中芯国际集成电路制造(上海)有限公司 Semiconductor device and method of forming the same
EP4195273A4 (en) * 2020-08-24 2024-01-31 Changxin Memory Tech Inc Semiconductor structure and manufacturing method therefor
US20220293736A1 (en) * 2021-03-11 2022-09-15 Taiwan Semiconductor Manufacturing Co., Ltd. 2D Channel Transistors with Low Contact Resistance

Citations (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6031261A (en) * 1997-12-15 2000-02-29 Lg Semicon Co., Ltd. Silicon-on-insulator-device and fabrication method thereof
US20050093033A1 (en) * 2003-09-05 2005-05-05 Atsuhiro Kinoshita Field effect transistor and manufacturing method thereof
US20060055392A1 (en) 2004-04-20 2006-03-16 Passmore John L Remotely communicating, battery-powered nanostructure sensor devices
US20090184389A1 (en) * 2005-05-09 2009-07-23 Bertin Claude L Nonvolatile Nanotube Diodes and Nonvolatile Nanotube Blocks and Systems Using Same and Methods of Making Same
US7622352B2 (en) 2006-03-15 2009-11-24 Promos Technologies Inc. Multi-step gate structure and method for preparing the same
US20110147742A1 (en) 2009-12-18 2011-06-23 Palo Alto Research Center Incorporated Thin Film Field Effect Transistor with Dual Semiconductor Layers
US20120049247A1 (en) * 2010-08-31 2012-03-01 Taiwan Semiconductor Manufacturing Company, Ltd. Modified profile gate structure for semiconductor device and methods of forming thereof
US20140134836A1 (en) * 2012-11-09 2014-05-15 GlobalFoundries, Inc. Dielectric cap layer for replacement gate with self-aligned contact
US20150041905A1 (en) * 2013-08-06 2015-02-12 International Business Machines Corporation Methods of forming replacement gate structures for transistors and the resulting devices
US20150243884A1 (en) 2014-02-27 2015-08-27 International Business Machines Corporation Metal nitride keyhole or spacer phase change memory cell structures
US20160218208A1 (en) * 2013-09-05 2016-07-28 Robert Bosch Gmbh Method for Producing a Substrate, Substrate, Metal-Oxide-Semiconductor Field-Effect Transistor with a Substrate, Micro-Electromechanical System with a Substrate, and Motor Vehicle
US20160358905A1 (en) 2015-06-05 2016-12-08 International Business Machines Corporation Compound semiconductor devices having buried resistors formed in buffer layer
US20160379901A1 (en) * 2015-06-29 2016-12-29 National Taiwan University Semiconductor Devices Comprising 2D-Materials and Methods of Manufacture Thereof
US20170263782A1 (en) * 2016-03-10 2017-09-14 Semiconductor Energy Laboratory Co., Ltd. Transistor and electronic device
US20180047851A1 (en) 2016-08-11 2018-02-15 Int Tech Co., Ltd. Vertical thin film transistor and method for fabricating the same

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100640159B1 (en) * 2005-03-31 2006-10-30 주식회사 하이닉스반도체 Semiconductor device increased channel length and method for manufacturing the same
KR100714307B1 (en) * 2005-08-05 2007-05-02 삼성전자주식회사 Semiconductor devices having recessed active edge and method of fabricating the same
CN103348464B (en) * 2011-01-26 2016-01-13 株式会社半导体能源研究所 Semiconductor device and manufacture method thereof
US8946812B2 (en) * 2011-07-21 2015-02-03 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
CN105552124B (en) * 2014-10-30 2018-11-16 中芯国际集成电路制造(上海)有限公司 Fin field effect pipe and forming method thereof

Patent Citations (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6031261A (en) * 1997-12-15 2000-02-29 Lg Semicon Co., Ltd. Silicon-on-insulator-device and fabrication method thereof
US20050093033A1 (en) * 2003-09-05 2005-05-05 Atsuhiro Kinoshita Field effect transistor and manufacturing method thereof
US20060055392A1 (en) 2004-04-20 2006-03-16 Passmore John L Remotely communicating, battery-powered nanostructure sensor devices
US20090184389A1 (en) * 2005-05-09 2009-07-23 Bertin Claude L Nonvolatile Nanotube Diodes and Nonvolatile Nanotube Blocks and Systems Using Same and Methods of Making Same
US7622352B2 (en) 2006-03-15 2009-11-24 Promos Technologies Inc. Multi-step gate structure and method for preparing the same
US20110147742A1 (en) 2009-12-18 2011-06-23 Palo Alto Research Center Incorporated Thin Film Field Effect Transistor with Dual Semiconductor Layers
US20120049247A1 (en) * 2010-08-31 2012-03-01 Taiwan Semiconductor Manufacturing Company, Ltd. Modified profile gate structure for semiconductor device and methods of forming thereof
US20140134836A1 (en) * 2012-11-09 2014-05-15 GlobalFoundries, Inc. Dielectric cap layer for replacement gate with self-aligned contact
US20150041905A1 (en) * 2013-08-06 2015-02-12 International Business Machines Corporation Methods of forming replacement gate structures for transistors and the resulting devices
US20160218208A1 (en) * 2013-09-05 2016-07-28 Robert Bosch Gmbh Method for Producing a Substrate, Substrate, Metal-Oxide-Semiconductor Field-Effect Transistor with a Substrate, Micro-Electromechanical System with a Substrate, and Motor Vehicle
US20150243884A1 (en) 2014-02-27 2015-08-27 International Business Machines Corporation Metal nitride keyhole or spacer phase change memory cell structures
US20160358905A1 (en) 2015-06-05 2016-12-08 International Business Machines Corporation Compound semiconductor devices having buried resistors formed in buffer layer
US20160379901A1 (en) * 2015-06-29 2016-12-29 National Taiwan University Semiconductor Devices Comprising 2D-Materials and Methods of Manufacture Thereof
US20170263782A1 (en) * 2016-03-10 2017-09-14 Semiconductor Energy Laboratory Co., Ltd. Transistor and electronic device
US20180047851A1 (en) 2016-08-11 2018-02-15 Int Tech Co., Ltd. Vertical thin film transistor and method for fabricating the same

Also Published As

Publication number Publication date
CN108807177A (en) 2018-11-13
US10535759B2 (en) 2020-01-14
US20180323289A1 (en) 2018-11-08
CN108807177B (en) 2021-07-13
US20200111899A1 (en) 2020-04-09

Similar Documents

Publication Publication Date Title
US11164786B2 (en) Power reduction in finFET structures
TWI736884B (en) Method for forming semiconductor device
US11056579B2 (en) Semiconductor device
CN106373924B (en) Method for forming semiconductor structure
US11588051B2 (en) Semiconductor device and fabrication method thereof
US20210398976A1 (en) Semiconductor structure and fabrication method thereof
US10833177B2 (en) Semiconductor device and fabrication method thereof
KR20180118586A (en) Semiconductor device and manufacturing method thereof
CN110364483B (en) Semiconductor structure and forming method thereof
CN109979986B (en) Semiconductor device and method of forming the same
US20200411361A1 (en) Semiconductor structure and formation method thereof
CN111354641B (en) Semiconductor device and method of forming the same
US10748814B2 (en) Fabrication method of semiconductor device by removing sacrificial layer on gate structures
CN110931356B (en) Semiconductor structure and manufacturing method thereof
CN113363321A (en) Semiconductor structure and forming method thereof
TWI785537B (en) Semiconductor device and method of forming thereof
CN113823691B (en) Semiconductor device and method of forming the same
CN113363154B (en) Method for forming semiconductor structure
CN113903666B (en) Semiconductor structure and forming method thereof
CN112992679B (en) Semiconductor structure and forming method thereof
US11011608B2 (en) Semiconductor structure and method for forming the same
US20220005931A1 (en) Semiconductor device and forming method thereof
CN113903666A (en) Semiconductor structure and forming method thereof
CN114823895A (en) Semiconductor structure and forming method thereof
CN114695348A (en) Semiconductor structure and forming method thereof

Legal Events

Date Code Title Description
FEPP Fee payment procedure

Free format text: ENTITY STATUS SET TO UNDISCOUNTED (ORIGINAL EVENT CODE: BIG.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

STPP Information on status: patent application and granting procedure in general

Free format text: DOCKETED NEW CASE - READY FOR EXAMINATION

STPP Information on status: patent application and granting procedure in general

Free format text: NON FINAL ACTION MAILED

STPP Information on status: patent application and granting procedure in general

Free format text: FINAL REJECTION MAILED

STPP Information on status: patent application and granting procedure in general

Free format text: NOTICE OF ALLOWANCE MAILED -- APPLICATION RECEIVED IN OFFICE OF PUBLICATIONS

STPP Information on status: patent application and granting procedure in general

Free format text: PUBLICATIONS -- ISSUE FEE PAYMENT VERIFIED

STCF Information on status: patent grant

Free format text: PATENTED CASE