US10833017B2 - Contact for semiconductor device - Google Patents
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- US10833017B2 US10833017B2 US15/352,342 US201615352342A US10833017B2 US 10833017 B2 US10833017 B2 US 10833017B2 US 201615352342 A US201615352342 A US 201615352342A US 10833017 B2 US10833017 B2 US 10833017B2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
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- H—ELECTRICITY
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
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- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
- H01L23/53223—Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53257—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a refractory metal
- H01L23/53266—Additional layers associated with refractory-metal layers, e.g. adhesion, barrier, cladding layers
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
Definitions
- aspects of the present disclosure relate to semiconductor devices, and more particularly to a contact that reduces spreading resistance and prevents contact to gate shorting.
- Interconnect layers connect different components of an integrated circuit. As device geometries become smaller, the separation between interconnect components (such as contacts) and/or transistors becomes smaller.
- Some implementations for small geometry circuitry are designed such that a distance between two components (e.g., contact and gate, gate and gate, or between multiple gates) is below or near the limit of design geometry constraints.
- a distance between a gate contact and an active contact e.g., contact associated with a source or drain of a transistor
- the spacing between gates becomes small, there is an increased risk that a gate contact will electrically connect to the source/drain contact. As a result, performance of the semiconductor device is degraded.
- a semiconductor device may include a source/drain contact trench adjacent to a gate.
- the term “source/drain” refers to a source or a drain.
- the source/drain contact trench may include a first portion and a second portion on the first portion.
- the semiconductor device may also include an insulating contact spacer liner within the source/drain contact trench. The insulating contact spacer liner contacts the first portion but not the second portion of the source/drain contact trench.
- the semiconductor device may further include a conductive material within the insulating contact spacer liner and the second portion of the source/drain contact trench, and landing in a source/drain region of the semiconductor device. For example, the conductive material lands in the source/drain region such the conductive material contacts the source/drain region.
- a method of making a semiconductor device may include etching a dielectric layer proximate a gate of the semiconductor device without reaching a source/drain region of the semiconductor device to open a first portion of a source/drain contact trench.
- the method may also include depositing an insulating contact spacer liner within the first portion of the source/drain contact trench.
- the method may further include etching through the insulating contact spacer liner at a base of the first portion of the source/drain contact trench to open a second portion of the source/drain contact trench to expose a source/drain region of the semiconductor device.
- the method may include depositing a conductive material on an exposed portion of the source/drain region of the semiconductor device.
- a semiconductor device may include a source/drain contact trench adjacent to a gate.
- the source/drain contact trench may include a first portion and a second portion on the first portion.
- the first portion may touch or physically contact the second portion.
- the semiconductor device may further include means for electrically isolating the source/drain contact trench.
- the isolating means lines the first portion but not the second portion of the source/drain contact trench.
- the semiconductor device may include a conductive material within the isolating means and the second portion of the source/drain contact trench, and landing in a source/drain region of the semiconductor device.
- FIG. 1 illustrates a perspective view of a semiconductor wafer in an aspect of the present disclosure.
- FIG. 2 illustrates a cross-sectional view of a die in accordance with an aspect of the present disclosure.
- FIG. 3 illustrates a cross-sectional view of a metal-oxide-semiconductor field-effect transistor (MOSFET) device in an aspect of the present disclosure.
- MOSFET metal-oxide-semiconductor field-effect transistor
- FIG. 4 illustrates a side view of an integrated circuit device including a middle-of-line interconnect layer.
- FIG. 5 illustrates a cross-sectional view of a semiconductor device.
- FIG. 6 illustrates a cross-sectional view of a semiconductor device according to an aspect of the present disclosure.
- FIGS. 7, 8, and 9A-9B illustrate cross-sectional views of exemplary processing to form a contact according to aspects of the present disclosure.
- the term “exemplary” refers to a non-limiting example.
- FIG. 9C illustrates multiple layers of the conductive contact within a second portion of a source/drain contact trench according to aspects of the present disclosure.
- FIG. 10 is a process flow diagram illustrating semiconductor device that reduces spreading resistance and prevents or reduces contact to gate shorting according to one aspect of the present disclosure.
- FIG. 11 is a block diagram showing an exemplary wireless communication system in which a configuration of the disclosure may be advantageously employed.
- FIG. 12 is a block diagram illustrating a design workstation used for circuit, layout, and logic design of a semiconductor component according to one configuration.
- Front-end-of-line processes include wafer preparation, isolation, well formation, gate patterning, spacers, and dopant implantation.
- a middle-of-line process may include gate and terminal contact formation. The gate and terminal contact formation of the middle-of-line process, however, is an increasingly challenging part of the fabrication flow, particularly for lithography patterning.
- Back-end-of-line processes include forming interconnects and dielectric layers for coupling to the FEOL devices. These interconnects may be fabricated with a dual damascene process using plasma-enhanced chemical vapor deposition (PECVD) deposited interlayer dielectric (ILD) materials.
- PECVD plasma-enhanced chemical vapor deposition
- ILD interlayer dielectric
- the number of interconnect levels for circuitry has substantially increased due to the large number of transistors that are now interconnected in a modern microprocessor.
- the increased number of interconnect levels for supporting the increased number of transistors involves more intricate middle-of-line processes to perform the gate and terminal contact formation.
- the separation between contacts and/or transistors is very small so that the components (e.g., transistor including gates, contacts, etc.) of current semiconductor devices have to be provided in accordance with a smaller geometry relative to their predecessors.
- Some implementations for small geometry circuitry are designed such that a distance between two components (e.g., contact and gate, gate and gate, or between multiple gates) is below or near the limit of design geometry constraints.
- a distance between a gate contact and an active contact e.g., contact associated with a source or drain of a transistor
- the spacing between gates becomes small, there is an increased risk that the gate contact will electrically connect to the source/drain contact. As a result, performance of the semiconductor device is degraded.
- a smaller geometry increases the likelihood of a short between the gate and a conductive contact to the diffusion region of the semiconductor device.
- the short may occur in a region that is not within the substrate.
- the short may occur at a region of the source/drain contact and the gate that is away from (e.g., above) the substrate.
- the reduced geometry may lead to opening of a source/drain contact trench for a conductive contact having a tapered shape.
- the tapered shape of the source/drain contact trench may cause unintended contact between a sidewall of the conductive contact and the gate as the conductive contact tapers toward the gate as the contact extends away from the substrate.
- the tapered shape of the conductive contact increases the possibility of a short between the conductive contact and the gate.
- the gate height may be thirty nanometers from a surface of the substrate to a distal portion of the gate.
- Mitigating degradation of semiconductor device performance involves isolating one semiconductor device and/or component from one another.
- adjacent devices such as transistors
- the term “adjacent” may refer to a neighboring relationship.
- the term “adjacent” may refer to a distance relationship understood by persons of ordinary skill in the art or defined by a design rule.
- spacers may be adopted to separate the devices or components. For example, to prevent a conductive contact to gate short, contact inner spacers are adopted to separate the conductive material of an active contact from the gate. The inner spacer may be deposited inside a contact trench to separate the conductive material of the contact from the gate.
- the term “deposit” may refer to providing by a means that is not limited to deposition.
- the inner spacer may be lined on one or more walls (sidewalls) of the contact trench and ultimately also on walls of the contact material when the trench is filled with the contact material.
- the inner spacer may be provided when the contact hole (or trench) is etched by depositing the inner spacer (e.g., dielectric material) on the sidewalls of the contact trench before the contact material fills the contact trench.
- the dielectric may be an insulator material such as silicon nitride (Si 3 N 4 ) or silicon oxynitride (SiON).
- the inner contact may prevent a short between the gate and the contact when the contact trench is filled with the conductive material.
- the inner spacer on the sidewalls of the conductive contact introduces large spreading resistance.
- current e.g., charge carriers forming a conductive path
- the spreading resistance may substantially degrade the semiconductor device performance.
- the inner spacer blocks the flow of current (e.g., charge carriers) from the conductive contact to the channel.
- the conductive contact may be etched deeper into the substrate to accommodate different devices or components of different shapes and sizes. The depth of the etch guarantees electrical contact between the conductive contact and a diffusion region of the substrate.
- the current has to spread or be carried over a longer distance, which introduces spreading resistance.
- a contact spacer liner (e.g., an insulating contact spacer liner) may be formed on a first portion of a source/drain contact trench above a source/drain region of a semiconductor device.
- a second portion of the source/drain contact trench may expose and land in the source/drain region of the semiconductor device.
- the second portion of the source/drain contact trench does not include the contact spacer liner.
- the contact spacer liner is only deposited in the first (e.g., upper) portion of the source/drain contact trench where it is effective for preventing a short between the gate and the conductive contact.
- the contact is not deposited in the second portion of the source/drain contract trench, where the presence of an inner spacer may cause spreading resistance.
- the first portion of the conductive contact may be separated by a predetermined distance (e.g., 2-5 nanometers) from the gate.
- the second (e.g., lower) portion of the source/drain contact trench does not include the contact spacer liner to prevent resistance spreading.
- the second portion of the conductive contact may be partially below the surface of the substrate where the source/drain contact trench is etched. Conductive contact material may be deposited into the trench on an exposed source/drain region of the substrate. The conductive contact does not extend through the substrate.
- the second portion of the source/drain contact trench may include a barrier layer (e.g., tantalum nitride or titanium nitride) between a conductive material (e.g., tungsten, copper, aluminum, titanium, or cobalt) and a contact layer (e.g., titanium and/or nickel).
- multiple layers may be deposited into the trench.
- One of the layers may include a contact silicide layer such as titanium or nickel.
- the contact silicide layer forms a metal silicide silicon or silicon germanium at the source and/or drain region.
- Another layer e.g., second layer
- the contact e.g., conductive material such as copper (Cu), tungsten (W), aluminum or other conductive material
- Cu copper
- W tungsten
- aluminum or other conductive material may be deposited in the trench after the first and second layer are deposited in the trench. Because the second portion of the conductive contact is free of the contact spacer liner, contact spreading resistance is low.
- the semiconductor device may include a source/drain contact trench adjacent to a gate.
- the source/drain contact trench may include a first portion (e.g., the upper portion) and a second portion (e.g., the lower portion) on the first portion.
- the first portion may touch, continue from, or may physically contact the second portion.
- the first portion may be separated from the second portion by an intervening portion and therefore may not be physically in contact with the second portion.
- the semiconductor device may also include a contact spacer liner within the source/drain contact trench.
- the contact spacer liner may line the first portion but not line the second portion of the source/drain contact trench.
- a conductive material e.g., tungsten
- the conductive material may extend through the contact spacer liner and the second portion of the source/drain contact trench, and land in a source/drain region of the semiconductor device. In other words, the conductive material may be within the contact spacer liner and the second portion of the source/drain contact trench and physically contact the source/drain region.
- a gate spacer may be positioned between the gate and the first portion of the conductive contact.
- the gate spacer may be on a sidewall of the gate, contacting the first portion, but not the second portion of the source/drain contact trench.
- the conductive material may be separated from the gate spacer by the contact spacer liner.
- the gate spacer may be silicon nitride.
- the contact spacer liner may be an insulator material including silicon nitride (Si 3 N 4 ) or silicon oxynitride (SiON).
- the gate spacer material may be different from the contact spacer liner material.
- the conductive contact may be a source/drain contact configured to contact the source/drain region of the semiconductor device. Accordingly, at least some portions of the second lower portion of the contact may be positioned on the source/drain region of the substrate.
- Some aspects of the present disclosure are directed to a method of reducing spreading resistance and preventing contact to gate shorting.
- the method may involve a two-step contact etch to form a contact to a diffusion region of a semiconductor device.
- the method of making the semiconductor device may include a first etch process, which may include etching a dielectric layer proximate a gate of the semiconductor device without etching into the substrate of the semiconductor device.
- proximate may indicate a minimum design rule spacing. In another example, “proximate” may be a close spacing understood by persons of ordinary skill in the art.
- the dielectric layer may be etched to create an active contact trench for the conductive contact, while leaving a portion of a dielectric layer between the active contact trench and the substrate (e.g., the source/drain region of the substrate).
- the dielectric layer of the semiconductor device may be an inter-layer dielectric (ILD).
- a timed etch may be performed to stop at a time corresponding to the first portion of the source/drain contact trench, so that a portion of the dielectric layer remains between the source/drain contact trench and the source/drain region of the semiconductor device.
- the etching may be a reactive ion etching (RIE), for example, carbon tetrafluoride (CF4) or sulfur hexafluoride (SF6).
- RIE reactive ion etching
- the etch may be in one direction.
- the etch may be a directional etch.
- the contact spacer (e.g., a contact spacer liner) may be deposited within only the first portion of the source/drain contact trench.
- the contact spacer liner may be deposited inside the contact trench to separate conductive material of the conductive contact from an adjacent gate.
- the contact spacer liner may be deposited on one or more walls (e.g., sidewalls and a base portion) of the source/drain contact trench and ultimately also on walls of the conductive contact when the source/drain contact trench is filled with a conductive contact material.
- the base of the source/drain contact trench may be on a surface of a portion of the dielectric layer that is between the substrate and the source/drain contact trench.
- the contact spacer liner may be a low K material.
- a second etch process may include etching through the contact spacer liner at a base of the source/drain contact trench to open a second portion of the source/drain contact trench exposing and landing in the source/drain region of the semiconductor device.
- the second etch process may include etching through the contact spacer liner, through the remaining dielectric separating the source/drain contact trench and the substrate and into the substrate (e.g., the source/drain region of the substrate) to expose the source/drain region of the substrate without etching entirely through the substrate. No contact spacer liner is introduced to the newly etched region, which forms the second portion (e.g., a lower portion) of the source/drain contact trench.
- the second portion of the contact trench is not surrounded with the contact spacer liner to prevent resistance spreading.
- the etch process may be slowed, which signals the start of the etch of the substrate.
- the etch rate may be reduced, indicating exposure of the source/drain region.
- the second etch process may be an anisotropic etch to break through the contact spacer liner at the base of the first portion of the source/drain contact trench and further into the source/drain region.
- a conductive material may be deposited to fill the source/drain contact trench with the conductive material.
- the conductive material may be deposited in the source/drain contact trench so that the conductive material is on the exposed portion of the source/drain region of the semiconductor device.
- FIG. 1 illustrates a perspective view of a semiconductor wafer in an aspect of the present disclosure.
- a wafer 100 may be a semiconductor wafer, or may be a substrate material with one or more layers of semiconductor material on a surface of the wafer 100 .
- the wafer 100 may be grown from a seed crystal using the Czochralski process, where the seed crystal is dipped into a molten bath of semiconductor material and slowly rotated and removed from the bath. The molten material then crystallizes onto the seed crystal in the orientation of the crystal.
- the wafer 100 may be a compound material, such as gallium arsenide (GaAs) or gallium nitride (GaN), a ternary material such as indium gallium arsenide (InGaAs), quaternary materials, or any material that can be a substrate material for other semiconductor materials. Although many of the materials may be crystalline in nature, polycrystalline or amorphous materials may also be used for the wafer 100 .
- the wafer 100 may be supplied with materials that make the wafer 100 more conductive.
- a silicon wafer may have phosphorus or boron added to the wafer 100 to allow for electrical charge to flow in the wafer 100 .
- These additives are referred to as dopants, and provide extra charge carriers (either electrons or holes) within the wafer 100 or portions of the wafer 100 .
- the wafer 100 has an orientation 102 that indicates the crystalline orientation of the wafer 100 .
- the orientation 102 may be a flat edge of the wafer 100 as shown in FIG. 1 , or may be a notch or other indicia to illustrate the crystalline orientation of the wafer 100 .
- the orientation 102 may indicate the Miller Indices for the planes of the crystal lattice in the wafer 100 .
- the wafer 100 is divided up along dicing lines 104 .
- the dicing lines 104 indicate where the wafer 100 is to be broken apart or separated into pieces.
- the dicing lines 104 may define the outline of the various integrated circuits that have been fabricated on the wafer 100 .
- the wafer 100 may be sawn or otherwise separated into pieces to form die 106 .
- Each of the die 106 may be an integrated circuit with many devices or may be a single electronic device.
- the physical size of the die 106 which may also be referred to as a chip or a semiconductor chip, depends at least in part on the ability to separate the wafer 100 into certain sizes, as well as the number of individual devices that the die 106 is designed to contain.
- the die 106 may be mounted into packaging to allow access to the devices and/or integrated circuits fabricated on the die 106 .
- Packaging may include single in-line packaging, dual in-line packaging, motherboard packaging, flip-chip packaging, indium dot/bump packaging, or other types of devices that provide access to the die 106 .
- the die 106 may also be directly accessed through wire bonding, probes, or other connections without mounting the die 106 into a separate package.
- FIG. 2 illustrates a cross-sectional view of a die 106 in accordance with an aspect of the present disclosure.
- a substrate 200 which may be a semiconductor material and/or may act as a mechanical support for electronic devices.
- the substrate 200 may be a doped semiconductor substrate, which has either electrons (designated N-channel) or holes (designated P-channel) charge carriers present throughout the substrate 200 . Subsequent doping of the substrate 200 with charge carrier ions/atoms may change the charge carrying capabilities of the substrate 200 .
- a substrate 200 there may be wells 202 and 204 , which may be the source and/or drain of a field-effect transistor (FET), or wells 202 and/or 204 may be fin structures of a fin structured FET (FinFET).
- Wells 202 and/or 204 may also be other devices (e.g., a resistor, a capacitor, a diode, or other electronic devices) depending on the structure and other characteristics of the wells 202 and/or 204 and the surrounding structure of the substrate 200 .
- the semiconductor substrate may also have a well 206 and a well 208 .
- the well 208 may be completely within the well 206 , and, in some cases, may form a bipolar junction transistor (BJT).
- BJT bipolar junction transistor
- the well 206 may also be used as an isolation well to isolate the well 208 from electric and/or magnetic fields within the die 106 .
- Layers may be added to the die 106 .
- the layer 210 may be, for example, an oxide or insulating layer that may isolate the wells (e.g., 202 - 208 ) from each other or from other devices on the die 106 .
- the layer 210 may be silicon dioxide, a polymer, a dielectric, or another electrically insulating layer.
- the layer 210 may also be an interconnection layer, in which case it may comprise a conductive material such as copper, tungsten, aluminum, an alloy, or other conductive or metallic materials.
- the layer 212 may also be a dielectric or conductive layer, depending on the desired device characteristics and/or the materials of the layers (e.g., 210 and 214 ).
- the layer 214 may be an encapsulating layer, which may protect the layers (e.g., 210 and 212 ), as well as the wells 202 - 208 and the substrate 200 , from external forces.
- the layer 214 may be a layer that protects the die 106 from mechanical damage, or the layer 214 may be a layer of material that protects the die 106 from electromagnetic or radiation damage.
- Electronic devices designed on the die 106 may comprise many features or structural components.
- the die 106 may be exposed to any number of methods to impart dopants into the substrate 200 , the wells 202 - 208 , and, if desired, the layers (e.g., 210 - 214 ).
- the die 106 may be exposed to ion implantation, deposition of dopant atoms that are driven into a crystalline lattice through a diffusion process, chemical vapor deposition, epitaxial growth, or other methods.
- the substrate 200 , the wells 202 - 208 , and the layers (e.g., 210 - 214 ) may be selectively removed or added through various processes.
- Chemical wet etching, chemical mechanical planarization (CMP), plasma etching, photoresist masking, damascene processes, and other methods may create the structures and devices of the present disclosure.
- FIG. 3 illustrates a cross-sectional view of a metal-oxide-semiconductor field-effect transistor (MOSFET) device 300 in an aspect of the present disclosure.
- the MOSFET device 300 may have four input terminals. The four inputs are a source 302 , a gate 304 , a drain 306 , and a substrate 308 .
- the source 302 and the drain 306 may be fabricated as the wells 202 and 204 in the substrate 308 , or may be fabricated as areas above the substrate 308 , or as part of other layers on the die 106 .
- Such other structures may be a fin or other structure that protrudes from a surface of the substrate 308 .
- the substrate 308 may be the substrate 200 on the die 106 , but substrate 308 may also be one or more of the layers (e.g., 210 - 214 ) that are coupled to the substrate 200 .
- the MOSFET device 300 is a unipolar device, as electrical current is produced by only one type of charge carrier (e.g., either electrons or holes) depending on the type of MOSFET.
- the MOSFET device 300 operates by controlling the amount of charge carriers in the channel 310 between the source 302 and the drain 306 .
- a voltage Vsource 312 is applied to the source 302
- a voltage Vgate 314 is applied to the gate 304
- a voltage Vdrain 316 is applied to the drain 306 .
- a separate voltage Vsubstrate 318 may also be applied to the substrate 308 , although the voltage Vsubstrate 318 may be coupled to one of the voltage Vsource 312 , the voltage Vgate 314 or the voltage Vdrain 316 .
- the voltage Vgate 314 creates an electric field in the channel 310 when the gate 304 accumulates charges.
- the opposite charge to that accumulating on the gate 304 begins to accumulate in the channel 310 .
- the gate insulator 320 insulates the charges accumulating on the gate 304 from the source 302 , the drain 306 , and the channel 310 .
- the gate 304 and the channel 310 with the gate insulator 320 in between, create a capacitor, and as the voltage Vgate 314 increases, the charge carriers on the gate 304 , acting as one plate of this capacitor, begin to accumulate.
- This accumulation of charges on the gate 304 attracts the opposite charge carriers into the channel 310 .
- the amount of voltage applied to the gate 304 that opens the channel 310 may vary.
- the voltage Vsource 312 is usually of a higher potential than that of the voltage Vdrain 316 .
- Making the voltage differential between the voltage Vsource 312 and the voltage Vdrain 316 larger will change the amount of the voltage Vgate 314 used to open the channel 310 .
- a larger voltage differential will change the amount of electromotive force moving charge carriers through the channel 310 , creating a larger current through the channel 310 .
- the gate insulator 320 material may be silicon oxide, or may be a dielectric or other material with a different dielectric constant (k) than silicon oxide. Further, the gate insulator 320 may be a combination of materials or different layers of materials. For example, the gate insulator 320 may be Aluminum Oxide, Hafnium Oxide, Hafnium Oxide Nitride, Zirconium Oxide, or laminates and/or alloys of these materials. Other materials for the gate insulator 320 may be used without departing from the scope of the present disclosure.
- the amount of charge on the gate 304 to open the channel 310 may vary.
- a symbol 322 showing the terminals of the MOSFET device 300 is also illustrated.
- N-channel MOSFETs using electrons as charge carriers in the channel 310
- an arrow is applied to the substrate 308 terminal in the symbol 322 pointing away from the gate 304 terminal.
- p-type MOSFETs using holes as charge carriers in the channel 310
- an arrow is applied to the substrate 308 terminal in the symbol 322 pointing towards the gate 304 terminal.
- the gate 304 may also be made of different materials.
- the gate 304 is made from polycrystalline silicon, also referred to as polysilicon or poly, which is a conductive form of silicon.
- polysilicon also referred to as “poly” or “polysilicon” herein, metals, alloys, or other electrically conductive materials are contemplated as appropriate materials for the gate 304 as described in the present disclosure.
- a high-k value material may be desired in the gate insulator 320 , and in such designs, other conductive materials may be employed.
- a “high-k metal gate” design may employ a metal, such as copper, for the gate 304 terminal.
- metal such as copper
- polycrystalline materials, alloys, or other electrically conductive materials are contemplated as appropriate materials for the gate 304 as described in the present disclosure.
- interconnect traces or layers are used. These interconnect traces may be in one or more of layers (e.g., 210 - 214 ), or may be in other layers of the die 106 .
- FIG. 4 shows a cross-sectional view illustrating an integrated circuit (IC) device 400 in which routing of conductive layers is performed within a middle-of-line (MOL) interconnect layer 410 according to one aspect of the disclosure.
- the IC device 400 may include a semiconductor substrate (e.g., a silicon wafer) 402 having inter-layer dielectric 404 . Within the inter-layer dielectric 404 and the substrate 402 is an active region in which active devices having a source region, a drain region, and a gate region (e.g., one of the conductive gates 406 ) are formed.
- the first MOL interconnect layer 410 may include a set of active (oxide diffusion (OD)) contacts, which are often referred to as metal diffusion (MD1) contacts, shown as MD1 412 - 1 , 412 - 2 , 412 , 3 , 412 - 4 , and 412 - 5 (collectively or generally referred to as MD1 412 ).
- the MD1 active contacts 412 are fabricated on the substrate 402 .
- the active contacts 412 may be coupled to the active devices (e.g., the source and drain regions).
- FIG. 5 illustrates a cross-sectional view of a semiconductor device 500 .
- the semiconductor device 500 may have several input terminals.
- the inputs may include a source (not shown) a gate 502 (e.g., similar to the conductive gates 406 or 304 ), a drain (not shown), and a substrate 504 .
- the source and the drain may be fabricated as wells in the substrate 504 , or may be fabricated as areas above the substrate, or as part of other layers on the die 106 , if desired.
- the source/drain may be represented by a source/drain region 506 .
- the source/drain region 506 may be similar to the source 302 or the drain 306 of FIG. 3 .
- the substrate 504 may be the substrate 200 on the die 106 , the substrate 504 may also be one or more of the layers 210 - 214 that are coupled to the substrate 200 .
- An adjacent conductive gate 512 is also shown, however, prevention of contact to gate shorting is described below with reference to the gate 502 .
- the semiconductor device 500 may include an interconnect layer 514 .
- the interconnect layer 514 is a middle-of-line (MOL) interconnect layer (e.g., 410 of FIG. 4 ).
- the interconnect layer 514 may include an inter-layer dielectric 516 , a gate 502 , a conductive contact 510 , and a gate spacer 520 (e.g., silicon nitride (SiN) spacer).
- the gate spacer 520 is positioned between the gate 502 and the conductive contact 510 .
- the gate spacer 520 is on a sidewall of the gate 502 and a sidewall of a source/drain contact trench 530 .
- spacers are adopted to electrically isolate the active devices from the conductive contacts.
- a contact spacer liner 508 is deposited to electrically isolate the conductive contact 510 (e.g., tungsten) from the gate 502 .
- the conductive contact 510 may be coupled to the diffusion regions of the active devices (e.g., the source and drain regions) of the substrate. For example, a portion of the conductive contact 510 may touch a source/drain region 506 of the substrate.
- the gate spacer 520 and the contact spacer liner 508 prevent the gate 502 from shorting to the conductive contact 510 when a separation 524 between the gate 502 and the conductive contact 510 is very small.
- the short may occur in a region that is not within the substrate 504 .
- the short may occur at a region of the conductive contact 510 and the gate 502 that is separate from the substrate 504 . This follows because the source/drain contact trench 530 and the conductive contact 510 are tapered.
- the conductive contact 510 tapers toward the gate 502 the further away regions of the conductive contact 510 are from the substrate 504 .
- the increased diameter of the conductive contact 510 toward the gate 502 increases the possibility of a short between the conductive contact 510 and the gate 502 , in an area where the conductive contact 510 is closest to the gate 502 (e.g., at separation 524 ).
- the contact spacer liner 508 on the sidewall of the conductive contact 510 proximate the contact region 526 introduces large spreading resistance.
- current charge carriers forming a conductive path
- the spreading resistance may substantially degrade the semiconductor device performance.
- the contact spacer liner 508 blocks the flow of current (e.g., charge carriers) from the conductive contact 510 to the channel.
- the current is carried over a longer distance (as shown by arrows 528 ), which introduces spreading resistance.
- aspects of the present disclosure are directed to reducing spreading resistance while preventing contact to gate shorting.
- the inner spacer may be formed only on portions of the contact where the inner spacer is effective to reduce a short between the gate and the contact.
- the inner space is not formed on other portions where a presence of the inner spacer may cause the spreading resistance.
- FIG. 6 illustrates a cross-sectional view of a semiconductor device 600 including a contact that reduces spreading resistance and prevents contact to gate shorting according to an aspect of the present disclosure.
- the semiconductor device 600 may include the source/drain region 506 adjacent to a gate 502 .
- the gate may include multiple layers of material.
- the gate 502 may be a replacement metal gate including one or more layers surrounding a conductive material to form a gate electrode.
- a source/drain contact trench 530 of the semiconductor device 600 may include a first portion (e.g., the upper portion) 532 and a second portion (e.g., the lower portion) 534 on the first portion 532 .
- the semiconductor device 600 may also include a contact spacer liner (e.g., the inner spacer) 508 within the source/drain contact trench 530 .
- the contact spacer liner 508 contacts the first portion 532 but does not contact the second portion 534 of the source/drain contact trench 530 .
- a conductive material e.g., tungsten
- the conductive material may extend through the contact spacer liner 508 and the second portion 534 of the source/drain contact trench 530 , and land in a source/drain region 506 of the semiconductor device 600 .
- the second portion may have a height of 205 nm from a surface within the substrate 504 to a section 540 , in one exemplary configuration.
- a gate spacer 520 may be positioned between the gate 502 and the first portion (or at least some portions of the first portion) 532 .
- the gate spacer 520 may be on a sidewall of the gate 502 and the first portion 532 and not on the second portion 534 of the source/drain contact trench 530 .
- the conductive contact 510 may be separated from the gate spacer 520 by the contact spacer liner 508 , an inter-layer dielectric 516 and/or both.
- the gate spacer 520 and the contact spacer liner 508 prevent the gate 502 from being shorted to the conductive contact 510 when a separation 524 between the gate 502 and the conductive contact 510 is very small.
- a region 544 at a distal portion of the gate 502 relative to a surface 538 is at risk of a gate to contact short.
- the gate spacer 520 may be silicon nitride.
- the conductive contact 510 may be a source/drain contact configured to provide contact to the source/drain region 506 of the semiconductor device 600 . Accordingly, at least some of the second portion 534 of the conductive contact 510 may be positioned on the source/drain region of the substrate 504 or within the source/drain region of the substrate 504 .
- the contact spacer liner 508 may be formed only on portions (e.g., the first portion 532 ) of the conductive contact 510 where the contact spacer liner 508 is effective to prevent a short between the gate 502 and the conductive contact 510 and not on other portions (e.g., the second portion 534 ) where a presence of the contact spacer liner 508 may cause spreading resistance.
- the first portion 532 of the conductive contact 510 may be separated by a distance 536 from the surface of the substrate 504 where the gate 502 is provided.
- the first portion 532 of the conductive contact 510 may start from a first upper portion section 540 proximate the substrate 504 and separated from the substrate 504 by the distance 536 to a second upper portion section 542 that is distal from the section 540 of the conductive contact 510 and further away from the surface 538 of the substrate 504 .
- the second portion 534 of the conductive contact 510 is not surrounded or lined with the contact spacer liner 508 in order to prevent resistance spreading.
- the second portion 534 may include a non-substrate portion of the spacer that is between the surface of the substrate 504 and the start of the upper portion of the contact (e.g., first upper portion section 540 ).
- the second portion 534 of the conductive contact 510 may also include a substrate portion that is below the surface of the substrate 504 when the source/drain contact trench 530 is etched into the substrate 504 .
- the conductive contact 510 may not extend through the substrate 504 . Because the second portion 534 of the conductive contact 510 is free of the contact spacer liner 508 , contact spreading resistance is low.
- FIGS. 7, 8, and 9A-9B illustrate cross-sectional views showing exemplary processing to form a semiconductor device including a contact for reducing spreading resistance and preventing contact to gate shorting, according to aspects of the present disclosure.
- some or all of the labelling and numbering of the components and features of FIGS. 7, 8, and 9A-9B are similar to those of FIGS. 5 and 6 .
- the method of forming the contact may involve a two-step etch.
- FIG. 7 illustrates a first etch of the two-step contact etch according to aspects of the present disclosure.
- the first etch may include etching the dielectric, insulator, and/or spacer layer proximate a gate 502 of a semiconductor device 700 without etching into a substrate 504 of the semiconductor device 700 .
- the dielectric, insulator, and/or spacer layer may include an inter-layer dielectric 516 , a gate spacer 520 or a combination of both.
- the dielectric, insulator, and/or spacer layer may be etched to open a source/drain contact trench 530 to enable formation of a conductive contact 510 , while leaving a layer of the dielectric, insulator, and/or spacer between the source/drain contact trench 530 and the substrate 504 (e.g., source/drain region 506 of the substrate).
- the dielectric, insulator, and/or spacer layer may be etched up to the first upper portion section 540 proximate to the substrate 504 .
- the section 540 may be separated from the substrate 504 by a distance 536 .
- a portion of the inter-layer dielectric 516 may remain between the source/drain region 506 of the substrate 504 and the source/drain contact trench 530 .
- the etching may be timed to stop at the first upper portion section 540 .
- the etching may be a reactive ion etch (RIE), for example, carbon tetrafluoride (CF4) or sulfur hexafluoride (SF6).
- RIE reactive ion etch
- the etch may be in one direction.
- the etch may be in a direction from the second upper portion section 542 to a surface 538 of the substrate 504 .
- FIG. 8 illustrates a process of depositing a contact spacer liner 508 according to aspects of the present disclosure.
- the contact spacer liner 508 may be deposited within the source/drain contact trench 530 to separate the conductive contact 510 from the gates 502 or 512 of a semiconductor device 800 .
- the contact spacer liner 508 may be lined on one or more walls (e.g., sidewalls and/or a bottom wall or base portion 507 ) of the source/drain contact trench 530 and ultimately also on walls of the contact material when the source/drain contact trench 530 is filled with the contact material.
- the bottom wall may be on a surface of the inter-layer dielectric 516 that is between the substrate 504 and the source/drain contact trench 530 .
- the contact spacer liner 508 may be provided by depositing the inner spacer (e.g., dielectric material) on the sidewalls and/or bottom wall of the source/drain contact trench 530 before the contact material for the conductive contact 510 fills the source/drain contact trench 530 .
- the inner spacer e.g., dielectric material
- FIG. 9A illustrates a second etch of the two-step contact etch according to aspects of the present disclosure.
- the second etch may include etching through the contact spacer liner 508 at a base portion of the source/drain contact trench 530 to expose the source/drain region of a semiconductor device 900 .
- the second etch process may include etching through the contact spacer liner 508 , through the remaining portion of the inter-layer dielectric 516 (corresponding to the distance 536 ) that was separating the source/drain contact trench 530 from the substrate 504 and into the substrate to expose the source/drain region 506 of the substrate 504 without etching entirely through the substrate 504 .
- the contact spacer liner 508 is not introduced into the newly etched region, which forms an additional portion (e.g., the second portion 534 ) of the source/drain contact trench 530 . That is, the second portion 534 of the source/drain contact trench 530 is not surrounded with the contact spacer liner 508 to prevent resistance spreading.
- the etch process may be slowed, which signals the start of the etch of the substrate 504 . For example, the etch rate may be reduced, indicating detection of an exposure of the source/drain region 506 .
- the second etch process may be an anisotropic etch to break through the contact spacer liner 508 at the bottom wall of the source/drain contact trench 530 and further into the source/drain region 506 .
- FIG. 9B further illustrates a process of forming the conductive contact 510 , according to aspects of the present disclosure.
- a conductive material may be deposited to fill the source/drain contact trench 530 to form the conductive contact 510 .
- the conductive material may be deposited in the source/drain contact trench 530 so that the conductive material is on the exposed portion of the source/drain region 506 of the semiconductor device 900 .
- multiple layers may be deposited into the second portion of the source/drain contact trench 530 , as illustrated in FIG. 9C .
- FIG. 9C illustrates an enlarged view of multiple layers of the conductive contact 510 within the second portion 534 of the source/drain contact trench 530 of FIG. 9A , according to aspects of the present disclosure.
- FIG. 9C shows an enlarged view of the section within a circle 531 of FIG. 9A .
- the second portion of the source/drain contact trench may include a barrier layer 533 between a conductive material forming the conductive contact 510 and a contact layer 535 .
- FIG. 10 is a process flow diagram illustrating a method 1000 for reducing spreading resistance and preventing contact to gate shorting.
- a dielectric layer may be etched proximate a gate of the semiconductor device. The etch may stop prior to reaching a source/drain region of the semiconductor device. The etch may open a first portion of a source/drain contact trench.
- the source/drain contact trench 530 may include a first portion 532 above the source/drain region 506 of the semiconductor device 700 .
- a portion of the inter-layer dielectric (ILD) remains between the source/drain region 506 and the source/drain contact trench 530 .
- ILD inter-layer dielectric
- a contact spacer liner may be deposited within the first portion of the source/drain trench.
- the contact spacer liner 508 is deposited and may line the source/drain contact trench 530 , including a base the source/drain contact trench.
- the contact spacer liner at a base of the source/drain contact trench may be etched to open a second portion of the source/drain contact trench, exposing the source/drain region of the semiconductor device.
- the second portion 534 of the source/drain contact trench may extend through the contact spacer liner 508 at the base of the source/drain contact trench 530 , exposing and landing in the source/drain region 506 of the semiconductor device 900 .
- Etching through the contact spacer liner 508 may include detecting exposure of the source/drain region 506 based on an etch rate.
- a conductive material may be deposited on the exposed portion of the source/drain region of the semiconductor device.
- a conductive material e.g., tungsten may be deposited within the first portion 532 and the second portion of the source/drain contact trench 530 as well as on the exposed portion of the source/drain region 506 of the semiconductor device 700 .
- a semiconductor device may include means for electrically isolating within a source/drain contact trench.
- the isolating means contacts a first portion but not a second portion of the source/drain contact trench.
- the electrically isolating means may be the contact spacer liner 508 shown in FIGS. 7, 8, and 9A-9B .
- the aforementioned means may be any module or any apparatus configured to perform the functions recited by the aforementioned means.
- FIG. 11 is a block diagram showing an exemplary wireless communication system 1100 in which an aspect of the disclosure may be advantageously employed.
- FIG. 11 shows three remote units 1120 , 1130 , and 1150 and two base stations 1140 .
- Remote units 1120 , 1130 , and 1150 include IC devices 1125 A, 1125 C, and 1125 B having the disclosed contacts. It will be recognized that other devices may also include the disclosed contacts, such as the base stations, switching devices, and network equipment.
- FIG. 11 shows forward link signals 1180 from the base station 1140 to the remote units 1120 , 1130 , and 1150 and reverse link signals 1190 from the remote units 1120 , 1130 , and 1150 to base stations 1140 .
- remote unit 1120 is shown as a mobile telephone
- remote unit 1130 is shown as a portable computer
- remote unit 1150 is shown as a fixed location remote unit in a wireless local loop system.
- the remote units may be a mobile phone, a hand-held personal communication systems (PCS) unit, a portable data unit such as a personal data assistant, a GPS enabled device, a navigation device, a set top box, a music player, a video player, an entertainment unit, a fixed location data unit, such as a meter reading equipment, or other devices that store or retrieve data or computer instructions, or combinations thereof.
- FIG. 11 illustrates remote units according to the aspects of the disclosure, the disclosure is not limited to these exemplary illustrated units. Aspects of the disclosure may be suitably employed in many devices, which include the disclosed contacts.
- FIG. 12 is a block diagram illustrating a design workstation used for circuit, layout, and logic design of a semiconductor component, such as the contacts disclosed above.
- a design workstation 1200 may include a hard disk 1201 containing operating system software, support files, and design software such as Cadence or OrCAD.
- the design workstation 1200 may also include a display 1202 to facilitate design of a circuit 1210 or a semiconductor component 1212 such as a contact in accordance with an aspect of the present disclosure.
- a storage medium 1204 is provided for tangibly storing the design of the circuit 1210 or the semiconductor component 1212 .
- the design of the circuit 1210 or the semiconductor component 1212 may be stored on the storage medium 1204 in a file format such as GDSII or GERBER.
- the storage medium 1204 may be a CD-ROM, DVD, hard disk, flash memory, or other appropriate device.
- the design workstation 1200 may include a drive apparatus 1203 for accepting input from or writing output to the storage medium 1204 .
- Data recorded on the storage medium 1204 may specify logic circuit configurations, pattern data for photolithography masks, or mask pattern data for serial write tools such as electron beam lithography.
- the data may further include logic verification data such as timing diagrams or net circuits associated with logic simulations.
- Providing data on the storage medium 1204 facilitates the design of the circuit 1210 or the semiconductor component 1212 by decreasing the number of processes for designing semiconductor wafers.
- DSP digital signal processor
- ASIC application specific integrated circuit
- FPGA field programmable gate array
- a general-purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine.
- a processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.
- a software module may reside in RAM, flash memory, ROM, EPROM, EEPROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
- An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium.
- the storage medium may be integral to the processor.
- the processor and the storage medium may reside in an ASIC.
- the ASIC may reside in a user terminal.
- the processor and the storage medium may reside as discrete components in a user terminal.
- the functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium.
- Computer-readable media may include both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another.
- a storage media may be any available media that can be accessed by a general purpose or special purpose computer.
- such computer-readable media can include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store specified program code means in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. Also, any connection is properly termed a computer-readable medium.
- Disk and disc may include compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.
Abstract
Description
Claims (12)
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20210375758A1 (en) * | 2020-05-29 | 2021-12-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Contact via formation |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10128377B2 (en) * | 2017-02-24 | 2018-11-13 | International Business Machines Corporation | Independent gate FinFET with backside gate contact |
US11257738B2 (en) * | 2017-12-27 | 2022-02-22 | Intel Corporation | Vertically stacked transistor devices with isolation wall structures containing an electrical conductor |
CN111200017B (en) * | 2018-11-16 | 2024-01-30 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
CN111354641B (en) * | 2018-12-21 | 2023-10-20 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and method of forming the same |
US11264393B2 (en) | 2019-09-30 | 2022-03-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | Source/drain contact having a protruding segment |
US11901434B2 (en) * | 2021-04-30 | 2024-02-13 | Qualcomm Incorporated | Semiconductor having a source/drain contact with a single inner spacer |
CN113644051A (en) * | 2021-07-29 | 2021-11-12 | 上海华力集成电路制造有限公司 | High dielectric constant metal gate MOS transistor and manufacturing method thereof |
Citations (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060284229A1 (en) | 2005-06-20 | 2006-12-21 | Samsung Electronics Co., Ltd. | Semiconductor device with a bit line contact plug and method of fabricating the same |
US20080272492A1 (en) | 2007-05-01 | 2008-11-06 | Freescale Semiconductor, Inc. | Method of blocking a void during contact formation process and device having the same |
US20090098732A1 (en) * | 2007-10-10 | 2009-04-16 | Hynix Semiconductor Inc. | Semiconductor device and method of forming contact plug of semiconductor device |
US7592650B2 (en) | 2005-06-06 | 2009-09-22 | M-Mos Semiconductor Sdn. Bhd. | High density hybrid MOSFET device |
US20100193963A1 (en) | 2009-01-30 | 2010-08-05 | Ralf Richter | Void sealing in a dielectric material of a contact level of a semiconductor device comprising closely spaced transistors |
US20110281426A1 (en) * | 2010-05-14 | 2011-11-17 | Samsung Electronics Co., Ltd. | Semiconductor device and method of forming the same |
US20110291292A1 (en) | 2010-05-31 | 2011-12-01 | Globalfoundries Inc. | Selective Shrinkage of Contact Elements in a Semiconductor Device |
US20120235299A1 (en) | 2011-03-16 | 2012-09-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device contact structures and methods for making the same |
US8981478B2 (en) | 2012-01-11 | 2015-03-17 | International Business Machines Corporation | Recessed source and drain regions for FinFETs |
US20150200269A1 (en) | 2012-07-13 | 2015-07-16 | Institute of Microelectronics, Chinese Academy of Sciences | Method for manufacturing semiconductor devices |
US20160013313A1 (en) | 2014-07-14 | 2016-01-14 | International Business Machines Corporation | Heterogeneous source drain region and extension region |
US20160148999A1 (en) | 2014-11-24 | 2016-05-26 | International Business Machines Corporation | Capacitance reduction for advanced technology nodes |
-
2016
- 2016-11-15 US US15/352,342 patent/US10833017B2/en active Active
-
2017
- 2017-08-04 WO PCT/US2017/045567 patent/WO2018052564A1/en active Application Filing
Patent Citations (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7592650B2 (en) | 2005-06-06 | 2009-09-22 | M-Mos Semiconductor Sdn. Bhd. | High density hybrid MOSFET device |
US20060284229A1 (en) | 2005-06-20 | 2006-12-21 | Samsung Electronics Co., Ltd. | Semiconductor device with a bit line contact plug and method of fabricating the same |
US20080272492A1 (en) | 2007-05-01 | 2008-11-06 | Freescale Semiconductor, Inc. | Method of blocking a void during contact formation process and device having the same |
US20090098732A1 (en) * | 2007-10-10 | 2009-04-16 | Hynix Semiconductor Inc. | Semiconductor device and method of forming contact plug of semiconductor device |
US7851350B2 (en) * | 2007-10-10 | 2010-12-14 | Hynix Semiconductor Inc. | Semiconductor device and method of forming contact plug of semiconductor device |
US20100193963A1 (en) | 2009-01-30 | 2010-08-05 | Ralf Richter | Void sealing in a dielectric material of a contact level of a semiconductor device comprising closely spaced transistors |
US20110281426A1 (en) * | 2010-05-14 | 2011-11-17 | Samsung Electronics Co., Ltd. | Semiconductor device and method of forming the same |
US20110291292A1 (en) | 2010-05-31 | 2011-12-01 | Globalfoundries Inc. | Selective Shrinkage of Contact Elements in a Semiconductor Device |
US8536050B2 (en) * | 2010-05-31 | 2013-09-17 | Globalfoundries Inc. | Selective shrinkage of contact elements in a semiconductor device |
US20120235299A1 (en) | 2011-03-16 | 2012-09-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device contact structures and methods for making the same |
US8518819B2 (en) * | 2011-03-16 | 2013-08-27 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device contact structures and methods for making the same |
US8981478B2 (en) | 2012-01-11 | 2015-03-17 | International Business Machines Corporation | Recessed source and drain regions for FinFETs |
US20150200269A1 (en) | 2012-07-13 | 2015-07-16 | Institute of Microelectronics, Chinese Academy of Sciences | Method for manufacturing semiconductor devices |
US20160013313A1 (en) | 2014-07-14 | 2016-01-14 | International Business Machines Corporation | Heterogeneous source drain region and extension region |
US20160148999A1 (en) | 2014-11-24 | 2016-05-26 | International Business Machines Corporation | Capacitance reduction for advanced technology nodes |
Non-Patent Citations (2)
Title |
---|
International Search Report and Written Opinion-PCT/US2017/045567-ISA/EPO-dated Nov. 2, 2017. |
International Search Report and Written Opinion—PCT/US2017/045567—ISA/EPO—dated Nov. 2, 2017. |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20210375758A1 (en) * | 2020-05-29 | 2021-12-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Contact via formation |
US11264326B2 (en) * | 2020-05-29 | 2022-03-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | Contact via formation |
US11798884B2 (en) | 2020-05-29 | 2023-10-24 | Taiwan Semiconductor Manufacturing Co., Ltd. | Contact via formation |
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