CN113644051A - High dielectric constant metal gate MOS transistor and manufacturing method thereof - Google Patents

High dielectric constant metal gate MOS transistor and manufacturing method thereof Download PDF

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Publication number
CN113644051A
CN113644051A CN202110862556.1A CN202110862556A CN113644051A CN 113644051 A CN113644051 A CN 113644051A CN 202110862556 A CN202110862556 A CN 202110862556A CN 113644051 A CN113644051 A CN 113644051A
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metal
gate
zero layer
layer
dielectric
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李勇
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Shanghai Huali Integrated Circuit Manufacturing Co Ltd
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Shanghai Huali Integrated Circuit Manufacturing Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry

Abstract

The invention discloses a high dielectric constant metal gate MOS transistor, comprising: the high-dielectric-constant metal gate and the source drain regions are formed in the semiconductor substrate on two sides of the high-dielectric-constant metal gate in a self-aligning mode; an active region metal zero layer at the top of the source drain region is formed in an active region metal zero layer opening; a first metal silicide is formed on the surface of the source drain region exposed at the bottom of the active region metal zero layer opening in a self-aligning mode, a first inner side wall is formed on the side face of the active region metal zero layer opening, and the active region metal zero layer is formed in the area surrounded by the first inner side wall. Reducing contact resistance through a first distance between a side surface provided with an opening of the source region metal zero layer and the high-dielectric-constant metal gate; and a second distance between the active region metal zero layer and the high-dielectric-constant metal gate is increased by setting the thickness of the first inner side wall, and bridging is avoided. And a second inner side wall is formed in the opening of the gate metal zero layer. The invention also discloses a manufacturing method of the high-dielectric-constant metal gate MOS transistor.

Description

High dielectric constant metal gate MOS transistor and manufacturing method thereof
Technical Field
The present invention relates to semiconductor integrated circuits, and more particularly, to a high dielectric constant metal gate (HKMG) MOS transistor and a method of manufacturing the same.
Background
As shown in fig. 1, it is a schematic structural diagram of a conventional high-k metal gate MOS transistor; conventional high-k metal gate MOS transistors include:
the high-dielectric-constant metal gate structure comprises a high-dielectric-constant metal gate 102 and source and drain regions which are formed in a semiconductor substrate 101 on two sides of the high-dielectric-constant metal gate 102 in a self-aligning mode.
Typically, the high-k metal gate 102 comprises a stacked high-k layer and a metal gate.
The high-k metal gate MOS transistor is a FinFET, and a Fin body (Fin) is formed in the semiconductor substrate 101. The fin body is formed by performing patterned etching on the semiconductor substrate 101.
An embedded epitaxial layer 104 is formed in the formation region of the source and drain regions.
When the high-k metal gate MOS transistor is an NMOS, the material of the embedded epi layer 104 includes SiP. When the high-k metal gate MOS transistor is a PMOS, the material of the embedded epitaxial layer 104 includes SiGe.
And an active region metal zero layer 107 penetrating through the interlayer film is formed at the top of the source and drain regions, and the active region metal zero layer 107 is formed in an opening of the active region metal zero layer.
And a first metal silicide 108 is formed on the surface of the source and drain region exposed at the bottom of the active region metal zero layer opening in a self-alignment manner. The bottom of the active region metal zero layer 107 is in contact with the first metal suicide 108.
Typically, a gate-region metal zero layer (not shown) is formed on top of the high-k metal gate 102.
The interlayer films include a zeroth interlayer film 105 and a first interlayer film 106. Wherein the top surface of the zero layer interlayer film 105 and the top surface of the high-k metal gate 102 are planar. The high-k metal gate 102 is formed by a metal gate replacement process, i.e., the high-k metal gate 102 replaces a dummy gate structure. The pseudo gate structure comprises a pseudo gate dielectric layer and a polycrystalline silicon pseudo gate, a side wall 103 is further formed on the side face of the pseudo gate structure, the embedded epitaxial layer 104 is formed under the self-alignment definition of the pseudo gate structure and the side wall 103, and source and drain injection is carried out in the embedded epitaxial layer 104 to form a source and drain region. Then, the zero interlayer film 105 is formed, a chemical mechanical polishing or etching process is performed to make the top surface of the zero interlayer film 105 and the top surface of the dummy gate structure flat, so that the top surface of the dummy gate structure is exposed, then the dummy gate structure is directly removed, and then the high-dielectric-constant metal gate 102 is formed in the dummy gate structure removal region.
As the process nodes are scaled down, the spacing between the high-k metal gates 102 is smaller, and the width of the active metal zero layer 107 and the spacing between the active metal zero layer 107 and the high-k metal gates 102 are smaller. When the width of the active region metal zero layer 107 is reduced, the contact area between the active region metal zero layer 107 and the source drain region at the bottom is reduced, and the contact circuit is increased; if the width of the active region metal zero layer 107 is increased to reduce the contact resistance, the distance between the active region metal zero layer 107 and the high-k metal gate 102 is decreased, which in turn easily causes a bridge between the active region metal zero layer 107 and the high-k metal gate 102.
Disclosure of Invention
The invention aims to solve the technical problem of providing a high-dielectric-constant metal gate MOS transistor, which can increase the contact area between a source drain region and an active region metal zero layer and further reduce the contact resistance, and can also increase the distance between the active region metal zero layer and a high-dielectric-constant metal gate and further prevent bridging between the active region metal zero layer and the high-dielectric-constant metal gate. The invention also provides a manufacturing method of the high-dielectric-constant metal gate MOS transistor.
In order to solve the above technical problem, the present invention provides a high-k metal gate MOS transistor comprising:
the high-dielectric-constant metal gate and the source drain regions are formed in the semiconductor substrate on two sides of the high-dielectric-constant metal gate in a self-aligning mode.
And forming an active region metal zero layer penetrating through the interlayer film on the top of the source and drain regions, wherein the active region metal zero layer is formed in an opening of the active region metal zero layer.
The method comprises the steps that a first metal silicide is formed on the surface, exposed at the bottom of an opening of the active area metal zero layer, of the source drain area in a self-aligning mode, a first inner side wall is formed on the side face of the opening of the active area metal zero layer, the active area metal zero layer is formed in the area, surrounded by the first inner side wall, in the opening of the active area metal zero layer, and the bottom of the active area metal zero layer is in contact with the first metal silicide.
A first distance is formed between the side face of the opening of the active region metal zero layer and the high-dielectric-constant metal gate, the first distance is defined according to the requirement of the contact area of the active region metal zero layer and the source drain region, the smaller the first distance is, the larger the contact area of the active region metal zero layer and the source drain region is, and the smaller the contact resistance is.
The first inner side wall is used for increasing a second distance between the active area metal zero layer and the high-dielectric-constant metal gate, and the thickness of the first inner side wall is set according to the requirement that the second distance is larger than the threshold distance when bridging is generated between the active area metal zero layer and the high-dielectric-constant metal gate.
And a gate metal zero layer is formed at the top of the high-dielectric-constant metal gate, the gate metal zero layer is formed in an opening of the gate metal zero layer, a second inner side wall is formed on the side surface of the opening of the gate metal zero layer, and the gate metal zero layer is formed in an area surrounded by the second inner side wall in the opening of the gate metal zero layer.
In a further improvement, the first inner sidewall 209a and the second inner sidewall are made of the same material, and the first inner sidewall 209a and the second inner sidewall are formed simultaneously by the same deposition and etching process.
In a further refinement, the high-k metal gate includes a stacked high-k layer and metal gate.
In a further improvement, the high-k metal gate MOS transistor is a FinFET and a fin is formed in the semiconductor substrate.
In a further improvement, an embedded epitaxial layer is formed in a forming region of the source and drain regions.
In a further improvement, when the high-k metal gate MOS transistor is an NMOS, the material of the embedded epitaxial layer includes SiP.
And when the high-dielectric-constant metal gate MOS transistor is a PMOS, the embedded epitaxial layer comprises SiGe.
In a further refinement, the first metal silicide comprises a nickel silicide or a titanium silicide.
In a further improvement, the active region metal zero layer is formed by stacking TiN and cobalt or TiN and tungsten.
In a further improvement, the material of the gate metal zero layer and the material of the active region metal zero layer are formed simultaneously.
In order to solve the above technical problem, the method for manufacturing a high-k metal gate MOS transistor according to the present invention includes the steps of:
step one, providing a front-layer structure which completes a forming process of a high-dielectric-constant metal gate, filling a zero-layer interlayer film in a region between the high-dielectric-constant metal gates, and forming a source drain region in a self-alignment manner in semiconductor substrates on two sides of the high-dielectric-constant metal gate; and forming a first layer interlayer film on the front layer structure and covering the surfaces of the high-dielectric-constant metal gate and the zero layer interlayer film.
And step two, forming an active area metal zero layer opening by adopting a photoetching definition and etching process, wherein the active area metal zero layer opening is positioned at the top of the source drain area and penetrates through an interlayer film formed by overlapping the zero layer interlayer film and the first layer interlayer film.
A first distance is formed between the side face of the opening of the active region metal zero layer and the high-dielectric-constant metal gate, the first distance is defined according to the requirement of the contact area of the active region metal zero layer and the source drain region, and the smaller the first distance is, the larger the contact area of the active region metal zero layer and the source drain region is.
And step three, forming a first metal silicide on the surface of the source drain region exposed at the bottom of the active region metal zero layer opening in a self-alignment manner.
And step four, forming a gate region metal zero layer opening on the top of the high-dielectric-constant metal gate by adopting a photoetching definition and etching process.
And fifthly, forming a first inner side wall on the side surface of the active area metal zero layer opening and forming a second inner side wall on the side surface of the gate area metal zero layer opening by adopting an inner side wall material deposition and etching process.
The first inner side wall is used for increasing a second distance between the active area metal zero layer and the high-dielectric-constant metal gate, and the thickness of the first inner side wall is set according to the requirement that the second distance is larger than the threshold distance when bridging is generated between the active area metal zero layer and the high-dielectric-constant metal gate.
And sixthly, filling metal, forming an active region metal zero layer in the region surrounded by the first inner side wall in the opening of the active region metal zero layer, and forming a gate region metal zero layer in the region surrounded by the second inner side wall in the opening of the gate region metal zero layer, wherein the bottom of the active region metal zero layer is in contact with the first metal silicide.
In a further refinement, the high-k metal gate includes a stacked high-k layer and metal gate.
In a further improvement, the high-k metal gate MOS transistor is a FinFET and a fin is formed in the semiconductor substrate.
In a further improvement, an embedded epitaxial layer is formed in a forming region of the source and drain regions.
The further improvement is that when the high-dielectric-constant metal gate MOS transistor is an NMOS, the material of the embedded epitaxial layer comprises SiP;
and when the high-dielectric-constant metal gate MOS transistor is a PMOS, the embedded epitaxial layer comprises SiGe.
In a further refinement, the first metal silicide comprises a nickel silicide or a titanium silicide.
The further improvement is that the metal filled in the sixth step is a stacked layer of TiN and cobalt or a stacked layer of TiN and tungsten.
According to the invention, the metal is not directly filled in the opening of the metal zero layer of the active region to form the metal zero layer of the active region, but the contradiction relation between the contact area of the metal zero layer of the active region and the source drain region and the second distance between the metal zero layer of the active region and the high-dielectric-constant metal gate is comprehensively considered, and the contradiction relation is solved by arranging the first inner side wall in the opening of the metal zero layer of the active region, so that the transverse size of the opening of the metal zero layer of the active region is larger than that of the metal zero layer of the active region, and the larger opening of the metal zero layer of the active region can be used for self-aligning to define the larger-size first metal silicide which is directly contacted with the source drain region, so that the final contact area of the metal zero layer of the active region and the source drain region can be kept or increased; the first inner side wall can increase the distance between the active area metal zero layer and the high-dielectric-constant metal grid, so that the contact area and the second distance between the active area metal zero layer and the source drain area can be increased simultaneously by arranging the first inner side wall, and the size of the opening of the active area metal zero layer and the thickness of the first inner side wall, and the contact area and the second distance can reach required values, thereby simultaneously reducing the contact resistance and preventing the bridging between the active area metal zero layer and the high-dielectric-constant metal grid.
In addition, the active region metal zero layer opening and the gate region metal zero layer opening are formed separately, so that the first metal silicide can be formed before the gate region metal zero layer opening is formed, and the manufacturing of the first metal silicide is facilitated, for example, the pre-amorphization (PAI) ion implantation can be carried out, and the PAI ion implantation does not influence the performance of a gate structure.
Drawings
The invention is described in further detail below with reference to the following figures and detailed description:
FIG. 1 is a schematic diagram of a conventional high-k metal gate MOS transistor;
FIG. 2 is a schematic diagram of a high-k metal gate MOS transistor according to an embodiment of the invention;
FIG. 2A is a schematic diagram of 2 adjacent high-K MOS transistors shown in FIG. 2;
fig. 3A-3D are schematic device structures in steps of a method for manufacturing a high-k metal gate MOS transistor according to an embodiment of the invention.
Detailed Description
FIG. 2 is a schematic diagram of a high-k metal gate MOS transistor according to an embodiment of the invention; the high-dielectric-constant metal gate MOS transistor comprises:
the high-dielectric-constant metal gate structure comprises a high-dielectric-constant metal gate 202 and source and drain regions which are formed in a semiconductor substrate 201 on two sides of the high-dielectric-constant metal gate 202 in a self-aligning mode.
In an embodiment of the present invention, the high-k metal gate 202 includes a stacked high-k layer and a metal gate.
The high-k metal gate MOS transistor is a FinFET and a fin is formed in the semiconductor substrate 201.
An embedded epitaxial layer 204 is formed in the formation region of the source and drain regions.
When the high-k metal gate MOS transistor is an NMOS, the material of the embedded epitaxial layer 204 includes SiP. When the high-k metal gate MOS transistor is a PMOS, the material of the embedded epitaxial layer 204 includes SiGe.
An active region metal zero layer 211a penetrating through the interlayer film is formed on the top of the source and drain regions, and the active region metal zero layer 211a is formed in the active region metal zero layer opening 207.
A first metal silicide 208 is formed on the surface of the source/drain region exposed at the bottom of the active region metal zero layer opening 207 in a self-aligned manner, a first inner side wall 209a is formed on the side surface of the active region metal zero layer opening 207, the active region metal zero layer 211a is formed in the region surrounded by the first inner side wall 209a in the active region metal zero layer opening 207, and the bottom of the active region metal zero layer 211a is in contact with the first metal silicide 208.
A first distance d1 is provided between the side surface of the active region metal zero layer opening 207 and the high-dielectric-constant metal gate 202, the first distance d1 is defined according to the requirement of the contact area between the active region metal zero layer 211a and the source drain region, the smaller the first distance d1 is, the larger the contact area between the active region metal zero layer 211a and the source drain region is, and the smaller the contact resistance is.
The first inner sidewall 209a is configured to increase a second distance d2 between the active region metal zero layer 211a and the high-k metal, and the thickness of the first inner sidewall 209a is set according to a requirement that the second distance d2 is greater than a threshold distance when bridging occurs between the active region metal zero layer 211a and the high-k metal gate 202.
Fig. 2 shows a schematic structure diagram of only one high-k MOS transistor, and in fact, in an integrated circuit chip, a plurality of high-k MOS transistors are simultaneously integrated on a corresponding semiconductor substrate 201 of the same chip. As shown in fig. 2A, it is a schematic structural diagram of 2 adjacent high-k metal gate MOS transistors shown in fig. 2; the gate metal zero layer 211b is omitted in fig. 2A; in fig. 2A, two adjacent high-k metal gate MOS transistors share a corresponding source/drain region and the active region metal zero layer 211a on the top of the source/drain region, and a distance d3 between two high-k metal gates 202 decreases with the continuous reduction of process nodes. The active metal zero layer 211a is usually disposed at the middle position between the two high-k metal gates 202, so that under the condition that the distance d3 is fixed, the embodiment of the invention can indeed achieve further reduction of the contact resistance and simultaneously avoid the generation of bridging between the active metal zero layer 211a and the high-k metal gates 202 by the arrangement of the first distance d1 and the second distance d 2.
A gate metal zero layer 211b is formed at the top of the high-k metal gate 202, the gate metal zero layer 211b is formed in a gate metal zero layer opening 210, a second inner sidewall 209b is formed on the side surface of the gate metal zero layer opening 210, and the gate metal zero layer 211b is formed in an area surrounded by the second inner sidewall 209b in the gate metal zero layer opening 210.
The first inner side walls 209a and the second inner side walls 209b are made of the same material, and the first inner side walls 209a and the second inner side walls 209b are formed simultaneously by the same deposition and etching process.
The first metal silicide 208 comprises nickel silicide or titanium silicide.
The active region metal zero layer 211a is formed by stacking TiN and cobalt or TiN and tungsten.
The gate metal zero layer 211b and the active metal zero layer 211a are formed of the same material and at the same time.
The interlayer films include a zeroth interlayer film 205 and a first interlayer film 206. Wherein the top surface of the zeroth interlayer film 205 and the top surface of the high-k metal gate 202 are planar. The high-k metal gate 202 is formed by a metal gate replacement process, i.e., the high-k metal gate 202 replaces a dummy gate structure. The pseudo gate structure comprises a pseudo gate dielectric layer and a polycrystalline silicon pseudo gate, a side wall 203 is further formed on the side face of the pseudo gate structure, the embedded epitaxial layer 204 is formed under the self-alignment definition of the pseudo gate structure and the side wall 203, and source and drain injection is carried out in the embedded epitaxial layer 204 to form a source and drain region. Then, the zero-layer interlayer film 205 is formed, a chemical mechanical polishing or etching back process is performed to make the top surface of the zero-layer interlayer film 205 and the top surface of the dummy gate structure flat, so that the top surface of the dummy gate structure is exposed, then the dummy gate structure is directly removed, and then the high-dielectric-constant metal gate 202 is formed in the dummy gate structure removal region.
In the embodiment of the invention, metal is not directly filled in the active region metal zero layer opening 207 to form the active region metal zero layer 211a, but the contradiction relationship between the contact area of the active region metal zero layer 211a and the source drain region and the second distance d2 between the active region metal zero layer 211a and the high-dielectric-constant metal gate 202 is comprehensively considered, and the contradiction relationship is solved by arranging the first inner side wall 209a in the active region metal zero layer opening 207, so that the transverse dimension of the active region metal zero layer opening 207 is larger than that of the active region metal zero layer 211a, and the larger active region metal zero layer opening 207 can be self-aligned to define the larger-dimension first metal silicide 208 which is directly contacted with the source drain region, and the final contact area of the active region metal zero layer 211a and the source drain region can still be maintained or increased; the first inner sidewall 209a can increase the distance between the active region metal zero layer 211a and the high-k metal gate 202, so in the embodiment of the present invention, by setting the first inner sidewall 209a and setting the size of the active region metal zero layer opening 207 and the thickness of the first inner sidewall 209a, the contact area between the active region metal zero layer 211a and the source/drain region and the second distance d2 can be simultaneously increased, and the contact area and the second distance d2 can reach required values, thereby simultaneously reducing the contact resistance and preventing bridging between the active region metal zero layer 211a and the high-k metal gate 202.
Fig. 3A to 3D are schematic diagrams of device structures in steps of a method for manufacturing a high-k metal gate MOS transistor according to an embodiment of the present invention; the manufacturing method of the high-dielectric-constant metal gate MOS transistor comprises the following steps of:
step one, as shown in fig. 3A, providing a front-layer structure after a forming process of a high-dielectric-constant metal gate 202 is completed, filling a zero-layer interlayer film 205 in a region between the high-dielectric-constant metal gates 202, and forming a source drain region in a self-aligned manner in a semiconductor substrate 201 on both sides of the high-dielectric-constant metal gate 202; a first interlayer film 206 is formed on the front layer structure covering the surface of the high-k metal gate 202 and the zero layer interlayer film 205.
In the method according to the embodiment of the present invention, the high-k metal gate 202 includes a stacked high-k layer and a metal gate.
The high-k metal gate MOS transistor is a FinFET and a fin is formed in the semiconductor substrate 201.
An embedded epitaxial layer 204 is formed in the formation region of the source and drain regions.
When the high-k metal gate MOS transistor is an NMOS, the material of the embedded epi layer 204 includes SiP. When the high-k metal gate MOS transistor is a PMOS, the material of the embedded epitaxial layer 204 includes SiGe. NMOS and PMOS can be integrated simultaneously on the same semiconductor substrate 201.
The top surface of the zeroth interlayer film 205 is planar with the top surface of the high-k metal gate 202. The high-k metal gate 202 is formed by a metal gate replacement process, i.e., the high-k metal gate 202 replaces a dummy gate structure. The pseudo gate structure comprises a pseudo gate dielectric layer and a polycrystalline silicon pseudo gate, a side wall 203 is further formed on the side face of the pseudo gate structure, the embedded epitaxial layer 204 is formed under the self-alignment definition of the pseudo gate structure and the side wall 203, and source and drain injection is carried out in the embedded epitaxial layer 204 to form a source and drain region. Then, the zero-layer interlayer film 205 is formed, a chemical mechanical polishing or etching back process is performed to make the top surface of the zero-layer interlayer film 205 and the top surface of the dummy gate structure flat, so that the top surface of the dummy gate structure is exposed, then the dummy gate structure is directly removed, and then the high-dielectric-constant metal gate 202 is formed in the dummy gate structure removal region.
Step two, as shown in fig. 3A, an active metal zero layer opening 207 is formed by using a photolithography definition and etching process, wherein the active metal zero layer opening 207 is located at the top of the source drain region and passes through an interlayer film formed by overlapping the zero interlayer film 205 and the first interlayer film 206.
A first distance d1 is provided between the side surface of the active region metal zero layer opening 207 and the high-dielectric-constant metal gate 202, the first distance d1 is defined according to the requirement of the contact area between the active region metal zero layer 211a and the source drain region, and the smaller the first distance d1 is, the larger the contact area between the active region metal zero layer 211a and the source drain region is.
Step three, as shown in fig. 3B, a first metal silicide 208 is formed on the surface of the source/drain region exposed at the bottom of the active region metal zero layer opening 207 in a self-aligned manner.
The first metal suicide 208 comprises nickel suicide.
The step of forming the first metal silicide 208 includes:
a pre-amorphizing ion implant is performed to amorphize the silicon in the regions where the first metal suicide 208 is formed.
A metal layer such as nickel or nickel platinum alloy is then formed.
An anneal is then performed to form the first metal silicide 208.
Step four, as shown in fig. 3C, forming a gate region metal zero layer opening 210 on the top of the high-k metal gate 202 by using a photolithography definition and etching process;
step five, as shown in fig. 3D, an inner sidewall material deposition and etching process is adopted to simultaneously form a first inner sidewall 209a on the side of the active region metal zero layer opening 207 and a second inner sidewall 209b on the side of the gate region metal zero layer opening 210.
The first inner sidewall 209a is configured to increase a second distance d2 between the active region metal zero layer 211a and the high-k metal, and the thickness of the first inner sidewall 209a is set according to a requirement that the second distance d2 is greater than a threshold distance when bridging occurs between the active region metal zero layer 211a and the high-k metal gate 202, so that bridging does not occur between the active region metal zero layer 211a and the high-k metal gate 202.
Sixthly, as shown in fig. 2, metal filling is performed while forming an active region metal zero layer 211a in a region surrounded by the first inner sidewall 209a in the active region metal zero layer opening 207 and forming a gate region metal zero layer 211b in a region surrounded by the second inner sidewall 209b in the gate region metal zero layer opening 210, and the bottom of the active region metal zero layer 211a is in contact with the first metal silicide 208.
And sixthly, filling metal which is a stacked layer of TiN and cobalt or a stacked layer of TiN and tungsten.
In addition, in the method according to the embodiment of the present invention, the active region metal zero layer opening 207 and the gate region metal zero layer opening 210 are separately formed, so that the first metal silicide 208 can be formed before the gate region metal zero layer opening 210 is formed, which is beneficial to the fabrication of the first metal silicide 208, for example, pre-amorphization ion implantation can be performed and PAI ion implantation does not affect the performance of the gate structure.
The present invention has been described in detail with reference to the specific embodiments, but these should not be construed as limitations of the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.

Claims (16)

1. A high-k metal gate MOS transistor, comprising:
the high-dielectric-constant metal gate and the source drain regions are formed in the semiconductor substrate on two sides of the high-dielectric-constant metal gate in a self-aligning mode;
an active region metal zero layer penetrating through the interlayer film is formed at the top of the source drain region, and the active region metal zero layer is formed in an opening of the active region metal zero layer;
forming a first metal silicide on the surface of the source and drain region exposed at the bottom of the active region metal zero layer opening in a self-aligning manner, forming a first inner side wall on the side surface of the active region metal zero layer opening, forming the active region metal zero layer in an area surrounded by the first inner side wall in the active region metal zero layer opening, and contacting the bottom of the active region metal zero layer with the first metal silicide;
a first distance is formed between the side surface of the opening of the active region metal zero layer and the high-dielectric-constant metal gate, the first distance is defined according to the requirement of the contact area of the active region metal zero layer and the source drain region, and the smaller the first distance is, the larger the contact area of the active region metal zero layer and the source drain region is, the smaller the contact resistance is;
the first inner side wall is used for increasing a second distance between the active area metal zero layer and the high-dielectric-constant metal gate, and the thickness of the first inner side wall is set according to the requirement that the second distance is larger than the threshold distance when bridging is generated between the active area metal zero layer and the high-dielectric-constant metal gate;
and a gate metal zero layer is formed at the top of the high-dielectric-constant metal gate, the gate metal zero layer is formed in an opening of the gate metal zero layer, a second inner side wall is formed on the side surface of the opening of the gate metal zero layer, and the gate metal zero layer is formed in an area surrounded by the second inner side wall in the opening of the gate metal zero layer.
2. The high-k metal-gate MOS transistor of claim 1, wherein: the first inner side wall 209a and the second inner side wall are made of the same material, and the first inner side wall 209a and the second inner side wall are formed simultaneously by the same deposition and etching process.
3. The high-k metal-gate MOS transistor of claim 1, wherein: the high-k metal gate includes a stacked high-k layer and a metal gate.
4. The high-k metal-gate MOS transistor of claim 1, wherein: the high-dielectric-constant metal gate MOS transistor is a FinFET, and a fin body is formed in the semiconductor substrate.
5. The high-k metal-gate MOS transistor of claim 1 or 4, wherein: and forming an embedded epitaxial layer in the forming region of the source and drain region.
6. The high-k metal-gate MOS transistor of claim 5, wherein: when the high-dielectric-constant metal gate MOS transistor is an NMOS, the material of the embedded epitaxial layer comprises SiP;
and when the high-dielectric-constant metal gate MOS transistor is a PMOS, the embedded epitaxial layer comprises SiGe.
7. The high-k metal-gate MOS transistor of claim 1, wherein: the first metal silicide comprises nickel silicide or titanium silicide.
8. The high-k metal-gate MOS transistor of claim 2, wherein: the active region metal zero layer is formed by superposing TiN and cobalt or TiN and tungsten.
9. The high-k metal-gate MOS transistor of claim 8, wherein: and the material of the gate region metal zero layer and the material of the active region metal zero layer are the same and are formed simultaneously.
10. A method for manufacturing a high dielectric constant metal gate MOS transistor is characterized by comprising the following steps:
step one, providing a front-layer structure which completes a forming process of a high-dielectric-constant metal gate, filling a zero-layer interlayer film in a region between the high-dielectric-constant metal gates, and forming a source drain region in a self-alignment manner in semiconductor substrates on two sides of the high-dielectric-constant metal gate; forming a first interlayer film on the front layer structure and covering the surfaces of the high-dielectric-constant metal gate and the zero-layer interlayer film;
forming an active area metal zero layer opening by adopting a photoetching definition and etching process, wherein the active area metal zero layer opening is positioned at the top of the source drain area and penetrates through an interlayer film formed by overlapping the zero layer interlayer film and the first layer interlayer film;
a first distance is formed between the side surface of the opening of the active region metal zero layer and the high-dielectric-constant metal gate, the first distance is defined according to the requirement of the contact area of the active region metal zero layer and the source drain region, and the smaller the first distance is, the larger the contact area of the active region metal zero layer and the source drain region is;
forming a first metal silicide on the surface of the source drain region exposed at the bottom of the active region metal zero layer opening in a self-alignment manner;
forming a gate region metal zero layer opening on the top of the high-dielectric-constant metal gate by adopting a photoetching definition and etching process;
step five, forming a first inner side wall on the side surface of the active area metal zero layer opening and forming a second inner side wall on the side surface of the gate area metal zero layer opening by adopting an inner side wall material deposition and etching process;
the first inner side wall is used for increasing a second distance between the active area metal zero layer and the high-dielectric-constant metal gate, and the thickness of the first inner side wall is set according to the requirement that the second distance is larger than the threshold distance when bridging is generated between the active area metal zero layer and the high-dielectric-constant metal gate;
and sixthly, filling metal, forming an active region metal zero layer in the region surrounded by the first inner side wall in the opening of the active region metal zero layer, and forming a gate region metal zero layer in the region surrounded by the second inner side wall in the opening of the gate region metal zero layer, wherein the bottom of the active region metal zero layer is in contact with the first metal silicide.
11. The method of claim 10, wherein the step of forming the high-k metal gate MOS transistor comprises: the high-k metal gate includes a stacked high-k layer and a metal gate.
12. The method of claim 10, wherein the step of forming the high-k metal gate MOS transistor comprises: the high-dielectric-constant metal gate MOS transistor is a FinFET, and a fin body is formed in the semiconductor substrate.
13. The method of manufacturing a high-k metal-gate MOS transistor according to claim 10 or 12, wherein: and forming an embedded epitaxial layer in the forming region of the source and drain region.
14. The method of manufacturing a high-k metal-gate MOS transistor as claimed in claim 13, wherein: when the high-dielectric-constant metal gate MOS transistor is an NMOS, the material of the embedded epitaxial layer comprises SiP;
and when the high-dielectric-constant metal gate MOS transistor is a PMOS, the embedded epitaxial layer comprises SiGe.
15. The method of claim 10, wherein the step of forming the high-k metal gate MOS transistor comprises: the first metal silicide comprises nickel silicide or titanium silicide.
16. The method of claim 10, wherein the step of forming the high-k metal gate MOS transistor comprises: and sixthly, filling metal which is a stacked layer of TiN and cobalt or a stacked layer of TiN and tungsten.
CN202110862556.1A 2021-07-29 2021-07-29 High dielectric constant metal gate MOS transistor and manufacturing method thereof Pending CN113644051A (en)

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US20150115335A1 (en) * 2013-10-30 2015-04-30 Taiwan Semiconductor Manufacturing Co., Ltd Mechanism for forming metal gate structure
US20160343825A1 (en) * 2015-05-20 2016-11-24 Samsung Electronics Co., Ltd. Method for fabricating semiconductor device having a silicide layer
US20180076139A1 (en) * 2016-09-13 2018-03-15 Qualcomm Incorporated Contact for semiconductor device
CN108122849A (en) * 2016-11-29 2018-06-05 台湾积体电路制造股份有限公司 For forming the method for metal layer and its forming apparatus in the opening

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102437089A (en) * 2011-07-12 2012-05-02 上海华力微电子有限公司 Copper subsequent interconnection technique
US20150115335A1 (en) * 2013-10-30 2015-04-30 Taiwan Semiconductor Manufacturing Co., Ltd Mechanism for forming metal gate structure
US20160343825A1 (en) * 2015-05-20 2016-11-24 Samsung Electronics Co., Ltd. Method for fabricating semiconductor device having a silicide layer
US20180076139A1 (en) * 2016-09-13 2018-03-15 Qualcomm Incorporated Contact for semiconductor device
CN108122849A (en) * 2016-11-29 2018-06-05 台湾积体电路制造股份有限公司 For forming the method for metal layer and its forming apparatus in the opening

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