US10504759B2 - Semiconductor metrology with information from multiple processing steps - Google Patents

Semiconductor metrology with information from multiple processing steps Download PDF

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US10504759B2
US10504759B2 US15/476,683 US201715476683A US10504759B2 US 10504759 B2 US10504759 B2 US 10504759B2 US 201715476683 A US201715476683 A US 201715476683A US 10504759 B2 US10504759 B2 US 10504759B2
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metrology
amount
tool
measurement
wafer
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US20170287751A1 (en
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Alexander Kuznetsov
Antonio Arion Gellineau
Andrei V. Shchegrov
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KLA Corp
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KLA Tencor Corp
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Priority to PCT/US2017/025757 priority patent/WO2017176637A1/en
Priority to KR1020187031524A priority patent/KR102274476B1/ko
Priority to CN201780021343.8A priority patent/CN108886006B/zh
Priority to DE112017001846.3T priority patent/DE112017001846T5/de
Priority to TW106111390A priority patent/TWI755386B/zh
Assigned to KLA-TENCOR CORPORATION reassignment KLA-TENCOR CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: GELLINEAU, Antonio Arion, KUZNETSOV, ALEXANDER, SHCHEGROV, ANDREI V.
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67242—Apparatus for monitoring, sorting or marking
    • H01L21/67253—Process monitoring, e.g. flow or thickness monitoring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70491—Information management, e.g. software; Active and passive control, e.g. details of controlling exposure processes or exposure tool monitoring processes
    • G03F7/705—Modelling or simulating from physical phenomena up to complete wafer processes or whole workflow in wafer productions
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70605—Workpiece metrology
    • G03F7/70616—Monitoring the printed patterns
    • G03F7/70625—Dimensions, e.g. line width, critical dimension [CD], profile, sidewall angle or edge roughness
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70605—Workpiece metrology
    • G03F7/70616—Monitoring the printed patterns
    • G03F7/70633—Overlay, i.e. relative alignment between patterns printed by separate exposures in different layers, or in the same layer in multiple exposures or stitching
    • G06F17/5009—
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/20—Design optimisation, verification or simulation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N20/00—Machine learning
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01B—MEASURING LENGTH, THICKNESS OR SIMILAR LINEAR DIMENSIONS; MEASURING ANGLES; MEASURING AREAS; MEASURING IRREGULARITIES OF SURFACES OR CONTOURS
    • G01B2210/00—Aspects not specifically covered by any group under G01B, e.g. of wheel alignment, caliper-like sensors
    • G01B2210/56—Measuring geometric parameters of semiconductor structures, e.g. profile, critical dimensions or trench depth
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N21/00—Investigating or analysing materials by the use of optical means, i.e. using sub-millimetre waves, infrared, visible or ultraviolet light
    • G01N21/84—Systems specially adapted for particular applications
    • G01N21/88—Investigating the presence of flaws or contamination
    • G01N21/95—Investigating the presence of flaws or contamination characterised by the material or shape of the object to be examined
    • G01N21/9501—Semiconductor wafers
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N2201/00—Features of devices classified in G01N21/00
    • G01N2201/12—Circuits of general importance; Signal processing

Definitions

  • the described embodiments relate to metrology systems and methods, and more particularly to methods and systems for improved measurement of parameters characterizing the dimensions of structures generated by multiple patterning processes.
  • Semiconductor devices such as logic and memory devices are typically fabricated by a sequence of processing steps applied to a specimen. The various features and multiple structural levels of the semiconductor devices are formed by these processing steps. For example, lithography among others is one semiconductor fabrication process that involves generating a pattern on a semiconductor wafer. Additional examples of semiconductor fabrication processes include, but are not limited to, chemical-mechanical polishing, etch, deposition, and ion implantation. Multiple semiconductor devices may be fabricated on a single semiconductor wafer and then separated into individual semiconductor devices.
  • FIGS. 1A-1D depict a double patterning lithography (DPL) technique commonly referred to as a litho-etch-litho-etch (LELE) process.
  • FIG. 1A depicts a silicon base layer 10 , an interface layer 11 such as silicon dioxide, a device layer 12 , a hard mask layer 13 , a sacrificial layer 14 , and a patterned resist layer 15 that results from a lithography patterning step.
  • the structure of depicted in FIG. 1A is then subjected to exposure and etch steps that result in the structure illustrated in FIG. 1B .
  • FIG. 1C illustrates another sacrificial layer 16 and patterned resist layer 17 built on top of the hard mask layer 13 .
  • Patterned resist layer 17 includes a pattern having the same pitch as the first patterned resist layer 15 , and also the same pitch as the pattern etched into the hard mask layer 13 .
  • the patterned resist layer 17 is offset from the pattern of the hard mask layer 13 by half of the pitch of the patterned resist layer 17 .
  • FIG. 1C is then subjected to exposure and etch steps that result in the structure illustrated in FIG. 1D .
  • the pattern of resist layer 17 has been effectively transferred to the hard mask layer 13 .
  • Both the sacrificial layer 16 and the patterned resist layer 17 have been removed.
  • FIG. 1D illustrates a pattern etched into hard mask 13 that is double the pitch of the patterned resist layers 15 and 17 generated by the mask of the lithographic system.
  • FIG. 1D also depicts the effects of a non-optimized DPL process.
  • the nominal pitch of the double patterned structure should be a constant value, P.
  • the pitch of the resulting structure may vary depending on location due to grating non-uniformities. This is commonly termed “pitch walk.”
  • a variation from the nominal pitch, P is depicted as ⁇ P in FIG. 1D .
  • a critical dimension of each resulting structure should be the same nominal value, CD.
  • a critical dimension e.g., middle critical dimension, bottom critical dimension, etc.
  • CD A variation from the desired critical dimension, CD, is depicted as ⁇ CD in FIG. 1D .
  • Pitch walk and ⁇ CD are exemplary geometric errors induced by imperfections in the DPL process such as misalignment between the two lithography layers, non-uniformities in the focus and exposure of the lithographic process, mask pattern errors, etc. Both pitch walk and ⁇ CD introduce a unit cell that is larger than expected. Although pitch walk and ⁇ CD are described in particular, other multiple patterning errors may be contemplated.
  • Metrology processes are used at various steps during a semiconductor manufacturing process to detect defects on wafers to promote higher yield.
  • Optical metrology techniques offer the potential for high throughput measurement without the risk of sample destruction.
  • a number of optical metrology based techniques including scatterometry and reflectometry implementations and associated analysis algorithms are commonly used to characterize critical dimensions, film thicknesses, composition and other parameters of nanoscale structures.
  • a common approach to control a semiconductor fabrication process is to employ a metrology tool after each critical process step in the fabrication process.
  • process control is improved.
  • inserting a metrology step after each process step is expensive, both in fabrication time and expense.
  • the insertion of a metrology step after each critical process step has become cost prohibitive.
  • the number of critical process steps that can be measured in a cost effective manner compared to the total number of critical process steps is decreasing.
  • a metrology step may be only performed after the last process step.
  • the results of this measurement may be effectively used to correct the last process step, but not earlier process steps. This limitation exists even if multiple metrology steps are employed.
  • the last process step before metrology may be effectively corrected, but current metrology does not provide sufficient measurement information to correct all other process steps.
  • Increasingly small resolution requirements, multi-parameter correlation, increasingly complex geometric structures, and increasing use of opaque materials complicate this problem, and leave undesirable gaps in the control of advanced fabrication processes.
  • methods and systems for improved process control of advanced fabrication processes are desired.
  • Methods and systems for measuring process induced errors in a multiple patterning semiconductor fabrication process based on measurements of a specimen and process information from one or more previous process steps employed to fabricate the specimen are presented herein. Based on measured errors, corrected process parameter values are communicated to the appropriate process tool to improve process performance. In this manner, a metrology tool provides corrections to one or more process tools employed to perform any of the preceding process steps.
  • the metrology system receives process information from any of the process tools employed to perform any of the preceding process steps.
  • Process tools include lithography tools, etch tools, deposition tools, chemical mechanical planarization (CMP) tools, etc.
  • Process information received by the metrology tool includes, but in not limited to, process control parameters, process tool set-up parameters, process environment parameters, process data collected from sensors on board a process tool, metrology data collected from sensors on board a process tool, etc.
  • a metrology tool is employed at a metrology step after a number of process steps have been executed.
  • the metrology tool measures structural parameters of interest of metrology targets on the wafer in physical state and communicates correctable process parameter values to one or more process tools involved in one or more of the previous process steps.
  • the correctable process parameter values reduce process induced errors in the geometry of the structures fabricated by the process flow.
  • multiple metrology tools are used to control a fabrication process in combination with process information from one or more process steps in the process flow.
  • metrology information from an additional metrology step inserted into the process flow is also employed to improve the metrology of the structure and to improve process control.
  • a metrology tool employs a physically based measurement model to estimate the values of structural parameters of interest from measurement data (e.g., measured spectra) and process information.
  • a metrology tool employs an input-output measurement model to estimate the values of structural parameters of interest from measurement data (e.g., measured spectra) and process information.
  • measurement data e.g., measured spectra
  • models include signal response metrology models, neural network models, support vector machines models, etc.
  • a signal response metrology (SRM) measurement model is trained on measurement signals and associated process information from multiple targets integrated into one multi-target set and operates on measurement signals from the same multiple targets. This approach de-correlates critical parameters from each other and from other process variations.
  • assist targets are located next to the primary measurement target and are subject to the same process variations.
  • the training set of metrology targets includes a primary, nominally dimensioned target and one or more assist targets that have different nominal values of the parameters of interest.
  • FIGS. 1A-1D depict selected steps of a double patterning lithography (DPL) technique commonly referred to as a litho-etch-litho-etch (LELE) process.
  • DPL double patterning lithography
  • LELE litho-etch-litho-etch
  • FIG. 2 depicts a fabrication process flow 100 that includes a sequence of fabrication process steps and a single metrology step.
  • FIG. 3 depicts an example of trench formation generated by a particular example of process flow 100 depicted in FIG. 2 .
  • FIG. 4 depicts a fabrication process flow 200 that includes a sequence of fabrication process steps and two metrology steps.
  • FIG. 5 depicts a process flow 300 exemplary of a self-aligned octuplet patterning process.
  • FIG. 6 depicts an example of fin spacer formation generated by a particular example of process flow 300 depicted in FIG. 5 .
  • FIG. 7 depicts a semiconductor wafer 130 having a number of metrology targets located at various measurement sites over the surface of the wafer.
  • FIG. 8 illustrates a system 500 for measuring characteristics of a specimen in accordance with the exemplary methods presented herein.
  • FIG. 9 is a flowchart illustrative of a method 500 of determining one or more parameter values characterizing geometric errors induced by a multiple patterning process based on measurements and process information.
  • the metrology system receives process information from any of the process tools employed to perform any of the preceding process steps.
  • Process tools include lithography tools, etch tools, deposition tools, chemical mechanical planarization (CMP) tools, etc.
  • Process information received by the metrology tool includes, but in not limited to, process control parameters, process tool set-up parameters, process environment parameters, process data collected from sensors on board a process tool, metrology data collected from sensors on board a process tool, etc.
  • a process tool includes integrated metrology sensors to measure process information that is communicated to the metrology tool.
  • a lithography tool may include an optical reflectometer to measure wafer geometry.
  • an etch tool may include an optical emission spectroscopy sensor to monitor and control a plasma source of the etch tool.
  • FIG. 2 depicts a fabrication process flow 100 that includes a sequence of fabrication process steps including a lithography step 101 , an etch step 102 , another lithography step 103 , another etch step 104 , and finally a metrology step 105 .
  • An incoming wafer in a particular physical state 114 within the fabrication process is transformed by lithography step 101 to a different physical state 115 as a result of the lithography process.
  • etch step 102 transforms the wafer from state 115 to state 116
  • lithography step 103 transforms the wafer from state 116 to state 117
  • etch step 104 transforms the wafer from state 117 to state 118 .
  • a metrology tool is employed at metrology step 105 to measure structural parameters of interest of metrology targets on the wafer in physical state 118 and to communicate correctable process parameter values to one or more process tools involved in one or more of process steps 101 - 104 .
  • the correctable process parameter values reduce process induced errors in the geometry of the structures fabricated by process flow 100 .
  • process information 106 is communicated from a lithography tool employed to execute lithography step 101 to the metrology tool employed to execute metrology step 105 .
  • process information 107 is communicated from an etch tool employed to execute etch step 102 to the metrology tool
  • process information 108 is communicated from a lithography tool employed to execute lithography step 103 to the metrology tool
  • process information 109 is communicated from an etch tool employed to execute etch step 104 to the metrology tool.
  • process information from each process step of process flow 100 is communicated to the metrology tool, in general, process information from any one or more of the process steps may be communicated to the metrology tool.
  • the metrology tool generates correctable process parameter values based on the values of one or more structural parameters of the wafer in state 118 measured by the metrology tool at metrology step 105 and the received process information (e.g., any of process information 106 - 109 ).
  • process information e.g., any of process information 106 - 109 .
  • correctable process parameter values 110 are communicated to the lithography tool employed to execute lithography step 101 .
  • correctable process parameter values 111 are communicated to an etch tool employed to execute etch step 102
  • correctable process parameter values 112 are communicated to the lithography tool employed to execute lithography step 103
  • correctable process parameter values 113 are communicated to an etch tool employed to execute etch step 104 .
  • correctable process parameter values are communicated to a tool executing each process step of process flow 100
  • correctable process parameter values may be communicated to a tool executing any one or more of the process steps.
  • FIG. 3 depicts an example of trench formation generated by a particular example of process flow 100 depicted in FIG. 2 .
  • FIG. 3 depicts a metrology target at each state of trench formation within lithography-etch, lithography-etch (LELE) process flow 100 .
  • the structure of interest includes a base layer 121 , a device layer 122 , and a patterned resist layer 123 .
  • the patterned resist layer 123 is completely removed, along with a portion of device layer 122 exposed to light during lithography step 101 . At this point, the first trench feature of the device layer is formed.
  • a sacrificial layer 124 , and another patterned resist layer 125 are added during lithography step 103 .
  • the patterned resist layer 125 , the sacrificial layer 124 , and another portion of device layer 122 are removed by etch step 104 .
  • the second trench feature of the device layer is formed, and the resulting structure is measured by a metrology tool at metrology step 105 .
  • the metrology tool is able to measure a critical dimension associated with each trench feature, CD1 and CD2.
  • dosage information 106 is communicated from the lithography tool employed to execute lithography step 101 to the metrology tool executing metrology step 105 .
  • dosage information 108 is communicated from the lithography tool employed to execute lithography step 103 to the metrology tool. Based on the received dosage information, the metrology tool associates the each trench with the corresponding lithography step that produced the particular trench.
  • a larger dosage at lithography step 101 i.e., Dose1>Dose2 causes a larger critical dimension (i.e., CD1>CD2).
  • CD1>CD2 a larger critical dimension
  • the first trench, having dimension CD1 is associated with lithography step 101 and the second trench, having dimension CD2 is associated with lithography step 103 .
  • the metrology tool generates and communicates a correctable process parameter value 110 to the lithography tool executing lithography step 101 to correct the dimension of trench 1.
  • the metrology tool generates and communicates a correctable process parameter value 112 to the lithography tool executing lithography step 103 to correct the dimension of trench 2.
  • the metrology tool is able to perform measurements of structural parameters of interest.
  • the metrology tool is able to independently measure CD1 and CD2 as described with reference to FIG. 2 .
  • the metrology tool is unable to independently measure all of the parameters of interest.
  • a metrology tool is capable of measuring average trench size (i.e., (CD1+CD2)/2) because the measured signals are mostly sensitive to changes in volume, rather than position.
  • process information received by the metrology tool enables a measurement of both CD1 and CD2, independently. In this manner, process information in combination with metrology signal information enables improved metrology capability in addition to improved process control.
  • FIG. 2 depicts a LELE, or (LE) 2 , fabrication process flow.
  • the methods and systems described herein may be applied to any multiple patterning process flow such as a (LE) N fabrication process flow that involves N litho-etch steps, where N is any positive integer number, any self-aligned multiple patterning technique, etc.
  • multiple metrology tools are used to control a fabrication process in combination with process information from one or more process steps in the process flow.
  • metrology information from any additional metrology step inserted into the process flow is also employed to improve the metrology of the structure and to improve process control.
  • FIG. 4 depicts a fabrication process flow 200 that includes a sequence of fabrication process steps and two metrology steps. Like numbered elements are analogous to those described with reference to FIG. 2 .
  • process flow 200 includes lithography steps 101 and 103 , and etch steps 102 and 104 , as described with reference to FIG. 2 .
  • process flow 200 includes two metrology steps. Metrology step 201 is inserted in the middle of process flow 200 and metrology step 202 is performed at the end of process flow 200 .
  • the wafer at physical state 117 is measured by a metrology tool executing metrology step 201 , and an indication of these measurement results is communicated to a metrology tool executing metrology step 202 at the end of the process flow 200 .
  • a metrology tool is employed to measure structural parameters of interest of metrology targets on the wafer in physical state 118 based on process information received from any of the previous process steps (i.e., steps 101 - 104 ) and the measurement results 203 received from the intermediate metrology step 201 .
  • the metrology tool executing metrology step 202 generates correctable process parameter values for one or more of the process steps of process flow 200 based on the measurement results obtained at metrology step 202 .
  • the correctable process parameter values are communicated to one for more process tools involved in one or more of process steps 101 - 104 .
  • the correctable process parameter values reduce process induced errors in the geometry of the structures fabricated by process flow 200 .
  • FIGS. 2-4 depict examples of (LE) N type multiple patterning processes.
  • the metrology and process control techniques described herein are applicable to self-aligned multiple patterning processes.
  • Advanced process nodes e.g., 5 nanometer and 3.5 nanometer process nodes
  • SAOP self-aligned octuplet patterning
  • FIG. 5 depicts a process flow 300 exemplary of a SAOP process.
  • Process flow 300 includes a lithography step followed by a repeating sequence of etch and deposition steps.
  • an incoming wafer in a particular physical state 310 within the fabrication process is transformed by lithography step 301 to a different physical state 311 as a result of the lithography process.
  • etch step 302 transforms the wafer from state 311 to state 312
  • deposition step 303 transforms the wafer from state 312 to state 313
  • etch step 304 transforms the wafer from state 313 to state 314
  • deposition step 305 transforms the wafer from state 314 to state 315
  • etch step 306 transforms the wafer from state 315 to state 316
  • deposition step 307 transforms the wafer from state 316 to state 317
  • etch step 308 transforms the wafer from state 317 to state 318 .
  • a metrology tool is employed at metrology step 309 to measure structural parameters of interest of metrology targets on the wafer in physical state 318 and communicate correctable process parameter values to one or more process tools involved in one or more of process steps 301 - 308 .
  • the correctable process parameter values reduce process induced errors in the geometry of the structures fabricated by process flow 300 .
  • process information 319 is communicated from a lithography tool employed to execute lithography step 301 to the metrology tool employed to execute metrology step 309 .
  • process information 320 is communicated from an etch tool employed to execute etch step 302 to the metrology tool
  • process information 321 is communicated from a deposition tool employed to execute deposition step 303 to the metrology tool
  • process information 322 is communicated from an etch tool employed to execute etch step 304 to the metrology tool
  • process information 323 is communicated from a deposition tool employed to execute deposition step 305 to the metrology tool
  • process information 324 is communicated from an etch tool employed to execute etch step 306 to the metrology tool
  • process information 325 is communicated from a deposition tool employed to execute deposition step 307 to the metrology tool
  • process information 326 is communicated from an etch tool employed to execute etch step 308 to the metrology tool.
  • process information from each process step of process flow 300 is communicated to the metrology tool, in general, process information from any one or more of the process steps may be communicated to the metrology tool.
  • the metrology tool generates correctable process parameter values based on the values of one or more structural parameters of the wafer in state 318 measured by the metrology tool at metrology step 309 and the received process information (e.g., any of process information 319 - 326 ).
  • correctable process parameter values 327 are communicated to the lithography tool employed to execute lithography step 301 .
  • correctable process parameter values 328 are communicated to an etch tool employed to execute etch step 302
  • correctable process parameter values 329 are communicated to the deposition tool employed to execute deposition step 303
  • correctable process parameter values 330 are communicated to an etch tool employed to execute etch step 304
  • correctable process parameter values 331 are communicated to the deposition tool employed to execute deposition step 305
  • correctable process parameter values 332 are communicated to an etch tool employed to execute etch step 306
  • correctable process parameter values 333 are communicated to the deposition tool employed to execute deposition step 307
  • correctable process parameter values 334 are communicated to an etch tool employed to execute etch step 308 .
  • correctable process parameter values are communicated to a tool executing each process step of process flow 300
  • correctable process parameter values may be communicated to a tool executing any one or more of the process steps.
  • FIG. 6 depicts an example of fin spacer formation generated by a particular example of process flow 300 depicted in FIG. 5 .
  • FIG. 6 depicts a metrology target at each state of fin spacer formation within SAOP process flow 300 .
  • the structure of interest includes a substrate layer 330 , and a repeating sequence of nitride layers 331 , 333 , 335 and oxide layers 332 , 334 , and 336 , a bottom anti-reflective coating (BARC) layer 337 , and a patterned resist layer 338 .
  • BARC bottom anti-reflective coating
  • the patterned resist layer 123 and BARC layer 337 are completely removed, along with a portion of nitride layer 335 , leaving behind two spacer structures 335 A-B.
  • the first set of fin spacer structures is formed.
  • layers 334 and 335 are removed, along with a portion of nitride layer 333 , leaving behind four spacer structures 333 A-D.
  • the second set of fin spacer structures is formed.
  • layers 332 and 333 are removed, along with a portion of nitride layer 331 , leaving behind eight spacer structures 331 A-H.
  • the third set of fin spacer structures is formed, and the resulting structure is measured by a metrology tool at metrology step 309 .
  • the metrology tool is not able to directly measure a critical dimension associated with each fin spacer feature 331 A-H. However, with additional process information the metrology system is able to determine the dimensions of each fin spacer feature and which fin spacer features are sensitive to each process step.
  • dosage information 319 is communicated from the lithography tool employed to execute lithography step 301 to the metrology tool, along with an indication 321 of the spacer critical dimension, CD1, an indication 323 of the spacer critical dimension, CD2, and an indication 325 of the spacer critical dimension, CD3.
  • the metrology tool associates each fin spacer with the corresponding process steps that produced the particular fin spacer feature. In this manner, augmenting metrology with process information enables control of the SAOP process with a single metrology tool.
  • a metrology tool employs a physically based measurement model to estimate the values of structural parameters of interest from measurement data (e.g., measured spectra).
  • Metrology techniques employing physical, model based measurements typically require a parameterized, geometric model of the patterned structure. Exemplary parameters include critical dimension, pitch walk, or other parameters of interest.
  • an accurate electromagnetic model of the interaction between the optical system and the structure under measurement is required to simulate signals generated during measurement. Nonlinear regression of simulated signals against measured signals is applied to determine parameters of the modeled structure. This approach requires accurate modeling of the structure and the material properties.
  • process information received from tools employed to execute previous process steps is fed directly into the measurement model.
  • process parameter values of the measurement model are fixed to values received from the process tools.
  • received process information is further processed to arrive at particular values of model parameters, or mathematical relationships among model parameters. In this manner, the received process information is employed to constrain the measurement model and reduce parameter correlations.
  • a metrology tool employs an input-output measurement model to estimate the values of structural parameters of interest from measurement data (e.g., measured spectra).
  • measurement data e.g., measured spectra
  • models include signal response metrology models, neural network models, support vector machines models, etc.
  • a trained input-output measurement model is employed to estimate values of structural parameters of interest based on measured signals and process information received from tools employed to fabricate the sample under measurement at previous process steps.
  • the combination of measurement signals and process information contains more information required to separate and measure critical features than would otherwise be achievable based on either measurement signals or process information alone.
  • a SRM measurement model is created based on process information from previous process steps (e.g., simulated process data or actual process data associated with the fabrication of a Design of Experiments (DOE) wafer) and raw measurement data (e.g., simulated spectra or spectra collected from the DOE wafer) collected from measurement sites including multiple pattern metrology targets (simulated or actual).
  • process information from previous process steps e.g., simulated process data or actual process data associated with the fabrication of a Design of Experiments (DOE) wafer
  • raw measurement data e.g., simulated spectra or spectra collected from the DOE wafer
  • multiple pattern metrology targets simulated or actual.
  • Machine learning, feature extraction, and other techniques are employed to build a direct input-output model (i.e., transfer function) that relates DOE process information and spectra of one or more multiple patterned targets and corresponding reference measurements of the parameter of interest.
  • the training set of multiple patterned metrology targets includes targets that are nominally the same, i.e., the targets vary from one another because of process variations.
  • the process variations that impact the parameters of interest are intentionally amplified for purposes of model training.
  • the transfer function relates process information and scatterometry signals with corresponding CD-SEM measurements of a SAQP target 131 depicted in FIG. 7 .
  • An SRM model is created for each parameter of interest, and the same model is used to perform subsequent measurements on other measurement sites.
  • an amount of raw measurement data associated with measurements of a plurality of measurement sites and corresponding process information from previous process steps is received by a computing system (e.g., computing system 330 ).
  • a computing system e.g., computing system 330
  • Each of the plurality of measurement sites includes a multiple patterned metrology target characterized by at least one parameter of interest generated by at least two patterning steps of a multiple patterning process.
  • a value of the parameter(s) of interest is known at each of the plurality of measurement sites.
  • measurement data may be acquired from any location with known perturbations in the design parameters, e.g., structure or process parameters. These locations, for example, may be in the scribe line, on-device, or may be at other locations on the wafer where, for example, lithographic exposure conditions or reticle design characteristics vary over a range of values.
  • measurement data may be acquired from different device locations (e.g., a location with dense features and a location with isolated features, or locations with two different CDs on mask).
  • the measurement data is acquired from different locations that are perturbed in a known way.
  • the perturbation may be known from mask data, Equipment Data Acquisition (EDA) data, process data, etc.
  • EDA Equipment Data Acquisition
  • any of focus, exposure, and overlay are varied systematically across the device or the wafer.
  • a randomized Focus and Exposure Matrix (FEM) is employed to reduce correlation with underlayer parameters as described in U.S. Pat. No. 8,142,966 to Izikson et al., the entirety of which is incorporated herein by reference.
  • the set of systematic variations is implemented in the fabrication of an actual DOE wafer.
  • the DOE wafer is subsequently measured to generate the raw measurement data.
  • a manufactured wafer includes systematic errors which cannot be easily modeled by simulation.
  • the effect of underlayers is more accurately captured by measurements of a real wafer.
  • the underlayer contribution can be decorrelated from the measurement responses by modifying process parameters during manufacture, e.g., focus and exposure variations, for a fixed underlayer condition.
  • the underlayer contribution can be mitigated by taking multiple data sets from features with varying top layer topography and constant underlayer conditions.
  • the top layer may include a periodic structure and the underlayer may be non-periodic.
  • Measurement locations may be selected to increase measurement sensitivity.
  • measurements performed at line ends are most sensitive to changes in focus.
  • measurements should be taken at structures that are most sensitive to changes in the parameter to be measured.
  • the process information and measurement response of a DOE wafer for different, known structural parameter values may be simulated.
  • the process information and raw measurement data is synthetically generated.
  • a process simulator such as the Positive Resist Optical Lithography (PROLITH) simulation software available from KLA-Tencor Corporation, Milpitas, Calif. (USA) may be employed.
  • PROLITH Positive Resist Optical Lithography
  • any process modeling technique or tool may be contemplated within the scope of this patent document (e.g., Coventor simulation software available from Coventor, Inc., Cary, N.C., USA).
  • the raw measurement data includes two ellipsometric parameters ( ⁇ , ⁇ ) over a spectral range obtained at different measurement sites.
  • the measurement data may be any measurement data indicative of the structural or geometric properties of the structures patterned onto the surface of a semiconductor wafer.
  • the measurement data is associated with simulations of process parameters and corresponding measurements of the measurement sites on the surface of a DOE wafer (e.g., wafer 130 ).
  • the measurement data may include simulated spectral measurements associated with the multiple pattern metrology target associated with each measurement site.
  • the measurement data is associated with actual measurements of the measurement sites on the surface of a DOE wafer (e.g., wafer 130 ).
  • the measurement data includes actual spectral measurements associated with the multiple pattern metrology target associated with each measurement site.
  • the measurement data is associated with measurements of the plurality of measurement sites on a Design of Experiments (DOE) wafer and the parameter(s) of interest characterizing the multiple patterned metrology target is measured by a reference measurement system at each of the measurement sites.
  • the reference metrology system is a trusted metrology system such as a Scanning Electron Microscope (SEM), Tunneling electron Microscope (TEM), Atomic Force Microscope (AFM), or an x-ray measurement system such as a Small-Angle X-Ray Scatterometer (SAXS) or an X-Ray Fluorescence (XRF) system that is able to accurately measure the parameter value.
  • SEM Scanning Electron Microscope
  • TEM Tunneling electron Microscope
  • AFM Atomic Force Microscope
  • SAXS Small-Angle X-Ray Scatterometer
  • XRF X-Ray Fluorescence
  • the reference metrology system typically lacks the capability to operate as an inline metrology system, for example, due to low throughput, high measurement uncertainty for the measurement of
  • process variations and corresponding parameter variations are organized in a Design of Experiments (DOE) pattern on the surface of a semiconductor wafer (e.g., DOE wafer), for example, as described herein with reference to FIG. 7 .
  • DOE Design of Experiments
  • the measurement system interrogates different locations on the wafer surface that correspond with different process and corresponding structural parameter values.
  • the measurement data is associated with a DOE wafer processed with known variations in CD1 and CD2 depicted in FIG. 6 .
  • CD1 is varied by changing dose during lithography
  • CD2 is varied by changing thickness of spacers 335 A-B.
  • dose and spacer thickness are varied to produce the desired parameter variations, in general, measurement data associated with any known variation of process parameters (e.g., lithography focus, exposure, and other local or global parameters), structural parameter, or both, may be contemplated.
  • FIG. 7 depicts a semiconductor wafer 130 having a number of die (e.g., die 133 ) located at various measurement sites over the surface of the wafer.
  • the die is located at measurement sites arranged in a rectangular grid pattern in alignment with the depicted x and y coordinate frame 132 .
  • Each die includes a SAQP metrology target 131 .
  • each multiple patterned metrology target 131 includes a set of lines that result from a first patterning step along with at least one more set of interposed lines that result from a subsequent step in the multiple patterning process.
  • each multiple patterned metrology target includes a grating structure having a repeated pattern of spacer structures such as multiple patterned unit cell 131 .
  • the geometry of multiple patterned unit cell 131 is characterized by CD1, CD2, CD3, and pitchwalk as described with reference to FIG. 6 .
  • Wafer 130 includes an array of die having different, known structural parameter values.
  • CD1 has different, known values depending on its location on the wafer 130 .
  • wafer 130 can be considered a Design of Experiments (DOE) wafer.
  • DOE Design of Experiments
  • the DOE wafer it is desirable for the DOE wafer to include a matrix of multiple patterned metrology targets that span the full range of structural parameter values (e.g., CD1) that are expected to arise from the underlying process window.
  • the values of CD1 change for different columns of die (columns index in the x-direction).
  • wafer 130 includes columns of die that include different values of CD1 depending on their location on the wafer.
  • the values of CD1 range over the values of CD1 that are expected to arise from the process window.
  • a set of DOE wafers similar to DOE wafer 130 are fabricated with each DOE wafer of the set having a different, known nominal value of CD2.
  • CD2 is varied by changing spacer thickness or etch conditions, which affect the entire wafer.
  • each DOE wafer is fabricated under slightly different process conditions to yield different nominal values of CD2.
  • Each DOE wafer of the set includes a range of different, known values of CD1 as described hereinbefore with reference to wafer 130 .
  • one or more features of the raw measurement data is extracted by reducing a dimension of the measurement data. Although, this reduction is optional, when it is employed, the SRM measurement model is determined based at least in part on the one or more extracted features. Similarly one or more features of the process information received from previous process steps is extracted by reducing a dimension of the process information.
  • the dimension of the measurement data, process information, or both may be reduced by a number of known methods, including a principal components analysis, a non-linear principal components analysis, a selection of individual signals from the second amount of measurement data, and a filtering of the second amount of measurement data.
  • the measurement data, process information, or both is analyzed using Principal Components Analysis (PCA), non-linear PCA, kernel PCA, Independent Component Analysis (ICA), Fast Fourier Transform analysis (FFT), Discrete Cosine Transform analysis (DCT), or a combination of these techniques to extract features that most strongly reflect the variations in process parameter, structural parameters, or both, that are present at the different measurement sites.
  • PCA Principal Components Analysis
  • ICA Independent Component Analysis
  • FFT Fast Fourier Transform analysis
  • DCT Discrete Cosine Transform analysis
  • a signal filtering technique may be applied to extract signal data that most strongly reflects the parameter variations present at the different measurement sites.
  • individual signals that most strongly reflect the parameter variations present at the different measurement sites may be selected from multiple signals present in the measurement data.
  • An SRM measurement model is determined based on process information and associated raw measurement signals, or reduced versions of one or both.
  • a trained SRM measurement model is structured to receive measurement data generated by a metrology system at one or more measurement sites and associated process information from previous process steps, and directly determine structural parameter values associated with each measurement target.
  • the SRM measurement model is implemented as a neural network model. In one example, the number of nodes of the neural network is selected based on the features extracted from the measurement data, process information, or both.
  • the SRM measurement model may be implemented as a linear model, a polynomial model, a response surface model, a decision tree model, a random forest model, a support vector machine model or other types of models.
  • the SRM measurement model is trained based on the known values of the parameter of interest.
  • the trained SRM measurement model is generated using DOE process information, raw measurement data, and known parameter values.
  • the model is trained such that its output fits the defined expected response for all the spectra in the process variation space defined by the DOE spectra.
  • the trained SRM model is used to calculate structure parameter values directly from measured data (e.g., spectra) collected from actual device structures of other wafers (e.g., product wafers) and associated process information from previous processes employed to fabricate the measured structures.
  • the SRM measurement model receives measurement data (e.g., measured spectra) and associated process information directly as input and provides parameter values as output, and is thus, a trained input-output model.
  • an amount of optical measurement data associated with measurements of a metrology target on a surface of a semiconductor wafer and process information associated with previous process steps employed to fabricate the metrology target are received by a computing system (e.g., computing system 330 ).
  • the parameter(s) of interest is indicative of a geometric error induced by the multiple patterning process.
  • structural parameters CD1, CD2, CD3, and pitchwalk of the target structure depicted in FIG. 6 are parameters of interest. These parameters are provided by way of non-limiting example. In general, many other structural parameters (e.g., sidewall angle, bottom critical dimension, etc.) may be employed to indicate geometric errors induced by a multiple patterning process.
  • a product wafer under measurement includes an array of nominally valued structures.
  • CD1, CD2, CD3, and pitchwalk have the same nominal values regardless of location on the wafer.
  • the measurement data includes two ellipsometric parameters ( ⁇ , ⁇ ) over a spectral range obtained at different measurement sites.
  • the measurement data includes spectral measurements associated with the multiple patterned metrology target associated with each measurement site.
  • the measurement data is spectral measurement data, in general, the measurement data may be any measurement data indicative of the structural or geometric properties of the structures patterned onto the surface of a semiconductor wafer.
  • the value of at least one parameter of interest associated with the metrology target is determined based on the measurement data, associated process information, and a trained SRM measurement model.
  • the value of the parameter of interest is indicative of a geometric error induced by the multiple patterning process.
  • the value of the parameter of interest is calculated directly from the trained SRM measurement model.
  • the value of the parameter of interest is stored in a memory (e.g., memory 332 ).
  • CD critical dimension
  • a SRM measurement model is trained on measurement signals and associated process information from multiple targets integrated into one multi-target set and operates on measurement signals from the same multiple targets. This approach de-correlates critical parameters from each other and from other process variations.
  • assist targets are located next to the primary measurement target and are subject to the same process variations (e.g., SAQP process variations).
  • the training set of metrology targets includes a primary, nominally dimensioned target and one or more assist targets that have different nominal values of the parameters of interest.
  • the assist targets are formed during the lithography process steps.
  • a mask with different line to space ratio and/or different pitch can be used to create assist targets. It is preferable to locate the primary and assist targets as close together as possible to enhance the accuracy of the SRM measurement model.
  • both primary and assist metrology targets are located adjacent to one another at each measurement site. By locating the metrology targets close together, simplifying assumptions used to link parameters of both metrology targets are less likely to induce significant errors. For example, the thickness of an underlying layer is very likely to be the same value for both metrology targets as long as the targets are located in close proximity. Thus, for adjacent metrology targets, the thickness of the underlying layer can be treated as the same constant value without inducing significant error.
  • assist targets to train and use a SRM measurement model
  • the training of the multi-target SRM measurement model requires training data from the assist targets and the primary metrology target.
  • the use of the multi-target SRM measurement model requires measurement data from the assist targets and the primary measurement target. It is noted however, that reference measurement data for training need only be collected from the primary target as the specific parameter values associated with the assist targets is not of interest.
  • a SRM measurement model is trained and used based on measurement signals from a metrology target measured at multiple steps of the multiple patterning process. Measured spectra or measured parameters of interest from one or more previous process steps are fed forward for training and use of the SRM measurement model associated with the primary target. This approach also de-correlates critical parameters from each other and from other process variations.
  • This approach does not require the extra wafer space needed to implement additional assist targets. However, this approach does require that wafer measurements be performed at multiple process steps.
  • CD-SEM is an exemplary measurement technique that is known for its high measurement uncertainty.
  • LELE and SAOP are described herein by way of non-limiting example.
  • the methods and systems described herein may be employed to improve measurement of parameters of interest generated by any multiple patterning technique (e.g., self-aligned double, triple, quadruple, octuple patterning, double litho, double etch (LELE) patterning, etc.).
  • FIG. 8 illustrates a system 400 for measuring characteristics of a specimen in accordance with the exemplary methods presented herein.
  • the system 400 may be used to perform spectroscopic ellipsometry measurements of one or more structures 410 of a specimen 401 .
  • the system 400 may include a spectroscopic ellipsometer equipped with an illuminator 402 and a spectrometer 404 .
  • the illuminator 402 of the system 400 is configured to generate and direct illumination of a selected wavelength range (e.g., 150-2000 nm) to the structure disposed on the surface of the specimen 401 .
  • the spectrometer 404 is configured to receive illumination reflected from the surface of the specimen 401 .
  • the light emerging from the illuminator 402 is polarized using a polarization state generator 407 to produce a polarized illumination beam 406 .
  • the radiation reflected by the structure disposed on the specimen 401 is passed through a polarization state analyzer 409 and to the spectrometer 404 .
  • the radiation received by the spectrometer 404 in the collection beam 408 is analyzed with regard to polarization state, allowing for spectral analysis by the spectrometer of radiation passed by the analyzer.
  • These spectra 411 are passed to the computing system 430 for analysis of the structure.
  • system 400 includes a single measurement technology (i.e., SE).
  • system 400 may include any number of different measurement technologies.
  • system 400 may be configured as a spectroscopic ellipsometer (including Mueller matrix ellipsometry), a spectroscopic reflectometer, a spectroscopic scatterometer, an overlay scatterometer, an angular resolved beam profile reflectometer, a polarization resolved beam profile reflectometer, a beam profile reflectometer, a beam profile ellipsometer, any single or multiple wavelength ellipsometer, or any combination thereof.
  • measurement data collected by different measurement technologies and analyzed in accordance with the methods described herein may be collected from multiple tools, rather than one tool integrating multiple technologies.
  • system 400 may include one or more computing systems 430 employed to perform measurements based on measured spectra and process information with as described herein.
  • the one or more computing systems 430 may be communicatively coupled to the spectrometer 404 .
  • the one or more computing systems 430 are configured to receive measurement data 411 associated with measurements of the structure of specimen 401 .
  • the one or more computing systems 430 may also be communicatively coupled to one or more process tools 420 configured to execute a previous process step employed to fabricate sample 401 under measurement.
  • the one or more computing systems 430 are configured to receive process information 421 associated with any of the previous process steps, measurements of the structure of specimen 401 at any of the previous process steps, or a combination thereof.
  • the various steps described throughout the present disclosure may be carried out by a single computer system 430 or, alternatively, a multiple computer system 430 .
  • different subsystems of the system 400 such as the spectroscopic ellipsometer 404 , may include a computer system suitable for carrying out at least a portion of the steps described herein. Therefore, the aforementioned description should not be interpreted as a limitation on the present invention but merely an illustration.
  • the one or more computing systems 430 may be configured to perform any other step(s) of any of the method embodiments described herein.
  • the computer system 430 may be communicatively coupled to the spectrometer 404 in any manner known in the art.
  • the one or more computing systems 430 may be coupled to computing systems associated with the spectrometer 404 .
  • the spectrometer 404 may be controlled directly by a single computer system coupled to computer system 430 .
  • the computer system 430 of the metrology system 400 may be configured to receive and/or acquire data or information from the subsystems of the system (e.g., spectrometer 404 and the like) or the one or more process tools 420 by a transmission medium that may include wireline and/or wireless portions. In this manner, the transmission medium may serve as a data link between the computer system 430 and other systems or subsystems of the system 400 .
  • Computer system 430 of the metrology system 400 may be configured to receive and/or acquire data or information (e.g., measurement results, modeling inputs, modeling results, etc.) from other systems by a transmission medium that may include wireline and/or wireless portions.
  • the transmission medium may serve as a data link between the computer system 430 and other systems (e.g., memory on-board metrology system 400 , external memory, process tools 420 , a reference measurement source, or other external systems).
  • the computing system 430 may be configured to receive measurement data from a storage medium (i.e., memory 432 or an external memory) via a data link.
  • spectral results obtained using spectrometer 404 may be stored in a permanent or semi-permanent memory device (e.g., memory 432 or an external memory).
  • the spectral results may be imported from on-board memory or from an external memory system.
  • the computer system 430 may send data to other systems via a transmission medium.
  • a measurement model or a structural parameter value 440 determined by computer system 430 may be communicated and stored in an external memory.
  • measurement results may be exported to another system.
  • Computing system 430 may include, but is not limited to, a personal computer system, mainframe computer system, workstation, image computer, parallel processor, or any other device known in the art.
  • the term “computing system” may be broadly defined to encompass any device having one or more processors, which execute instructions from a memory medium.
  • Program instructions 434 implementing methods such as those described herein may be transmitted over a transmission medium such as a wire, cable, or wireless transmission link.
  • a transmission medium such as a wire, cable, or wireless transmission link.
  • program instructions 434 stored in memory 432 are transmitted to processor 431 over bus 433 .
  • Program instructions 434 are stored in a computer readable medium (e.g., memory 432 ).
  • Exemplary computer-readable media include read-only memory, a random access memory, a magnetic or optical disk, or a magnetic tape.
  • the illumination light and light collected from the illuminated measurement site includes multiple, different wavelengths.
  • the light is collected from the illuminated measurement site at multiple, different collection angles. By detecting light at multiple wavelengths and angles of collection, measurement sensitivity to pitch walk and variation in critical dimensions (e.g., CD) is improved.
  • the light is collected from the illuminated measurement site at multiple, different azimuthal angles. These out-of-plane measurements may also improve measurement sensitivity to pitch walk and variations in critical dimensions.
  • the collection of optical measurement data is optimized for a particular set of system settings, e.g., spectroscopic or angular resolved system, one or more azimuth angles one or more wavelengths, and any combination thereof.
  • FIG. 9 illustrates a method 500 suitable for implementation by a metrology system such as metrology system 400 illustrated in FIG. 8 of the present invention.
  • data processing blocks of method 500 may be carried out via a pre-programmed algorithm executed by one or more processors of computing system 430 , or any other general purpose computing system. It is recognized herein that the particular structural aspects of metrology system 400 do not represent limitations and should be interpreted as illustrative only.
  • a wafer is received by a metrology system (e.g., metrology system 400 ).
  • the wafer includes one or more metrology targets fabricated by a plurality of process steps of a fabrication process flow executed by a plurality of process tools.
  • a first amount of process information is received onto a computing system of the metrology system from a first process tool employed to execute a first process step of the plurality of process steps on the wafer.
  • a second amount of process information is received onto the computing system of the metrology system from the first process tool or another process tool employed to execute a second process step of the plurality of process steps on the wafer.
  • an amount of illumination light is provided to the one or more metrology targets by an illumination subsystem of the metrology system.
  • an amount of light from the one or more metrology targets in response to the illumination is detected by a detector subsystem of the metrology system.
  • measurement signals are generated by the detector subsystem in response to the amount of detected light.
  • a value of a parameter of interest of the one or more metrology targets is estimated based on the measurement signals and the first and second amounts of process information.
  • a value of a correctable parameter associated with at least one of the process steps is estimated based on the measured characteristic of the metrology target and the first and second amounts of process information.
  • the value of the correctable parameter is communicated a process tool employed to execute the at least one process step.
  • the use of measurement data associated with multiple targets for model building, training, and measurement eliminates, or significantly reduces, the effect of under layers in the measurement result.
  • measurement signals from two targets are subtracted to eliminate, or significantly reduce, the effect of under layers in each measurement result.
  • the use of measurement data associated with multiple targets increases the sample and process information embedded in the model.
  • the use of training data that includes measurements of multiple, different targets at one or more measurement sites enables more accurate measurements.
  • a measurement model is created from spectral measurements of a DOE wafer for both isolated and dense targets.
  • the measurement model is then trained based on the spectral measurement data and known structural parameter values.
  • the resulting trained measurement models are subsequently employed to calculate structural parameter values for both isolated and dense targets on sample wafers.
  • each parameter has its own trained model that calculates the parameter value from the measured spectra (or extracted features) associated with both isolated and dense targets.
  • measurement data derived from measurements performed by a combination of multiple, different measurement techniques is collected for model building, training, and measurement.
  • the use of measurement data associated with multiple, different measurement techniques increases the sample and process information embedded in the model and enables more accurate measurements.
  • Measurement data may be derived from measurements performed by any combination of multiple, different measurement techniques. In this manner, different measurement sites may be measured by multiple, different measurement techniques to enhance the measurement information available for characterization of the semiconductor structures.
  • any measurement technique, or combination of two or more measurement techniques may be contemplated within the scope of this patent document.
  • Exemplary measurement techniques include, but are not limited to spectroscopic ellipsometry, including Mueller matrix ellipsometry, spectroscopic reflectometry, spectroscopic scatterometry, scatterometry overlay, beam profile reflectometry, both angle-resolved and polarization-resolved, beam profile ellipsometry, single or multiple discrete wavelength ellipsometry, transmission small angle x-ray scatterometer (TSAXS), small angle x-ray scattering (SAXS), grazing incidence small angle x-ray scattering (GISAXS), wide angle x-ray scattering (WARS), x-ray reflectivity (XRR), x-ray diffraction (XRD), grazing incidence x-ray diffraction (GIXRD), high resolution x-ray diffraction (HRXRD), x-ray photoelectron spectroscopy (XPS),
  • any metrology technique applicable to the characterization of semiconductor structures including image based metrology techniques, may be contemplated.
  • Additional sensor options include electrical sensors such as non-contact capacitance/voltage or current/voltage sensors which bias the device and detect the resulting bias with an optical sensor (or the converse), or assisted optical techniques, such as XRD, XRF, XPS, LEXES, SAXS, and pump probe techniques.
  • a two-dimensional beam profile reflectometer may be used to collect both angle resolved and/or multi-spectral data in a small spot size.
  • a UV Linnik interferometer may also be used as a Mueller matrix spectral pupil imager.
  • model building, training, and measurement methods described herein are implemented as an element of a SpectraShape® optical critical-dimension metrology system available from KLA-Tencor Corporation, Milpitas, Calif., USA. In this manner, the model is created and ready for use immediately after the DOE wafer spectra are collected by the system.
  • model building and training methods described herein are implemented off-line, for example, by a computing system implementing AcuShape® software available from KLA-Tencor Corporation, Milpitas, Calif., USA.
  • the resulting, trained model may be incorporated as an element of an AcuShape® library that is accessible by a metrology system performing measurements.
  • the methods and systems described herein may be applied to overlay metrology.
  • Grating measurements are particularly relevant to the measurement of overlay.
  • the objective of overlay metrology is to determine shifts between different lithographic exposure steps. Performing overlay metrology on-device is difficult due to the small size of on-device structures, and the typically small overlay value.
  • the pitch of typical scribe line overlay metrology structures varies from 200 nanometers to 2,000 nanometers. But, the pitch of on-device, overlay metrology structures is typically 100 nanometers or less.
  • the device overlay is only a small fraction of the periodicity of the device structure.
  • proxy metrology structures used in scatterometry overlay are frequently offset at larger values, e.g., quarter of the pitch, to enhance signal sensitivity to overlay.
  • overlay metrology is performed with sensor architectures having sufficient sensitivity to small offset, small pitch overlay.
  • the methods and systems described herein may be employed to obtain a measurement signal sensitive to overlay based on on-device structures, proxy structures, or both.
  • the measured signals are analyzed to determine overlay error based on variations in the measured signals.
  • the spectral or angle-resolved data is analyzed using PCA, and an overlay model is trained to determine overlay based on the principal components detected in the measured signal.
  • the overlay model is a neural network model. In this sense, the overlay model is not a parametric model, and thus is not prone to errors introduced by inaccurate modeling assumptions.
  • the training of the overlay metrology model is based on measurements of dedicated metrology structures which are nominally identical to the device features but with larger offsets. This can help to overcome the sensitivity problem.
  • These offsets can be introduced by fixed design offsets introduced between features in the two layers to be measured during reticle design. The offsets can also be introduced by shifts in the lithography exposure.
  • the overlay error may be extracted more efficiently from the compressed signal (e.g., PCA signal) by using multiple, shifted targets (e.g., pitch/4 and ⁇ pitch/4) and the effect of the underlayer may also be reduced.
  • the methods and systems for performing semiconductor metrology presented herein may be applied directly to actual device structures or to dedicated metrology targets (e.g., proxy structures) located in-die or within scribe lines.
  • dedicated metrology targets e.g., proxy structures
  • the measurement techniques described herein can be used to provide active feedback to a process tool (e.g., lithography tool, etch tool, deposition tool, etc.).
  • a process tool e.g., lithography tool, etch tool, deposition tool, etc.
  • values of the structural parameters determined using the methods described herein can be communicated to a lithography tool to adjust the lithography system to achieve a desired output.
  • etch parameters e.g., etch time, diffusivity, etc.
  • deposition parameters e.g., time, concentration, etc.
  • systems and methods described herein can be implemented as part of a dedicated metrology tool, or alternatively implemented as part of a process tool (e.g., lithography tool, etch tool, etc.).
  • a process tool e.g., lithography tool, etch tool, etc.
  • critical dimension includes any critical dimension of a structure (e.g., bottom critical dimension, middle critical dimension, top critical dimension, sidewall angle, grating height, etc.), a critical dimension between any two or more structures (e.g., distance between two structures), and a displacement between two or more structures (e.g., overlay displacement between overlaying grating structures, etc.).
  • Structures may include three dimensional structures, patterned structures, overlay structures, etc.
  • critical dimension application or “critical dimension measurement application” includes any critical dimension measurement.
  • the term “metrology system” includes any system employed at least in part to characterize a specimen in any aspect, including measurement applications such as critical dimension metrology, overlay metrology, focus/dosage metrology, and composition metrology. However, such terms of art do not limit the scope of the term “metrology system” as described herein.
  • the metrology system 400 may be configured for measurement of patterned wafers and/or unpatterned wafers.
  • the metrology system may be configured as a LED inspection tool, edge inspection tool, backside inspection tool, macro-inspection tool, or multi-mode inspection tool (involving data from one or more platforms simultaneously), and any other metrology or inspection tool that benefits from the calibration of system parameters based on critical dimension data.
  • a semiconductor processing system e.g., an inspection system or a lithography system
  • a specimen e.g., a wafer, a reticle, or any other sample that may be processed (e.g., printed or inspected for defects) by means known in the art.
  • wafer generally refers to substrates formed of a semiconductor or non-semiconductor material. Examples include, but are not limited to, monocrystalline silicon, gallium arsenide, and indium phosphide. Such substrates may be commonly found and/or processed in semiconductor fabrication facilities. In some cases, a wafer may include only the substrate (i.e., bare wafer). Alternatively, a wafer may include one or more layers of different materials formed upon a substrate. One or more layers formed on a wafer may be “patterned” or “unpatterned.” For example, a wafer may include a plurality of dies having repeatable pattern features.
  • a “reticle” may be a reticle at any stage of a reticle fabrication process, or a completed reticle that may or may not be released for use in a semiconductor fabrication facility.
  • a reticle, or a “mask,” is generally defined as a substantially transparent substrate having substantially opaque regions formed thereon and configured in a pattern.
  • the substrate may include, for example, a glass material such as amorphous SiO 2 .
  • a reticle may be disposed above a resist-covered wafer during an exposure step of a lithography process such that the pattern on the reticle may be transferred to the resist.
  • One or more layers formed on a wafer may be patterned or unpatterned.
  • a wafer may include a plurality of dies, each having repeatable pattern features. Formation and processing of such layers of material may ultimately result in completed devices.
  • Many different types of devices may be formed on a wafer, and the term wafer as used herein is intended to encompass a wafer on which any type of device known in the art is being fabricated.
  • the functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium.
  • Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another.
  • a storage media may be any available media that can be accessed by a general purpose or special purpose computer.
  • such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code means in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. Also, any connection is properly termed a computer-readable medium.
  • Disk and disc includes compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk and blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.

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CN201780021343.8A CN108886006B (zh) 2016-04-04 2017-04-03 利用来自多个处理步骤的信息的半导体计量
DE112017001846.3T DE112017001846T5 (de) 2016-04-04 2017-04-03 Halbleitermetrologie mit Information von mehreren Prozessschritten
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Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3290911A1 (de) * 2016-09-02 2018-03-07 ASML Netherlands B.V. Verfahren und system zur überwachung einer prozessvorrichtung
US10499876B2 (en) * 2017-07-31 2019-12-10 Taiwan Semiconductor Manufacturing Company, Ltd. Test key design to enable X-ray scatterometry measurement
US11380594B2 (en) * 2017-11-15 2022-07-05 Kla-Tencor Corporation Automatic optimization of measurement accuracy through advanced machine learning techniques
KR102666904B1 (ko) * 2018-03-13 2024-05-20 어플라이드 머티어리얼스, 인코포레이티드 반도체 처리의 모니터링을 위한 기계 학습 시스템들
CN110660702B (zh) * 2018-06-29 2022-11-29 台湾积体电路制造股份有限公司 覆盖管理方法、覆盖管理***及计算***
US11199505B2 (en) 2018-08-23 2021-12-14 International Business Machines Corporation Machine learning enhanced optical-based screening for in-line wafer testing
US11244873B2 (en) * 2018-10-31 2022-02-08 Tokyo Electron Limited Systems and methods for manufacturing microelectronic devices
US11410290B2 (en) * 2019-01-02 2022-08-09 Kla Corporation Machine learning for metrology measurements
US11436506B2 (en) * 2019-03-06 2022-09-06 Carl Zeiss Smt Gmbh Method and devices for determining metrology sites
US11990380B2 (en) * 2019-04-19 2024-05-21 Kla Corporation Methods and systems for combining x-ray metrology data sets to improve parameter estimation
US11914290B2 (en) * 2019-07-24 2024-02-27 Kla Corporation Overlay measurement targets design
US11568101B2 (en) * 2019-08-13 2023-01-31 International Business Machines Corporation Predictive multi-stage modelling for complex process control
US20220236647A1 (en) * 2019-08-20 2022-07-28 Asml Netherlands B.V. Method for controlling a semiconductor manufacturing process
KR20210064445A (ko) 2019-11-25 2021-06-03 삼성전자주식회사 반도체 공정 시뮬레이션 시스템 및 그것의 시뮬레이션 방법
US11520321B2 (en) * 2019-12-02 2022-12-06 Kla Corporation Measurement recipe optimization based on probabilistic domain knowledge and physical realization
DE102020100565A1 (de) * 2020-01-13 2021-07-15 Aixtron Se Verfahren zum Abscheiden von Schichten
US11530913B2 (en) * 2020-09-24 2022-12-20 Kla Corporation Methods and systems for determining quality of semiconductor measurements
US20220114438A1 (en) * 2020-10-09 2022-04-14 Kla Corporation Dynamic Control Of Machine Learning Based Measurement Recipe Optimization
EP4016186A1 (de) * 2020-12-18 2022-06-22 ASML Netherlands B.V. Metrologieverfahren zur messung eines geätzten grabens und zugehörige metrologievorrichtung
US20230160960A1 (en) * 2021-11-22 2023-05-25 Onto Innovation Semiconductor substrate yield prediction based on spectra data from multiple substrate dies
US20230259035A1 (en) * 2022-02-11 2023-08-17 Applied Materials, Inc. Characterization of photosensitive materials

Citations (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5608526A (en) 1995-01-19 1997-03-04 Tencor Instruments Focused beam spectroscopic ellipsometry method and system
US5859424A (en) 1997-04-08 1999-01-12 Kla-Tencor Corporation Apodizing filter system useful for reducing spot size in optical measurements and other applications
US6429943B1 (en) 2000-03-29 2002-08-06 Therma-Wave, Inc. Critical dimension analysis with simultaneous multiple angle of incidence measurements
US6633831B2 (en) 2000-09-20 2003-10-14 Kla Tencor Technologies Methods and systems for determining a critical dimension and a thin film characteristic of a specimen
US6734967B1 (en) 1995-01-19 2004-05-11 Kla-Tencor Technologies Corporation Focused beam spectroscopic ellipsometry method and system
US6816570B2 (en) 2002-03-07 2004-11-09 Kla-Tencor Corporation Multi-technique thin film analysis tool
US6895075B2 (en) 2003-02-12 2005-05-17 Jordan Valley Applied Radiation Ltd. X-ray reflectometry with small-angle scattering measurement
US7092096B2 (en) * 2004-02-20 2006-08-15 Taiwan Semiconductor Manufacturing Co., Ltd. Optical scatterometry method of sidewall spacer analysis
US20080144919A1 (en) 2006-12-14 2008-06-19 Tokyo Electron Limited Determining transmittance of a photomask using optical metrology
US7478019B2 (en) 2005-01-26 2009-01-13 Kla-Tencor Corporation Multiple tool and structure analysis
US7826071B2 (en) 2001-12-19 2010-11-02 Kla-Tencor Corporation Parametric profiling using optical spectroscopic systems
US7929667B1 (en) 2008-10-02 2011-04-19 Kla-Tencor Corporation High brightness X-ray metrology
US7933026B2 (en) 2006-02-02 2011-04-26 Kla-Tencor Corporation High resolution monitoring of CD variations
US8142966B2 (en) 2008-05-21 2012-03-27 Kla-Tenor Corporation Substrate matrix to decouple tool and process effects
US20130114085A1 (en) 2011-10-27 2013-05-09 Kla-Tencor Corporation Dynamically Adjustable Semiconductor Metrology System
US20130155406A1 (en) 2007-12-17 2013-06-20 Asml Netherlands B.V. Diffraction Based Overlay Metrology Tool and Method of Diffraction Based Overlay Metrology
US20140111791A1 (en) 2012-10-19 2014-04-24 Kla-Tencor Corporation Phase characterization of targets
US20140132948A1 (en) 2012-11-09 2014-05-15 Kla-Tencor Corporation Apparatus and Method for Optical Metrology with Optimized System Parameters
US20140172394A1 (en) 2012-12-18 2014-06-19 Kla-Tencor Corporation Integrated use of model-based metrology and a process model
US8797554B2 (en) * 2012-05-21 2014-08-05 Asml Netherlands B.V. Determining a structural parameter and correcting an asymmetry property
US20140222380A1 (en) 2013-02-05 2014-08-07 Alexander Kuznetsov Method of electromagnetic modeling of finite structures and finite illumination for metrology and inspection
US8843875B2 (en) 2012-05-08 2014-09-23 Kla-Tencor Corporation Measurement model optimization based on parameter variations across a wafer
US20140297211A1 (en) 2013-03-27 2014-10-02 Kla-Tencor Corporation Statistical model-based metrology
US20140316730A1 (en) 2013-04-19 2014-10-23 Kla-Tencor Corporation On-device metrology
US20150042984A1 (en) 2013-08-10 2015-02-12 Kla-Tencor Corporation Methods and apparatus for determining focus
US20150046118A1 (en) 2013-08-11 2015-02-12 Kla-Tencor Corporation Differential methods and apparatus for metrology of semiconductor targets
US20150176985A1 (en) 2013-12-23 2015-06-25 Kla-Tencor Corporation Measurement Of Multiple Patterning Parameters
US20150235108A1 (en) 2014-02-20 2015-08-20 Kla-Tencor Corporation Signal Response Metrology For Image Based Overlay Measurements
US20150241790A1 (en) 2014-02-21 2015-08-27 Kla-Tencor Corporation System and Method for Field-By-Field Overlay Process Control Using Measured and Estimated Field Parameters
US20150323471A1 (en) 2014-05-12 2015-11-12 Kla-Tencor Corporation Apparatus, techniques, and target designs for measuring semiconductor parameters
US20160109230A1 (en) 2014-10-16 2016-04-21 Kla-Tencor Corporation Metrology Of Multiple Patterning Processes

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020177245A1 (en) * 2001-03-29 2002-11-28 Sonderman Thomas J. Method and apparatus for controlling feature critical dimensions based on scatterometry derived profile
US7327475B1 (en) * 2006-12-15 2008-02-05 Tokyo Electron Limited Measuring a process parameter of a semiconductor fabrication process using optical metrology
US8437870B2 (en) * 2009-06-05 2013-05-07 Taiwan Semiconductor Manufacturing Company, Ltd. System and method for implementing a virtual metrology advanced process control platform
JP2011027461A (ja) * 2009-07-22 2011-02-10 Renesas Electronics Corp パターン形状計測方法、半導体装置の製造方法、およびプロセス制御システム
CN201502829U (zh) * 2009-09-28 2010-06-09 江苏亿丰机械制造有限公司 免维护双向旋转补偿器
WO2013130426A1 (en) * 2012-03-02 2013-09-06 Codexis, Inc. Recombinant host cells and processes for producing 1,3-butadiene through a 5-hydroxypent-3-enoate intermediate

Patent Citations (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6734967B1 (en) 1995-01-19 2004-05-11 Kla-Tencor Technologies Corporation Focused beam spectroscopic ellipsometry method and system
US5608526A (en) 1995-01-19 1997-03-04 Tencor Instruments Focused beam spectroscopic ellipsometry method and system
US5859424A (en) 1997-04-08 1999-01-12 Kla-Tencor Corporation Apodizing filter system useful for reducing spot size in optical measurements and other applications
US6429943B1 (en) 2000-03-29 2002-08-06 Therma-Wave, Inc. Critical dimension analysis with simultaneous multiple angle of incidence measurements
US6972852B2 (en) 2000-03-29 2005-12-06 Therma-Wave, Inc. Critical dimension analysis with simultaneous multiple angle of incidence measurements
US6633831B2 (en) 2000-09-20 2003-10-14 Kla Tencor Technologies Methods and systems for determining a critical dimension and a thin film characteristic of a specimen
US7826071B2 (en) 2001-12-19 2010-11-02 Kla-Tencor Corporation Parametric profiling using optical spectroscopic systems
US6816570B2 (en) 2002-03-07 2004-11-09 Kla-Tencor Corporation Multi-technique thin film analysis tool
US6895075B2 (en) 2003-02-12 2005-05-17 Jordan Valley Applied Radiation Ltd. X-ray reflectometry with small-angle scattering measurement
US7092096B2 (en) * 2004-02-20 2006-08-15 Taiwan Semiconductor Manufacturing Co., Ltd. Optical scatterometry method of sidewall spacer analysis
US7478019B2 (en) 2005-01-26 2009-01-13 Kla-Tencor Corporation Multiple tool and structure analysis
US7933026B2 (en) 2006-02-02 2011-04-26 Kla-Tencor Corporation High resolution monitoring of CD variations
US20080144919A1 (en) 2006-12-14 2008-06-19 Tokyo Electron Limited Determining transmittance of a photomask using optical metrology
US20130155406A1 (en) 2007-12-17 2013-06-20 Asml Netherlands B.V. Diffraction Based Overlay Metrology Tool and Method of Diffraction Based Overlay Metrology
US8142966B2 (en) 2008-05-21 2012-03-27 Kla-Tenor Corporation Substrate matrix to decouple tool and process effects
US7929667B1 (en) 2008-10-02 2011-04-19 Kla-Tencor Corporation High brightness X-ray metrology
US20130114085A1 (en) 2011-10-27 2013-05-09 Kla-Tencor Corporation Dynamically Adjustable Semiconductor Metrology System
US8843875B2 (en) 2012-05-08 2014-09-23 Kla-Tencor Corporation Measurement model optimization based on parameter variations across a wafer
US8797554B2 (en) * 2012-05-21 2014-08-05 Asml Netherlands B.V. Determining a structural parameter and correcting an asymmetry property
US20140111791A1 (en) 2012-10-19 2014-04-24 Kla-Tencor Corporation Phase characterization of targets
US20140132948A1 (en) 2012-11-09 2014-05-15 Kla-Tencor Corporation Apparatus and Method for Optical Metrology with Optimized System Parameters
US20140172394A1 (en) 2012-12-18 2014-06-19 Kla-Tencor Corporation Integrated use of model-based metrology and a process model
US20140222380A1 (en) 2013-02-05 2014-08-07 Alexander Kuznetsov Method of electromagnetic modeling of finite structures and finite illumination for metrology and inspection
US20140297211A1 (en) 2013-03-27 2014-10-02 Kla-Tencor Corporation Statistical model-based metrology
US20140316730A1 (en) 2013-04-19 2014-10-23 Kla-Tencor Corporation On-device metrology
US20150042984A1 (en) 2013-08-10 2015-02-12 Kla-Tencor Corporation Methods and apparatus for determining focus
US20150046118A1 (en) 2013-08-11 2015-02-12 Kla-Tencor Corporation Differential methods and apparatus for metrology of semiconductor targets
US20150176985A1 (en) 2013-12-23 2015-06-25 Kla-Tencor Corporation Measurement Of Multiple Patterning Parameters
US20150235108A1 (en) 2014-02-20 2015-08-20 Kla-Tencor Corporation Signal Response Metrology For Image Based Overlay Measurements
US20150241790A1 (en) 2014-02-21 2015-08-27 Kla-Tencor Corporation System and Method for Field-By-Field Overlay Process Control Using Measured and Estimated Field Parameters
US20150323471A1 (en) 2014-05-12 2015-11-12 Kla-Tencor Corporation Apparatus, techniques, and target designs for measuring semiconductor parameters
US20160109230A1 (en) 2014-10-16 2016-04-21 Kla-Tencor Corporation Metrology Of Multiple Patterning Processes

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
International Search Report dated Jul. 18, 2017, for PCT Application No. PCT/US2017/025757 filed on Apr. 3, 2017 by KLA-Tencor Corporation, 3 pages.
Kim, Dongil, et al., "Improvement of virtual metrology performance by removing metrology noises in a training dataset," Pattern Anal Applic (2015) 18:173-189.

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