TWM641563U

TWM641563U - Heat-dissipation substrate

Info

Publication number: TWM641563U
Application number: TW112201452U
Authority: TW
Inventors: 賴囿儒; 陳禹伸; 林建辰
Original assignee: 欣興電子股份有限公司
Priority date: 2023-02-20
Filing date: 2023-02-20
Publication date: 2023-05-21

Abstract

A heat-dissipation substrate is provided. The heat-dissipation substrate includes a main body, an electronic element, an element plated conductive via, and a fluid hole. The main body has a first surface and a second surface opposite to each other, and the main body has an accommodating space therein. The electronic element is disposed in the accommodating space of the main body. The element plated conductive via is disposed in the main body and electrically connected to the electronic element. The fluid hole is disposed in the main body and penetrates through the first surface and the second surface of the main body, and the fluid hole is in fluid communication with the accommodating space.

Description

散熱基板Heat sink

本創作是關於散熱基板，特別是關於具有導流孔的散熱基板。 The present invention is about a heat dissipation substrate, especially a heat dissipation substrate with a flow guide hole.

在電子產品中，可將諸如晶片等的具有運算功能的電子元件埋置在基板的內部，以保護這些電子元件不受到水氣或是腐蝕性物質的侵蝕。然而，隨著電子元件的功率逐漸上升，現有的基板已難以即時移除電子元件在運行中所產生之高熱。是以，雖然現存的埋置有電子元件的基板已逐步滿足它們既定的用途，但它們並非在各方面皆符合要求。因此，關於基板仍有一些問題需要克服。 In electronic products, electronic components with computing functions, such as chips, can be embedded inside the substrate to protect these electronic components from being corroded by moisture or corrosive substances. However, as the power of electronic components gradually increases, it is difficult for the existing substrates to remove the high heat generated by the electronic components in real time. Therefore, although existing substrates embedded with electronic components have gradually met their intended purpose, they are not satisfactory in every respect. Therefore, there are still some issues to be overcome regarding the substrate.

在一些實施例中，提供散熱基板。所述散熱基板包括主體、電子元件、元件導電孔及導流孔。主體具有彼此相對的第一表面及第二表面，且主體內具有容置空間。電子元件設置於主體的容置空間中。元件導電孔設置於主體中並電性連接至電子元件。導流孔設置於主體中並貫穿主體的第一表面與第二表面，且導流孔與容置空間流體連通。 In some embodiments, a heat sink substrate is provided. The heat dissipation substrate includes a main body, electronic components, component conductive holes and flow guide holes. The main body has a first surface and a second surface opposite to each other, and there is an accommodating space in the main body. The electronic components are arranged in the accommodating space of the main body. The component conductive hole is disposed in the main body and electrically connected to the electronic component. The diversion hole is arranged in the main body and runs through the first surface and the second surface of the main body, and the diversion hole In fluid communication with the receiving space.

在一些實施例中，導流孔暴露電子元件的複數個側表面中的至少一個。 In some embodiments, the flow guide hole exposes at least one of the plurality of side surfaces of the electronic component.

在一些實施例中，導流孔非封閉地環繞電子元件的些側表面。 In some embodiments, the air guiding hole non-closedly surrounds some side surfaces of the electronic component.

在一些實施例中，導流孔對稱設置於電子元件的兩側。 In some embodiments, the guide holes are symmetrically disposed on two sides of the electronic component.

在一些實施例中，導流孔在第一表面及/或第二表面上的截面形狀為矩形。 In some embodiments, the cross-sectional shape of the diversion hole on the first surface and/or the second surface is a rectangle.

在一些實施例中，散熱基板更包括保護層，保護層設置於主體的第一表面及第二表面上。導電孔貫穿設置於主體的第一表面上的保護層，且導流孔貫穿設置於主體的第一表面及第二表面上的保護層。 In some embodiments, the heat dissipation substrate further includes a protection layer, and the protection layer is disposed on the first surface and the second surface of the main body. The conductive hole penetrates the protection layer disposed on the first surface of the main body, and the conduction hole penetrates the protection layer disposed on the first surface and the second surface of the main body.

在一些實施例中，散熱基板更包括彼此相對的第一導電層及第二導電層。第一導電層及第二導電層設置於主體中，且第一導電層藉由第一導電孔與第二導電層電性連接。 In some embodiments, the heat dissipation substrate further includes a first conductive layer and a second conductive layer opposite to each other. The first conductive layer and the second conductive layer are arranged in the main body, and the first conductive layer is electrically connected with the second conductive layer through the first conductive hole.

在一些實施例中，第一導電層的底表面與電子元件的頂表面齊平，且第二導電層的頂表面與電子元件的底表面齊平。 In some embodiments, the bottom surface of the first conductive layer is flush with the top surface of the electronic component, and the top surface of the second conductive layer is flush with the bottom surface of the electronic component.

在一些實施例中，散熱基板更包括彼此相對的第三導電層及第四導電層，第三導電層及第四導電層設置於主體中或主體上。第三導電層藉由第二導電孔與第一導電層電性連接，且第四導電層藉由第三導電孔與第二導電層電性連接。 In some embodiments, the heat dissipation substrate further includes a third conductive layer and a fourth conductive layer opposite to each other, and the third conductive layer and the fourth conductive layer are disposed in or on the main body. The third conductive layer is electrically connected to the first conductive layer through the second conductive hole, and the fourth conductive layer is electrically connected to the second conductive layer through the third conductive hole.

在一些實施例中，第三導電層及第四導電層設置於主體上。第三導電層的底表面與設置於第一表面上的保護層的底表面齊平，且第四導電層的頂表面與設置於第二表面上的保護層的頂表面齊平。 In some embodiments, the third conductive layer and the fourth conductive layer are disposed on the main body. The bottom surface of the third conductive layer is flush with the bottom surface of the protective layer disposed on the first surface, and the top surface of the fourth conductive layer is flush with the top surface of the protective layer disposed on the second surface.

在一些實施例中，第三導電層及第四導電層設置於主體中，且散熱基板更包括彼此相對的第五導電層及第六導電層。第五導電層及第六導電層設置於主體上。第五導電層藉由第四導電孔與第三導電層電性連接，且第六導電層藉由第五導電孔與第四導電層電性連接。 In some embodiments, the third conductive layer and the fourth conductive layer are disposed in the main body, and the heat dissipation substrate further includes a fifth conductive layer and a sixth conductive layer opposite to each other. The fifth conductive layer and the sixth conductive layer are disposed on the main body. The fifth conductive layer is electrically connected to the third conductive layer through the fourth conductive hole, and the sixth conductive layer is electrically connected to the fourth conductive layer through the fifth conductive hole.

在一些實施例中，第五導電層的底表面與設置於第一表面上的保護層的底表面齊平，且第六導電層的頂表面與設置於第二表面上的保護層的頂表面齊平。 In some embodiments, the bottom surface of the fifth conductive layer is flush with the bottom surface of the protective layer disposed on the first surface, and the top surface of the sixth conductive layer is flush with the top surface of the protective layer disposed on the second surface. flush.

本揭露的散熱基板可應用於多種類型的電子裝置中。為讓本揭露之特徵及優點能更明顯易懂，下文特舉出各種實施例，並配合所附圖式，作詳細說明如下。 The heat dissipation substrate of the present disclosure can be applied to various types of electronic devices. In order to make the features and advantages of the present disclosure more comprehensible, various embodiments are specially cited below, together with the accompanying drawings, to be described in detail as follows.

1a,1b:散熱基板 1a, 1b: heat sink substrate

10:基礎基板 10: Basic substrate

100:核心層 100: core layer

102,103:容置空間 102,103: storage space

11,24,32,39:圖案化遮罩層 11,24,32,39: patterned mask layer

12:通孔 12: Through hole

13,14,101,181,191,25,26,331,341,40,41:導電層 13,14,101,181,191,25,26,331,341,40,41: conductive layer

13a,17b,100b,25a,30a,40a,Sb:底表面 13a, 17b, 100b, 25a, 30a, 40a, Sb: bottom surface

14a,16a,17a,100a,26a,30b,41a,Sa:頂表面 14a, 16a, 17a, 100a, 26a, 30b, 41a, Sa: top surface

15,27,28,29,42,43,44:導電孔 15,27,28,29,42,43,44: conductive hole

16:承載基板 16: Carrier substrate

17:電子元件 17: Electronic components

17c:側表面 17c: side surface

18,19,33,34:增層結構 18,19,33,34: Build-up structure

180,190,330,340:介電層 180, 190, 330, 340: dielectric layer

20,35:主體 20,35: main body

20a,35a:第一表面 20a, 35a: first surface

20b,35b:第二表面 20b, 35b: second surface

21,22,23,36,37,38:盲孔 21,22,23,36,37,38: Blind holes

30:保護層 30: protective layer

31,45:導流孔 31,45: diversion hole

d1,d2:距離 d1, d2: distance

H1,H2,H3:高度 H1, H2, H3: Height

S:氣室 S: air chamber

W1~W5:寬度 W1~W5: Width

藉由以下的詳細敘述配合所附圖式，能更加理解本揭露實施例的觀點。值得注意的是，依照慣例，一些部件(feature)可能沒有按照比例繪製。事實上，為了能清楚地描述，不同部件的尺寸可能被增加或減少。 The viewpoints of the embodiments of the present disclosure can be better understood through the following detailed description and the accompanying drawings. It is worth noting that, in accordance with common practice, some features may not be drawn to scale. In fact, the dimensions of various components may be increased or decreased for clarity of description.

圖1至圖15分別是根據本揭露的一些實施例，顯示在製造方法中的各階段的散熱基板的剖面圖。 1 to 15 are respectively according to some embodiments of the present disclosure, showing the manufacturing method Cross-sectional views of the heat sink substrate in various stages.

圖16是根據本揭露的一些實施例，顯示導流孔的上視圖。 FIG. 16 is a top view showing a flow guide hole, according to some embodiments of the present disclosure.

圖17至圖29分別是根據本揭露的另一些實施例，顯示在製造方法中的各階段的散熱基板的剖面圖。 17 to 29 are cross-sectional views of the heat dissipation substrate at various stages in the manufacturing method according to other embodiments of the present disclosure.

以下揭露提供了很多不同的實施例或範例，用於實施所提供的散熱基板中的不同部件。各部件及其配置的具體範例描述如下，以簡化本揭露實施例，當然並非用以限定本揭露。舉例而言，敘述中若提及第一部件形成在第二部件之上，可能包括第一部件及第二部件直接接觸的實施例，也可能包括形成額外的部件在第一部件及第二部件之間，使得第一部件及第二部件不直接接觸的實施例。此外，本揭露可能在不同的實施例或範例中重複元件符號及/或字符。如此重複是為了簡明及清楚，而非用以表示所討論的不同實施例及/或範例之間的關係。 The following disclosure provides many different embodiments or examples for implementing different components in the provided heat dissipation substrate. Specific examples of components and their configurations are described below to simplify the embodiments of the disclosure, but certainly not to limit the disclosure. For example, if it is mentioned in the description that the first component is formed on the second component, it may include an embodiment in which the first component and the second component are in direct contact, or may include forming an additional component on the first component and the second component An embodiment in which the first component and the second component are not in direct contact. In addition, the present disclosure may repeat element symbols and/or characters in different embodiments or examples. This repetition is for brevity and clarity and does not represent a relationship between the various embodiments and/or examples discussed.

本文中所提到的方向用語，例如：「上」、「下」、「左」、「右」及其類似用語是參考圖式的方向。因此，使用的方向用語是用來說明而非限制本揭露。 The directional terms mentioned herein, such as "upper", "lower", "left", "right" and similar terms refer to the directions of the drawings. Accordingly, the directional language used is to illustrate, not to limit, the present disclosure.

在本揭露的一些實施例中，關於設置、連接之用語例如「設置」、「連接」及其類似用語，除非特別定義，否則可指兩個部件直接接觸，或者亦可指兩個部件並非直接接觸，其中有額外結部件位於此兩個結構之間。關於設置、連接之用語亦可包括兩個結構都可移動，或者兩個結構都固定的情況。 In some embodiments of the present disclosure, terms such as "arrangement", "connection" and similar terms related to arrangement and connection, unless otherwise specified, may refer to two parts in direct contact, or may also refer to two parts that are not in direct contact. Contact, where there is an extra junction component between the two structures. The terms about setting and connection can also include two Both structures are movable, or both structures are fixed.

另外，本說明書或申請專利範圍中提及的「第一」、「第二」及其類似用語是用以命名不同的部件或區別不同實施例或範圍，而並非用來限制部件數量上的上限或下限，也並非用以限定部件的製造順序或設置順序。 In addition, the "first", "second" and similar terms mentioned in this specification or the scope of the patent application are used to name different components or to distinguish different embodiments or ranges, and are not used to limit the upper limit of the number of components or lower limit, nor is it intended to limit the order of manufacture or arrangement of components.

於下文中，「大約」、「實質上」或其類似用語表示在一給定數值或數值範圍的10%內、或5%內、或3%之內、或2%之內、或1%之內、或0.5%之內。在此給定的數量為大約的數量，亦即在沒有特定說明「大約」或「實質上」的情況下，仍可隱含「大約」或「實質上」的含義。 Hereinafter, "about", "substantially" or similar terms mean within 10%, or within 5%, or within 3%, or within 2%, or within 1% of a given value or range of values within, or within 0.5%. The quantities given here are approximate quantities, that is, the meaning of "approximately" or "substantially" may still be implied if "approximately" or "substantially" is not specified.

除非另外定義，在此使用的全部用語(包括技術及科學用語)具有與所屬技術領域中具有通常知識者通常理解的相同涵義。能理解的是，這些用語例如在通常使用的字典中定義用語，應被解讀成具有與相關技術及本揭露的背景或上下文一致的意思，而不應以一理想化或過度正式的方式解讀，除非在本揭露的實施例有特別定義。 Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. It can be understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having meanings consistent with the background or context of the related technology and the present disclosure, and should not be interpreted in an idealized or overly formal manner, Unless otherwise specified in the embodiments of the present disclosure.

以下描述實施例的一些變化。在不同圖式和說明的實施例中，相同或相似的元件符號被用來標明相同或相似的部件。可以理解的是，在方法之前、期間中、之後可以提供額外的步驟，且一些所敘述的步驟可為了方法的其他實施例被取代或刪除。 Some variations of the embodiment are described below. In different drawings and described embodiments, the same or similar reference numerals are used to designate the same or similar components. It is understood that additional steps may be provided before, during, and after the method, and that some recited steps may be substituted or deleted for other embodiments of the method.

在一些散熱基板中，為了提升埋置電子元件的製程裕度，通常會在製作過程中形成較大的容置空間。然而，在將電子元件埋置於容置空間後，未被填滿的容置空間就會形成氣孔或是氣室。這些氣室不與外界流體連通，從而導致其中的氣體容易因熱漲冷縮而在散熱基板內產生非預期的熱應力。 In some heat-dissipating substrates, in order to improve the process margin of embedding electronic components, a larger accommodating space is usually formed during the manufacturing process. However, in the electronic After the components are embedded in the accommodation space, air holes or air chambers will be formed in the unfilled accommodation space. These air chambers are not in fluid communication with the outside world, so that the gas in them is prone to generate unintended thermal stress in the heat dissipation substrate due to thermal expansion and contraction.

據此，本揭露提供了一種具有導流通道的散熱基板。藉由在散熱基板上形成與容置空間流體連通的導流通道，不僅可以避免散熱基板因熱應力損壞，更可有效地提升電子元件的散熱效果。 Accordingly, the present disclosure provides a heat dissipation substrate with a conduction channel. By forming the conduction channel in fluid communication with the accommodation space on the heat dissipation substrate, not only can the heat dissipation substrate be prevented from being damaged due to thermal stress, but also the heat dissipation effect of the electronic components can be effectively improved.

參照圖1-15，其是根據本揭露的一些實施例，顯示在製造方法中的各階段的散熱基板的剖面示意圖。首先參照圖1，在一些實施例中，提供基礎基板10，基礎基板10可為或可包括銅箔基板，但本揭露不限於此。在一些實施例中，基礎基板10可包括核心層100及導電層101。在一些實施例中，核心層100可為或可包括含有高分子材料、纖維材料、其他合適的材料的預浸材(prepreg)，但本揭露不限於此。舉例而言，高分子材料可為或可包括環氧樹脂(epoxy resin)、聚醯亞胺(polyimide，PI)、其他合適的高分子材料或其組合，但本揭露不限於此。纖維材料可包括碳纖維(carbon fiber)、玻璃纖維(glass fiber)、其他合適的纖維材料或其組合，但本揭露不限於此。 Referring to FIGS. 1-15 , which are schematic cross-sectional views of a heat dissipation substrate at various stages in a manufacturing method according to some embodiments of the present disclosure. Referring first to FIG. 1 , in some embodiments, a base substrate 10 is provided, which may be or include a copper foil substrate, but the disclosure is not limited thereto. In some embodiments, the base substrate 10 may include a core layer 100 and a conductive layer 101 . In some embodiments, the core layer 100 may be or may include a prepreg including polymer materials, fiber materials, or other suitable materials, but the present disclosure is not limited thereto. For example, the polymer material may be or include epoxy resin, polyimide (PI), other suitable polymer materials or combinations thereof, but the disclosure is not limited thereto. The fiber material may include carbon fiber, glass fiber, other suitable fiber materials or combinations thereof, but the present disclosure is not limited thereto.

在一些實施例中，導電層101可設置於核心層100上。舉例而言，導電層101可完整覆蓋核心層100的頂表面100a及底表面100b，或部分覆蓋核心層100的頂表面100a及底表面100b。在一些實施例中，導電層101可為或可包括導電材料。舉例而言，所述導電材料可為鋁(Al)、銅(Cu)、其合金或其化合物，但本揭露不限於此。在一些實施例中，導電層101可為銅箔。舉例而言，銅箔可為或可包括黃銅(brass)、磷青銅(phosphor bronze)、鈹銅(berylliun alloy)或無氧銅，但本揭露不限於此。 In some embodiments, the conductive layer 101 can be disposed on the core layer 100 . For example, the conductive layer 101 can completely cover the top surface 100 a and the bottom surface 100 b of the core layer 100 , or partially cover the top surface 100 a and the bottom surface 100 b of the core layer 100 . In some embodiments, the conductive layer 101 can be or include a conductive material. For example, the conductive material may be aluminum (Al), copper (Cu), alloys thereof, or compounds thereof, but The present disclosure is not limited thereto. In some embodiments, the conductive layer 101 can be copper foil. For example, the copper foil may be or include brass, phosphor bronze, berylliun alloy or oxygen-free copper, but the disclosure is not limited thereto.

參照圖2，在一些實施例中，形成圖案化遮罩層11在導電層101上。舉例而言，圖案化遮罩層11可為或可包括光阻，但本揭露不限於此。接著，形成貫穿基礎基板10的通孔(through hole)12。在一些實施例中，可藉由雷射鑽孔製程、機械鑽孔製程、其他合適的鑽孔製程或其組合形成通孔12，但本揭露不限於此。可替代地，可先形成通孔12在基礎基板10中，再形成圖案化遮罩層11在基礎基板10上。 Referring to FIG. 2 , in some embodiments, a patterned mask layer 11 is formed on the conductive layer 101 . For example, the patterned mask layer 11 may be or may include photoresist, but the disclosure is not limited thereto. Next, through holes 12 penetrating through the base substrate 10 are formed. In some embodiments, the via hole 12 may be formed by a laser drilling process, a mechanical drilling process, other suitable drilling processes or a combination thereof, but the disclosure is not limited thereto. Alternatively, the through hole 12 may be formed in the base substrate 10 first, and then the patterned mask layer 11 may be formed on the base substrate 10 .

參照圖3，在一些實施例中，設置導電材料於由圖案化遮罩層11暴露的導電層101上以形成第一導電層13及第二導電層14，以及設置導電材料於通孔12中以形成第一導電孔15。其中，第一導電層13及第二導電層14彼此相對，且第一導電層13藉由第一導電孔15與第二導電層14電性連接。舉例而言，可藉由電鍍製程設置導電材料於導電層101上及通孔12中，但本揭露不限於此。在一些實施例中，上述的導電材料可相似或相同於導電層101的材料，但本揭露不限於此。在一些實施例中，第一導電層13及第二導電層14可為導電線路或導電圖案，但本揭露不限於此。在形成第一導電層13、第二導電層14及第一導電孔15之後，移除圖案化遮罩層11。舉例而言，可藉由選擇性蝕刻移除圖案化遮罩層11，但本揭露不限於此。 Referring to FIG. 3 , in some embodiments, a conductive material is disposed on the conductive layer 101 exposed by the patterned mask layer 11 to form the first conductive layer 13 and the second conductive layer 14, and the conductive material is disposed in the through hole 12 to form the first conductive hole 15 . Wherein, the first conductive layer 13 and the second conductive layer 14 are opposite to each other, and the first conductive layer 13 is electrically connected to the second conductive layer 14 through the first conductive hole 15 . For example, the conductive material can be disposed on the conductive layer 101 and in the through hole 12 through an electroplating process, but the disclosure is not limited thereto. In some embodiments, the aforementioned conductive material may be similar or identical to the material of the conductive layer 101 , but the disclosure is not limited thereto. In some embodiments, the first conductive layer 13 and the second conductive layer 14 can be conductive lines or conductive patterns, but the disclosure is not limited thereto. After forming the first conductive layer 13 , the second conductive layer 14 and the first conductive hole 15 , the patterned mask layer 11 is removed. For example, the patterned mask layer 11 can be removed by selective etching, but the disclosure is not limited thereto.

參照圖4，其是根據本揭露的一些實施例，顯示在製造方法中的各階段的散熱基板的剖面示意圖。在一些實施例中，移除未被第一導電層13及第二導電層14遮蔽的導電層101。舉例而言，可對第一導電層13、第二導電層14及導電層101執行蝕刻製程，直到暴露未被第一導電層13及第二導電層14覆蓋的核心層100為止。在一些實施例中，在上述製程之後，被第一導電層13遮蔽的殘留導電層101可視為第一導電層13的一部份，且被第二導電層14遮蔽的殘留導電層101可視為第二導電層14的一部份。 Referring to FIG. 4 , it is a schematic cross-sectional view of the heat dissipation substrate at various stages in the manufacturing method according to some embodiments of the present disclosure. In some embodiments, the conductive layer 101 not covered by the first conductive layer 13 and the second conductive layer 14 is removed. For example, an etching process may be performed on the first conductive layer 13 , the second conductive layer 14 and the conductive layer 101 until the core layer 100 not covered by the first conductive layer 13 and the second conductive layer 14 is exposed. In some embodiments, after the above process, the residual conductive layer 101 covered by the first conductive layer 13 can be regarded as a part of the first conductive layer 13, and the residual conductive layer 101 covered by the second conductive layer 14 can be regarded as a part of the first conductive layer 13. A part of the second conductive layer 14 .

參照圖5，其是根據本揭露的一些實施例，顯示在製造方法中的各階段的散熱基板的剖面示意圖。在一些實施例中，移除核心層100的一部分，以形成用來放置電子元件的容置空間102。舉例而言，可藉由諸如鑽孔製程、蝕刻製程、其組合或其他合適的製程形成容置空間102，但本揭露不限於此。在一些實施例中，容置空間102位於彼此相對的兩個第一導電孔15之間，但本揭露不限於此。舉例而言，容置空間102可位於相鄰的兩個第一導電孔15之間。可替代地，容置空間102被多個第一導電孔15環繞。 Referring to FIG. 5 , it is a schematic cross-sectional view showing the heat dissipation substrate at various stages in the manufacturing method according to some embodiments of the present disclosure. In some embodiments, a portion of the core layer 100 is removed to form a receiving space 102 for placing electronic components. For example, the accommodating space 102 may be formed by a drilling process, an etching process, a combination thereof, or other suitable processes, but the disclosure is not limited thereto. In some embodiments, the accommodating space 102 is located between two first conductive holes 15 opposite to each other, but the disclosure is not limited thereto. For example, the accommodating space 102 can be located between two adjacent first conductive holes 15 . Alternatively, the accommodating space 102 is surrounded by a plurality of first conductive holes 15 .

參照圖6，在一些實施例中，設置承載基板16於核心層100的底表面100b上，以遮蔽容置空間102的底部。舉例而言，承載基板16可為或可包括膠帶(tape)、其他合適的載板材料或其組合，但本揭露不限於此。 Referring to FIG. 6 , in some embodiments, the carrier substrate 16 is disposed on the bottom surface 100 b of the core layer 100 to cover the bottom of the accommodating space 102 . For example, the carrier substrate 16 can be or include tape, other suitable carrier materials, or a combination thereof, but the disclosure is not limited thereto.

參照圖7，在一些實施例中，設置電子元件17於容置空間102中。具體而言，可藉由承載基板16將電子元件17安置於容置空間102中。在一些實施例中，電子元件17可為各種半導體晶片(chip)、微機電晶片或其類似物，但本揭露不限於此。在一些實施例中，承載基板16的頂表面16a與電子元件17的底表面17b齊平，從而使第二導電層14的頂表面14a與電子元件17的底表面17b齊平。 Referring to FIG. 7 , in some embodiments, an electronic component 17 is disposed in the accommodating space 102 . Specifically, the electronic components 17 can be mounted on the carrier substrate 16 placed in the accommodating space 102. In some embodiments, the electronic component 17 can be various semiconductor chips, micro-electro-mechanical chips or the like, but the disclosure is not limited thereto. In some embodiments, the top surface 16a of the carrier substrate 16 is flush with the bottom surface 17b of the electronic component 17 such that the top surface 14a of the second conductive layer 14 is flush with the bottom surface 17b of the electronic component 17 .

在一些實施例中，電子元件17的寬度W1小於容置空間102的寬度W2，以提高放置電子元件17的製程裕度。舉例而言，電子元件17的寬度W1可為0.1mm至20mm，且容置空間102的寬度W2可為0.1mm至20mm。在一些實施例中，寬度W1小於寬度W2，但本揭露不限於此。換言之，在寬度W1小於寬度W2的實施例中，當電子元件17放入容置空間102之後，容置空間102並未完全地(fully)被電子元件17填滿，而會留下一部分的容置空間102。在下文中，所留下的容置空間102可被稱為「氣室」(如圖8所示的氣室S)。 In some embodiments, the width W1 of the electronic component 17 is smaller than the width W2 of the accommodating space 102 to improve the process margin for placing the electronic component 17 . For example, the width W1 of the electronic component 17 may be 0.1 mm to 20 mm, and the width W2 of the accommodating space 102 may be 0.1 mm to 20 mm. In some embodiments, the width W1 is smaller than the width W2, but the disclosure is not limited thereto. In other words, in the embodiment where the width W1 is smaller than the width W2, when the electronic component 17 is put into the accommodating space 102, the accommodating space 102 is not completely (fully) filled by the electronic component 17, but a part of the accommodating space will be left. Setting space 102. Hereinafter, the remaining accommodating space 102 may be referred to as an "air chamber" (such as the air chamber S shown in FIG. 8 ).

值得一提的是，雖然圖7中的電子元件17是設置於容置空間102的中心，並與其兩側的核心層100彼此隔開，但本揭露不限於此。在一些實施例中，電子元件17可設置於容置空間102的一側，並與位於該側的核心層100直接接觸(例如，貼合)，而與位於另一側的核心層100彼此隔開。除此之外，雖然在圖7的平面中僅繪示了電子元件17與其兩側的核心層100彼此隔開，但本揭露不限於此。在其他實施例中，可使電子元件17與其周緣的所有核心層100彼此隔開，以更加提高製程裕度。 It should be noted that although the electronic component 17 in FIG. 7 is disposed at the center of the accommodating space 102 and separated from the core layers 100 on both sides thereof, the present disclosure is not limited thereto. In some embodiments, the electronic component 17 may be disposed on one side of the accommodating space 102, and be in direct contact with (for example, bonded to) the core layer 100 on the side, while being separated from the core layer 100 on the other side. open. In addition, although the electronic component 17 and the core layers 100 on both sides thereof are separated from each other in the plane of FIG. 7 , the present disclosure is not limited thereto. In other embodiments, the electronic component 17 and all the core layers 100 around it can be separated from each other, so as to further improve the process margin.

在一些實施例中，電子元件17的高度H1等於容置空間102的高度H2。舉例而言，電子元件17的高度H1可為0.04mm至5mm，且容置空間102的高度H2可為0.04mm至5mm，且高度H1等於高度H2，但本揭露不限於此。當高度H1等於高度H2時，第一導電層13的底表面13a與電子元件17的頂表面17a齊平。在一些實施例中，高度H1可小於高度H2。 In some embodiments, the height H1 of the electronic component 17 is equal to the height H2 of the accommodating space 102 . For example, the height H1 of the electronic component 17 may be 0.04 mm to 5 mm, and the height H2 of the accommodating space 102 may be 0.04 mm to 5 mm, and the height H1 is equal to the height H2, but the disclosure is not limited thereto. When the height H1 is equal to the height H2 , the bottom surface 13 a of the first conductive layer 13 is flush with the top surface 17 a of the electronic component 17 . In some embodiments, height H1 may be less than height H2.

參照圖8，在一些實施例中，設置增層結構18於核心層100上，以覆蓋核心層100的頂表面100a、第一導電層13以及電子元件17。舉例而言，可藉由增層製程將增層結構18層壓於核心層100上，但本揭露不限於此。在一些實施例中，增層結構18包括介電層180以及導電層181，且導電層181位於介電層180遠離核心層100的一側。在一些實施例中，介電層180的材料可相似或相同於核心層100的材料，但本揭露不限於此。在一些實施例中，導電層181的材料可相似或相同於導電層101的材料，但本揭露不限於此。 Referring to FIG. 8 , in some embodiments, a build-up structure 18 is disposed on the core layer 100 to cover the top surface 100 a of the core layer 100 , the first conductive layer 13 and the electronic components 17 . For example, the build-up structure 18 may be laminated on the core layer 100 through a build-up process, but the disclosure is not limited thereto. In some embodiments, the build-up structure 18 includes a dielectric layer 180 and a conductive layer 181 , and the conductive layer 181 is located on a side of the dielectric layer 180 away from the core layer 100 . In some embodiments, the material of the dielectric layer 180 may be similar or identical to the material of the core layer 100 , but the disclosure is not limited thereto. In some embodiments, the material of the conductive layer 181 may be similar or identical to the material of the conductive layer 101 , but the disclosure is not limited thereto.

在一些實施例中，將介電層180的一部份填充至氣室S中。舉例而言，可施加較高的壓力或溫度使介電層180在與核心層100的交界處形成流體或半流體，並使介電層180的一部份進入氣室S中，以提升固定效果。在這種情況下，氣室S的頂表面Sa與電子元件17的頂表面17a不齊平。值得一提的是，本揭露不限於此。在其他實施例中，氣室S的頂表面Sa可與電子元件17的頂表面17a齊平。 In some embodiments, a portion of the dielectric layer 180 is filled into the air space S. Referring to FIG. For example, higher pressure or temperature can be applied to make the dielectric layer 180 form a fluid or semi-fluid at the interface with the core layer 100, and make a part of the dielectric layer 180 enter the air chamber S to improve the fixation. Effect. In this case, the top surface Sa of the air chamber S is not flush with the top surface 17 a of the electronic component 17 . It is worth mentioning that this disclosure is not limited thereto. In other embodiments, the top surface Sa of the gas chamber S may be flush with the top surface 17 a of the electronic component 17 .

參照圖9，在一些實施例中，移除承載基板16，並設置增層結構19於核心層100上，以覆蓋核心層100的底表面100b、第二導電層14以及電子元件17。舉例而言，可藉由增層製程將增層結構19層壓於核心層100上，但本揭露不限於此。在一些實施例中，增層結構19包括介電層190以及導電層191，且導電層191位於介電層190遠離核心層100的一側。在一些實施例中，介電層190的材料可相似或相同於核心層100的材料，但本揭露不限於此。在一些實施例中，導電層191的材料可相似或相同於導電層101的材料，但本揭露不限於此。 Referring to FIG. 9 , in some embodiments, the carrier substrate 16 is removed, and a build-up structure 19 is disposed on the core layer 100 to cover the bottom surface 100 b of the core layer 100 , the second conductive layer 14 and the electronic components 17 . For example, the build-up structure 19 may be laminated on the core layer 100 through a build-up process, but the disclosure is not limited thereto. In some embodiments, the build-up structure 19 includes a dielectric layer 190 and a conductive layer 191 , and the conductive layer 191 is located on a side of the dielectric layer 190 away from the core layer 100 . In some embodiments, the material of the dielectric layer 190 may be similar or identical to the material of the core layer 100 , but the disclosure is not limited thereto. In some embodiments, the material of the conductive layer 191 may be similar or identical to the material of the conductive layer 101 , but the disclosure is not limited thereto.

在一些實施例中，將介電層190的一部份填充至氣室S中。舉例而言，可施加較高的壓力或溫度使介電層190在與核心層100的交界處形成流體或半流體，並使介電層190的一部份進入氣室S中，以提升固定效果。在這種情況下，氣室S的底表面Sb與電子元件17的底表面17b不齊平。值得一提的是，本揭露不限於此。在其他實施例中，氣室S的底表面Sb可與電子元件17的底表面17b齊平。 In some embodiments, a portion of the dielectric layer 190 is filled into the air space S. Referring to FIG. For example, higher pressure or temperature can be applied to make the dielectric layer 190 form a fluid or semi-fluid at the interface with the core layer 100, and make a part of the dielectric layer 190 enter the air chamber S to improve the fixation. Effect. In this case, the bottom surface Sb of the air chamber S is not flush with the bottom surface 17b of the electronic component 17 . It is worth mentioning that this disclosure is not limited thereto. In other embodiments, the bottom surface Sb of the gas chamber S may be flush with the bottom surface 17b of the electronic component 17 .

在一些實施例中，介電層180、核心層100與介電層190可共同稱為主體(如圖10所示的主體20)。在這種情況下，介電層180的頂表面可稱為主體的第一表面(如圖10所示的第一表面20a)。介電層190的底表面可稱為主體的第二表面(如圖10所示的第二表面20b)。其中，第一導電層13及第二導電層14設置於主體中。 In some embodiments, the dielectric layer 180 , the core layer 100 and the dielectric layer 190 may be collectively referred to as a body (such as the body 20 shown in FIG. 10 ). In this case, the top surface of the dielectric layer 180 may be referred to as the first surface of the body (the first surface 20a shown in FIG. 10). The bottom surface of the dielectric layer 190 may be referred to as the second surface of the body (the second surface 20b shown in FIG. 10). Wherein, the first conductive layer 13 and the second conductive layer 14 are disposed in the main body.

參照圖10，在一些實施例中，形成盲孔(blind via)21、盲孔22及盲孔23於主體20中，以分別暴露電子元件17上的接點、第一導電層13及第二導電層14。舉例而言，可藉由雷射鑽孔製程、機械鑽孔製程、其他合適的鑽孔製程或其組合形成盲孔21、盲孔22及盲孔23，但本揭露不限於此。在一些實施例中，可在同一道製程中形成盲孔21、盲孔22及盲孔23，但本揭露不限於此。 Referring to FIG. 10 , in some embodiments, a blind via 21, a blind via 22 and a blind via 23 are formed in the main body 20 to expose the contacts on the electronic component 17, the first conductive layer 13 and the second via respectively. Conductive layer 14. For example, the blind holes 21 , the blind holes 22 and the blind holes 23 may be formed by a laser drilling process, a mechanical drilling process, other suitable drilling processes or a combination thereof, but the disclosure is not limited thereto. In some embodiments, the blind holes 21 , the blind holes 22 and the blind holes 23 can be formed in the same process, but the disclosure is not limited thereto.

參照圖11，在一些實施例中，形成圖案化遮罩層24在導電層181及導電層191上。舉例而言，圖案化遮罩層24的材料可為或可包括光阻，但本揭露不限於此。在一些實施例中，圖案化遮罩層24暴露盲孔21、盲孔22、盲孔23、導電層181的一部分及導電層191的一部分。 Referring to FIG. 11 , in some embodiments, a patterned mask layer 24 is formed on the conductive layer 181 and the conductive layer 191 . For example, the material of the patterned mask layer 24 may be or include photoresist, but the disclosure is not limited thereto. In some embodiments, the patterned mask layer 24 exposes the blind holes 21 , the blind holes 22 , the blind holes 23 , a part of the conductive layer 181 and a part of the conductive layer 191 .

參照圖12，在一些實施例中，在圖案化遮罩層24所暴露區域填入導電材料，以在導電層181及導電層191上分別形成第三導電層25及第四導電層26，並於盲孔21、盲孔22及盲孔23中分別形成元件導電孔27、第二導電孔28及第三導電孔29。其中，第三導電層25與第四導電層26彼此相對，並設置於主體20上。第三導電層25藉由第二導電孔28與第一導電層13電性連接，且第四導電層26藉由第三導電孔29與第二導電層14電性連接。元件導電孔27設置於主體20中，並電性連接至電子元件17。 Referring to FIG. 12, in some embodiments, the exposed area of the patterned mask layer 24 is filled with a conductive material to form a third conductive layer 25 and a fourth conductive layer 26 on the conductive layer 181 and the conductive layer 191, respectively, and A component conductive hole 27 , a second conductive hole 28 and a third conductive hole 29 are respectively formed in the blind hole 21 , the blind hole 22 and the blind hole 23 . Wherein, the third conductive layer 25 and the fourth conductive layer 26 are opposite to each other and disposed on the main body 20 . The third conductive layer 25 is electrically connected to the first conductive layer 13 through the second conductive hole 28 , and the fourth conductive layer 26 is electrically connected to the second conductive layer 14 through the third conductive hole 29 . The component conductive hole 27 is disposed in the main body 20 and electrically connected to the electronic component 17 .

舉例而言，可藉由電鍍製程設置導電材料於導電層181、導電層191上及盲孔21、盲孔22及盲孔23中，但本揭露不限於此。在一些實施例中，上述的導電材料可相似或相同於導電層101的材料，但本揭露不限於此。在一些實施例中，第三導電層25及第四導電層26可為導電線路或導電圖案，但本揭露不限於此。在形成第三導電層25、第四導電層26、元件導電孔27、第二導電孔28及第三導電孔29之後，移除圖案化遮罩層24。 For example, the conductive material can be disposed on the conductive layer 181, the conductive layer 191 and in the blind holes 21, 22 and 23 through an electroplating process, but this disclosure does not limited to this. In some embodiments, the aforementioned conductive material may be similar or identical to the material of the conductive layer 101 , but the disclosure is not limited thereto. In some embodiments, the third conductive layer 25 and the fourth conductive layer 26 can be conductive lines or conductive patterns, but the disclosure is not limited thereto. After forming the third conductive layer 25 , the fourth conductive layer 26 , the device conductive hole 27 , the second conductive hole 28 and the third conductive hole 29 , the patterned mask layer 24 is removed.

參照圖13，在一些實施例中，移除未被元件導電孔27、第三導電層25及第四導電層26遮蔽的導電層181及導電層191。舉例而言，對第三導電層25、第四導電層26、導電層181及導電層191執行蝕刻製程，直到暴露未被第三導電層25遮蔽的介電層180及未被第四導電層26遮蔽的介電層190為止。在一些實施例中，在上述製程之後，被元件導電孔27遮蔽殘留導電層181可視為元件導電孔27的一部份，被第三導電層25遮蔽的殘留導電層181可視為第三導電層25的一部份，且被第四導電層26遮蔽的殘留導電層191可視為第四導電層26的一部份。因此，第三導電層25的底表面25a與主體20的第一表面20a齊平，且第四導電層26的頂表面25a與主體20的第二表面20b齊平。 Referring to FIG. 13 , in some embodiments, the conductive layer 181 and the conductive layer 191 that are not covered by the device conductive hole 27 , the third conductive layer 25 and the fourth conductive layer 26 are removed. For example, an etching process is performed on the third conductive layer 25, the fourth conductive layer 26, the conductive layer 181, and the conductive layer 191 until the dielectric layer 180 not covered by the third conductive layer 25 and the dielectric layer not covered by the fourth conductive layer are exposed. 26 masked dielectric layer 190 so far. In some embodiments, after the above process, the residual conductive layer 181 covered by the element conductive hole 27 can be regarded as a part of the element conductive hole 27, and the residual conductive layer 181 covered by the third conductive layer 25 can be regarded as the third conductive layer. 25 , and the residual conductive layer 191 covered by the fourth conductive layer 26 can be regarded as a part of the fourth conductive layer 26 . Therefore, the bottom surface 25 a of the third conductive layer 25 is flush with the first surface 20 a of the body 20 , and the top surface 25 a of the fourth conductive layer 26 is flush with the second surface 20 b of the body 20 .

參照圖14，在一些實施例中，設置保護層30於主體20的第一表面20a及第二表面20b上。其中，保護層30不遮蔽元件導電孔27、第三導電層25及第四導電層26。易言之，元件導電孔27貫穿設置於第一表面20a上的保護層30。在一些實施例中，可藉由浸塗(dip coating)、滾塗(roller coating)、簾塗(curtain coating)、噴塗(spraying)、印刷(screen printing)、其他合適的製程或其組合設置保護層30，但本揭露不限於此。在一些實施例中，保護層30的材料可為或可包括樹脂或其他合適的材料，但本揭露不限於此。舉例而言，保護層30可為防焊油墨。 Referring to FIG. 14 , in some embodiments, a protection layer 30 is disposed on the first surface 20 a and the second surface 20 b of the main body 20 . Wherein, the protective layer 30 does not cover the element conductive hole 27 , the third conductive layer 25 and the fourth conductive layer 26 . In other words, the component conductive hole 27 penetrates the protection layer 30 disposed on the first surface 20 a. In some embodiments, dip coating, roller coating, curtain coating, spraying, screen printing, etc. Other suitable processes or combinations thereof are used to dispose the passivation layer 30 , but the disclosure is not limited thereto. In some embodiments, the material of the protective layer 30 may be or include resin or other suitable materials, but the disclosure is not limited thereto. For example, the protective layer 30 can be solder resist ink.

在一些實施例中，第三導電層25的底表面25a與設置於第一表面20a上的保護層30的底表面30a齊平，且第四導電層26的頂表面26a與設置於第二表面20b上的保護層30的頂表面30b齊平。 In some embodiments, the bottom surface 25a of the third conductive layer 25 is flush with the bottom surface 30a of the protective layer 30 disposed on the first surface 20a, and the top surface 26a of the fourth conductive layer 26 is flush with the bottom surface 30a disposed on the second surface. The top surface 30b of the protective layer 30 on 20b is flush.

參照圖15，在一些實施例中，形成導流孔31於主體20中，以獲得散熱基板1a。其中，導流孔31貫穿主體20的第一表面20a及第二表面20b，且貫穿設置於主體20的第一表面20a及第二表面20b上的保護層30。具體而言，導流孔31與容置空間102流體連通，並暴露電子元件17的複數個側表面中的一個(例如，側表面17c)。舉例而言，可藉由雷射鑽孔製程、機械鑽孔製程、其他合適的鑽孔製程或其組合形成導流孔31，但本揭露不限於此。在一些實施例中，可使導流孔31貫穿氣室S的全部或一部分。 Referring to FIG. 15 , in some embodiments, a flow guide hole 31 is formed in the main body 20 to obtain a heat dissipation substrate 1a. Wherein, the guide hole 31 penetrates the first surface 20 a and the second surface 20 b of the main body 20 , and penetrates the protective layer 30 disposed on the first surface 20 a and the second surface 20 b of the main body 20 . Specifically, the guide hole 31 is in fluid communication with the accommodating space 102 and exposes one of the plurality of side surfaces (eg, the side surface 17 c ) of the electronic component 17 . For example, the guide hole 31 may be formed by a laser drilling process, a mechanical drilling process, other suitable drilling processes or a combination thereof, but the disclosure is not limited thereto. In some embodiments, the flow guide hole 31 can penetrate all or part of the air chamber S. As shown in FIG.

在一些實施例中，導流孔31與電子元件17的側表面17c之間相距一距離d1。在一些實施例中，距離d1可為0。換言之，導流孔31可緊靠電子元件17的側表面17c設置。在一些實施例中，距離d1可為0.02mm至0.2mm，但本揭露不限於此。藉由使距離d1大於0，可提高製程裕度，以避免在鑽孔製程中破壞到電子元件17。在一些情況下，當距離d1小於0.02mm時，導流孔31的形成過程可能會破壞到電子元件17。反之，當距離d1大於0.2mm時，導流孔31可能會離電子元件17過遠，從而降低散熱效果(下文中會詳細解釋)，甚至無法貫穿氣室S以使電子元件17暴露於空氣中。 In some embodiments, there is a distance d1 between the guide hole 31 and the side surface 17 c of the electronic component 17 . In some embodiments, distance d1 may be zero. In other words, the guide hole 31 can be disposed close to the side surface 17 c of the electronic component 17 . In some embodiments, the distance d1 may be 0.02 mm to 0.2 mm, but the present disclosure is not limited thereto. By making the distance d1 greater than 0, the process margin can be improved to avoid damage to the electronic device 17 during the drilling process. In some cases, when the distance d1 is less than 0.02 mm, the forming process of the guide hole 31 may damage the electronic component 17 . Conversely, when the distance d1 is large When it is 0.2 mm, the air guide hole 31 may be too far away from the electronic component 17, thereby reducing the heat dissipation effect (explained in detail below), and even cannot penetrate the air chamber S to expose the electronic component 17 to the air.

在一些實施例中，導流孔31的寬度W3可為0.04mm至1mm，但本揭露不限於此。在一些情況下，當寬度W3小於0.04mm時，導流孔31因過於窄小而不利於空氣流動，從而降低散熱效果。反之，當寬度W3大於1mm時，散熱基板1a的強度可能不足。 In some embodiments, the width W3 of the guide hole 31 may be 0.04 mm to 1 mm, but the disclosure is not limited thereto. In some cases, when the width W3 is less than 0.04 mm, the air guide hole 31 is too narrow to facilitate air flow, thereby reducing the heat dissipation effect. On the contrary, when the width W3 is larger than 1 mm, the strength of the heat dissipation substrate 1a may be insufficient.

參照圖16，其是根據本揭露的一些實施例，顯示導流孔的上視圖。具體而言，圖16的(A)至(F)分別為不同態樣的導流孔的上視圖。如(A)所示，在一些實施例中，導流孔31可設置於電子元件17的相對兩側。然而，本揭露不限於此，導流孔31的數量及位置可對應於氣室S的數量及位置。如(B)所示，在一些實施例中，導流孔31可設置於電子元件17的相鄰兩側。如(C)所示，在一些實施例中，當電子元件17的三個側表面旁均有氣室S時，導流孔31可對應設置於電子元件17的三個側表面，以使多個氣室S與外界流體連通。值得一提的是，導流孔31被配置為非封閉地環繞電子元件17的側表面，以避免電子元件17與周緣的主體20之間的連接強度不足。 Referring to FIG. 16 , it is a top view showing a flow guide hole according to some embodiments of the present disclosure. Specifically, (A) to (F) of FIG. 16 are top views of diversion holes in different forms. As shown in (A), in some embodiments, the guide holes 31 can be disposed on opposite sides of the electronic component 17 . However, the present disclosure is not limited thereto, and the number and positions of the flow guide holes 31 may correspond to the number and positions of the air chambers S. As shown in FIG. As shown in (B), in some embodiments, the guide holes 31 can be disposed on adjacent two sides of the electronic component 17 . As shown in (C), in some embodiments, when there are air chambers S beside the three side surfaces of the electronic component 17, the guide holes 31 can be correspondingly arranged on the three side surfaces of the electronic component 17, so that more Each chamber S is in fluid communication with the outside world. It is worth mentioning that the guide hole 31 is configured to surround the side surface of the electronic component 17 in a non-closed manner, so as to avoid insufficient connection strength between the electronic component 17 and the peripheral body 20 .

在一些實施例中，導流孔31在第一表面20a及/或第二表面20b的截面形狀可為圓弧形或具有圓弧角的長條形(如(A)至(C)所示)，但本揭露不限於此。如(D)或(E)所示，在一些實施例中，導流孔31在第一表面20a及/或第二表面20b的截面形狀可為一或多個圓形，且可以設置於電子元件17的任意一側或非封閉地環繞電子元件17。如(F)所示，導流孔31亦可用圓形、具有圓弧角的長條形、多邊形及其組合的方式設置。 In some embodiments, the cross-sectional shape of the diversion hole 31 on the first surface 20a and/or the second surface 20b may be arc-shaped or elongated with arc angles (as shown in (A) to (C) ), but the disclosure is not limited thereto. As shown in (D) or (E), in some embodiments Among them, the cross-sectional shape of the guide hole 31 on the first surface 20 a and/or the second surface 20 b may be one or more circles, and may be disposed on any side of the electronic component 17 or surround the electronic component 17 non-closed. As shown in (F), the diversion hole 31 can also be provided in a circular shape, a strip shape with arc angles, a polygonal shape and a combination thereof.

在一些實施例中，在第一表面20a及/或第二表面20b上，導流孔31在第一表面20a及/或第二表面20b的截面積可大於或等於元件導電孔27的截面積，但本揭露不限於此。 In some embodiments, on the first surface 20a and/or the second surface 20b, the cross-sectional area of the guide hole 31 on the first surface 20a and/or the second surface 20b may be greater than or equal to the cross-sectional area of the element conductive hole 27 , but the disclosure is not limited thereto.

在使用過程中，電子元件17可能會產生高熱，從而加熱周緣的主體20或是容置空間102(例如，氣室S)中的空氣。因此，藉由設置導流孔31在電子元件17的周緣，可使電子元件17旁的空氣產生諸如煙囪效應(stack effect)或負壓效應(negative pressure)的氣流流動，從而實現快速散熱的有利功效。在一些情況下，也可避免容置空間102中的氣體受熱膨脹，導致主體20因內部壓力升高而破裂。 During use, the electronic components 17 may generate high heat, thereby heating the peripheral body 20 or the air in the receiving space 102 (eg, the air chamber S). Therefore, by arranging the guide hole 31 on the periphery of the electronic component 17, the air beside the electronic component 17 can be generated such as the air flow of the chimney effect (stack effect) or negative pressure effect (negative pressure), thereby realizing the advantage of rapid heat dissipation effect. In some cases, it is also possible to prevent the gas in the accommodation space 102 from expanding due to heat, causing the main body 20 to rupture due to increased internal pressure.

雖然在上文中已提供具有導流孔的散熱基板的一種實施態樣，但本揭露不限於此。在下文中，將提供具有導流孔的散熱基板的另一種實施態樣作為參考。 Although an implementation of the heat dissipation substrate with the conduction holes has been provided above, the present disclosure is not limited thereto. Hereinafter, another implementation of the heat dissipation substrate with the air guide holes will be provided as a reference.

參照圖17-29，其是根據本揭露的另一些實施例，顯示散熱基板在各製造階段的剖面示意圖。其中，圖17係承接圖4之後續步驟，之前的所有步驟皆可參照圖1至圖4所述，因此不再加以贅述。此外，與前述步驟類似之步驟亦不再多加贅述。本實施例與前述實施例的主要差別在於，本實施例的散熱基板是先執行增層製程，再形成容置空間，以具有更多層的導電圖案或導電線路，從而應用在不同的電子裝置中。接續圖4，設置增層結構18及增層結構19於核心層100的兩側上，以覆蓋核心層100的頂表面100a、底表面100b、第一導電層13及第二導電層14。其中，增層結構18包括介電層180及導電層181，且增層結構19包括介電層190及導電層191。 Referring to FIGS. 17-29 , which are schematic cross-sectional views showing various manufacturing stages of the heat dissipation substrate according to other embodiments of the present disclosure. Wherein, FIG. 17 is a follow-up step of FIG. 4 , and all previous steps can be described with reference to FIG. 1 to FIG. 4 , so details are not repeated here. In addition, steps similar to the aforementioned steps will not be repeated here. The main difference between this embodiment and the previous embodiments is that the heat dissipation substrate of this embodiment is first implemented Layer manufacturing process, and then form accommodating space to have more layers of conductive patterns or conductive lines, so as to be applied in different electronic devices. Following FIG. 4 , build-up structures 18 and build-up structures 19 are disposed on both sides of the core layer 100 to cover the top surface 100 a , bottom surface 100 b , first conductive layer 13 and second conductive layer 14 of the core layer 100 . Wherein, the build-up structure 18 includes a dielectric layer 180 and a conductive layer 181 , and the build-up structure 19 includes a dielectric layer 190 and a conductive layer 191 .

參照圖18，在一些實施例中，形成盲孔22及盲孔23於介電層180及介電層190中，以分別暴露第一導電層13及第二導電層14。接著，形成圖案化遮罩層32在導電層181上。舉例而言，圖案化遮罩層32的材料可為或可包括光阻，但本揭露不限於此。在一些實施例中，圖案化遮罩層32暴露盲孔22、盲孔23、導電層181及導電層191。可替代地，先執行微影製程，再形成盲孔22及盲孔23。 Referring to FIG. 18 , in some embodiments, a blind hole 22 and a blind hole 23 are formed in the dielectric layer 180 and the dielectric layer 190 to expose the first conductive layer 13 and the second conductive layer 14 respectively. Next, a patterned mask layer 32 is formed on the conductive layer 181 . For example, the material of the patterned mask layer 32 may be or include photoresist, but the disclosure is not limited thereto. In some embodiments, the patterned mask layer 32 exposes the blind holes 22 , the blind holes 23 , the conductive layer 181 and the conductive layer 191 . Alternatively, the lithography process is performed first, and then the blind holes 22 and 23 are formed.

參照圖19，在一些實施例中，在圖案化遮罩層32所暴露區域填有導電材料，以在導電層181及導電層191上分別形成第三導電層25及第四導電層26，並於盲孔22及盲孔23中分別形成第二導電孔28及第三導電孔29。 Referring to FIG. 19, in some embodiments, the exposed area of the patterned mask layer 32 is filled with a conductive material to form a third conductive layer 25 and a fourth conductive layer 26 on the conductive layer 181 and the conductive layer 191, respectively, and A second conductive hole 28 and a third conductive hole 29 are respectively formed in the blind hole 22 and the blind hole 23 .

參照圖20，在一些實施例中，移除未被第三導電層25及第四導電層26遮蔽的導電層181及導電層191。舉例而言，對第三導電層25、第四導電層26、導電層181及導電層191執行蝕刻製程，直到暴露未被第三導電層25遮蔽的介電層180及未被第四導電層26遮蔽的介電層190為止。在一些實施例中，在上述製程之後，被第三導電層25遮蔽殘留導電層181可視為第三導電層25的一部份，且被第四導電層26遮蔽的殘留導電層191可視為第四導電層26的一部份。 Referring to FIG. 20 , in some embodiments, the conductive layer 181 and the conductive layer 191 not shielded by the third conductive layer 25 and the fourth conductive layer 26 are removed. For example, an etching process is performed on the third conductive layer 25, the fourth conductive layer 26, the conductive layer 181, and the conductive layer 191 until the dielectric layer 180 not covered by the third conductive layer 25 and the dielectric layer not covered by the fourth conductive layer are exposed. 26 masked dielectric layer 190 so far. In some embodiments, in the above After the process, the residual conductive layer 181 masked by the third conductive layer 25 can be regarded as a part of the third conductive layer 25, and the residual conductive layer 191 covered by the fourth conductive layer 26 can be regarded as a part of the fourth conductive layer 26 .

參照第21圖，在一些實施例中，移除核心層100及介電層180的一部分，以形成容置空間103。舉例而言，可藉由諸如鑽孔製程、蝕刻製程、其組合或其他合適的製程形成容置空間103，但本揭露不限於此。 Referring to FIG. 21 , in some embodiments, a portion of the core layer 100 and the dielectric layer 180 are removed to form the accommodating space 103 . For example, the accommodating space 103 can be formed by a drilling process, an etching process, a combination thereof, or other suitable processes, but the disclosure is not limited thereto.

參照第22圖，在一些實施例中，設置電子元件17於容置空間103中。在一些實施例中，電子元件17的寬度W1小於容置空間103的寬度W4，以提高放置電子元件17的製程裕度。舉例而言，電子元件17的寬度W1可為0.1mm至20mm，且容置空間103的寬度W4可為0.1mm至20mm。在一些實施例中，寬度W1小於寬度W4，但本揭露不限於此。換言之，在寬度W1小於寬度W4的實施例中，當電子元件17放入容置空間103之後，容置空間103並未完全地被電子元件17填滿，而會留下一部分的空間。 Referring to FIG. 22 , in some embodiments, electronic components 17 are disposed in the accommodating space 103 . In some embodiments, the width W1 of the electronic component 17 is smaller than the width W4 of the accommodating space 103 to improve the process margin for placing the electronic component 17 . For example, the width W1 of the electronic component 17 may be 0.1 mm to 20 mm, and the width W4 of the accommodating space 103 may be 0.1 mm to 20 mm. In some embodiments, the width W1 is smaller than the width W4, but the disclosure is not limited thereto. In other words, in the embodiment where the width W1 is smaller than the width W4 , when the electronic component 17 is put into the accommodating space 103 , the accommodating space 103 is not completely filled by the electronic component 17 , but a part of the space remains.

在一些實施例中，電子元件17的高度H1小於容置空間103的高度H3。舉例而言，電子元件17的高度H1可為0.04mm至5mm，且容置空間103的高度H3可為0.04mm至5mm，且高度H1小於高度H3，但本揭露不限於此。在一些實施例中，高度H1可等於高度H3 In some embodiments, the height H1 of the electronic component 17 is smaller than the height H3 of the accommodating space 103 . For example, the height H1 of the electronic component 17 may be 0.04 mm to 5 mm, and the height H3 of the accommodating space 103 may be 0.04 mm to 5 mm, and the height H1 is smaller than the height H3, but the disclosure is not limited thereto. In some embodiments, height H1 may be equal to height H3

參照第23圖，在一些實施例中，設置增層結構33及增層結構34於介電層180及介電層190上，以覆蓋介電層180的頂表面、介電層190的底表面、第三導電層25及第四導電層26，並遮蔽容置空間103的頂部。舉例而言，可藉由增層製程將增層結構33及增層結構34層壓於介電層180及介電層190上。其中，增層結構33包括介電層330及導電層331，且增層結構34包括介電層340及導電層341。在一些實施例中，介電層330及介電層340的材料可相似或相同於核心層100的材料，但本揭露不限於此。在一些實施例中，導電層331及導電層341的材料可相似或相同於導電層101的材料，但本揭露不限於此。 Referring to FIG. 23, in some embodiments, the build-up structure 33 and the build-up structure 34 are disposed on the dielectric layer 180 and the dielectric layer 190 to cover the top surface of the dielectric layer 180 and the bottom surface of the dielectric layer 190. , the third conductive layer 25 and the fourth conductive layer 26 , and cover the top of the accommodating space 103 . For example, the build-up structure 33 and the build-up structure 34 can be laminated on the dielectric layer 180 and the dielectric layer 190 through a build-up process. Wherein, the build-up structure 33 includes a dielectric layer 330 and a conductive layer 331 , and the build-up structure 34 includes a dielectric layer 340 and a conductive layer 341 . In some embodiments, the materials of the dielectric layer 330 and the dielectric layer 340 may be similar or identical to the material of the core layer 100 , but the disclosure is not limited thereto. In some embodiments, the materials of the conductive layer 331 and the conductive layer 341 may be similar or identical to the material of the conductive layer 101 , but the disclosure is not limited thereto.

在一些實施例中，將介電層330的一部份填充至氣室S中。舉例而言，可施加較高的壓力或溫度使介電層330在與介電層330的交界處形成流體或是半流體，並使介電層330的一部份進入氣室S中，以提升固定效果。在這種情況下，氣室S的頂表面Sa與電子元件17的頂表面17a不齊平。值得一提的是，本揭露不限於此。在其他實施例中，氣室S的頂表面Sa可與電子元件17的頂表面17a齊平。另一方面，由於介電層340與氣室S之間隔著介電層190，因此介電層340不會填充至氣室S中。換言之，氣室S的底表面Sb與電子元件17的底表面17b齊平。 In some embodiments, a portion of the dielectric layer 330 is filled into the air space S. Referring to FIG. For example, higher pressure or temperature can be applied to make the dielectric layer 330 form a fluid or semi-fluid at the junction with the dielectric layer 330, and make a part of the dielectric layer 330 enter the air chamber S, so as to Improve the fixed effect. In this case, the top surface Sa of the air chamber S is not flush with the top surface 17 a of the electronic component 17 . It is worth mentioning that this disclosure is not limited thereto. In other embodiments, the top surface Sa of the gas chamber S may be flush with the top surface 17 a of the electronic component 17 . On the other hand, since the dielectric layer 190 is interposed between the dielectric layer 340 and the gas chamber S, the dielectric layer 340 will not be filled into the gas chamber S. Referring to FIG. In other words, the bottom surface Sb of the air chamber S is flush with the bottom surface 17b of the electronic component 17 .

在一些實施例中，介電層330、介電層180、核心層100、介電層190與介電層340可共同稱為主體(如圖24所示的主體35)。在這種情況下，介電層330的頂表面可稱為主體的第一表面(如圖24所示的第一表面35a)。介電層340的底表面可稱為主體的第二表面(如圖24所示的第二表面35b)。其中，第一導電層13、第二導電層14、第三導電層25及第四導電層26設置於主體中。 In some embodiments, the dielectric layer 330 , the dielectric layer 180 , the core layer 100 , the dielectric layer 190 and the dielectric layer 340 may be collectively referred to as a body (such as the body 35 shown in FIG. 24 ). In this case, the top surface of the dielectric layer 330 may be referred to as the first surface (the first surface 35a shown in FIG. 24). The bottom surface of the dielectric layer 340 may be referred to as the second surface of the body (the second surface 35b shown in FIG. 24). Wherein, the first conductive layer 13 , the second conductive layer 14 , the third conductive layer 25 and the fourth conductive layer 26 are disposed in the main body.

參照圖24，在一些實施例中，形成盲孔36、盲孔37及盲孔38於主體35中，以分別暴露電子元件17、第三導電層25及第四導電層26。舉例而言，可藉由雷射鑽孔製程、機械鑽孔製程、其他合適的鑽孔製程或其組合形成盲孔36、盲孔37及盲孔38，但本揭露不限於此。在一些實施例中，可在同一道製程中形成盲孔36、盲孔37及盲孔38，但本揭露不限於此。 Referring to FIG. 24 , in some embodiments, a blind hole 36 , a blind hole 37 and a blind hole 38 are formed in the main body 35 to expose the electronic component 17 , the third conductive layer 25 and the fourth conductive layer 26 respectively. For example, the blind holes 36 , 37 and 38 may be formed by a laser drilling process, a mechanical drilling process, other suitable drilling processes or a combination thereof, but the disclosure is not limited thereto. In some embodiments, the blind hole 36 , the blind hole 37 and the blind hole 38 can be formed in the same process, but the disclosure is not limited thereto.

參照圖25，在一些實施例中，形成圖案化遮罩層39在導電層331及導電層341上。舉例而言，圖案化遮罩層39的材料可為或可包括光阻，但本揭露不限於此。在一些實施例中，圖案化遮罩層24暴露盲孔36、盲孔37、盲孔38、導電層331的一部分及導電層341的一部分。 Referring to FIG. 25 , in some embodiments, a patterned mask layer 39 is formed on the conductive layer 331 and the conductive layer 341 . For example, the material of the patterned mask layer 39 may be or include photoresist, but the disclosure is not limited thereto. In some embodiments, the patterned mask layer 24 exposes the blind holes 36 , the blind holes 37 , the blind holes 38 , a portion of the conductive layer 331 and a portion of the conductive layer 341 .

參照圖26，在一些實施例中，在圖案化遮罩層39所暴露區域填入導電材料，以在導電層331及導電層341分別形成第五導電層40及第六導電層41，並於盲孔36、盲孔37及盲孔38中分別形成元件導電孔42、第三導電孔43及第四導電孔44。其中，第五導電層40及第六導電層41彼此相對，並設置於主體35上。第五導電層40藉由第三導電孔43與第三導電層25電性連接，且第六導電層41藉由第四導電孔44與第四導電層26電性連接。舉例而言，可藉由電鍍製程設置導電材料於導電層331、導電層341上及盲孔36、盲孔37及盲孔38中，但本揭露不限於此。在一些實施例中，所述的導電材料可相似或相同於導電層101的材料，但本揭露不限於此。在一些實施例中，第五導電層40及第六導電層41可為導電線路或導電圖案，但本揭露不限於此。在形成第五導電層40、第六導電層41、元件導電孔42、第三導電孔43及第四導電孔44之後，移除圖案化遮罩層39。 Referring to FIG. 26 , in some embodiments, the exposed area of the patterned mask layer 39 is filled with conductive material to form the fifth conductive layer 40 and the sixth conductive layer 41 on the conductive layer 331 and the conductive layer 341 respectively, and then The component conductive hole 42 , the third conductive hole 43 and the fourth conductive hole 44 are respectively formed in the blind hole 36 , the blind hole 37 and the blind hole 38 . Wherein, the fifth conductive layer 40 and the sixth conductive layer 41 are opposite to each other and disposed on the main body 35 . The fifth conductive layer 40 is electrically connected to the third conductive layer 25 through the third conductive hole 43 , and the sixth conductive layer 41 is electrically connected to the fourth conductive layer 26 through the fourth conductive hole 44 . For example, the conductive material can be disposed on the conductive layer 331 , on the conductive layer 341 and in the blind holes 36 , 37 and 38 through an electroplating process, but the disclosure is not limited thereto. In some embodiments, the conductive material may be similar or identical to the material of the conductive layer 101 , but the disclosure is not limited thereto. In some embodiments, the fifth conductive layer 40 and the sixth conductive layer 41 may be conductive lines or conductive patterns, but the disclosure is not limited thereto. After forming the fifth conductive layer 40 , the sixth conductive layer 41 , the component conductive holes 42 , the third conductive holes 43 and the fourth conductive holes 44 , the patterned mask layer 39 is removed.

參照圖27，在一些實施例中，移除未被元件導電孔42、第五導電層40及第六導電層41遮蔽的導電層331及導電層341。舉例而言，對元件導電孔42、第五導電層40、第六導電層41、導電層331及導電層341執行蝕刻製程，直到暴露未被元件導電孔42遮蔽的介電層330、未被第五導電層40遮蔽的介電層330及未被第六導電層41遮蔽的介電層340為止。在一些實施例中，被元件導電孔42遮蔽的殘留導電層331可視為元件導電孔42的一部份，被第五導電層40遮蔽的殘留導電層331可視為第五導電層40的一部份，且被第六導電層41遮蔽的殘留導電層341可視為第六導電層41的一部份。因此，第五導電層40的底表面40a與主體35的第一表面35a齊平，且第六導電層41的頂表面41a與主體35的第二表面35b齊平。 Referring to FIG. 27 , in some embodiments, the conductive layer 331 and the conductive layer 341 that are not covered by the device conductive hole 42 , the fifth conductive layer 40 and the sixth conductive layer 41 are removed. For example, an etching process is performed on the element conductive hole 42, the fifth conductive layer 40, the sixth conductive layer 41, the conductive layer 331, and the conductive layer 341 until the dielectric layer 330 not covered by the element conductive hole 42 is exposed, The dielectric layer 330 covered by the fifth conductive layer 40 and the dielectric layer 340 not covered by the sixth conductive layer 41 end. In some embodiments, the residual conductive layer 331 covered by the component conductive hole 42 can be regarded as a part of the component conductive hole 42, and the residual conductive layer 331 covered by the fifth conductive layer 40 can be regarded as a part of the fifth conductive layer 40. part, and the remaining conductive layer 341 covered by the sixth conductive layer 41 can be regarded as a part of the sixth conductive layer 41 . Therefore, the bottom surface 40 a of the fifth conductive layer 40 is flush with the first surface 35 a of the body 35 , and the top surface 41 a of the sixth conductive layer 41 is flush with the second surface 35 b of the body 35 .

參照圖28，在一些實施例中，設置保護層30於主體35的第一表面35a及第二表面35b上。其中，保護層30不遮蔽元件導電孔42、第五導電層40及第六導電層41。易言之，元件導電孔42貫穿設置於第一表面35a上的保護層30。在一些實施例中，第五導電層40的底表面40a與設置於第一表面35a上的保護層30的底表面30a齊平，且第六導電層41的頂表面41a與設置於第二表面35b上的保護層30的頂表面30b齊平。 Referring to FIG. 28 , in some embodiments, the protection layer 30 is disposed on the first surface 35 a and the second surface 35 b of the main body 35 . Wherein, the passivation layer 30 does not cover the element conductive hole 42 , the fifth conductive layer 40 and the sixth conductive layer 41 . In other words, components The conductive hole 42 penetrates through the protection layer 30 disposed on the first surface 35a. In some embodiments, the bottom surface 40a of the fifth conductive layer 40 is flush with the bottom surface 30a of the protection layer 30 disposed on the first surface 35a, and the top surface 41a of the sixth conductive layer 41 is flush with the bottom surface 30a disposed on the second surface. The top surface 30b of the protective layer 30 is flush with the top surface 35b.

參照圖29，在一些實施例中，形成導流孔45於主體35中，以獲得散熱基板1b。其中，導流孔45貫穿主體35的第一表面35a及第二表面35b，且貫穿設置於主體35的第一表面35a及第二表面35b上的保護層30。具體而言，導流孔45與容置空間103流體連通，並暴露電子元件17的複數個側表面中的一個(例如，側表面17c)。舉例而言，可藉由雷射鑽孔製程、機械鑽孔製程、其他合適的鑽孔製程或其組合形成導流孔45，但本揭露不限於此。在一些實施例中，可使導流孔45貫穿氣室S的全部或一部分。 Referring to FIG. 29 , in some embodiments, a flow guide hole 45 is formed in the main body 35 to obtain a heat dissipation substrate 1 b. Wherein, the guide hole 45 penetrates the first surface 35 a and the second surface 35 b of the main body 35 , and penetrates the protective layer 30 disposed on the first surface 35 a and the second surface 35 b of the main body 35 . Specifically, the guide hole 45 is in fluid communication with the accommodating space 103 and exposes one of the plurality of side surfaces (eg, the side surface 17c ) of the electronic component 17 . For example, the guide hole 45 may be formed by a laser drilling process, a mechanical drilling process, other suitable drilling processes or a combination thereof, but the disclosure is not limited thereto. In some embodiments, the air guide hole 45 may pass through all or a part of the air chamber S. As shown in FIG.

在一些實施例中，導流孔45與電子元件17的側表面17c之間相距一距離d2。在一些實施例中，距離d2可為0。換言之，導流孔45可緊靠電子元件17的側表面17c設置。在一些實施例中，距離d2可為0.02mm至0.2mm，但本揭露不限於此。藉由使距離d2大於0，可提高製程裕度。在一些情況下，當距離d2小於0.02mm時，導流孔45的形成過程可能會破壞到電子元件17。反之，當距離d2大於0.2mm時，導流孔45可能會離電子元件17過遠，從而降低散熱效果。 In some embodiments, there is a distance d2 between the guide hole 45 and the side surface 17 c of the electronic component 17 . In some embodiments, distance d2 may be zero. In other words, the guide hole 45 can be disposed close to the side surface 17 c of the electronic component 17 . In some embodiments, the distance d2 may be 0.02 mm to 0.2 mm, but the present disclosure is not limited thereto. By making the distance d2 greater than 0, the process margin can be improved. In some cases, when the distance d2 is less than 0.02 mm, the forming process of the guide hole 45 may damage the electronic component 17 . On the contrary, when the distance d2 is greater than 0.2 mm, the guide hole 45 may be too far away from the electronic component 17, thereby reducing the heat dissipation effect.

在一些實施例中，導流孔45的寬度W5可為0.04mm至1mm，但本揭露不限於此。在一些情況下，當寬度W5小於0.04mm時，導流孔45因過於窄小而不利於空氣流動，從而降低散熱效果。反之，當寬度W5大於1mm時，散熱基板1b的強度可能不足。在一些實施例中，導流孔45的形狀、數量及設置位置可以相似或相同於導流孔31，於此不再贅述。 In some embodiments, the width W5 of the guide hole 45 may be 0.04 mm to 1 mm, but the disclosure is not limited thereto. In some cases, when the width W5 is small When the thickness is 0.04mm, the air guide hole 45 is too narrow to be conducive to air flow, thereby reducing the heat dissipation effect. On the contrary, when the width W5 is larger than 1 mm, the strength of the heat dissipation substrate 1b may be insufficient. In some embodiments, the shape, quantity and location of the diversion holes 45 may be similar or identical to those of the diversion holes 31 , which will not be repeated here.

綜上所述，根據本揭露的實施例，提供一種具有導流孔的散熱基板，其中導流孔暴露電子元件的一部分。如此一來，便可藉由空氣流動快速地排除電子元件所產生之熱量，從而提升整個散熱基板的散熱能力。 To sum up, according to the embodiments of the present disclosure, there is provided a heat dissipation substrate with a flow guide hole, wherein the flow guide hole exposes a part of the electronic component. In this way, the heat generated by the electronic components can be quickly removed by the air flow, thereby improving the heat dissipation capability of the entire heat dissipation substrate.

本揭露實施例之間的部件只要不違背創作精神或相衝突，均可任意混合搭配使用。此外，本揭露之保護範圍並未侷限於說明書內所述特定實施例中的製程、機器、製造、物質組成、裝置、方法及步驟，任何本領域中的通常知識者可從本揭露揭示內容中理解現行或未來所發展出的製程、機器、製造、物質組成、裝置、方法及步驟，只要可以在此處所述實施例中實施實質上相同功能或獲得實質上相同結果皆可根據本揭露使用。因此，本揭露之保護範圍包括上述製程、機器、製造、物質組成、裝置、方法及步驟。本揭露的任一實施例或請求項不須達成本揭露所公開的全部目的、優點及/或特點。 As long as the components in the disclosed embodiments do not violate the spirit of creation or conflict, they can be mixed and matched arbitrarily. In addition, the scope of protection of the present disclosure is not limited to the process, machine, manufacture, material composition, device, method and steps in the specific embodiments described in the specification. Understand the process, machine, manufacture, material composition, device, method and steps developed in the present or in the future, as long as they can implement substantially the same function or obtain substantially the same result in the embodiments described herein, they can be used according to the present disclosure . Therefore, the protection scope of the present disclosure includes the above-mentioned process, machine, manufacture, composition of matter, device, method and steps. Any embodiment or claims of the present disclosure need not achieve all the objectives, advantages and/or features disclosed in the present disclosure.

以上概述數個實施例，以便本領域中的通常知識者可以更理解本揭露實施例的觀點。本領域中的通常知識者應該理解的是，能以本揭露實施例為基礎，設計或修改其他製程與結構，以達到與在此介紹的實施例相同之目的及/或優勢。本領域中的通常知識者也應該理解的是，此類等效的製程與結構並無悖離本揭露的精神與範圍，且能在不違背本揭露之精神與範圍之下，做各式各樣的改變、取代與替換。 Several embodiments are summarized above so that those skilled in the art can better understand the viewpoints of the embodiments of the present disclosure. Those skilled in the art should understand that other processes and structures can be designed or modified based on the embodiments disclosed herein to achieve the same purpose and/or advantages as the embodiments introduced herein. common in the field People with common knowledge should also understand that such equivalent processes and structures do not deviate from the spirit and scope of this disclosure, and various changes can be made without violating the spirit and scope of this disclosure. Replace and replace.

1a:散熱基板 1a: Heat sink substrate

102:容置空間 102:Accommodating space

13,14,25,26:導電層 13,14,25,26: conductive layer

15,27,28,29:導電孔 15,27,28,29: conductive holes

17:電子元件 17: Electronic components

17c:側表面 17c: side surface

20:主體 20: subject

20a:第一表面 20a: first surface

20b:第二表面 20b: second surface

30:保護層 30: protective layer

31:導流孔 31: diversion hole

d1:距離 d1: distance

W3:寬度 W3: width

Claims

一種散熱基板，包括：一主體，具有彼此相對的一第一表面及一第二表面，且該主體具有一容置空間；一電子元件，設置於該主體的該容置空間中；一元件導電孔，設置於該主體中並電性連接至該電子元件；以及一導流孔，設置於該主體中並貫穿該主體的該第一表面與該第二表面，且該導流孔與該容置空間流體連通。 A heat dissipation substrate, comprising: a main body with a first surface and a second surface opposite to each other, and the main body has an accommodating space; an electronic component is arranged in the accommodating space of the main body; a conductive element A hole is disposed in the main body and electrically connected to the electronic component; and a diversion hole is disposed in the body and runs through the first surface and the second surface of the body, and the diversion hole and the container The space is fluidly connected.

如請求項1所述之散熱基板，其中該導流孔暴露該電子元件的複數個側表面中的至少一個。 The heat dissipation substrate as claimed in claim 1, wherein the conduction hole exposes at least one of the plurality of side surfaces of the electronic component.

如請求項2所述之散熱基板，其中該導流孔非封閉地環繞該電子元件的該些側表面。 The heat-dissipating substrate as claimed in claim 2, wherein the air guiding hole surrounds the side surfaces of the electronic component in a non-closed manner.

如請求項1所述之散熱基板，其中該導流孔對稱設置於該電子元件的兩側。 The heat dissipation substrate according to claim 1, wherein the air guide holes are symmetrically arranged on both sides of the electronic component.

如請求項1所述之散熱基板，其中該導流孔在該第一表面及/或該第二表面上的截面形狀為矩形。 The heat dissipation substrate according to claim 1, wherein the cross-sectional shape of the air guide hole on the first surface and/or the second surface is a rectangle.

如請求項1所述之散熱基板，更包括一保護層，該保護層設置於該主體的該第一表面及該第二表面上，其中該元件導電孔貫穿設置於該主體的該第一表面上的該保護層，且該導流孔貫穿設置於該主體的該第一表面及該第二表面上的該保護層。 The heat dissipation substrate as claimed in claim 1, further comprising a protective layer, the protective layer is disposed on the first surface and the second surface of the main body, wherein the element conductive hole is provided through the first surface of the main body The protection layer on the body, and the guide hole penetrates the protection layer disposed on the first surface and the second surface of the main body.

如請求項6所述之散熱基板，更包括彼此相對的一第一導電層及一第二導電層，該第一導電層及該第二導電層設置於該主體中，且該第一導電層藉由一第一導電孔與該第二導電層電性連接。 The heat dissipation substrate as described in claim 6 further includes a first conductive layer and a second conductive layer opposite to each other, the first conductive layer and the second conductive layer are arranged in the main body, and the first conductive layer through a first conductive hole and the second conductive layer sexual connection.

如請求項7所述之散熱基板，其中該第一導電層的底表面與該電子元件的頂表面齊平，且該第二導電層的頂表面與該電子元件的底表面齊平。 The heat dissipation substrate as claimed in claim 7, wherein the bottom surface of the first conductive layer is flush with the top surface of the electronic component, and the top surface of the second conductive layer is flush with the bottom surface of the electronic component.

如請求項7所述之散熱基板，更包括彼此相對的一第三導電層及一第四導電層，該第三導電層及該第四導電層設置於該主體中或該主體上，該第三導電層藉由一第二導電孔與該第一導電層電性連接，且該第四導電層藉由一第三導電孔與該第二導電層電性連接。 The heat dissipation substrate as described in claim 7 further includes a third conductive layer and a fourth conductive layer opposite to each other, the third conductive layer and the fourth conductive layer are disposed in or on the main body, the first The third conductive layer is electrically connected to the first conductive layer through a second conductive hole, and the fourth conductive layer is electrically connected to the second conductive layer through a third conductive hole.

如請求項9所述之散熱基板，其中該第三導電層及該第四導電層設置於該主體上，該第三導電層的底表面與設置於該第一表面上的該保護層的底表面齊平，且該第四導電層的頂表面與設置於該第二表面上的該保護層的頂表面齊平。 The heat dissipation substrate according to claim 9, wherein the third conductive layer and the fourth conductive layer are disposed on the main body, the bottom surface of the third conductive layer and the bottom surface of the protective layer disposed on the first surface The surfaces are flush, and the top surface of the fourth conductive layer is flush with the top surface of the protective layer disposed on the second surface.

如請求項9所述之散熱基板，其中該第三導電層及該第四導電層設置於該主體中，且該散熱基板更包括彼此相對的一第五導電層及一第六導電層，該第五導電層及該第六導電層設置於該主體上，該第五導電層藉由一第四導電孔與該第三導電層電性連接，且該第六導電層藉由一第五導電孔與該第四導電層電性連接。 The heat dissipation substrate as described in claim 9, wherein the third conductive layer and the fourth conductive layer are disposed in the main body, and the heat dissipation substrate further includes a fifth conductive layer and a sixth conductive layer opposite to each other, the The fifth conductive layer and the sixth conductive layer are disposed on the main body, the fifth conductive layer is electrically connected to the third conductive layer through a fourth conductive hole, and the sixth conductive layer is electrically connected to the third conductive layer through a fifth conductive layer. The hole is electrically connected with the fourth conductive layer.

如請求項11所述之散熱基板，其中該第五導電層的底表面與設置於該第一表面上的該保護層的底表面齊平，且該第六導電層的頂表面與設置於該第二表面上的該保護層的頂表面齊平。The heat dissipation substrate according to claim 11, wherein the bottom surface of the fifth conductive layer is flush with the bottom surface of the protective layer disposed on the first surface, and the top surface of the sixth conductive layer is flush with the protective layer disposed on the first surface. The top surface of the protective layer on the second surface is flush.