TWM583569U

TWM583569U - Display device

Info

Publication number: TWM583569U
Application number: TW108205917U
Authority: TW
Inventors: 陳致豪; 周凱茹; 陳辰恩; 鍾佩芳; 呂宣毅
Original assignee: 凌巨科技股份有限公司
Priority date: 2019-05-10
Filing date: 2019-05-10
Publication date: 2019-09-11

Abstract

A display device is disclosed. The display device comprises: a timing control unit providing a plurality of timing signals, and a display panel. The display panel comprises a pixel array including a plurality of pixel units and a gate driver connected to the pixel array and the timing control unit, and the gate driver includes a plurality of gate driving units. Each of gate driving unit has a timing signal, a start signal and a stop signal. The wave widths of start signals of the gate driving units are to be combined to generate a start shared signal, and a stop shared signal is generated according to the stop signal outputted from the last gate driving unit.

Description

顯示裝置Display device

本申請有關於一種顯示裝置，特別是有關於一種可產生共用訊號，以減少訊號線使用的顯示裝置。The present application relates to a display device, and more particularly to a display device capable of generating a common signal to reduce the use of signal lines.

隨著系統整合式玻璃面板（SOG, System-on-Glass）技術的發展，閘極驅動(GOA, Gate-Driver-on-Array)電路漸漸成為液晶顯示器驅動電路的主要設計方式，這種將顯示器驅動電路中的閘極掃描驅動電路(Gate driver或Scan driver)整合在玻璃上的設計具有諸多優勢，除了可以減少顯示器邊框的面積以達成窄邊框之外，更能夠減少閘極掃描驅動積體電路（IC）的使用，降低購買IC成本及避免玻璃與IC貼合時斷線問題，進而提升產品良率。因此目前閘極驅動電路已廣泛運用於手機、筆記型電腦等中小型顯示器或者大型顯示器。With the development of System-on-Glass (SOG) technology, Gate-Driver-on-Array (GOA) circuits have gradually become the main design method of LCD display driver circuits. The design of the gate scan driving circuit (Gate driver or Scan driver) integrated in the driving circuit on the glass has many advantages. In addition to reducing the area of the display frame to achieve a narrow frame, the gate scan driving integrated circuit can be reduced. The use of (IC) reduces the cost of purchasing IC and avoids the problem of disconnection when glass and IC are bonded, thereby improving product yield. Therefore, the gate drive circuit has been widely used in small and medium displays or large displays such as mobile phones and notebook computers.

在窄邊框(Narrow Border)的設計趨勢下，面板的邊框逐漸變窄，屏佔比逐漸提高，要求的解析度也越來越高，電路佈局所需要的面積亦跟著提升。為了達到窄邊框的目的，縮減電路中元件（例如薄膜電晶體，Thin-Film Transistor，TFT)尺寸為常見的手法，但是縮減電路元件尺寸會造成電路元件充電能力的下降，如圖1所示，圖1是現有技術的尺寸縮減畫素電極充電時間-電壓曲線圖，圖1中左圖顯示原始正常的電路佈局面積於時間區間t1的充電情形可以達到電壓V1，而圖1中右圖顯示縮減電路佈局的尺寸縮減後，於相同時間區間t1的充電情形可以達到電壓V1’，其中電壓V1’小於電壓V1，充電能力下降。為了改善減少電路佈局的面積所造成充電能力下降的情形，現有技術用多相位(multi-phase)的處理技術來解決上述的問題，如圖2所示。圖2是現有技術的多相位畫素電極充電時間-電壓曲線圖，圖2中左圖顯示原始正常的電路佈局面積於時間區間t1的充電情形可以達到電壓V2，圖2中右圖顯示藉由多相位畫素電極充電可以增加為多點充電時間t2抬升充電電壓V2’，使畫素電極充電能力提升。但由於隨著相位數目的提升，閘極驅動電路由IC所提供的起始訊號、截止訊號數目也會逐漸增加。Under the design trend of the narrow border, the border of the panel is gradually narrowed, the screen ratio is gradually increased, the required resolution is also getting higher and higher, and the area required for the circuit layout is also increasing. In order to achieve the narrow frame, it is a common method to reduce the size of components in the circuit (such as thin-film transistor, thin-film transistor, TFT), but reducing the size of the circuit components will reduce the charging capacity of the circuit components, as shown in Figure 1, FIG. 1 is a prior art size reduction pixel electrode charging time-voltage curve. The left figure in FIG. 1 shows that the charging condition of the original normal circuit layout area in the time interval t1 can reach the voltage V1, and the right figure in FIG. 1 shows the reduction. After the size of the circuit layout is reduced, the charging situation in the same time interval t1 can reach the voltage V1 ′, where the voltage V1 ′ is less than the voltage V1, and the charging capacity is reduced. In order to improve the situation that the charging capacity is reduced due to the reduction of the area of the circuit layout, the prior art uses a multi-phase processing technology to solve the above problems, as shown in FIG. 2. FIG. 2 is a prior art multi-phase pixel electrode charging time-voltage curve. The left graph in FIG. 2 shows that the charging condition of the original normal circuit layout area during the time interval t1 can reach the voltage V2. The right graph in FIG. 2 shows that The multi-phase pixel electrode charging can increase the multi-point charging time t2 to raise the charging voltage V2 ', so that the pixel electrode charging ability is improved. However, as the number of phases increases, the number of start signals and cut-off signals provided by the gate drive circuit from the IC will gradually increase.

為解決起始訊號和截止訊號逐漸增加的問題，現有技術雖將起始訊號、截止訊號分別共用一組訊號源，減少由IC所提供的訊號源，因此，IC需要的訊號線也會跟著減少，同時提供予閘極驅動電路的起始訊號及截止訊號的數量也將會減少一半，故可減少訊號線的佈局數量及電路佈局所需要的面積，但仍無法滿足現今觸控裝置愈朝向輕、薄、短、小的需求。In order to solve the problem that the start signal and the cut-off signal increase gradually, although the prior art uses the same set of signal sources as the start signal and the cut-off signal to reduce the signal sources provided by the IC, the signal lines required by the IC will also decrease At the same time, the number of start signals and cut-off signals provided to the gate driving circuit will also be reduced by half, so the number of signal lines and the area required for circuit layout can be reduced, but it still cannot meet the current trend of lighter touch devices. , Thin, short, small demand.

有鑑於此，本申請提供一種顯示裝置，藉以解決先前技術無法減少電路佈局的面積，而造成充電能力下降等問題或缺點。In view of this, the present application provides a display device, so as to solve the problems or disadvantages such as the decrease in the charging capacity that cannot be reduced by the circuit layout area of the prior art.

根據本申請提供的一顯示裝置，包括一時序控制單元，提供多個時脈訊號；一顯示面板，包括：一畫素陣列，具有多個畫素單元；以及一閘極驅動電路，耦接該時序控制單元及該畫素陣列，該閘極驅動電路包括多個閘極驅動單元，其中每一個該閘極驅動單元各具有一時脈訊號、一起始訊號以及一截止訊號；其中，多個該閘極驅動單元之多個該起始訊號之波寬將被聯集，以產生一起始共用訊號，並根據最後一個該閘極驅動單元所輸出的該截止訊號，進而產生一截止共用訊號。A display device provided in accordance with the present application includes a timing control unit that provides multiple clock signals; a display panel including: a pixel array with multiple pixel units; and a gate driving circuit coupled to the A timing control unit and the pixel array. The gate driving circuit includes a plurality of gate driving units, each of which has a clock signal, a start signal, and a cut-off signal; among them, a plurality of gates The wave widths of the plurality of start signals of the pole driving unit will be combined to generate an initial common signal, and according to the cut-off signal output by the last gate driving unit, a cut-off common signal will be generated.

本申請將多個閘極驅動單元的起始訊號進行聯集，以產生起始共用訊號，並根據最後一個閘極驅動單元所輸出的截止訊號作為截止共用訊號，因此，可應用起始共用訊號和截止共用訊號來減少電路佈局的面積，進而提升顯示裝置的充電能力、執行時間和效率。This application combines the start signals of multiple gate drive units to generate a start common signal, and uses the cut-off signal output by the last gate drive unit as the cut-off common signal. Therefore, the start common signal can be applied The signal is shared with the cutoff to reduce the area of the circuit layout, thereby improving the charging ability, execution time and efficiency of the display device.

以上之關於本申請內容之說明及以下之實施方式之說明用以示範與解釋本申請之精神與原理，並且提供本申請之專利申請範圍更進一步之解釋。The above description of the content of this application and the description of the following embodiments are used to demonstrate and explain the spirit and principles of this application, and provide a further explanation of the scope of patent applications of this application.

以下在實施方式中詳細敘述本申請之詳細特徵以及優點，其內容足以使任何熟習相關技藝者了解本申請之技術內容並據以實施，且根據本說明書所揭露之內容、申請專利範圍及圖式，任何熟習相關技藝者可輕易地理解本申請相關之目的及優點。以下的實施例說明是進一步詳細說明本申請之觀點，並非以任何觀點限制本申請之範疇。以下所列舉的各實施例中，將以相同的標號代表相同或相似的元件或構件。The detailed features and advantages of this application are described in detail in the following embodiments. The content is sufficient for any person skilled in the art to understand and implement the technical content of this application, and according to the content disclosed in this specification, the scope of the patent application and the drawings. Anyone skilled in the relevant art can easily understand the purpose and advantages related to this application. The following example description is to further explain the viewpoints of this application in detail, and is not intended to limit the scope of this application in any way. In the embodiments listed below, the same reference numerals are used to represent the same or similar elements or components.

圖3是根據本申請一實施例的顯示裝置方塊圖。圖4是根據本申請的顯示裝置中的每一閘極驅動單元的起始訊號。圖5是根據本申請的顯示裝置中的每一閘極驅動單元的截止訊號。如圖3所示，本申請提供的一種顯示裝置包括時序控制單元11及顯示面板12。時序控制單元11耦接顯示面板12，並提供多個時脈訊號給閘極驅動電路122。顯示面板12包括畫素陣列121及閘極驅動電路122。畫素陣列121具有多個畫素單元(未標示)，閘極驅動電路122耦接時序控制單元11及畫素陣列121，閘極驅動電路122包括多個閘極驅動單元1221，其中每一個閘極驅動單元1221各具有時脈訊號、起始訊號以及截止訊號。在本實施例中，多個閘極驅動單元1221之多個起始訊號之波寬將被聯集，以產生起始共用訊號(如圖4所示)，並根據最後一個閘極驅動單元1221所輸出的截止訊號，進而產生截止共用訊號(如圖5所示)。FIG. 3 is a block diagram of a display device according to an embodiment of the present application. FIG. 4 is a start signal of each gate driving unit in a display device according to the present application. FIG. 5 is a cut-off signal of each gate driving unit in a display device according to the present application. As shown in FIG. 3, a display device provided in this application includes a timing control unit 11 and a display panel 12. The timing control unit 11 is coupled to the display panel 12 and provides a plurality of clock signals to the gate driving circuit 122. The display panel 12 includes a pixel array 121 and a gate driving circuit 122. The pixel array 121 has a plurality of pixel units (not labeled). The gate driving circuit 122 is coupled to the timing control unit 11 and the pixel array 121. The gate driving circuit 122 includes a plurality of gate driving units 1221. Each of the gates The pole driving units 1221 each have a clock signal, a start signal, and a cut-off signal. In this embodiment, the wave widths of the plurality of start signals of the plurality of gate driving units 1221 will be combined to generate an initial common signal (as shown in FIG. 4), and according to the last gate driving unit 1221 The output cut-off signal further generates a cut-off shared signal (as shown in FIG. 5).

詳細而言之，多個被聯集的波寬為各起始訊號位於高位準的波幅寬度。如圖4所示，起始共用訊號的波寬是起始訊號1、起始訊號2….起始訊號n波寬的聯集。起始共用訊號的初始時脈上升緣為第一個閘極驅動單元1221之起始訊號的初始時脈上升緣，而起始共用訊號的初始時脈下降緣為最後一個閘極驅動單元1221之起始訊號的初始時脈下降緣。In detail, the wave widths of the plurality of associated sets are the wave widths of each start signal at a high level. As shown in FIG. 4, the wave width of the initial common signal is a joint set of the initial signal 1, the initial signal 2, ..., the initial signal n wave width. The initial clock rising edge of the initial common signal is the initial clock rising edge of the first gate driving unit 1221, and the initial clock falling edge of the initial common signal is the last gate driving unit 1221. The falling edge of the initial clock of the start signal.

此外，如圖5所示，閘極驅動電路122之截止共用訊號的初始時脈上升緣為最後一級閘極驅動單元1221之截止訊號的初始時脈上升緣，而截止共用訊號的初始時脈下降緣為最後一級閘極驅動單元1221之截止訊號的初始時脈下降緣。In addition, as shown in FIG. 5, the initial rising edge of the cut-off common signal of the gate driving circuit 122 is the initial rising edge of the cut-off signal of the last-stage gate driving unit 1221, and the initial clock of the cut-off shared signal decreases. The edge is the initial falling edge of the cut-off signal of the last-stage gate driving unit 1221.

多個閘極驅動單元1221為N級陣列閘極驅動(gate driver on array, GOA)電路，各級閘極驅動電路的閘極可輸入起始共用訊號。目前現有的閘極驅動電路技術，每一個閘極驅動電路是由多個電晶體所組成，多個電晶體在不同時間下，會個別在不同時間區間導通，進而提供不同的充放電路徑的功能，如圖6所示。圖6顯示單級閘極驅動單元的詳細電路示意圖，每一級閘極驅動電路基本由第一電晶體M1、第二電晶體M2及第三電晶體M3所組成，其中，第一電晶體M1、第二電晶體M2、第三電晶體M3可為N型的薄膜電晶體(Thin-Film Transistor，TFT)，圖中的VDD表示正參考電壓，VSS表示負參考電壓，An、GN為節點，CLK1為時脈訊號， Gn、Gn-X、Gn+(X+1)為閘極訊號，n為級數(Stage)，X為相位數(Phase)(亦即時脈數)的一半。第一電晶體M1的汲極接收正參考電壓VDD，第一電晶體M1的源極與第三電晶體M3的汲極電性連接，第一電晶體M1的閘極由閘極訊號Gn-X控制。第二電晶體的汲極接收時脈訊號CLK1，第二電晶體M2的源極由節點GN輸出閘極訊號Gn，第二電晶體M2的閘極電性連接至第一電晶體M1的源極與第三電晶體M3的汲極之間。第三電晶體M3的源極接收負參考電壓VSS，第三電晶體M3的閘極由閘極訊號Gn+(X+1)控制。每一級閘極驅動電路需要有其起始訊號 (Gn-X) 對節點An進行預充電，再由截止訊號 (Gn+(X+1)) 清除節點An電壓。The plurality of gate driving units 1221 are N-level gate driver on array (GOA) circuits, and the gates of the gate driving circuits of each level can input the initial common signal. At present, the current gate driving circuit technology, each gate driving circuit is composed of multiple transistors, and the multiple transistors will be turned on at different time intervals at different times, thereby providing different functions of charging and discharging paths. ,As shown in Figure 6. FIG. 6 shows a detailed circuit diagram of a single-stage gate driving unit. Each stage of the gate driving circuit is basically composed of a first transistor M1, a second transistor M2, and a third transistor M3. Among them, the first transistor M1, The second transistor M2 and the third transistor M3 may be N-type thin-film transistors (TFTs), where VDD represents a positive reference voltage, VSS represents a negative reference voltage, An and GN are nodes, and CLK1 Gn, Gn-X, Gn + (X + 1) are the gate signals, n is the number of stages, and X is half the number of phases (also the number of real-time pulses). The drain of the first transistor M1 receives a positive reference voltage VDD, the source of the first transistor M1 is electrically connected to the drain of the third transistor M3, and the gate of the first transistor M1 is provided by a gate signal Gn-X. control. The drain of the second transistor receives the clock signal CLK1, and the source of the second transistor M2 outputs the gate signal Gn from the node GN. The gate of the second transistor M2 is electrically connected to the source of the first transistor M1. And the drain of the third transistor M3. The source of the third transistor M3 receives the negative reference voltage VSS, and the gate of the third transistor M3 is controlled by the gate signal Gn + (X + 1). Each level of gate driving circuit needs its start signal (Gn-X) to pre-charge node An, and then the cut-off signal (Gn + (X + 1)) clears the node An voltage.

本申請更可透過另外的訊號產生電路（例如積體電路(未繪示)），以提供外部截止訊號與外部起始訊號給該閘極驅動電路122，其中，積體電路的外部起始訊號會輸入至第一個閘極驅動單元G1(第1級(G1)閘極驅動單元)，外部截止訊號會輸入至最後一個閘極驅動單元G720(第720級(G720)閘極驅動單元)，更詳而言之，以16相位720級閘極驅動電路為例，積體電路提供外部起始訊號作為第1級(G1)至第8級(G8)閘極驅動單元的起始共用訊號，其外部截止信號作為第712級(G712)至第720級(G720)閘極驅動單元的截止共用訊號。In this application, another signal generating circuit (such as an integrated circuit (not shown)) can be used to provide an external cut-off signal and an external start signal to the gate driving circuit 122. Among them, the external start signal of the integrated circuit Will be input to the first gate drive unit G1 (G1) gate drive unit, and the external cut-off signal will be input to the last gate drive unit G720 (G720 720th gate drive unit), More specifically, taking a 16-phase 720-level gate drive circuit as an example, the integrated circuit provides an external start signal as the start common signal of the first-level (G1) to eight-level (G8) gate drive units. Its external cut-off signal is used as the cut-off common signal for the 712th (G712) to 720th (720) gate drive units.

為了更清楚顯示應用本申請後的多個閘極驅動單元可共用起始訊號，以及共用截止訊號，進而減少積體電路尺寸的優點，將16相位720級閘極驅動電路未應用本申請前以及應用本申請後，所產生波形圖，進行比較，其比較結果的圖形顯示如下所述。In order to more clearly show that multiple gate driving units after applying this application can share the start signal and the common cut-off signal, thereby reducing the advantages of the size of the integrated circuit, the 16-phase 720-level gate driving circuit is not applied before this application and After applying this application, the generated waveform graphs are compared, and the graphical display of the comparison results is as follows.

圖7是未應用本申請的16相位720級閘極驅動電路圖。如圖7所示，第1級(G1)至第8級(G8)閘極驅動單元，每一個閘極驅動單元都需要一條起始訊號Vstart1~Vstart8，而第712級(G712)至第720級(G720)閘極驅動單元，每一個閘極驅動單元都需要一條截止訊號Vstop1~Vstop9。圖8A是圖7的16相位720級閘極驅動電路的起始訊號波形圖。於本實施例中，給予閘極驅動電路環境中時脈訊號、起始訊號、截止訊號的高電壓為15V，低電壓為-12V，上升時間(rising time，Tr)為由低電壓充電至高電壓時，充電10%至充電90%間的電壓變化和所需的時間，下降時間(falling time，Tf)為由高電壓放電至低電壓時，放電10%至放電90%間的電壓變化和所需的時間。如圖8A所示，並請同時參照圖6，在節點An上量測波形，第1級(G1)至第8級(G8)閘極驅動單元都會需要一條起始訊號。FIG. 7 is a circuit diagram of a 16-phase 720-level gate driving circuit to which the present application is not applied. As shown in Fig. 7, for each of the gate drive units of the first (G1) to eighth (G8) gate drive units, a start signal Vstart1 to Vstart8 is required, and the 712th (G712) to 720th Level (G720) gate drive unit, each gate drive unit needs a stop signal Vstop1 ~ Vstop9. FIG. 8A is a waveform diagram of a start signal of the 16-phase 720-level gate driving circuit of FIG. 7. In this embodiment, the high voltage of the clock signal, the start signal, and the cutoff signal in the environment of the gate driving circuit is 15V, the low voltage is -12V, and the rising time (Tr) is charged from low voltage to high voltage. , The voltage change between 10% and 90% of charging and the time required, the falling time (Tf) is the voltage change between 10% and 90% of the discharge when the high voltage to low voltage is discharged Time required. As shown in FIG. 8A, please also refer to FIG. 6. To measure the waveform at the node An, the first (G1) to the eighth (G8) gate drive units all need a start signal.

圖8B是圖7的16相位720級閘極驅動電路的第1級(G1)閘極驅動單元在節點An的起始訊號的最高電壓值，其最高電壓值為31.73V。圖8C是圖7的16相位720級閘極驅動電路的第1級(G1)閘極驅動單元在節點GN的起始訊號的最高電壓值，其最高電壓值為14.98V, Tr=4.6(us), Tf=4.57(us)。圖8D是圖7的16相位720級閘極驅動電路的截止訊號波形圖。如圖8D所示，在節點An上量測波形，第712級(G712)至第720級(G720)閘極驅動單元，每級閘極驅動單元輸出一條截止訊號。圖8E是圖7的16相位720級閘極驅動電路的最後一級閘極驅動單元在節點An所輸出的截止訊號的最高電壓值，其最高電壓值為31.62V。圖8F是圖7的16相位720級閘極驅動電路的最後一級閘極驅動單元在節點GN所輸出的截止訊號的最高電壓值，其最高電壓值為14.98V, Tr=4.62(us), Tf=4.58(us) 。FIG. 8B is the highest voltage value of the start signal of the first stage (G1) gate drive unit of the 16-phase 720-stage gate drive circuit of FIG. 7 at the node An, and the highest voltage value is 31.73V. FIG. 8C is the highest voltage value of the start signal of the first-stage (G1) gate drive unit of the 16-phase 720-stage gate drive circuit of FIG. 7 at the node GN. The highest voltage value is 14.98V, Tr = 4.6 (us ), Tf = 4.57 (us). FIG. 8D is a waveform diagram of the cutoff signal of the 16-phase 720-level gate driving circuit of FIG. 7. As shown in FIG. 8D, the waveform is measured on the node An. The gate driving units of the 712th (G712) to 720th (G720) gate driving units each output a cutoff signal. FIG. 8E is the highest voltage value of the cut-off signal output by the last-stage gate driving unit of the 16-phase 720-level gate driving circuit of FIG. 7 at the node An, and the highest voltage value is 31.62V. FIG. 8F is the highest voltage value of the cut-off signal output by the last-stage gate driving unit of the 16-phase 720-level gate driving circuit of FIG. 7 at the node GN. The highest voltage value is 14.98V, Tr = 4.62 (us), Tf = 4.58 (us).

圖9是已應用本申請的16相位720級閘極驅動電路圖。如圖9所示，第1級(G1)至第8級(G8)閘極驅動單元共用一條起始訊號Vstart1，第712級(G712)至第716級(G716)閘極驅動單元共用一條截止訊號Vstop1，第717級(G717)至第720級(G720)閘極驅動單元共用一條截止訊號Vstop2。圖10A是圖9的16相位720級閘極驅動電路的起始訊號波形圖。於本實施例，圖10A~圖10F的量測環境和前述圖8A~圖8F的量測環境相同，故不再贅述。如圖10A所示，並同時參照圖6，在節點An上量測波形，第1級(G1)至第8級(G8)閘極驅動單元，都共用一條起始訊號。圖10B是圖9的16相位720級閘極驅動電路的第1級(G1)閘極驅動單元在節點An的起始訊號的最高電壓值，其最高電壓值為32.41V。圖10C是圖9的16相位720級閘極驅動電路的第1級(G1)閘極驅動單元在節點GN的起始訊號的最高電壓值，其最高電壓值為14.98V, Tr=4.5(us), Tf=4.54(us)。FIG. 9 is a diagram of a 16-phase 720-level gate driving circuit to which the present application is applied. As shown in FIG. 9, the gate driving units of the first (G1) to eight stages (G8) share a start signal Vstart1, and the gate driving units of the 712th (G712) to 716 (G716) share a cutoff The signal Vstop1, the 717th (G717) to 720th (720) gate drive units share one stop signal Vstop2. FIG. 10A is a waveform diagram of a start signal of the 16-phase 720-level gate driving circuit of FIG. 9. In this embodiment, the measurement environment in FIGS. 10A to 10F is the same as the measurement environment in FIG. 8A to FIG. 8F described above, and details are not described herein again. As shown in FIG. 10A and referring to FIG. 6 at the same time, the waveforms are measured at the node An, and the first (G1) to the eighth (G8) gate driving units all share a start signal. FIG. 10B is the highest voltage value of the start signal of the first stage (G1) gate drive unit of the 16-phase 720-stage gate drive circuit of FIG. 9 at the node An, and the highest voltage value is 32.41V. FIG. 10C is the highest voltage value of the start signal of the first stage (G1) gate drive unit of the 16-phase 720-level gate drive circuit of FIG. 9 at the node GN. The highest voltage value is 14.98V, Tr = 4.5 (us ), Tf = 4.54 (us).

圖10D是圖9的16相位720級閘極驅動電路的截止訊號波形圖。如圖10D所示，在節點An上量測波形，第712級(G712)至第716級(G716)閘極驅動單元共用一條截止訊號，第717級(G717)至第720級(G720)閘極驅動單元，共用一條截止訊號。圖10E是圖9的16相位720級閘極驅動電路的最後一級閘極驅動單元在節點An所輸出的截止訊號的最高電壓值，其最高電壓值為31.64V。圖10F是圖9的16相位720級閘極驅動電路的最後一級閘極驅動單元在節點GN所輸出的截止訊號的最高電壓值，其最高電壓值為14.98V, Tr=4.65(us), Tf=4.57(us)。FIG. 10D is a waveform diagram of the cutoff signal of the 16-phase 720-level gate driving circuit of FIG. 9. As shown in FIG. 10D, the waveform is measured at the node An. The gate driver units of the 712th (G712) to 716 (G716) gates share a cut-off signal, and the 717th (G717) to 720th (G720) gates Pole drive unit, sharing a cut-off signal. FIG. 10E is the highest voltage value of the cut-off signal output by the last-stage gate driving unit of the 16-phase 720-level gate driving circuit of FIG. 9 at the node An, and the highest voltage value is 31.64V. FIG. 10F is the highest voltage value of the cut-off signal output by the last-stage gate driving unit of the 16-phase 720-level gate driving circuit of FIG. 9 at the node GN. The highest voltage value is 14.98V, Tr = 4.65 (us), Tf = 4.57 (us).

由上述圖8A~8F和圖10A~圖10F的比較可知，在應用本申請前和應用本申請後的16相位720級閘極驅動電路，在訊號共用下，使用共用訊號之閘極驅動電路的節點An之波形會和未使用共用訊號的節點An的波形不一樣。以波形高度、時間Tr和Tf作為評估依據，只要經評估後的衰減均在合理範圍5%內，都是合理的。From the above comparison between FIGS. 8A to 8F and FIGS. 10A to 10F, it can be known that before the application of this application and after the application of this application, the 16-phase 720-level gate driving circuit is used, and under the signal sharing, the gate driving circuit of the common signal The waveform of node An will be different from the waveform of node An that does not use a shared signal. Taking the waveform height, time Tr, and Tf as the basis for evaluation, as long as the attenuation after evaluation is within a reasonable range of 5%, it is reasonable.

因此，由上述的量測，可驗證經過縮減訊並共用訊號線後，並不影響閘極驅動電路輸出功能。Therefore, from the above measurement, it can be verified that after reducing the signal and sharing the signal line, the output function of the gate driving circuit is not affected.

本申請除了上述16相位720級閘極驅動電路作說明外，亦可應用於其他多相位多級的閘極驅動電路，例如，圖11是應用本申請的12相位720級的閘極驅動電路的圖式，如圖11所示，本申請可讓12相位720級閘極驅動電路共用起始訊號及截止訊號，其中閘極驅動電路中的第1級(G1)閘極驅動單元至第6級(G6)閘極驅動單元共用起始共用訊號，第714級(G714)閘極驅動單元至第717級(G717)閘極驅動單元共用一個截止訊號，第718級(G718)閘極驅動單元至第720級(G720)閘極驅動單元共用另一個截止共用訊號；圖12是應用本申請的8相位720級的閘極驅動電路的圖式，如圖12所示，本申請可讓8相位720級閘極驅動電路共用起始訊號及截止訊號，其中閘極驅動電路中的第1級(G1)閘極驅動單元至第4級(G4)閘極驅動單元共用起始共用訊號，第716級(G716)閘極驅動單元至第718級(G718)閘極驅動單元共用同一個截止訊號，第719級(G719)閘極驅動單元至第720級(G720)閘極驅動單元共用另一個截止共用訊號。雖上述8相位720級閘極驅動電路的截止訊號分別以第716級(G716)閘極驅動單元至第718級(G718)閘極驅動單元以及第719級(G719)閘極驅動單元至第720級(G720)閘極驅動單元共用一條截止訊號，但亦可根據實際需求調整應用截止訊號的級數，例如，以第716級(G716)閘極驅動單元至第717級(G717)閘極驅動單元共用一截止訊號，以第718級(G718)閘極驅動單元至第720級(G720)閘極驅動單元共用一截止共用訊號。其他相位720級的閘極驅動電路的截止訊號所共用的級數，亦可根據實際需求作調整，故不再贅述。In addition to the description of the above-mentioned 16-phase 720-level gate driving circuit, the present application can also be applied to other multi-phase and multi-level gate driving circuits. For example, FIG. 11 shows the application of the 12-phase 720-level gate driving circuit of the present application. As shown in the figure, as shown in FIG. 11, the present application may allow a 12-phase 720-level gate driving circuit to share a start signal and a cut-off signal. Among them, the gate driving circuit of the first level (G1) to the sixth level (G6) The gate drive unit shares the common start signal, the 714th (G714) gate drive unit to the 717th (G717) gate drive unit shares a cutoff signal, and the 718th (G718) gate drive unit to The 720th stage (G720) gate drive unit shares another cut-off common signal; Figure 12 is a schematic diagram of the 8-phase 720-stage gate drive circuit to which the present application is applied. As shown in FIG. 12, this application allows 8-phase 720 Level gate drive circuits share the start signal and cut-off signal. Among them, the first level (G1) gate drive unit to the fourth level (G4) gate drive unit in the gate drive circuit share the start common signal, level 716. (G716) Gate drive unit to level 718 (G718) Gate drive units share the same Off signal, the first 719 (G719) to the second gate driving unit 720 (G720,) the gate driving units share another common signal is turned off. Although the cut-off signals of the above-mentioned 8-phase 720-level gate driving circuit are respectively the 716th (G716) gate driving unit to the 718th (G718) gate driving unit and the 719th (G719) gate driving unit to 720th Level (G720) gate drive unit shares a cut-off signal, but the number of levels of cut-off signals can be adjusted according to actual needs, for example, from the 716th (G716) gate drive unit to the 717th (G717) gate drive The units share a cut-off signal. The 718-level (G718) gate drive unit to the 720-level (G720) gate-drive unit share a cut-off shared signal. The number of stages common to the cut-off signals of the gate driving circuits of other phases of 720 stages can also be adjusted according to actual needs, so it will not be described again.

圖13是應用本申請的4相位720級的閘極驅動電路的圖式，如圖13所示，本申請亦可讓4相位720級的閘極驅動電路共用起始訊號及截止訊號，其中4相位720級的閘極驅動電路中的第1級(G1)閘極驅動單元至第2級(G2)閘極驅動單元共用起始共用訊號，第717級(G717)閘極驅動單元使用一個截止訊號，第718級(G718)閘極驅動單元至第720級(G720)閘極驅動單元共用另一截止共用訊號。FIG. 13 is a diagram of a 4-phase 720-level gate driving circuit to which the present application is applied. As shown in FIG. 13, the application can also allow a 4-phase 720-level gate driving circuit to share a start signal and a cut-off signal, of which 4 In the gate driving circuit of phase 720, the first (G1) gate driving unit to the second (G2) gate driving unit share a common start signal, and the 717th (G717) gate driving unit uses a cutoff Signal, the 718th (G718) gate drive unit to the 720th (G720) gate drive unit share another cut-off shared signal.

因此，不論多少相位的720級閘極驅動電路，通過本申請的顯示裝置的設計，可將原本所需的訊號線縮減，例如，16相位720級的閘極驅動電路，其16相位數等於16個時脈數目，依現有技術，其需要8條起始訊號線和9條截止訊號線，共需17條訊號線，通用本申請的應用可減少為共用起始訊號線一條，截止共用訊號線二條(如圖9所示)，共三條訊號線便可運作16相位720級的閘極驅動電路；同樣地，12相位720級的閘極驅動電路，依現有技術，其需要6條起始訊號線和7條截止訊號線，共需13條訊號線，通用本申請的應用可減少為共用起始訊號線一條，截止共用訊號線二條(如圖11所示)；同樣地，8相位720級的閘極驅動電路，依現有技術，其需要4條起始訊號線和5條截止訊號線，共需9條訊號線，通用本申請的應用可減少為共用起始訊號線一條，截止共用訊號線二條(如圖12所示)；同樣地，4相位720級的閘極驅動電路，依現有技術，其需要2條起始訊號線和3條截止訊號線，共需5條訊號線，通用本申請的應用可減少為共用起始訊號線一條，截止共用訊號線二條(如圖13所示)。所以，不論多少相位的720級閘極驅動電路，通過本申請的顯示裝置的設計，可將原本所需的訊號線縮減為3條訊號線，可減少現有技術電路佈局所使用訊號線的面積，進而達到減少邊框屏佔比的尺寸的目的。於本實施例，截止訊號共用受限於時脈訊號的波形設定，若上述相位級閘極驅動電路僅用一個截止共用訊號線將會造成電路誤輸出，故必須至少共用使用二條截止訊號線才可防止電路的誤輸出。Therefore, no matter how many phases of the 720-level gate driving circuit, the design of the display device of the present application can reduce the originally required signal lines. For example, for a 16-phase 720-level gate driving circuit, the number of 16 phases is equal to 16 The number of clocks, according to the existing technology, requires 8 start signal lines and 9 cut-off signal lines, and a total of 17 signal lines. The application of this application can be reduced to one shared start signal line and cut-off shared signal line. Two (as shown in Figure 9), a total of three signal lines can operate a 16-phase 720-level gate drive circuit; similarly, a 12-phase 720-level gate drive circuit, according to the existing technology, requires 6 start signals Line and 7 cut-off signal lines, a total of 13 signal lines are required. The application of this application can be reduced to one shared start signal line and two cut-off shared signal lines (as shown in Figure 11). Similarly, 8-phase 720 levels According to the existing technology, the gate driving circuit requires 4 start signal lines and 5 cut-off signal lines, and a total of 9 signal lines are required. The application of this application can be reduced to one shared start signal line and cut-off shared signals. Two lines (as shown in Figure 12 In the same way, a 4-phase 720-level gate drive circuit requires 2 start signal lines and 3 cut-off signal lines according to the prior art, and a total of 5 signal lines are needed. The application of this application can be reduced to One common start signal line and two common end signal lines (as shown in Figure 13). Therefore, regardless of the number of phases of the 720-level gate driving circuit, through the design of the display device of the present application, the originally required signal lines can be reduced to three signal lines, and the area of the signal lines used in the prior art circuit layout can be reduced. The purpose of reducing the size of the border screen is further achieved. In this embodiment, the cut-off signal sharing is limited by the waveform setting of the clock signal. If the above-mentioned phase-level gate drive circuit uses only one cut-off shared signal line, it will cause a false output of the circuit. Therefore, at least two cut-off signal lines must be shared. It can prevent the erroneous output of the circuit.

綜上所述，本申請減少訊號線的作法為，將電路所有起始訊號的波寬聯集產生一個起始共用訊號，以減少應用多少相位必須提供多少起始訊號的製作，接著，等待最後一級的電路的截止訊號產生後，再產生一個截止共用訊號，並和外部積體電路產生的訊號共用，進而減少電路佈局所使用的面積，達到減少邊框面積，提升屏佔比。In summary, the method of reducing signal lines in this application is to generate a starting common signal by combining the widths of all the starting signals of the circuit to reduce the number of phases that must be provided for the application. Then, wait for the final After the cut-off signal of the first-level circuit is generated, a cut-off common signal is generated and shared with the signal generated by the external integrated circuit, thereby reducing the area used for the circuit layout, reducing the area of the frame, and increasing the screen ratio.

雖然本申請以前述之實施例揭露如上，然其並非用以限定本申請。在不脫離本申請之精神和範圍內，所為之更動與潤飾，均屬本申請之專利保護範圍。關於本申請所界定之保護範圍請參考所附之申請專利範圍。Although the present application is disclosed above with the foregoing embodiments, it is not intended to limit the present application. Changes and modifications made without departing from the spirit and scope of this application are within the scope of patent protection of this application. For the protection scope defined in this application, please refer to the attached patent application scope.

11‧‧‧時序控制單元
12‧‧‧顯示面板
121‧‧‧畫素陣列
122‧‧‧閘極驅動電路
1221‧‧‧閘極驅動單元
M1、M2、M3‧‧‧電晶體
VDD‧‧‧正參考電壓
VSS‧‧‧負參考電壓
An‧‧‧節點
GN‧‧‧節點
CLK1‧‧‧時脈訊號
Gn、Gn-8、Gn+9‧‧‧閘極訊號
Gn-X、Gn+(X+1)‧‧‧閘極訊號
X‧‧‧相位數(Phase)的一半
Vstart1，Vstart2‧‧‧起始訊號
Vstop1、Vstop2‧‧‧截止訊號
Tr、Tf‧‧‧時間 11‧‧‧sequence control unit
12‧‧‧Display Panel
121‧‧‧ pixel array
122‧‧‧Gate driving circuit
1221‧‧‧Gate drive unit
M1, M2, M3 ‧‧‧ Transistors
VDD‧‧‧Positive reference voltage
VSS‧‧‧Negative reference voltage
An‧‧‧node
GN‧‧‧node
CLK1‧‧‧clock signal
Gn, Gn-8, Gn + 9‧‧‧Gate signal
Gn-X, Gn + (X + 1) ‧‧‧Gate signal
X‧‧‧ half of phase
Vstart1, Vstart2 ‧‧‧ start signal
Vstop1, Vstop2‧‧‧ cut-off signals
Tr, Tf‧‧‧time

圖1是現有技術的尺寸縮減畫素電極充電時間-電壓曲線圖。
圖2是現有技術的多相位畫素電極充電時間-電壓曲線圖。
圖3是根據本申請一實施例的顯示裝置方塊圖。
圖4是根據本申請的顯示裝置中的每一閘極驅動單元的起始訊號。
圖5是根據本申請的顯示裝置中的每一閘極驅動單元的截止訊號。
圖6是單級閘極驅動單元的詳細電路示意圖。
圖7是未應用本申請的16相位720級閘極驅動電路圖。
圖8A是圖7的16相位720級閘極驅動電路的起始訊號波形圖。
圖8B是圖7的16相位720級閘極驅動電路的第1級閘極驅動單元在節點An的起始訊號的最高電壓值。
圖8C是圖7的16相位720級閘極驅動電路的第1級閘極驅動單元在節點GN的起始訊號的最高電壓值。
圖8D是圖7的16相位720級閘極驅動電路的截止訊號波形圖。
圖8E是圖7的16相位720級閘極驅動電路的最後一級閘極驅動單元在節點An所輸出的截止訊號的最高電壓值。
圖8F是圖7的16相位720級閘極驅動電路的最後一級閘極驅動單元在節點GN所輸出的截止訊號的最高電壓值。
圖9是已應用本申請的16相位720級閘極驅動電路圖。
圖10A是圖9的16相位720級閘極驅動電路的起始訊號波形圖。
圖10B是圖9的16相位720級閘極驅動電路的第1級閘極驅動單元在節點An的起始訊號的最高電壓值。
圖10C是圖9的16相位720級閘極驅動電路的第1級閘極驅動單元在節點GN的起始訊號的最高電壓值。
圖10D是圖9的16相位720級閘極驅動電路的截止訊號波形圖。
圖10E是圖9的16相位720級閘極驅動電路的最後一級閘極驅動單元在節點An所輸出的截止訊號的最高電壓值。
圖10F是圖9的16相位720級閘極驅動電路的最後一級閘極驅動單元在節點GN所輸出的截止訊號的最高電壓值。
圖11是應用本申請的12相位720級的閘極驅動電路的圖式。
圖12是應用本申請的8相位720級的閘極驅動電路的圖式。
圖13是應用本申請的4相位720級的閘極驅動電路的圖式。 FIG. 1 is a charging time-voltage curve diagram of a conventional size-reduced pixel electrode.
FIG. 2 is a prior art multi-phase pixel electrode charging time-voltage curve.
FIG. 3 is a block diagram of a display device according to an embodiment of the present application.
FIG. 4 is a start signal of each gate driving unit in a display device according to the present application.
FIG. 5 is a cut-off signal of each gate driving unit in a display device according to the present application.
FIG. 6 is a detailed circuit diagram of a single-stage gate driving unit.
FIG. 7 is a circuit diagram of a 16-phase 720-level gate driving circuit to which the present application is not applied.
FIG. 8A is a waveform diagram of a start signal of the 16-phase 720-level gate driving circuit of FIG. 7.
FIG. 8B is the highest voltage value of the start signal of the first-stage gate driving unit of the 16-phase 720-stage gate driving circuit of FIG. 7 at the node An.
FIG. 8C is the highest voltage value of the start signal of the first-stage gate driving unit of the 16-phase 720-stage gate driving circuit of FIG. 7 at the node GN.
FIG. 8D is a waveform diagram of the cutoff signal of the 16-phase 720-level gate driving circuit of FIG. 7.
FIG. 8E is the highest voltage value of the cut-off signal output by the last-stage gate driving unit of the 16-phase 720-stage gate driving circuit of FIG. 7 at the node An.
FIG. 8F is the highest voltage value of the cut-off signal output by the last-stage gate driving unit of the 16-phase 720-stage gate driving circuit of FIG. 7 at the node GN.
FIG. 9 is a diagram of a 16-phase 720-level gate driving circuit to which the present application is applied.
FIG. 10A is a waveform diagram of a start signal of the 16-phase 720-level gate driving circuit of FIG. 9.
FIG. 10B is the highest voltage value of the start signal of the first-stage gate driving unit of the 16-phase 720-stage gate driving circuit of FIG. 9 at the node An.
FIG. 10C is the highest voltage value of the start signal of the first-stage gate driving unit of the 16-phase 720-stage gate driving circuit of FIG. 9 at the node GN.
FIG. 10D is a waveform diagram of the cutoff signal of the 16-phase 720-level gate driving circuit of FIG. 9.
FIG. 10E is the highest voltage value of the cut-off signal output by the last-stage gate driving unit of the 16-phase 720-stage gate driving circuit of FIG. 9 at the node An.
FIG. 10F is the highest voltage value of the cut-off signal output by the last-stage gate driving unit of the 16-phase 720-stage gate driving circuit of FIG. 9 at the node GN.
FIG. 11 is a diagram of a 12-phase 720-level gate driving circuit to which the present application is applied.
FIG. 12 is a diagram of an eight-phase 720-stage gate driving circuit to which the present application is applied.
FIG. 13 is a diagram of a 4-phase 720-level gate driving circuit to which the present application is applied.

Claims

一種顯示裝置，包括：
一時序控制單元，提供多個時脈訊號；
一顯示面板，包括：
一畫素陣列，具有多個畫素單元；以及
一閘極驅動電路，耦接該時序控制單元及該畫素陣列，該閘極驅動電路包括多個閘極驅動單元，其中每一個該閘極驅動單元各具有一時脈訊號、一起始訊號以及一截止訊號；
其中，多個該閘極驅動單元之多個該起始訊號之波寬將被聯集，以產生一起始共用訊號，並根據最後一個該閘極驅動單元所輸出的該截止訊號，進而產生一截止共用訊號。 A display device includes:
A timing control unit that provides multiple clock signals;
A display panel including:
A pixel array having a plurality of pixel units; and a gate driving circuit coupled to the timing control unit and the pixel array. The gate driving circuit includes a plurality of gate driving units, each of which is a gate electrode. The driving units each have a clock signal, a start signal and a cut-off signal;
Wherein, the wave widths of the plurality of the start signals of the plurality of gate driving units will be combined to generate an initial common signal, and according to the cut-off signal output by the last gate driving unit, a Cut off the shared signal.

如申請專利範圍第1項所述之顯示裝置，其中該波寬為各起始訊號位於高位準的波幅寬度。The display device according to item 1 of the scope of patent application, wherein the wave width is the amplitude width of each starting signal at a high level.

如申請專利範圍第1項所述之顯示裝置，其中該起始共用訊號的初始時脈上升緣為第一級閘極驅動單元之起始訊號的初始時脈上升緣，而該起始共用訊號的初始時脈下降緣為最後一級閘極驅動單元之起始訊號的初始時脈下降緣。The display device according to item 1 of the scope of patent application, wherein the initial clock rising edge of the initial common signal is the initial clock rising edge of the initial signal of the first-level gate driving unit, and the initial common signal The initial clock falling edge of is the initial clock falling edge of the start signal of the last-stage gate driving unit.

如申請專利範圍第1項所述之顯示裝置，其中該多個閘極驅動單元為N級陣列閘極驅動(gate driver on array, GOA)電路。The display device according to item 1 of the scope of patent application, wherein the plurality of gate driving units are N-level gate driver on array (GOA) circuits.

如申請專利範圍第4項所述之顯示裝置，其中各級該閘極驅動電路的閘極輸入該起始共用訊號。The display device as described in item 4 of the scope of patent application, wherein the gates of the gate driving circuits at all levels input the initial common signal.

如申請專利範圍第4項所述之顯示裝置，其中閘極驅動電路由多個電晶體所組成。The display device according to item 4 of the scope of patent application, wherein the gate driving circuit is composed of a plurality of transistors.

如申請專利範圍第6項所述之顯示裝置，其中多個該電晶體在不同時間下，會個別在不同時間區間導通，提供不同的充放電路徑。According to the display device described in item 6 of the scope of patent application, a plurality of the transistors will be turned on at different time intervals at different times to provide different charging and discharging paths.

如申請專利範圍第1項所述之顯示裝置，其中該閘極驅動電路之截止共用訊號的初始時脈上升緣為最後一級該閘極驅動單元之截止訊號的初始時脈上升緣，而該截止共用訊號的初始時脈下降緣為最後一級該閘極驅動單元之截止訊號的初始時脈下降緣。The display device according to item 1 of the scope of patent application, wherein the initial rising edge of the cutoff common signal of the gate driving circuit is the initial rising edge of the cutoff signal of the gate driving unit in the last stage, and the cutoff The initial clock falling edge of the common signal is the initial clock falling edge of the cut-off signal of the gate drive unit in the last stage.

如申請專利範圍第1項所述之顯示裝置，更包括一積體電路，提供一外部截止訊號與一外部起始訊號予該閘極驅動電路，其中，該外部起始訊號輸入至第一個該閘極驅動單元，該外部截止訊號輸入至最後一個該閘極驅動單元。The display device described in item 1 of the patent application scope further includes an integrated circuit that provides an external cut-off signal and an external start signal to the gate driving circuit, wherein the external start signal is input to the first For the gate driving unit, the external cut-off signal is input to the last gate driving unit.

如申請專利範圍第1項所述之顯示裝置，其中該時序控制單元更配置在該顯示面板中。The display device according to item 1 of the scope of patent application, wherein the timing control unit is further disposed in the display panel.