TWM571104U - Circuit board - Google Patents

Abstract

一種電路板，包含：基板、第一圖案化線路層、至少三塊第一擋塊以及第一介電材料。基板包含第一表面，其中第一表面包含第一有效區以及第一無效區，且第一無效區圍繞第一有效區。第一圖案化線路層配置於第一有效區中。所述至少三塊第一擋塊配置於第一有效區以及第一無效區之交界處，且不接觸第一圖案化線路層，其中所述至少三塊第一擋塊實質上圍繞第一圖案化線路層，所述至少三塊第一擋塊彼此之間不接觸，兩相鄰第一擋塊之間形成第一缺口，第一缺口之寬度為10μm至80μm。第一介電材料配置於第一表面上，且覆蓋第一圖案化線路層以及第一擋塊。 A circuit board comprising: a substrate, a first patterned circuit layer, at least three first stops, and a first dielectric material. The substrate includes a first surface, wherein the first surface includes a first active area and a first inactive area, and the first inactive area surrounds the first active area. The first patterned circuit layer is disposed in the first active area. The at least three first stops are disposed at a boundary between the first active area and the first inactive area and do not contact the first patterned circuit layer, wherein the at least three first blocks substantially surround the first pattern The at least three first stoppers are not in contact with each other, and a first notch is formed between the two adjacent first stoppers, and the first notch has a width of 10 μm to 80 μm. The first dielectric material is disposed on the first surface and covers the first patterned circuit layer and the first stopper.

Description

電路板 Circuit board

本揭露內容實施例是關於一種電路板，特別是一種具有擋塊結構的電路板。 The present disclosure relates to a circuit board, and more particularly to a circuit board having a stopper structure.

現今各種電子產品廣泛地用於例如個人電腦、行動電話、數位相機、以及其他電子設備中。隨著電子產業的發達，電子產品無不往輕薄短小與功能多樣化的方向設計，此時也相對要求半導體封裝技術的提升。為了增加印刷電路板的應用，可依據需求將單面版的印刷電路板設計成雙面板，甚至是多層板的態樣，以增加其內部用來線路佈局的空間，並將許多不同種類的主動電子元或被動電子元件，例如連接器、晶片或者是光電元件，依據需求配置在增層的印刷電路板上，以增加其使用功能。 Various electronic products are widely used in, for example, personal computers, mobile phones, digital cameras, and other electronic devices. With the development of the electronics industry, electronic products are designed in the direction of lightness, thinness, and diversification. At this time, semiconductor packaging technology is relatively required. In order to increase the application of printed circuit boards, single-sided printed circuit boards can be designed as double-sided or even multi-layer boards according to requirements, in order to increase the space used for circuit layout inside, and many different kinds of active Electronic components or passive electronic components, such as connectors, wafers or optoelectronic components, are placed on the printed circuit board as needed to increase their functionality.

由於電路板上的圖案化線路層的線路排列是依據需求而設計，因此線路與線路之間的間距可為等距或非等距，因此，習知進行增層法製備多層板時，在欲壓合的表面上的介電材料容易產生局部厚度不均勻的現象，甚至線路與線路之間可能產生空隙。空隙的產生，將或多或少影響電路板的結構強度，使得無法在如振動測試、衝擊測試、可焊性測 試等等的可靠性測試中得到保證。 Since the line arrangement of the patterned circuit layer on the circuit board is designed according to requirements, the spacing between the lines and the lines can be equidistant or non-equidistant. Therefore, it is conventional to carry out the layering method to prepare the multi-layer board. The dielectric material on the pressed surface is prone to local unevenness in thickness, and even voids may occur between the line and the line. The generation of voids will affect the structural strength of the board more or less, making it impossible to perform tests such as vibration test, impact test, and solderability. Tests and other reliability tests are guaranteed.

鑒於以上習知技術的缺失，本揭露內容實施例提出一種具有擋塊結構的電路板。藉由在電路板的表面上配置擋塊結構，可使在進行增層法製備多層板時，在欲壓合的表面上的線路層之間能均勻地填充介電材料。 In view of the above-mentioned deficiencies of the prior art, the disclosed embodiments propose a circuit board having a stopper structure. By arranging the stopper structure on the surface of the circuit board, it is possible to uniformly fill the dielectric material between the wiring layers on the surface to be pressed when the multilayering method is performed by the build-up method.

在本揭露內容的一實施例中，揭露一種電路板，包含基板，其包含具有第一有效區以及第一無效區的第一表面，其中第一無效區圍繞第一有效區；第一圖案化線路層，配置於第一有效區中；至少三塊第一擋塊，配置於第一有效區以及第一無效區之交界處，且不接觸第一圖案化線路層，其中第一擋塊實質上圍繞第一圖案化線路層，第一擋塊彼此之間不接觸，第一擋塊之相鄰兩者之間形成第一缺口，第一缺口之寬度為10μm至80μm；以及第一介電材料，配置於第一表面上，且覆蓋第一圖案化線路層以及第一擋塊。 In an embodiment of the disclosure, a circuit board is disclosed, including a substrate including a first surface having a first active area and a first inactive area, wherein the first inactive area surrounds the first active area; a circuit layer disposed in the first active area; at least three first blocks disposed at a boundary between the first active area and the first inactive area and not contacting the first patterned circuit layer, wherein the first block is substantially Surrounding the first patterned circuit layer, the first stoppers are not in contact with each other, and a first gap is formed between adjacent ones of the first stoppers, the first notch having a width of 10 μm to 80 μm; and the first dielectric The material is disposed on the first surface and covers the first patterned circuit layer and the first stopper.

在本揭露內容的一實施例中，電路板更包含第二圖案化線路層，配置於和第一表面相對配置的第二表面上，其中第二表面包含第二有效區以及第二無效區，且第二無效區圍繞第二有效區；至少一導通孔導體，貫通基板，並於第一表面上和第二表面上具有一寬度；至少三塊第二擋塊，配置於第二有效區以及第二無效區之交界處，且不接觸第二圖案化線路層，其中第二擋塊實質上圍繞第二圖案化線路層，第二擋塊彼此之間不接觸，第二擋塊之相鄰兩者之間形成第二缺口，第二 缺口之寬度為10μm至80μm；以及第二介電材料，配置於第二表面上，且覆蓋第二圖案化線路層、至少一導通孔導體，以及第二擋塊。 In an embodiment of the disclosure, the circuit board further includes a second patterned circuit layer disposed on the second surface disposed opposite to the first surface, wherein the second surface includes the second active area and the second inactive area. And the second inactive area surrounds the second active area; the at least one via conductor extends through the substrate and has a width on the first surface and the second surface; at least three second stops are disposed in the second active area and a junction of the second inactive area, and not contacting the second patterned circuit layer, wherein the second stop substantially surrounds the second patterned circuit layer, the second stops are not in contact with each other, and the second stop is adjacent Forming a second gap between the two, second The width of the notch is 10 μm to 80 μm; and the second dielectric material is disposed on the second surface and covers the second patterned wiring layer, the at least one via conductor, and the second stopper.

在本揭露內容的一實施例中，電路板更包含第三圖案化線路層，配置於第一介電材料之上；第四圖案化線路層，配置於第二介電材料之上；以及至少三塊第三擋塊，配置於第一介電材料上且不接觸第三圖案化線路層，並對準第一擋塊，其中第三擋塊實質上圍繞第三圖案化線路層，第三擋塊彼此之間不接觸，第三擋塊之相鄰兩者之間形成第三缺口，第三缺口之寬度為10μm至80μm；以及至少三塊第四擋塊，配置於第二介電材料上且不接觸第四圖案化線路層，並對準第二擋塊，其中第四擋塊實質上圍繞第四圖案化線路層，第四擋塊彼此之間不接觸，第四擋塊之相鄰兩者之間形成第四缺口，第四缺口之寬度為10μm至80μm。 In an embodiment of the disclosure, the circuit board further includes a third patterned circuit layer disposed on the first dielectric material, and a fourth patterned circuit layer disposed on the second dielectric material; The third block is disposed on the first dielectric material and does not contact the third patterned circuit layer and is aligned with the first block, wherein the third block substantially surrounds the third patterned circuit layer, and the third The stoppers are not in contact with each other, and a third notch is formed between adjacent ones of the third stoppers, the third notch having a width of 10 μm to 80 μm; and at least three fourth stoppers disposed on the second dielectric material Up and down without contacting the fourth patterned circuit layer, and aligning with the second block, wherein the fourth block substantially surrounds the fourth patterned circuit layer, the fourth block does not contact each other, and the fourth block phase A fourth gap is formed between the adjacent ones, and the width of the fourth notch is 10 μm to 80 μm.

在本揭露內容的一實施例中，其中第一擋塊、第二擋塊、第三擋塊以及第四擋塊之高度或寬度為相同。 In an embodiment of the disclosure, the heights or widths of the first block, the second block, the third block, and the fourth block are the same.

在本揭露內容的一實施例中，其中第一擋塊之高度大於或等於第一圖案化線路層之高度，第二擋塊之高度大於或等於第二圖案化線路層之高度，第三擋塊之高度大於或等於第三圖案化線路層之高度，以及第四擋塊之高度大於或等於第四圖案化線路層之高度。 In an embodiment of the disclosure, wherein the height of the first block is greater than or equal to the height of the first patterned circuit layer, the height of the second block is greater than or equal to the height of the second patterned circuit layer, and the third block The height of the block is greater than or equal to the height of the third patterned circuit layer, and the height of the fourth block is greater than or equal to the height of the fourth patterned circuit layer.

在本揭露內容的一實施例中，其中第一擋塊之材質係相同於第一圖案化線路層，第二擋塊之材質係相同於第二圖案化線路層，第三擋塊之材質係相同於第三圖案化線路層， 以及第四擋塊之材質係相同於第四圖案化線路層。 In an embodiment of the disclosure, the material of the first block is the same as the first patterned circuit layer, the material of the second block is the same as the second patterned circuit layer, and the material of the third block is Same as the third patterned circuit layer, And the material of the fourth block is the same as the fourth patterned circuit layer.

在本揭露內容的一實施例中，其中每個第一擋塊包含至多三塊不互相接觸的第一子擋塊，每個第二擋塊包含至多三塊不互相接觸的第二子擋塊，每個第三擋塊包含至多三塊不互相接觸的第三子擋塊，以及每個第四擋塊包含至多三塊不互相接觸的第四子擋塊。 In an embodiment of the disclosure, each of the first stops includes at most three first sub-blocks that are not in contact with each other, and each of the second blocks includes at most three second sub-blocks that are not in contact with each other. Each third stop includes at most three third sub-blocks that are not in contact with each other, and each fourth block includes at most three fourth sub-blocks that are not in contact with each other.

在本揭露內容的一實施例中，其中不互相接觸的第一子擋塊之相鄰兩者之間形成第一子缺口、不互相接觸的第二子擋塊之相鄰兩者之間形成第二子缺口、不互相接觸的第三子擋塊之相鄰兩者之間形成第三子缺口，以及不互相接觸的第四子擋塊之相鄰兩者之間形成第四子缺口。 In an embodiment of the present disclosure, a first sub-gap is formed between adjacent ones of the first sub-blocks that are not in contact with each other, and a second sub-block that does not contact each other is formed between adjacent ones of the two sub-blocks A second sub-gap, a third sub-gap between adjacent ones of the third sub-blocks that do not contact each other, and a fourth sub-gap between the adjacent ones of the fourth sub-stops that are not in contact with each other.

在本揭露內容的一實施例中，其中第一子缺口之寬度小於或等於第一缺口之寬度、第二子缺口之寬度小於或等於第二缺口之寬度、第三子缺口之寬度小於或等於第三缺口之寬度，以及第四子缺口之寬度小於或等於第四缺口之寬度。 In an embodiment of the disclosure, the width of the first sub-notch is less than or equal to the width of the first notch, the width of the second sub-gap is less than or equal to the width of the second notch, and the width of the third sub-gap is less than or equal to The width of the third notch, and the width of the fourth sub-notch are less than or equal to the width of the fourth notch.

在本揭露內容的一實施例中，其中基板為玻璃基板、有機基板、矽基板、碳化矽基板、或是陶瓷基板。 In an embodiment of the disclosure, the substrate is a glass substrate, an organic substrate, a germanium substrate, a tantalum carbide substrate, or a ceramic substrate.

綜上所述，本揭露的技術方案與現有技術相比具有明顯的優點和有益的效果。 In summary, the technical solution of the present disclosure has obvious advantages and beneficial effects compared with the prior art.

以下將以實施方式對上述之說明做詳細的描述，並對本揭露之技術方案提供更進一步的解釋。 The above description will be described in detail in the following embodiments, and further explanation of the technical solutions of the disclosure will be provided.

100‧‧‧前驅電路板 100‧‧‧Precursor board

101‧‧‧基板 101‧‧‧Substrate

102‧‧‧第一表面 102‧‧‧ first surface

103‧‧‧第一有效區 103‧‧‧First effective area

104‧‧‧第一無效區 104‧‧‧First invalid area

105‧‧‧第一圖案化線路層 105‧‧‧First patterned circuit layer

106‧‧‧第一有效區和第一無效區的交界處 106‧‧‧ Junction between the first effective area and the first invalid area

107‧‧‧第一擋塊 107‧‧‧First stop

108‧‧‧第二表面 108‧‧‧second surface

109‧‧‧第二有效區 109‧‧‧Second effective area

110‧‧‧第二無效區 110‧‧‧Second ineffective area

111‧‧‧第二圖案化線路層 111‧‧‧Second patterned circuit layer

112‧‧‧第二有效區和第二無效區的交界處 112‧‧‧ Junction between the second effective area and the second invalid area

113‧‧‧第二擋塊 113‧‧‧second stop

114‧‧‧導通孔導體 114‧‧‧via conductor

115‧‧‧第一缺口 115‧‧‧ first gap

116‧‧‧第二缺口 116‧‧‧ second gap

201‧‧‧第一介電材料 201‧‧‧First dielectric material

202‧‧‧第二介電材料 202‧‧‧Second dielectric material

301‧‧‧第一盲孔 301‧‧‧ first blind hole

302‧‧‧第二盲孔 302‧‧‧Second blind hole

401‧‧‧第一銅層 401‧‧‧First copper layer

402‧‧‧第二銅層 402‧‧‧Second copper layer

501‧‧‧第一抗鍍乾膜層 501‧‧‧First anti-plated dry film

502‧‧‧第二抗鍍乾膜層 502‧‧‧Second anti-plated dry film

701‧‧‧第三擋塊 701‧‧‧third stop

702‧‧‧第四擋塊 702‧‧‧4th stop

901‧‧‧第三抗鍍乾膜層 901‧‧‧ Third anti-plating dry film

902‧‧‧第四抗鍍乾膜層 902‧‧‧fourth anti-plating dry film

1001‧‧‧第一開口部 1001‧‧‧First opening

1002‧‧‧第二開口部 1002‧‧‧second opening

1101‧‧‧第一導體層 1101‧‧‧First conductor layer

1102‧‧‧第二導體層 1102‧‧‧Second conductor layer

1301‧‧‧第一盲孔導體 1301‧‧‧First blind via conductor

1302‧‧‧第三圖案化線路層 1302‧‧‧The third patterned circuit layer

1303‧‧‧第二盲孔導體 1303‧‧‧Second blind hole conductor

1304‧‧‧第四圖案化線路層 1304‧‧‧fourth patterned circuit layer

1400‧‧‧電路板 1400‧‧‧ boards

1401‧‧‧第一絕緣保護層 1401‧‧‧First insulation protection layer

1402‧‧‧第一導電凸塊 1402‧‧‧First conductive bump

1403‧‧‧第二絕緣保護層 1403‧‧‧Second insulation protection layer

1404‧‧‧第二導電凸塊 1404‧‧‧Second conductive bump

1601‧‧‧第一子擋塊 1601‧‧‧First sub-block

1602‧‧‧第一子缺口 1602‧‧‧First child gap

1603‧‧‧第二子擋塊 1603‧‧‧Second sub-block

1604‧‧‧第二子缺口 1604‧‧‧ second sub-gap

W₁‧‧‧第一缺口的寬度(四塊第一擋塊的實施例) W ₁ ‧‧‧Width of the first notch (example of four first stops)

W₂‧‧‧第二缺口的寬度(四塊第二擋塊的實施例) W ₂ ‧‧‧Width of the second notch (example of four second stops)

W₃‧‧‧第一缺口的寬度(三塊第一擋塊的實施例) W ₃ ‧‧‧Width of the first notch (example of three first stops)

W₄‧‧‧第二缺口的寬度(三塊第二擋塊的實施例) W ₄ ‧‧‧Width of the second notch (example of three second stops)

W₅‧‧‧第一子缺口的寬度(四塊第一擋塊的實施例) W ₅ ‧‧‧Width of the first sub-notch (example of four first stops)

W₆‧‧‧第二子缺口的寬度(四塊第二擋塊的實施例) W ₆ ‧‧‧Width of the second sub-notch (example of four second stops)

為使本揭露之上述和其他目的、特徵、優點與 實施例能更明顯易懂，請詳閱以下的詳細敘述並搭配對應的圖式：第1A圖繪示根據本揭露內容多個實施例前驅電路板在某個製造電路板階段的剖面示意圖；第1B圖繪示根據本揭露內容多個實施例前驅電路板的俯視圖或仰視圖；第2圖至第13圖繪示根據本揭露內容多個實施例製造電路板的方法的剖面示意圖；第14A圖係假定第13圖為根據最終電路層數需求的電路板的根據本揭露內容多個實施例的剖面示意圖；第14B圖為繪示第14A圖中的根據本揭露內容多個實施例電路板的俯視圖或仰視圖；第15圖繪示了根據本揭露內容另一實施例的前驅電路板的俯視圖或仰視圖；以及第16圖繪示了根據本揭露內容又一實施例的前驅電路板的俯視圖或仰視圖。 The above and other objects, features, advantages and advantages of the present disclosure are The embodiment can be more clearly understood. Please refer to the following detailed description in conjunction with the corresponding drawings: FIG. 1A is a cross-sectional view showing a predecessor circuit board in a certain manufacturing circuit board stage according to various embodiments of the present disclosure; 1B is a top or bottom view of a precursor circuit board according to various embodiments of the present disclosure; and FIGS. 2 to 13 are cross-sectional views showing a method of manufacturing a circuit board according to various embodiments of the present disclosure; FIG. 14A It is assumed that FIG. 13 is a schematic cross-sectional view of a circuit board according to the requirements of the final circuit layer number according to various embodiments of the present disclosure; FIG. 14B is a diagram showing a circuit board according to various embodiments of the present disclosure in FIG. 14A FIG. 15 is a top view or a bottom view of a front circuit board according to another embodiment of the present disclosure; and FIG. 16 is a top view of a front circuit board according to still another embodiment of the present disclosure. Or bottom view.

為了使本揭露內容的敘述更加詳盡與完備，可參照所附的圖式以及以下所述各種實施例，圖式中相同的號碼代表相同或相似的元件。另一方面，眾所周知的元件與步驟並未描述於實施例中，以避免對本揭露造成不必要的限制。 In order to make the description of the present disclosure more detailed and complete, reference is made to the accompanying drawings and the various embodiments described below. On the other hand, well-known elements and steps are not described in the embodiments to avoid unnecessarily limiting the disclosure.

下文針對了本揭露內容的實施態樣與具體實施例提出了說明性的描述，但這並非實施或運用本揭露內容具體實 施例的唯一形式。以下所揭露的各實施例，在有益的情形下可相互組合或取代，也可在一實施例中附加其他的實施例，而無須進一步的記載或說明。 The following description of the embodiments of the present disclosure and the specific embodiments are provided for illustrative description, but this is not an implementation or application of the disclosure. The only form of the case. The embodiments disclosed herein may be combined or substituted with each other in an advantageous manner, and other embodiments may be added to an embodiment without further description or description.

儘管本揭露內容中可使用“第一”、“第二”等用語來描述各種元件、區域、層以及/或部分，但是這些用語不應限制此等元件、區域、層以及/或部分。這些用語只是用來將某一元件、區域、層以及/或部分區別於另一區域、層以及/或部分。因此，在不脫離本揭露內容的情況下，下文所述的第一元件、區域、層或部分可稱為第二元件、區域、層或部分。 The terms "first", "second", and the like may be used to describe various elements, regions, layers and/or portions in the present disclosure, but such terms are not limited to such elements, regions, layers and/or portions. These terms are only used to distinguish one element, region, layer and/or portion from another region, layer and/or portion. Thus, a first element, region, layer or portion described hereinafter may be referred to as a second element, region, layer or portion, without departing from the disclosure.

另外應注意的是，在本文中使用空間相對用語，例如「下方」、「之下」、「上方」、「之上」等，這是為了便於敘述一元件或特徵與另一元件或特徵之間的相對關係，如圖中所繪示。這些空間上的相對用語的真實意義包含其他的方位。例如，當圖示上下翻轉180度時，一元件與另一元件之間的關係，可能從「下方」、「之下」變成「上方」、「之上」。此外，本文中所使用的空間上的相對敘述也應作相同地解釋。 In addition, it should be noted that spatial relative terms such as "below", "below", "above", "above", etc. are used herein to facilitate the description of one element or feature and another element or feature. The relative relationship between the two is shown in the figure. The true meaning of these spatial relative terms includes other orientations. For example, when the illustration is flipped up and down by 180 degrees, the relationship between one component and another component may change from "below" or "below" to "above" and "above". Moreover, the spatially relative narratives used herein should also be interpreted identically.

第1A圖至第14B圖繪示根據本揭露內容多個實施例製造電路板的方法在不同製程階段的剖面示意圖。首先，請同時參閱第1A圖和第1B圖。第1A圖繪示前驅電路板100在某個製造電路板階段的剖面示意圖，第1B圖繪示前驅電路板100俯視圖或仰視圖。前驅電路板100包含基板101，其包含第一表面102，其中基板101可為玻璃基板、有機基板、矽基板、碳化矽基板、或是陶瓷基板。第一表面102包含第一 有效區103以及第一無效區104，第一無效區104圍繞著第一有效區103。前驅電路板100也包含第一圖案化線路層105，其配置於第一有效區103中。前驅電路板100更包含至少三塊第一擋塊107，例如四塊第一擋塊107，配置在第一有效區103和第一無效區104的交界處106。第一擋塊107與第一圖案化線路層105不互相接觸，且第一擋塊107彼此之間也不互相接觸，又上述至少三塊第一擋塊107大致上圍繞第一圖案化線路層105。在一些實施例中，第一擋塊107的材質與第一圖案化線路層105可為相同，例如為電鍍銅。在一些實施例中，第一擋塊107的材質與第一圖案化線路層105可不為相同。另外，第一擋塊107可在第一圖案化線路層105形成之前、期間或之後形成。 1A to 14B are schematic cross-sectional views showing a method of manufacturing a circuit board according to various embodiments of the present disclosure at different process stages. First, please refer to both Figure 1A and Figure 1B. FIG. 1A is a cross-sectional view showing a state of the front circuit board 100 at a certain manufacturing circuit board, and FIG. 1B is a top view or a bottom view of the front circuit board 100. The precursor circuit board 100 includes a substrate 101 including a first surface 102, wherein the substrate 101 may be a glass substrate, an organic substrate, a germanium substrate, a tantalum carbide substrate, or a ceramic substrate. The first surface 102 includes the first The active area 103 and the first inactive area 104 surround the first active area 103. The precursor circuit board 100 also includes a first patterned circuit layer 105 disposed in the first active area 103. The precursor circuit board 100 further includes at least three first stops 107, such as four first stops 107, disposed at a junction 106 between the first active area 103 and the first inactive area 104. The first stopper 107 and the first patterned wiring layer 105 are not in contact with each other, and the first stoppers 107 are not in contact with each other, and the at least three first stoppers 107 substantially surround the first patterned circuit layer. 105. In some embodiments, the material of the first stopper 107 may be the same as the first patterned wiring layer 105, such as electroplated copper. In some embodiments, the material of the first stopper 107 may not be the same as the first patterned wiring layer 105. In addition, the first stopper 107 may be formed before, during or after the formation of the first patterned wiring layer 105.

同樣地，基板101也包含相對配置於第一表面102的第二表面108。第二表面108包含第二有效區109以及第二無效區110，第二無效區110係圍繞著第二有效區109。前驅電路板100也包含第二圖案化線路層111，其配置於第二有效區109中。前驅電路板100更包含至少三塊第二擋塊113，例如四塊第二擋塊113，配置在第二有效區109和第二無效區110的交界處112。第二擋塊113與第二圖案化線路層111不互相接觸，且第二擋塊113彼此之間也不互相接觸，又所述至少三塊第二擋塊113實質上圍繞第二圖案化線路層111。在一些實施例中，第二擋塊113的材質與第二圖案化線路層111可為相同，例如為電鍍銅。在一些實施例中，第二擋塊113的材質與第二圖案化線路層111可不為 相同。另外，第二擋塊113可在第二圖案化線路層111形成之前、期間或之後形成。為了實現第一圖案化線路層105和第二圖案化線路層111的電性連接，前驅電路板100包含了至少一導通孔導體114，其貫通基板101，並連接第一圖案化線路層105和第二圖案化線路層111。 Likewise, the substrate 101 also includes a second surface 108 that is disposed opposite the first surface 102. The second surface 108 includes a second active area 109 and a second inactive area 110 that surrounds the second active area 109. The precursor circuit board 100 also includes a second patterned circuit layer 111 disposed in the second active area 109. The precursor circuit board 100 further includes at least three second stops 113, such as four second stops 113, disposed at the interface 112 of the second active area 109 and the second inactive area 110. The second stopper 113 and the second patterned wiring layer 111 are not in contact with each other, and the second stoppers 113 are not in contact with each other, and the at least three second stoppers 113 substantially surround the second patterned wiring. Layer 111. In some embodiments, the material of the second stopper 113 and the second patterned wiring layer 111 may be the same, for example, electroplated copper. In some embodiments, the material of the second stopper 113 and the second patterned circuit layer 111 may not be the same. In addition, the second stopper 113 may be formed before, during or after the formation of the second patterned wiring layer 111. In order to achieve electrical connection between the first patterned circuit layer 105 and the second patterned circuit layer 111, the precursor circuit board 100 includes at least one via conductor 114 penetrating through the substrate 101 and connecting the first patterned circuit layer 105 and The second patterned circuit layer 111.

請繼續參閱第1B圖，在前驅電路板100中，四塊第一擋塊107實質上圍繞第一圖案化線路層105。兩相鄰的第一擋塊107之間形成第一缺口115。第一缺口115的寬度W₁為10μm至80μm之間，更佳為20μm至60μm之間，最佳為40μm至50μm之間。 Continuing to refer to FIG. 1B, in the precursor circuit board 100, four first stops 107 substantially surround the first patterned circuit layer 105. A first gap 115 is formed between the two adjacent first stoppers 107. The width W ₁ of the first notch 115 is between 10 μm and 80 μm, more preferably between 20 μm and 60 μm, and most preferably between 40 μm and 50 μm.

請再繼續參閱第1B圖，在前驅電路板100中，四塊第二擋塊113圍繞第二圖案化線路層111。兩相鄰的第二擋塊113之間形成第二缺口115。第二缺口116的寬度W₂為10μm至80μm之間，更佳為20μm至60μm之間，最佳為40μm至50μm之間。 Referring again to FIG. 1B, in the precursor circuit board 100, four second stoppers 113 surround the second patterned wiring layer 111. A second notch 115 is formed between the two adjacent second stoppers 113. The width W ₂ of the second notch 116 is between 10 μm and 80 μm, more preferably between 20 μm and 60 μm, and most preferably between 40 μm and 50 μm.

為使後續進行增層法製備多層板時，在欲壓合的表面上的線路層之間能均勻地填充介電材料，擋塊的高度須大於或等於與圖案化線路層的高度。也就是說，第一擋塊107的高度須大於或等於第一圖案化線路層105的高度，第二擋塊113的高度須大於或等於第二圖案化線路層111的高度。 In order to prepare the multilayer board by the subsequent build-up method, the dielectric material can be uniformly filled between the circuit layers on the surface to be pressed, and the height of the stopper must be greater than or equal to the height of the patterned wiring layer. That is, the height of the first stopper 107 must be greater than or equal to the height of the first patterned wiring layer 105, and the height of the second stopper 113 must be greater than or equal to the height of the second patterned wiring layer 111.

接著，請參閱第2圖，將第一介電材料201壓合於第一表面102上，以使第一介電材料201覆蓋第一圖案化線路層105、導通孔導體114以及第一擋塊107。藉由第一 檔塊107的設置，線路層之間能均勻地填充第一介電材料201，而不發生線路層之間因介電材料填充不均產生空隙甚至無填充介電材料的情形。在一些實施例中，第一介電材料201可包含玻璃纖維(prepreg)和環氧樹酯。因此，將利用玻璃纖維在浸膠半乾成膠片後再經高溫軟化液化而呈現黏著性，並經由壓合與再硬化後達成前驅電路板100的增厚。 Next, referring to FIG. 2, the first dielectric material 201 is pressed onto the first surface 102 such that the first dielectric material 201 covers the first patterned wiring layer 105, the via conductor 114, and the first stopper. 107. By the first The arrangement of the blocks 107 allows the first dielectric material 201 to be uniformly filled between the circuit layers without occurrence of voids or even filling of dielectric materials between the circuit layers due to uneven filling of the dielectric material. In some embodiments, the first dielectric material 201 can comprise prepreg and epoxy resin. Therefore, the glass fiber is subjected to high-temperature softening and liquefaction after being dipped into a film, and the adhesiveness is exhibited, and the thickness of the precursor circuit board 100 is achieved by press-fitting and re-hardening.

同樣地，將第二介電材料202壓合於第二表面108上，以使第二介電材料202均勻地覆蓋第二圖案化線路層111、導通孔導體114，以及第二擋塊113。在一些實施例中，第二介電材料202可包含玻璃纖維(prepreg)和環氧樹酯。 Similarly, the second dielectric material 202 is pressed onto the second surface 108 such that the second dielectric material 202 uniformly covers the second patterned wiring layer 111, the via conductors 114, and the second stoppers 113. In some embodiments, the second dielectric material 202 can comprise prepreg and epoxy resin.

接著，請參閱第3圖，在第一介電材料201中形成第一盲孔301，其中第一盲孔301暴露了部分的導通孔導體114。同樣地，也在第二介電材料202中形成第二盲孔302，而第二盲孔302也暴露了部分的導通孔導體114。在一些實施例中，形成第一盲孔301和第二盲孔302的步驟可為雷射製程或其他適合的製程，而使第一盲孔301和第二盲孔302成為雷射盲孔，但本揭露不以此為限制。 Next, referring to FIG. 3, a first blind via 301 is formed in the first dielectric material 201, wherein the first blind via 301 exposes a portion of the via via conductor 114. Likewise, a second blind via 302 is also formed in the second dielectric material 202, while the second blind via 302 also exposes a portion of the via via conductor 114. In some embodiments, the step of forming the first blind hole 301 and the second blind hole 302 may be a laser process or other suitable process, and the first blind hole 301 and the second blind hole 302 are made into a laser blind hole. However, this disclosure is not intended to be limiting.

接著，請參閱第4圖，利用化學鍍製程或濺鍍製程或其他適合的製程在第一介電材料201、第一盲孔301和部分暴露的導通孔導體114上形成第一銅層401，以及在第二介電材料202、第二盲孔302和部分暴露的導通孔導體114上形成第二銅層402。第一銅層401以及第二銅層402可用以提供更精細的導電線路，或者用以提供線路層之間的 導電通路。在一些實施例中，第一銅層401的厚度可相同於第二銅層402的厚度。在一些實施例中，第一銅層401的厚度可不同於第二銅層402的厚度。 Next, referring to FIG. 4, a first copper layer 401 is formed on the first dielectric material 201, the first blind via 301, and the partially exposed via conductor 114 by an electroless plating process or a sputtering process or other suitable process, And forming a second copper layer 402 on the second dielectric material 202, the second blind via 302, and the partially exposed via conductor 114. The first copper layer 401 and the second copper layer 402 can be used to provide finer conductive lines or to provide between circuit layers Conductive path. In some embodiments, the thickness of the first copper layer 401 can be the same as the thickness of the second copper layer 402. In some embodiments, the thickness of the first copper layer 401 can be different than the thickness of the second copper layer 402.

接著，請參閱第5圖，在抗電鍍乾膜的壓合製程中，形成第一抗鍍乾膜層501在第一銅層401上並填充滿第一盲孔301，以及形成第二抗鍍乾膜層502在第二銅層402上並填充滿第二盲孔302。在一些實施例中，第一抗鍍乾膜層501的厚度可相同於第二抗鍍乾膜層502的厚度。在一些實施例中，第一抗鍍乾膜層501的厚度可不同於第二抗鍍乾膜層502的厚度。本揭露的實施例中，第一抗鍍乾膜層501和第二抗鍍乾膜層502可為任何適合的抗電鍍材料。 Next, referring to FIG. 5, in the galvanizing process of the anti-plating dry film, the first anti-plating dry film layer 501 is formed on the first copper layer 401 and filled with the first blind via 301, and the second anti-plating is formed. The dry film layer 502 is on the second copper layer 402 and fills the second blind via 302. In some embodiments, the first anti-plating dry film layer 501 may have the same thickness as the second anti-plating dry film layer 502. In some embodiments, the thickness of the first anti-plating dry film layer 501 may be different from the thickness of the second anti-plating dry film layer 502. In the embodiment of the present disclosure, the first anti-plating dry film layer 501 and the second anti-plating dry film layer 502 may be any suitable anti-plating material.

接著，請參閱第6圖，利用圖案化製程移除部分的第一抗鍍乾膜層501和部分的第二抗鍍乾膜層502，其中圖案化製程可為濕式蝕刻製程或顯影製程或其他適合的製程，但本揭露不以此為限制。具體的，利用圖案化製程將對準第一擋塊107的第一抗鍍乾膜層501的部分移除，以及將對準第二擋塊113的第二抗鍍乾膜層502的部分移除。 Next, referring to FIG. 6 , a portion of the first anti-plating dry film layer 501 and a portion of the second anti-plating dry film layer 502 are removed by a patterning process, wherein the patterning process may be a wet etching process or a developing process or Other suitable processes, but the disclosure is not limited thereto. Specifically, a portion of the first anti-plating dry film layer 501 aligned with the first stopper 107 is removed by a patterning process, and a portion of the second anti-plating dry film layer 502 aligned with the second stopper 113 is moved. except.

接著，請參閱第7圖，在被移除的抗鍍乾膜層的位置形成第三擋塊701和第四擋塊702，其中擋塊可利用任何適合的製程，例如電鍍來形成，但本揭露不以此為限制。具體的，在第一介電材料201上形成彼此不接觸至少三塊第三擋塊701，例如四塊第三擋塊701。上述四塊第三擋塊701的上視圖案可與第1B圖繪示的第一擋塊107相同或相似，且這四塊第三擋塊701對準第1B圖繪示的四塊第一擋塊 107。此外，在第二介電材料202上形成彼此不接觸的至少三個第四擋塊702，例如四塊第四擋塊702。這四塊第四擋塊702的上視圖案可與第1B圖繪示的第二擋塊113相同或相似，這四塊第四擋塊702對準第1B圖繪示的四塊第二擋塊113。第三檔塊701的厚度大於第一銅層401的厚度，第四檔塊702的厚度大於第二銅層402的厚度。 Next, referring to FIG. 7, a third stopper 701 and a fourth stopper 702 are formed at positions of the removed anti-plating dry film layer, wherein the stopper can be formed by any suitable process such as electroplating, but Exposure is not limited to this. Specifically, at least three third stoppers 701, for example, four third stoppers 701 are formed on the first dielectric material 201 without contacting each other. The top view of the four third blocks 701 may be the same as or similar to the first block 107 shown in FIG. 1B, and the four third blocks 701 are aligned with the first four pieces shown in FIG. Stoppers 107. Further, at least three fourth stops 702, such as four fourth stops 702, are formed on the second dielectric material 202 that are not in contact with each other. The top view of the four fourth blocks 702 may be the same as or similar to the second block 113 shown in FIG. 1B. The four fourth blocks 702 are aligned with the four second blocks shown in FIG. Block 113. The thickness of the third block 701 is greater than the thickness of the first copper layer 401, and the thickness of the fourth block 702 is greater than the thickness of the second copper layer 402.

在本揭露中，兩相鄰的第三擋塊701之間形成第三缺口，第三缺口的寬度為10μm至80μm之間。 In the disclosure, a third notch is formed between the two adjacent third stoppers 701, and the width of the third notch is between 10 μm and 80 μm.

同樣地，兩相鄰的第四擋塊702之間形成第四缺口，其中第四缺口的寬度為10μm至80μm之間。 Similarly, a fourth gap is formed between the two adjacent fourth stoppers 702, wherein the width of the fourth notch is between 10 μm and 80 μm.

接著，請參閱第8圖，移除剩下的抗鍍乾膜層。具體的，利用合適製程移除剩下的第一抗鍍乾膜層501和第二抗鍍乾膜層502。 Next, please refer to Figure 8 to remove the remaining dry plating layer. Specifically, the remaining first anti-plating dry film layer 501 and second anti-plating dry film layer 502 are removed by a suitable process.

接著，請參閱第9圖，在乾膜的壓合製程中，形成第三抗鍍乾膜層901在第一銅層401及第三檔塊701上並填滿第一盲孔301，以及形成第四抗鍍乾膜層902在第二銅層402和第四檔塊702上並填滿第二盲孔302。第三抗鍍乾膜層901的厚度大於第三檔塊701的厚度，第四抗鍍乾膜層902的厚度大於第四檔塊702的厚度。在一些實施例中，第三抗鍍乾膜層901的厚度可相同於第四抗鍍乾膜層902的厚度。在一些實施例中，第三抗鍍乾膜層901的厚度可不同於第四抗鍍乾膜層902的厚度。本揭露的實施例中，第三抗鍍乾膜層901和第四抗鍍乾膜層902可為任何適合的抗電鍍材料。 Next, referring to FIG. 9, in the dry film pressing process, the third anti-plating dry film layer 901 is formed on the first copper layer 401 and the third stop 701 and fills the first blind via 301, and is formed. The fourth anti-plating dry film layer 902 is on the second copper layer 402 and the fourth stop 702 and fills the second blind via 302. The thickness of the third anti-plating dry film layer 901 is greater than the thickness of the third step 701, and the thickness of the fourth anti-plating dry film layer 902 is greater than the thickness of the fourth step 702. In some embodiments, the thickness of the third anti-plating dry film layer 901 may be the same as the thickness of the fourth anti-plating dry film layer 902. In some embodiments, the thickness of the third anti-plating dry film layer 901 may be different from the thickness of the fourth anti-plating dry film layer 902. In the embodiment of the present disclosure, the third anti-plating dry film layer 901 and the fourth anti-plating dry film layer 902 may be any suitable anti-plating material.

接著，請參閱第10圖，利用曝光製程與顯影製程在第三抗鍍乾膜層901中形成第一開口部1001，第一開口部1001露出部分的第一銅層401。同樣地，也在第四抗鍍乾膜層902中形成第二開口部1002，第二開口部1002露出部分的第二銅層402。 Next, referring to FIG. 10, the first opening portion 1001 is formed in the third plating resist dry film layer 901 by the exposure process and the developing process, and the first opening portion 1001 exposes a portion of the first copper layer 401. Similarly, the second opening portion 1002 is also formed in the fourth plating resist dry film layer 902, and the second opening portion 1002 exposes a portion of the second copper layer 402.

接著，請參閱第11圖，可利用合適製程，例如電鍍，沉積第一導體層1101在第一開口部1001中，並填滿第一盲孔301。同樣地，沉積第二導體層1102在第二開口部1002中，並填滿第二盲孔302。 Next, referring to FIG. 11, the first conductor layer 1101 may be deposited in the first opening portion 1001 by a suitable process such as electroplating, and the first blind via 301 may be filled. Similarly, the second conductor layer 1102 is deposited in the second opening portion 1002 and fills the second blind via 302.

接著，請參閱第12圖，移除第三抗鍍乾膜層901的剩餘部分和第四抗鍍乾膜層902的剩餘部分。在一些實施例中，可利用乾膜剝離劑移除第三抗鍍乾膜層901的剩餘部分和第四抗鍍乾膜層902的剩餘部分，但本揭露不以此為限制。 Next, referring to FIG. 12, the remaining portion of the third anti-plating dry film layer 901 and the remaining portion of the fourth anti-plating dry film layer 902 are removed. In some embodiments, the remaining portion of the third anti-plating dry film layer 901 and the remaining portion of the fourth anti-plating dry film layer 902 may be removed using a dry film stripper, although the disclosure is not limited thereto.

接著，請參閱第13圖，利用回蝕製程將暴露的第一銅層401移除，而形成第三圖案化線路層1302。第三圖案化線路層1302可包含填滿第一盲孔301的第一盲孔導體1301。第三擋塊701與第三圖案化線路層1302不互相接觸。在一些實施例中，第三擋塊701的材質與第三圖案化線路層1302可為相同，例如為電鍍銅。在一些實施例中，第三擋塊701的材質與第三圖案化線路層1302可不為相同。 Next, referring to FIG. 13, the exposed first copper layer 401 is removed by an etch back process to form a third patterned circuit layer 1302. The third patterned circuit layer 1302 may include a first blind via conductor 1301 that fills the first blind via 301. The third stopper 701 and the third patterned wiring layer 1302 are not in contact with each other. In some embodiments, the material of the third stopper 701 and the third patterned wiring layer 1302 may be the same, for example, electroplated copper. In some embodiments, the material of the third block 701 and the third patterned circuit layer 1302 may not be the same.

同樣地，上述回蝕製程將暴露的第二銅層402移除，而形成第四圖案化線路層1304。第四圖案化線路層1304可包含填滿第二盲孔302的第二盲孔導體1303。第四 擋塊702與第四圖案化線路層1304不互相接觸。在一些實施例中，第四擋塊702的材質與第四圖案化線路層1304可為相同，例如為電鍍銅。在一些實施例中，第四擋塊702的材質與第四圖案化線路層1304可不為相同。 Likewise, the etchback process removes the exposed second copper layer 402 to form a fourth patterned circuit layer 1304. The fourth patterned circuit layer 1304 can include a second blind via conductor 1303 that fills the second blind via 302. fourth The stopper 702 and the fourth patterned wiring layer 1304 do not contact each other. In some embodiments, the material of the fourth stopper 702 and the fourth patterned wiring layer 1304 may be the same, for example, electroplated copper. In some embodiments, the material of the fourth stopper 702 and the fourth patterned wiring layer 1304 may not be the same.

接著，可重覆第2圖至第13圖對電路板進行增層。如前述，為使線路層之間能均勻地填充介電材料，擋塊的高度須大於或等於圖案化線路層的高度。也就是說，第三擋塊701的高度須大於或等於第三圖案化線路層1302的高度，第四擋塊702的高度須大於或等於第四圖案化線路層1304的高度。 Then, the circuit board can be layered by repeating FIGS. 2 to 13. As described above, in order to uniformly fill the dielectric material between the wiring layers, the height of the stopper must be greater than or equal to the height of the patterned wiring layer. That is, the height of the third stopper 701 must be greater than or equal to the height of the third patterned wiring layer 1302, and the height of the fourth stopper 702 must be greater than or equal to the height of the fourth patterned wiring layer 1304.

應注意的是，在一些實施例中，第三擋塊701可在第三圖案化線路層1302形成之前、期間或之後形成，第四擋塊702亦可在第四圖案化線路層1304形成之前、期間或之後形成。因此，本領域的技術人員當可視製程設計在第7圖至第13圖的製程中，刪減製程或增加其他製程以同時或分別形成第三擋塊701(或第四擋塊702)和第三圖案化線路層1302(或第四圖案化線路層1304)。 It should be noted that in some embodiments, the third stop 701 may be formed before, during or after the formation of the third patterned circuit layer 1302, and the fourth stop 702 may also be formed before the fourth patterned circuit layer 1304 is formed. Formed during, during or after. Therefore, those skilled in the art can reduce the process or add other processes to simultaneously or separately form the third block 701 (or the fourth block 702) and the first process in the process of the process design of FIG. 7 to FIG. Three patterned circuit layers 1302 (or fourth patterned circuit layers 1304).

假定第13圖為根據最終電路層數需求的電路板。接著，請參閱第14A圖，形成第一絕緣保護層1401在第三擋塊701、第三圖案化線路層1302和第一盲孔導體1301上。具體的，第一絕緣保護層1401覆蓋第三擋塊701、第一盲孔導體1301和第三圖案化線路層1302。接著，利用曝光、顯影製程暴露出部分的第三圖案化線路層1302後，再形成複數個第一導電凸塊1402於暴露的第三圖案化線路層 1302上，而形成電路板1400。 Assume that Figure 13 is a circuit board based on the final circuit layer requirements. Next, referring to FIG. 14A, a first insulating protective layer 1401 is formed on the third stopper 701, the third patterned wiring layer 1302, and the first blind via conductor 1301. Specifically, the first insulating protective layer 1401 covers the third stopper 701, the first blind via conductor 1301, and the third patterned wiring layer 1302. Then, after exposing a portion of the third patterned circuit layer 1302 by using an exposure and development process, a plurality of first conductive bumps 1402 are formed on the exposed third patterned circuit layer. On the 1302, a circuit board 1400 is formed.

或者，形成第二絕緣保護層1403在第四擋塊702、第四圖案化線路層1304和第二盲孔導體1303上。具體的，第二絕緣保護層1403將覆蓋第四擋塊702、第二盲孔導體1303和第四圖案化線路層1304。接著，利用曝光、顯影製程暴露出部分的第四圖案化線路層1304後，再形成複數個第二導電凸塊1404於暴露的第四圖案化線路層1304上，而形成電路板1400。 Alternatively, the second insulating protective layer 1403 is formed on the fourth stopper 702, the fourth patterned wiring layer 1304, and the second blind via conductor 1303. Specifically, the second insulating protective layer 1403 will cover the fourth stopper 702, the second blind via conductor 1303, and the fourth patterned wiring layer 1304. Then, after a portion of the fourth patterned circuit layer 1304 is exposed by the exposure and development process, a plurality of second conductive bumps 1404 are formed on the exposed fourth patterned circuit layer 1304 to form the circuit board 1400.

第14B圖為繪示第14A圖中的電路板1400的俯視圖或仰視圖。第一導電凸塊1402(或第二導電凸塊1404)可在後續的應用中藉由銲錫材料結合半導體晶片或將電路板1400接置在適當的電子裝置上(未繪示於圖中)。 Figure 14B is a top or bottom view of the circuit board 1400 of Figure 14A. The first conductive bump 1402 (or the second conductive bump 1404) can be used to bond the semiconductor wafer with a solder material or to connect the circuit board 1400 to a suitable electronic device (not shown) in a subsequent application.

在本揭露中，擋塊的數量不限於上述實施例揭露的四塊擋塊。具體的，請參閱第15圖，繪示了根據本揭露內容另一實施例的前驅電路板100a的俯視圖或仰視圖。在第15圖中，前驅電路板100a包含三塊第一擋塊107。這三塊第一擋塊107(或第二擋塊113)與第一圖案化線路層105(或第二圖案化線路層111)不互相接觸，且第一擋塊107(或第二擋塊113)彼此之間也不互相接觸，又第一擋塊107(或第二擋塊113)實質上圍繞第一圖案化線路層105(或第二圖案化線路層111)。兩相鄰的第一擋塊107(或第二擋塊113)之間形成第一缺口115(或第二缺口116)，其寬度W₃(或W₄)為10μm至80μm之間，更佳為20m至60μm之間，最佳為40μm至50μm之間。 In the present disclosure, the number of the stoppers is not limited to the four stoppers disclosed in the above embodiments. Specifically, please refer to FIG. 15 , which illustrates a top view or a bottom view of a precursor circuit board 100 a according to another embodiment of the present disclosure. In Fig. 15, the precursor circuit board 100a includes three first stoppers 107. The three first stoppers 107 (or the second stoppers 113) are not in contact with the first patterned wiring layer 105 (or the second patterned wiring layer 111), and the first stoppers 107 (or the second stoppers) 113) They are also not in contact with each other, and the first stopper 107 (or the second stopper 113) substantially surrounds the first patterned wiring layer 105 (or the second patterned wiring layer 111). A first notch 115 (or a second notch 116) is formed between the two adjacent first stoppers 107 (or the second stoppers 113), and the width W ₃ (or W ₄ ) is between 10 μm and 80 μm, more preferably It is between 20 m and 60 μm, preferably between 40 μm and 50 μm.

在本揭露中，每個擋塊亦可包含多個子擋塊。具體的，請參閱第16圖，同樣繪示根據本揭露內容又一實施例的前驅電路板100b的俯視圖或仰視圖。在第16圖中，每個第一擋塊107可包含至多三塊不互相接觸的第一子擋塊1601，其中兩相鄰的不互相接觸的第一子擋塊1601之間形成了第一子缺口1602，第一子缺口的寬度W₅小於或等於第一缺口的寬度W₁。 In the present disclosure, each of the stops may also include a plurality of sub-blocks. Specifically, please refer to FIG. 16 , which also illustrates a top view or a bottom view of the precursor circuit board 100 b according to still another embodiment of the present disclosure. In FIG. 16, each of the first stoppers 107 may include at most three first sub-blocks 1601 that are not in contact with each other, wherein a first one of the two adjacent non-contact first sub-blocks 1601 forms a first Sub-notch 1602, the width W _{5 of the} first sub-notch is less than or equal to the width W _{1 of the} first notch.

同樣地，每個第二擋塊113可包含至多三塊不互相接觸的第二子擋塊1603，其中兩相鄰的不互相接觸的第二子擋塊1603之間形成了第二子缺口1604，第二子缺口的寬度W₆小於或等於第二缺口的寬度W₁(或第二缺口的寬度W₂)。 Similarly, each of the second stoppers 113 may include at most three second sub-blocks 1603 that are not in contact with each other, and a second sub-gap 1604 is formed between the two adjacent non-contacting second sub-blocks 1603. The width W _{6 of the} second sub-notch is less than or equal to the width W _{1 of the} second notch (or the width W _{2 of the} second notch).

同樣地，每個第三擋塊701(或每個第四擋塊702)也可包含至多三塊不互相接觸的第三子擋塊(或包含至多三塊不互相接觸的第四子擋塊)，其中不互相接觸的第三子擋塊之相鄰兩者之間可形成第三子缺口(或不互相接觸的第四子擋塊之相鄰兩者)之間形成了第三子缺口(或第四子缺口)，第三子缺口的寬度(或第四子缺口的寬度)小於或等於第三缺口的寬度(或第四缺口的寬度)(未繪示於圖中)。 Similarly, each third stop 701 (or each fourth stop 702) may also include up to three third sub-blocks that do not contact each other (or contain at most three fourth sub-blocks that are not in contact with each other) a third sub-gap formed between the adjacent ones of the third sub-blocks that are not in contact with each other to form a third sub-gap (or adjacent ones of the fourth sub-blocks that are not in contact with each other) (or the fourth sub-notch), the width of the third sub-notch (or the width of the fourth sub-notch) is less than or equal to the width of the third notch (or the width of the fourth notch) (not shown in the figure).

應注意的是，在本揭露中形成的第一擋塊107、第二擋塊113、第三擋塊701以及第四擋塊702，其各自的高度及/或寬度可根據設計需求為相同或不同。 It should be noted that the heights and/or widths of the first block 107, the second block 113, the third block 701, and the fourth block 702 formed in the present disclosure may be the same according to design requirements or different.

雖然本揭露內容已以實施方式揭露如上，然其 並非用以限定本揭露內容，任何熟習此技藝者，於不脫離本揭露內容的精神和範圍內，當可作各種的變動與潤飾，因此本揭露內容的保護範圍當視後附的申請專利範圍所界定者為準。 Although the disclosure has been disclosed in the above embodiments, It is not intended to limit the scope of the disclosure, and any person skilled in the art can make various changes and refinements without departing from the spirit and scope of the disclosure. The definition is final.

Claims (10)

一種電路板，包含：一基板，包含一第一表面，其中該第一表面包含一第一有效區以及一第一無效區，該第一無效區圍繞該第一有效區；一第一圖案化線路層，配置於該第一有效區中；至少三塊第一擋塊，配置於該第一有效區以及該第一無效區之交界處，且不接觸該第一圖案化線路層，其中該些第一擋塊實質上圍繞該第一圖案化線路層，該些第一擋塊彼此之間不接觸，該些第一擋塊之相鄰兩者之間形成一第一缺口，各該第一缺口之寬度為10μm至80μm；以及一第一介電材料，配置於該第一表面上，且覆蓋該第一圖案化線路層以及該些第一擋塊。 A circuit board comprising: a substrate comprising a first surface, wherein the first surface comprises a first active area and a first inactive area, the first inactive area surrounding the first active area; a first patterning a circuit layer disposed in the first active area; at least three first blocks disposed at a boundary between the first active area and the first inactive area and not contacting the first patterned circuit layer, wherein the The first stop substantially surrounds the first patterned circuit layer, the first stops are not in contact with each other, and a first gap is formed between adjacent ones of the first stops. A gap has a width of 10 μm to 80 μm; and a first dielectric material is disposed on the first surface and covers the first patterned circuit layer and the first stoppers. 如申請專利範圍第1項所述之電路板，更包含：一第二圖案化線路層，配置於和該第一表面相對配置的一第二表面上，其中該第二表面包含一第二有效區以及一第二無效區，該第二無效區圍繞該第二有效區；至少一導通孔導體，貫通該基板；至少三塊第二擋塊，配置於該第二有效區以及該第二無效區之交界處，且不接觸該第二圖案化線路層，其中該些第二擋塊實質上圍繞該第二圖案化線路層，該些第二擋塊彼此之間不接觸，該些第二擋塊之相鄰兩者之間形成一第二缺口，各該第二缺口之寬度為10μm至80μm；以及 一第二介電材料，配置於該第二表面上，且覆蓋該第二圖案化線路層、該至少一導通孔導體，以及該些第二擋塊。 The circuit board of claim 1, further comprising: a second patterned circuit layer disposed on a second surface disposed opposite the first surface, wherein the second surface comprises a second effective And a second inactive area surrounding the second active area; at least one via conductor conducting through the substrate; at least three second stops disposed in the second active area and the second invalid a junction of the regions, and not contacting the second patterned circuit layer, wherein the second stops substantially surround the second patterned circuit layer, the second stops are not in contact with each other, and the second Forming a second gap between adjacent ones of the stoppers, each of the second notches having a width of 10 μm to 80 μm; A second dielectric material is disposed on the second surface and covers the second patterned circuit layer, the at least one via conductor, and the second stops. 如申請專利範圍第2項所述之電路板，更包含：一第三圖案化線路層，配置於該第一介電材料之上；一第四圖案化線路層，配置於該第二介電材料之上；以及至少三塊第三擋塊，配置於該第一介電材料上且不接觸該第三圖案化線路層，並對準該些第一擋塊，其中該些第三擋塊實質上圍繞該第三圖案化線路層，該些第三擋塊彼此之間不接觸，該些第三擋塊之相鄰兩者之間形成一第三缺口，各該第三缺口之寬度為10μm至80μm；以及至少三塊第四擋塊，配置於該第二介電材料上且不接觸該第四圖案化線路層，並對準該些第二擋塊，其中該些第四擋塊實質上圍繞該第四圖案化線路層，該些第四擋塊彼此之間不接觸，該些第四擋塊之相鄰兩者之間形成一第四缺口，各該第四缺口之寬度為10μm至80μm。 The circuit board of claim 2, further comprising: a third patterned circuit layer disposed on the first dielectric material; and a fourth patterned circuit layer disposed on the second dielectric Above the material; and at least three third stops disposed on the first dielectric material and not contacting the third patterned circuit layer and aligned with the first stops, wherein the third stops Substantially surrounding the third patterned circuit layer, the third blocks are not in contact with each other, and a third gap is formed between adjacent ones of the third blocks, and the width of each of the third notches is 10 μm to 80 μm; and at least three fourth blocks disposed on the second dielectric material and not contacting the fourth patterned circuit layer, and aligned with the second blocks, wherein the fourth blocks Substantially surrounding the fourth patterned circuit layer, the fourth blocks are not in contact with each other, and a fourth gap is formed between adjacent ones of the fourth blocks, and the width of each of the fourth notches is 10 μm to 80 μm. 如申請專利範圍第3項所述之電路板，其中該些第一擋塊、該些第二擋塊、該些第三擋塊以及該些第四擋塊之高度或寬度為相同。 The circuit board of claim 3, wherein the first block, the second block, the third block, and the fourth block have the same height or width. 如申請專利範圍第3項所述之電路板，其 中該些第一擋塊之高度大於或等於該第一圖案化線路層之高度，該些第二擋塊之高度大於或等於該第二圖案化線路層之高度，該些第三擋塊之高度大於或等於該第三圖案化線路層之高度，以及該些第四擋塊之高度大於或等於該第四圖案化線路層之高度。 a circuit board as described in claim 3, The height of the first blocking block is greater than or equal to the height of the first patterned circuit layer, and the height of the second blocking blocks is greater than or equal to the height of the second patterned circuit layer, and the third blocking blocks The height is greater than or equal to the height of the third patterned circuit layer, and the height of the fourth stops is greater than or equal to the height of the fourth patterned circuit layer. 如申請專利範圍第3項所述之電路板，其中該些第一擋塊之材質係相同於該第一圖案化線路層，該些第二擋塊之材質係相同於該第二圖案化線路層，該些第三擋塊之材質係相同於該第三圖案化線路層，以及該些第四擋塊之材質係相同於該第四圖案化線路層。 The circuit board of claim 3, wherein the materials of the first blocks are the same as the first patterned circuit layer, and the materials of the second blocks are the same as the second patterned circuit. The material of the third block is the same as the third patterned circuit layer, and the materials of the fourth blocks are the same as the fourth patterned circuit layer. 如申請專利範圍第3項所述之電路板，其中各該第一擋塊包含至多三塊不互相接觸的第一子擋塊，各該第二擋塊包含至多三塊不互相接觸的第二子擋塊，各該第三擋塊包含至多三塊不互相接觸的第三子擋塊，以及各該第四擋塊包含至多三塊不互相接觸的第四子擋塊。 The circuit board of claim 3, wherein each of the first stops comprises at most three first sub-blocks that are not in contact with each other, and each of the second blocks comprises at most three second non-contacting ones. The sub-blocks each include at most three third sub-blocks that are not in contact with each other, and each of the fourth blocks includes at most three fourth sub-blocks that are not in contact with each other. 如申請專利範圍第7項所述之電路板，其中該些不互相接觸的第一子擋塊之相鄰兩者之間形成一第一子缺口、該些不互相接觸的第二子擋塊之相鄰兩者之間形成一第二子缺口、該些不互相接觸的第三子擋塊之相鄰兩者之間形成一第三子缺口，以及該些不互相接觸的第四子擋塊之相鄰兩者之間形成一第四子缺口。 The circuit board of claim 7, wherein a first sub-gap is formed between adjacent ones of the first sub-blocks that are not in contact with each other, and the second sub-blocks are not in contact with each other. Forming a second sub-gap between adjacent ones, forming a third sub-gap between adjacent ones of the third sub-blocks not in contact with each other, and the fourth sub-blocks not contacting each other A fourth sub-gap is formed between adjacent ones of the blocks. 如申請專利範圍第8項所述之電路板，其中各該第一子缺口之寬度小於或等於該些第一缺口之寬度、各該第二子缺口之寬度小於或等於該些第二缺口之寬度、各該第三子缺口之寬度小於或等於該些第三缺口之寬度，以及各該第四子缺口之寬度小於或等於該些第四缺口之寬度。 The circuit board of claim 8, wherein the width of each of the first sub-notches is less than or equal to the width of the first notches, and the width of each of the second sub-gaps is less than or equal to the second notches. The width, the width of each of the third sub-notches is less than or equal to the width of the third notches, and the width of each of the fourth sub-notches is less than or equal to the width of the fourth notches. 如申請專利範圍第1項所述之電路板，其中該基板為玻璃基板、有機基板、矽基板、碳化矽基板、或是陶瓷基板。 The circuit board according to claim 1, wherein the substrate is a glass substrate, an organic substrate, a germanium substrate, a tantalum carbide substrate, or a ceramic substrate.