TWM440536U - Semiconductor chip heat dissipation substrate and semiconductor chip package structure - Google Patents

Semiconductor chip heat dissipation substrate and semiconductor chip package structure Download PDF

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Publication number
TWM440536U
TWM440536U TW101211103U TW101211103U TWM440536U TW M440536 U TWM440536 U TW M440536U TW 101211103 U TW101211103 U TW 101211103U TW 101211103 U TW101211103 U TW 101211103U TW M440536 U TWM440536 U TW M440536U
Authority
TW
Taiwan
Prior art keywords
semiconductor chip
heat dissipation
package structure
dissipation substrate
chip package
Prior art date
Application number
TW101211103U
Other languages
Chinese (zh)
Inventor
Hsiang-Yun Yang
Kuo-Hsun Chen
Yi-An Sha
Original Assignee
Polytronics Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Polytronics Technology Corp filed Critical Polytronics Technology Corp
Priority to TW101211103U priority Critical patent/TWM440536U/en
Publication of TWM440536U publication Critical patent/TWM440536U/en
Priority to CN2012207462154U priority patent/CN203013789U/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Led Device Packages (AREA)

Description

第101211103號專利申請案 申請專利範圍更正102年10月28曰 7·根據請求項1之半導體芯片散熱基板，其中該高分 子散熱絕緣層之熱傳導係數介於8〜12w/mK。 8. (刪除）根據請求項丨之半導體芯片散熱基板，其 申該高分子散熱絕緣層之厚度小於等於15〇叫。 9. ·一種半導體芯片封裝結構，包括： 一散熱基板，其係包括第一金屬層、高分子散熱 絕緣層以及第二金屬層之層疊式結構，其中該高 分子散熱絕緣層之熱傳導係數大於等於7 w/mK， 且該高分子散熱絕緣層之厚度小於等於15〇μιη; 以及 一半導體芯片，配置於該散熱基板上，使半導體 芯片的熱源可透過散熱基板迅速外擴傳導。 10. 根據請求項9之半導體芯片封裝結構’其中該半 導體芯片為LED芯片。 11. 根據請求項9之半導體芯片封裝結構，其中該第 一金屬層和高分子散熱絕緣層中設有開口，該第 二金屬層於該開口處對應設有一凹部，該半導體 芯片係設於該凹部表面。 12. 根據請求項9之半導體芯片封裴結構，其中該半 導體芯片係設於該第一金屬層表面。 13·根據請求項9之半導體芯片封裝結構，其中該散 熱基板另包含一導熱柱，該導熱柱設置於該半導 14. 15. 16. 17. 第101211103號專利申請案 m ^ u ~ 申請專利範圍更正102年10月28曰 " 方，貝穿該高分子散熱絕緣層，並連接 該半導體芯片及第二金屬層。 =據請求項9之半導m封裝結構，其中該高 分子散熱絕緣層之熱傳導係數介於8〜12W/mK。 ^刪除）根據請求項9之半導體芯片封裝結構， 其中該高分子散熱絕緣層之厚度小於等於 150μχη。 根據請求項9之半導體μ封裝結構，其中該第 一金屬層包含電氣連接該半導體芯片之正、負電 極。 根據請求項9之半導體芯片封裝結構，其中該半 導體芯片包含以打線或覆晶方式安裝於該半導體 芯片散熱基板之結構。 3Patent Application No. 101,211,103, the entire disclosure of which is incorporated herein by reference. 8. (Remove) According to the request item, the semiconductor chip heat-dissipating substrate has a thickness of the polymer heat-dissipating insulating layer of less than or equal to 15 yaw. 9. A semiconductor chip package structure, comprising: a heat dissipation substrate comprising a first metal layer, a polymer heat dissipation insulation layer, and a second metal layer stacked structure, wherein a thermal conductivity of the polymer heat dissipation insulation layer is greater than or equal to 7 w / mK, and the thickness of the polymer heat dissipation insulating layer is less than or equal to 15 μm; and a semiconductor chip is disposed on the heat dissipation substrate, so that the heat source of the semiconductor chip can be rapidly expanded and transmitted through the heat dissipation substrate. 10. The semiconductor chip package structure according to claim 9, wherein the semiconductor chip is an LED chip. The semiconductor chip package structure of claim 9, wherein the first metal layer and the polymer heat dissipation insulating layer are provided with an opening, and the second metal layer is correspondingly provided with a recess at the opening, and the semiconductor chip is disposed on the semiconductor chip The surface of the recess. 12. The semiconductor chip package structure of claim 9, wherein the semiconductor chip is disposed on a surface of the first metal layer. The semiconductor chip package structure of claim 9, wherein the heat dissipation substrate further comprises a heat conducting column, the heat conducting column being disposed on the semiconductor. 14. 15. 16. 17. Patent Application No. 101211103 m ^ u ~ Patent Application The correction of the range is October 28, 曰, and the square wears the polymer heat-dissipating insulating layer and connects the semiconductor chip and the second metal layer. = The semiconducting m package structure of claim 9, wherein the high molecular thermal insulating layer has a thermal conductivity of 8 to 12 W/mK. [Deleted] The semiconductor chip package structure according to claim 9, wherein the thickness of the polymer heat-dissipating insulating layer is 150 μχη or less. A semiconductor μ package structure according to claim 9, wherein the first metal layer comprises positive and negative electrodes electrically connected to the semiconductor chip. The semiconductor chip package structure of claim 9, wherein the semiconductor chip comprises a structure in which the semiconductor chip heat dissipation substrate is mounted in a wire bonding or flip chip manner. 3

TW101211103U 2012-06-07 2012-06-07 Semiconductor chip heat dissipation substrate and semiconductor chip package structure TWM440536U (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
TW101211103U TWM440536U (en) 2012-06-07 2012-06-07 Semiconductor chip heat dissipation substrate and semiconductor chip package structure
CN2012207462154U CN203013789U (en) 2012-06-07 2012-12-31 Semiconductor chip heat dissipation substrate and semiconductor chip packaging structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW101211103U TWM440536U (en) 2012-06-07 2012-06-07 Semiconductor chip heat dissipation substrate and semiconductor chip package structure

Publications (1)

Publication Number Publication Date
TWM440536U true TWM440536U (en) 2012-11-01

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Family Applications (1)

Application Number Title Priority Date Filing Date
TW101211103U TWM440536U (en) 2012-06-07 2012-06-07 Semiconductor chip heat dissipation substrate and semiconductor chip package structure

Country Status (2)

Country Link
CN (1) CN203013789U (en)
TW (1) TWM440536U (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105355622A (en) * 2014-08-21 2016-02-24 上海威廉照明电气有限公司 Integrated super-quantum LED light-emitting device
CN115020359A (en) * 2022-08-09 2022-09-06 成都复锦功率半导体技术发展有限公司 Semiconductor chip packaging structure and preparation method thereof

Also Published As

Publication number Publication date
CN203013789U (en) 2013-06-19

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