M410982 五、新型說明： 【新型所屬之技術領域】 本創作係關於一種半導體封裝結構，尤指一種可避免 黏晶溢膠問題之半導體封裝結構。 - 【先前技術】 • 在半導體元件封裝製程卞，當晶片已被切割出，次一 φ 步驟便是將其黏著到基板上，亦即俗稱之黏晶。黏晶使用 的材料例如黏性膠膜，但元件成本過高且膠帶廢料量大， 故目前也有改用糊狀黏晶膠者，但使用黏晶膠易有溢膠情 形，將導致封裝不良率增加。 參考圖1、2A、2B，分別為習知塗佈有黏晶膠之基板 上視圖、已完成黏晶之基板上視圖及剖視圖。圖中示出一 基板91於頂面界定有複數個金手指（finger)區域911〜913， 而金手指區域911〜913以外之基板頂面其它部分則形成有 • 一絕緣漆層92。上述金手指區域911〜913中露出有用於電 •性銲接之金手指。金手指區域911〜913基本上圍繞在晶片 94預定放置之區域附近。 在黏晶步驟時，先以適當量之黏晶膠93均勻塗佈在晶 片94預定放置之區域’再將晶片置放於黏晶膠93上。一般 預期黏晶膠93會佈滿晶片94底，而為確保上述目的，通常 會規定一判別黏晶失敗之門檻’例如規定於晶片94每一側 邊溢出膠料總長D2若小於該侧邊長D1之70%，則判定失 敗0 3 M410982 在圓2A中即顯示出黏晶膠量控制不當而導致溢膠，進 而污染到金手指914之情形，如此將報廢整個材料，降低生 產良率。 【新型内容】 本創作之主要目的係在提供一種半導體封裝結構，俾 能解決習知上晶步驟時所發生溢膠問題。 為達成上述目的’本創作之半導體封裝結構包括一基 板、一絕緣漆層、一黏晶膠以及一晶片。上述基板之頂面 界定有相隔開之至少一金手指區域及一黏晶區域，絕緣漆 層則形成於金手指區域及黏晶區域以外之基板頂面之其它 區域。黏晶膠是塗佈於黏晶區域之内，晶片則黏著於黏晶 膠上。 藉由上述半導體封裝結構設計，黏晶區域周圍因絕緣 漆層本身具有一定厚度，構成一凹槽結構，上晶片時黏晶 膠會被侷限在凹槽結構内，不容易溢至附近的金手指區域 而污染到金手指。本創作減少封裝製程中產品報廢之情 形，提升製程良率。 上述金手指區域可以位於晶片外圍。上述基板可為黏 晶區域具有裸露電路圊案者、或為黏晶區域無裸露電路圖 案之一印刷電路板。黏晶膠可為絕緣膠或非絕緣膠。 【實施方式】 參考圖3Α與圖3Β。本創作之半導體封裝結構之形成依 M410982 次敘述如下。首先，取一製作好之基板11，其頂面界定有 複數個金手指區域111〜113以及一黏晶區域114，黏晶區域 114係指預定放置晶片（繪於圖5A)之區域，其略大於晶片本 身面積。每一金手指區域111,112,113中包括有至少一金手 指11 la，l 12a，113a，而黏晶區域114也包括有裸露之一電路 圖案115。本實施例中，金手指區域ill，112,113分佈在黏 晶區域114(及晶片）外圍。 接著在基板11頂面以避開複數個金手指區域11丨〜113 以及黏晶區域114之方式形成一絕緣漆層12,也就是基板η 頂面除了複數個金手指區域111〜113以及黏晶區域114是 對外裸露狀態’其餘部分被絕緣漆層12覆蓋。 然後將一黏晶膠13均勻塗佈在裸露之黏晶區域！ 中，如圖4所示。本例特別使用絕緣膠作為黏晶膠丨3。最後 再將晶片14放置於黏晶勝13上使晶片14適當黏固在基板 11，如圖5A與5B所示。 由於圍繞黏晶區域114周遭之絕緣漆層12具有一厚 度，其與黏晶區域114共同構造成一凹槽之態樣。當晶片14 放置時，黏晶膠13即使會向外擴散，也因被侷限於上述凹 槽中而不會擴散到鄰近金手指區域1Π〜113。所以這樣的 半導體封裝結構並不會有金手指llla，112a,113a因黏晶膠 13逸出而發生污染的情形。 也因為使用了黏晶膠13在晶片14與基板91之間，避免 了黏晶區域114中裸露之電路圖案115與晶片14間直接短 路。但在其它實施例中，所用基板可為印刷電路板（Printed 5 M410982 circuit board ; PCB)、陶珐始 ^ # }网是線路板、電路薄膜等作為晶p 載趙並與之共同進行電性傳導，其可為單層或多層為：二 黏晶區域中並無稞露之電路圖案，因此黏晶膠不限於使用 絕緣勝。黏晶膠材質例如為環氧膠、B階固化膠等。 本創作相較於f知半導體封裝結構不僅絕緣漆層用 量減少’也避免了因溢膠而污染金手指故可減少製品報 廢之比率，在製造成本方面有極大的優勢。 上述實施例僅係為了方便說明而舉例而已，本創作所 主張之權利範圍自應以申請專利範圍所述為準，而非僅限 於上述實施例。 【圖式簡單說明】 圖1係習知塗佈有黏晶膠之基板上視圖。 圖2A係已完成黏晶之基板上視圖。 圖2B係沿圖2A之A-A線剖視圖。 圖3A係本創作一較佳實施例之尚未塗佈黏晶膠之基板上 視圖。 圖3B係沿圖3A之B-B線剖視圖。 圖4係本創作一較佳實施例之塗佈有黏晶膠之基板上視圖。 圖5 A4本創作一較佳實施例之已完成黏晶之基板上視圊。 圊5B係沿圊5A之C-C線剖視囷。 【主要元件符號說明】 基板91 金手指區域911,912,913 M410982 金手指914 絕緣漆層92 黏晶膠93 晶片94 基板11 金手指區域111,112,113 金手指 111a,112a,113a 黏晶區域114 電路圖案115 絕緣漆層12 黏晶膠13 晶片14 側邊長D1 溢出膠料總長D2M410982 V. New Description: [New Technology Field] This creation is about a semiconductor package structure, especially a semiconductor package structure that avoids the problem of adhesion. - [Prior Art] • In the semiconductor component packaging process, when the wafer has been cut, the next step is to adhere it to the substrate, also known as the die bond. The material used for the die-bonding is, for example, a viscous film, but the component cost is too high and the amount of tape waste is large. Therefore, there is also a change to the paste-like viscous gel, but the use of the viscous gel is easy to overflow, which will result in a poor package ratio. increase. Referring to Figures 1, 2A and 2B, there are respectively a top view of a substrate coated with a viscous gel, a top view of the substrate on which the viscous crystal has been completed, and a cross-sectional view. The figure shows a substrate 91 having a plurality of finger regions 911 to 913 defined on the top surface, and other portions of the top surface of the substrate other than the gold finger regions 911 to 913 are formed with an insulating varnish layer 92. Gold fingers for electrical welding are exposed in the gold finger regions 911 to 913. The gold finger regions 911 to 913 substantially surround the area where the wafer 94 is intended to be placed. In the die bonding step, an appropriate amount of the adhesive 93 is uniformly applied to the area where the wafer 94 is intended to be placed, and the wafer is placed on the adhesive 93. It is generally expected that the adhesive 93 will fill the bottom of the wafer 94. To ensure the above purpose, a threshold for discriminating the failure of the die is generally specified. For example, the total length D2 of the overflow compound on each side of the wafer 94 is less than the length of the side. 70% of D1, the failure is judged. 0 3 M410982 In the circle 2A, the improper control of the amount of the glue is caused to cause the glue to overflow, and thus the gold finger 914 is contaminated, so that the entire material is scrapped and the production yield is lowered. [New Content] The main purpose of this creation is to provide a semiconductor package structure that can solve the problem of overflow of glue when the conventional epitaxial step is performed. To achieve the above objectives, the semiconductor package structure of the present invention includes a substrate, an insulating varnish layer, a die attach adhesive, and a wafer. The top surface of the substrate defines at least one gold finger region and a die bonding region, and the insulating varnish layer is formed in other regions of the top surface of the substrate other than the gold finger region and the die bonding region. The adhesive is applied to the bonded area and the wafer is adhered to the adhesive. According to the above semiconductor package structure design, the periphery of the die-bonding region has a certain thickness by the thickness of the insulating varnish layer, and a groove structure is formed. When the wafer is on the wafer, the adhesive is confined in the groove structure, and it is not easy to overflow to the nearby gold finger. The area is polluted to the golden finger. This creation reduces the situation of product scrapping in the packaging process and improves the process yield. The above gold finger area may be located at the periphery of the wafer. The substrate may be a printed circuit board having a bare circuit pattern in the bonded region or a bare circuit pattern in the bonded region. The adhesive can be an insulating or non-insulating adhesive. [Embodiment] Referring to Fig. 3A and Fig. 3A. The formation of the semiconductor package structure of this creation is described as follows in M410982 times. First, a fabricated substrate 11 is obtained, the top surface of which defines a plurality of gold finger regions 111 to 113 and a die bonding region 114, and the die bonding region 114 refers to a region where a wafer is placed (shown in FIG. 5A). Greater than the area of the wafer itself. Each of the gold finger regions 111, 112, 113 includes at least one gold finger 11 la, l 12a, 113a, and the die region 114 also includes a bare circuit pattern 115. In this embodiment, the gold finger regions ill, 112, 113 are distributed around the periphery of the adhesion region 114 (and the wafer). Then, an insulating varnish layer 12 is formed on the top surface of the substrate 11 so as to avoid the plurality of gold finger regions 11丨 to 113 and the die bonding region 114, that is, the top surface of the substrate η except the plurality of gold finger regions 111 to 113 and the die bond crystal The area 114 is exposed to the exposed state 'the rest is covered by the insulating lacquer layer 12. Then apply a layer of adhesive 10 evenly in the exposed area! In, as shown in Figure 4. In this case, an insulating glue is particularly used as the adhesive crystal crucible 3. Finally, the wafer 14 is placed on the die 13 to properly adhere the wafer 14 to the substrate 11, as shown in Figures 5A and 5B. Since the insulating varnish layer 12 surrounding the die-bonding region 114 has a thickness, it is configured together with the die-bonding region 114 to form a groove. When the wafer 14 is placed, the adhesive 13 is not restricted to diffuse into the adjacent gold finger regions 1Π to 113 even if it is diffused outward. Therefore, such a semiconductor package structure does not cause contamination of the gold fingers 111a, 112a, 113a due to the escape of the adhesive. Also, since the adhesive 13 is used between the wafer 14 and the substrate 91, a direct short circuit between the exposed circuit pattern 115 and the wafer 14 in the die region 114 is avoided. However, in other embodiments, the substrate used may be a printed circuit board (Printed 5 M410982 circuit board; PCB), a ceramic circuit, a circuit board, a circuit film, etc., and is electrically connected thereto. Conduction, which can be single layer or multiple layers: there is no exposed circuit pattern in the two-bonded crystal region, so the adhesive is not limited to the use of insulation. The adhesive material is, for example, an epoxy glue, a B-stage curing glue, or the like. Compared with the semiconductor package structure, this design not only reduces the amount of the insulating lacquer layer, but also avoids the contamination of the gold finger due to the overflow of the glue, thereby reducing the ratio of product scrapping, and has great advantages in manufacturing cost. The above-described embodiments are merely examples for convenience of description, and the scope of the claims is intended to be based on the scope of the patent application, and is not limited to the above embodiments. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a top view of a substrate coated with a viscous gel. Figure 2A is a top view of the substrate on which the die bond has been completed. Fig. 2B is a cross-sectional view taken along line A-A of Fig. 2A. Fig. 3A is a top view of a substrate on which a die bond has not been applied in accordance with a preferred embodiment of the present invention. Fig. 3B is a cross-sectional view taken along line B-B of Fig. 3A. 4 is a top view of a substrate coated with a die bond in a preferred embodiment of the present invention. FIG. 5 is a top view of the substrate on which the die-bonded crystal has been completed in accordance with a preferred embodiment of the present invention.圊5B is cut along the C-C line of 圊5A. [Main component symbol description] Substrate 91 Gold finger area 911, 912, 913 M410982 Gold finger 914 Insulating varnish layer 92 Adhesive glue 93 Wafer 94 Substrate 11 Gold finger area 111, 112, 113 Gold finger 111a, 112a, 113a Bonded area 114 Circuit pattern 115 Insulating lacquer layer 12 Adhesive glue 13 wafer 14 side length D1 overflow compound total length D2