TWM327089U - LED chip package structure - Google Patents

LED chip package structure Download PDF

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Publication number
TWM327089U
TWM327089U TW096214234U TW96214234U TWM327089U TW M327089 U TWM327089 U TW M327089U TW 096214234 U TW096214234 U TW 096214234U TW 96214234 U TW96214234 U TW 96214234U TW M327089 U TWM327089 U TW M327089U
Authority
TW
Taiwan
Prior art keywords
light
emitting diode
unit
positive
substrate
Prior art date
Application number
TW096214234U
Other languages
Chinese (zh)
Inventor
bing-long Wang
feng-hui Zhuang
Wen-Kui Wu
Original Assignee
Harvatek Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Harvatek Corp filed Critical Harvatek Corp
Priority to TW096214234U priority Critical patent/TWM327089U/en
Priority to JP2007008249U priority patent/JP3138582U/en
Priority to DE202007015174U priority patent/DE202007015174U1/en
Publication of TWM327089U publication Critical patent/TWM327089U/en

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Led Device Packages (AREA)

Abstract

An LED chip package structure includes a substrate unit, alight-emitting unit, and a colloid unit. The substrate unit has a substrate body, and a positive pole and a negative pole formed on the substrate body respectively. The light-emitting unit has plurality LED chips disposed on the substrate body. Each LED chip has a positive pole terminal and a negative pole terminal, the positive pole terminal and the negative pole terminal electrical connect with the positive pole and the negative pole respectively. The colloid unit covers on the substrate unit and the light-emitting unit. Whereby, the light-emitting unit produces the light by conducting to the positive pole and the negative pole, the light products a continuous emitted area in the colloid unit through the guide of the colloid unit.

Description

M327089 八、新型說明: 【新型所屬之技術領域】 本創作係有關於發光二極體晶片之 將發光二極體晶片設置於基材本體上,乂羞結構,指一種 連接而產生電性連接,再利用膠體以髮透過導電介質 光二極體晶片結構,使該發光二極體之方式封裝該發 成一連續光束,並且縮短其製程時間。、衣、、、°構卷光日寸形 【先前技術】 請參閱第一圖所示,其係羽 (wire-boimding)製程製作之發光、二極^習壯知以打線 圖。由圖中可知,習知之發光二極=衣結構之示意 基板結構1 a、複數個設置於該基板4、、;構,包括:一 極體2 a、複數條導線Ί a、芬°構1 a上之發光二 中’每-個發光二極體2 “卜::螢光膠體4 a。其 並每-個發光二極體該基底結構“上, 對應之正、負電二Γ:連=該=構一 蓋於每一發光二=== 上,以保濩该發光二極體2 a。 ,a a以該等發光二極體2 a封裝須切割成單顆, 術(SMT)製程,將該發光二極體2 a置 χ九—極體2 a之間會有暗帶現像存在, 6 M327089 對於使用者視線仍然產生不佳效果。 緣是,本創作人有感上述缺失之可改善,且依據多年 來從事此方面之相關經驗,悉心觀察且研究之,並配合學 理之運用,而提出一種設計合裡且有效改善上述缺失之本 創作。 【新型内容】M327089 VIII. New Description: [New Technology Field] This creation is about the arrangement of a light-emitting diode chip on a substrate body for a light-emitting diode chip. The structure is a kind of connection and electrical connection. The colloid is used to transmit the photodiode wafer structure through the conductive medium, so that the light emitting diode encapsulates the continuous light beam and shortens the processing time thereof. ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, As can be seen from the figure, the conventional light-emitting diodes=the schematic substrate structure 1 a of the clothing structure, and the plurality of structures are disposed on the substrate 4, and include: a pole body 2 a, a plurality of wires Ί a, a f a luminescence in the second 'every-light-emitting diode 2' Bu:: fluorescent colloid 4 a. and each of the light-emitting diodes of the base structure "on, corresponding to positive and negative electricity two: continuous = The = structure is covered on each of the two light=== to protect the light-emitting diode 2a. , aa in these LEDs 2 a package must be cut into a single, SMT process, the light-emitting diode 2 a placed between the nine-pole body 2 a there will be a dark band image, 6 M327089 still has a poor effect on the user's line of sight. The reason is that the creator feels that the above-mentioned deficiencies can be improved, and based on years of experience in this field, carefully observe and study, and with the use of academics, propose a design and effectively improve the above-mentioned deficiency. creation. [New content]

本創作所要解決的技術問題,在於提供一種發光二極 體晶片之封裝結構,係以黏著或印刷等方式將發光二極體 晶片設置於基材本體上,該基材本體可為印刷電路板、軟 基板、紹基板或是陶瓷基板,並且利用導線打線 (wire-bounding)或錫球覆晶(flip chip)等方式,使該發光 二極體晶片與該基材本體產生電性連接,並且利用壓模(die mold)等方式,將以環氧樹脂為材質之膠體覆著於該基材 本體與該發光二極體晶片上。The technical problem to be solved by the present invention is to provide a package structure of a light-emitting diode chip, in which a light-emitting diode chip is disposed on a substrate body by adhesion or printing, and the substrate body can be a printed circuit board. a soft substrate, a substrate or a ceramic substrate, and electrically connected to the substrate body by using wire-bounding or flip chip or the like, and utilizing A die made of epoxy resin is applied to the substrate body and the LED substrate by a die mold or the like.

句』胛决上返技術問題,根據本創作之一種方案,提 供一種發光二極體晶片之封裝結構,其包括··一基材單元, 其具有-紐核及分卿成於該絲本體之正極導電執 跡(elect· trace)與負極導電軌跡;—發光單元,且呈 複數個設置於該基材本體上之發光二= ,發光二極體晶片係具有—正極端與—負並 生電性連接;以及一以環氧:=2極導電軌跡產 著於該基料讀該發為H料元,其覆 7 M327089 . 藉此,當該發光二極體結構發光時,形成一連續之發 、 光區域,而無亮暗帶情況發生,並且有效縮短其製程時間, 再者,该發光二極體結構可為一藍光發光二極體搭配一螢 光型悲之膠體的組合;此外本創作之結構設計更適用於各 種光,,诸如背光模組、裝飾燈條、照明用燈或是Scanner -光源等應用,皆為本創作所應用之範圍與產品。 、 /為了能更進一步瞭解本創作為達成預定目的所採取之 技術手&及功效,請茶閱以下有關本創作之詳細說明與 附圖,相信本創作之目的、特徵與特點,當可由此得一深 入且’、體之瞭解,然而所附圖式僅提供參考與說明用,並 非用來對本創作加以限制者。 L貫施方式】 狀心J弟:,所不’係為本創作發光二極體晶片之封 1、一發光單元2、一膠體單元Ί。 括.基材早兀 (bakelitelayer) 1〇B, 〇A上之電木層 導電軌跡12可藉由軌跡11及負極 形成。該發光單元2具有複數個發光二 8 M327089 利用黏著或熱壓印刷等方式’設置於該基材本許 每一發光二極體晶片2 0具有一正極端2 〇丄上’ 2 0 2,每一發光二極體之正極端2 〇 二::= =並聯方式,並且透過導線打線相對應地與該二: 1 0上之正極導電軌跡1 1、負極導電軌跡i 且 此外,每一發光二極體之正極端2 〇 i與負屯極。 3可以並聯方式並透過錫球覆晶相對應地與該基材 1 0上之正極導電執跡1 1、負極導電執跡 = 接。另外,提供-膠體單S3,其為―覆著^連 3與該發光單元2上之膠體,藉此,當該發光 =極導電執跡i !、負極導電執2的通電^ 線日寸,該光線係透過該膠體單元3之導引而於先 巧形成一連續之發光區域’同時’也用 兮 几2而不容易遭到破壞。 隻-先早 此外,從第二C圖及第二D圖所示,本 Ξ體裝?構可以複數條發光單元2排稿; 在该基材早兀1可切割成數條發光單元 子 體,再將該等發光二極體依需求而組合成不 板狀)之發光二極體組。 v °面 請參閱第三圖所示,係為本創作發光二 裝結構之第二實_之示意圖。由时可知 片m 例與該第-實施例最大的不同在於:該發 光二極體晶片20間,每一個相鄰之發光二 之正極端20 1之擺放方向相反而排列,並且各正極端2 9 M327089 Ο 1負極端2 〇 2以串聯方式並透過導線打線與該正、 負極導電轨跡產生電性連接,其外觀為一 U型串聯形式。 此外,從第三C圖及第三D圖所示,本創作之發光二 極體晶片之封裝結構可以複數條發光單元2排列形式存 在,該基材單元1可切割成數條發光單元2之發光二極 體,再將該等發光二極體依需求而組合成不同形狀 (如面 板狀)之發光二極體組。According to one aspect of the present invention, a package structure of a light-emitting diode chip is provided, which includes a substrate unit having a core and a core The positive conductive trace (elect· trace) and the negative conductive track; the light-emitting unit, and a plurality of light-emitting diodes disposed on the substrate body, the light-emitting diode chip has a positive terminal and a negative cogeneration And an epoxy:=2 pole conductive trace is produced on the base material to read the hair as a H element, which covers 7 M327089. Thereby, when the light emitting diode structure emits light, a continuous shape is formed. The light and light regions are generated without the occurrence of bright and dark bands, and the process time is effectively shortened. Further, the light emitting diode structure can be a combination of a blue light emitting diode and a fluorescent type of sad colloid; The structural design of the creation is more suitable for all kinds of light, such as backlight modules, decorative light strips, lighting lights or Scanner-light source applications, all of which are the scope and products of the creation. / In order to better understand the technical hand & and effectiveness of this creation in order to achieve the intended purpose, please read the following detailed description and drawings of this creation, and believe that the purpose, characteristics and characteristics of this creation can be There is a deep understanding and understanding of the subject, however, the drawings are provided for reference and explanation only, and are not intended to limit the creation. L-through mode] The heart-shaped J brother: No, it is the seal of the created light-emitting diode chip, a light-emitting unit 2, and a colloid unit. Bakelitelayer 1〇B, 电A on the bakelite layer The conductive track 12 can be formed by the track 11 and the negative electrode. The light-emitting unit 2 has a plurality of light-emitting diodes 8 M327089, which are disposed on the substrate by adhesion or hot stamping, etc. Each of the light-emitting diode chips 20 has a positive terminal 2 ' '2 0 2 , each The positive terminal 2 of a light-emitting diode is 〇2::==the parallel mode, and the wire is connected through the wire corresponding to the second: the positive conductive track 1 1 on the positive electrode, the negative conductive track i and, in addition, each of the two light The positive terminal 2 of the polar body is 〇i and the negative drain. 3 can be connected in parallel and through the solder ball flip-chip corresponding to the positive conductive trace 1 1 on the substrate 10, the negative conductive trace = connect. In addition, a colloidal single S3 is provided, which is a colloid covering the ^3 and the light-emitting unit 2, whereby when the light-emitting=polar conductive trace i!, the negative conductive conduction 2 is energized, The light is guided through the colloidal unit 3 to form a continuous illuminating region 'at the same time' and is also less likely to be damaged. Only - firstly, in addition, as shown in the second C diagram and the second diagram D, the body assembly structure can be printed by a plurality of illumination units 2; the substrate can be cut into a plurality of illumination unit sub-frames as early as 1 Then, the light-emitting diodes are combined into a non-plate-shaped light-emitting diode group as needed. v ° surface Please refer to the third figure, which is the second embodiment of the creation of the light-emitting two-pack structure. It can be seen from the time that the maximum difference between the example of the sheet m and the first embodiment is that the anodes 20 of each adjacent light-emitting diode 20 are arranged in opposite directions, and the positive terminals are arranged. 2 9 M327089 Ο 1 The negative terminal 2 〇 2 is electrically connected to the positive and negative conductive traces in series and through the wire. The appearance is a U-series. In addition, as shown in the third C diagram and the third D diagram, the package structure of the LED array of the present invention may exist in the form of a plurality of illumination units 2, and the substrate unit 1 may be cut into the illumination of the plurality of illumination units 2. The diodes are then combined into a light-emitting diode group of different shapes (such as a panel shape) according to requirements.

士 s月爹閲弟四圖所示,係為本創作發光二極體晶片之封 衣第二實施例之示意圖。由圖中可知,本第三實施 例與該第二實施例最大的不同在於:該發光單元2之各發 極體晶片2 Q間’每-個發光二極體晶片2 〇之正極 化2 0 1之擺放方向—致而排列,並且各正極端2◦工、 =極端202以串聯方式並透過導線打線與該正、負極導 電執跡產生電性連接,其外觀為_§型串聯形式。、 桎/日1 ’從第四C圖及第四D圖所示,本創作之發光二 ”曰=裝結構可以複數條發光單元2排列形式存 Ϊ ’if1可切割成數條發光單元2之發光二極 板狀)發光二極體依需求而組合成不同形狀(如面 板狀)之發光二極體組。 裝㈣示,係為本創作Μ二極體晶片之封 方塊圖。由圖上得知’本 括:_首先,提方法,其包 一基材本體1 〇、及分卿’该基材早元1係具有 另形成於該基材本體之正極導電軌 M327089 跡1 1 ( electron trace )與負極導電軌跡1 2 ; S203接著, 設置一發光單元2於該基材本體1 〇上,該發光單元2係 具有複數個設置於該基材本體1 〇上之發光二極體晶片2' 〇,每一個發光二極體晶片2 〇係具有一正極端工與 一負極端2 0 2 ; S205然後,其中每一發光二極體晶片2' 0之正2 0 1、負極端2 0 2係以並聯方式並且透過相對 應之導線打線(錫球覆晶)與該正1 i、負極導電軌跡i 2產 生電性連接;S207再來,覆著一膠體單元3於該基材單元 1與該發光單元2上,以使得當該發光單元2藉由該正工 1、負極導電執跡1 2的通電而產生光線時,該光線係透 過該膠體單元3之導引而於該膠體單元3上形成一連續之 發光區域。 士请麥閱第六圖所示,係為本創作發光二極體晶片之封 ^結構方法之第二實施例之步驟方塊圖。由圖中可知,本 第二^施例與該第一實施例之最大不同之處在於:在%〇5 中,每一發光二極體晶片2 0之正極端2 〇q之擺設方向 與相鄰之發光二極體晶片2 0之正極端2 〇 ;[相反,以串 聯方式並透過導線打線與該正1 1、負極導電軌跡1 2產 生電性連接。 凊麥閱第七圖所示,係為本創作發光二極體晶片之封 ,結構方法之第三實施例之步驟方塊圖。由圖中可知,本 第二實施例與該第二實施例之最大不同之處在於··在S4〇5 中母务光一極體晶片2 0之正極端2 0 1朝同一方向 排列’以串聯方式並透過導線打線與該正1 1、負極導電 M327089 執跡1 2產生電性連接。 綜上所述,本創作之發光二極體晶片之封裝結構,係 藉由傳統壓模(die mold)或印刷(printing)方法、及打線 (wire-bounding)或覆晶(flip chip)之製程,克服該發光: ,體間之暗光帶問題,並且使該發光二極體之封裝結構 單化,並且縮短其製程時間。 ^ ,以上所述,僅為本創作最佳之一的具體實施例之 坪細說明與®[式,惟本創作之贼並不侷限於此 =本創作’本創作之所有範圍應以下述之申請= 二凡合於本創作申請專利範圍之精神與其類似變化 之广例,皆應包含於本創作之料中,任⑽㈣ς匕 蓋在以下杨之專利 “狀心祕料可涵 【圖式簡單說明】 係爲習知發光二極體封裝結構之立體圖; 第一 糸爲習知發光二極體封裝結構之前視圖; 第 第 第 第 第二A=舄習知發光二極體封裴結構之俯視圖; 二糸爲本創作之發光二極體封裝結構之立. ^係爲本創作之發光二極體封之 排列結構之俯視圖; 禾貫^之 D圖係為本創作之發光二极體龍結構— 排列組合; 弟貫%的 M327089 ^本創作之發光二極體封裝 發光二極體封物冓之二: 圖^本創作之發光二極體封震結構之第二實施之 排列結構之俯視圖; 、之 弟二D _為本解之發光二極體 排列組合; 傅爻弟一貝轭的 之t先二極體封裳結構之立趙圖; 二極體封敦結構之俯視圖; 極物結構之第三實施之 弟四D圖作之發先二極體縣結構之第三實施的 第五圖係麻創作發光二極體W之縣結财法 貫施例之驟步方塊圖; 弟 第六圖係爲本創作科二極體晶片之㈣ 實施例之驟步方塊圖;以及 / 弟一 第七圖係,本創作發光二極體晶片之封裝結構 貫施例之驟步方塊圖。 之弟一 【主要元件符號說明】 [習知J 基板結構 1 a 發光二極體 2 a 正電極區域 i工a 負電極區域工2 a 正電極區域 2 1 a M327089 負電極區域 22a 導線 3 a ' 螢光膠體 4 a • [本創作] 基材單元 1 發光單元 2 膠體單元 3 基材本體 金屬層 電木層 正極導電軌跡 負極導電軌跡 發光二極體晶片 正極端 負極端 A B ο ο ο ο 2 ο ο 14The figure of the second embodiment of the package of the light-emitting diode chip is shown in Figure 4 of the book. It can be seen from the figure that the biggest difference between the third embodiment and the second embodiment is that the anode of each of the emitter wafers 2 of the light-emitting unit 2 is 'opposited by each of the light-emitting diode chips 2 The arrangement direction of 1 is arranged, and each positive terminal 2 is completed, and the = extreme electrode 202 is electrically connected to the positive and negative conductive traces in series and through a wire, and the appearance thereof is a _§ type series connection. , 桎 / 日 1 'From the fourth C picture and the fourth D picture, the light of the creation of the two "曰 = installation structure can be arranged in a plurality of light-emitting units 2 Ϊ 'if1 can be cut into several light-emitting units 2 The two-pole plate-shaped light-emitting diodes are combined into a light-emitting diode group of different shapes (such as a panel shape) according to requirements. The package (4) shows the block diagram of the created diode chip. Knowing the following: _ First, the method, which comprises a substrate body 1 〇, and a division of the substrate, the substrate 1 has a positive conductive track M327089 formed on the substrate body. And the negative conductive track 1 2; S203, then, a light-emitting unit 2 is disposed on the substrate body 1 , the light-emitting unit 2 has a plurality of light-emitting diode chips 2 ′ disposed on the substrate body 1 〇 〇, each of the light-emitting diode chips 2 has a positive terminal and a negative terminal 2 0 2 ; S205, then each of the light-emitting diode chips 2'0 is positive 2 0 1 and the negative terminal 2 0 2 Connected in parallel and through the corresponding wire (tin ball flip chip) and the positive 1 i, negative conductor track The trace i 2 is electrically connected; S207 is repeated, and a colloid unit 3 is coated on the base unit 1 and the light-emitting unit 2, so that when the light-emitting unit 2 is guided by the work 1, the negative conductive track 1 When the light is generated by the energization of 2, the light is guided through the colloid unit 3 to form a continuous light-emitting area on the colloid unit 3. As shown in the sixth figure, the figure is a creative light-emitting diode. The block diagram of the second embodiment of the method for sealing the bulk wafer. It can be seen from the figure that the biggest difference between the second embodiment and the first embodiment is that in %〇5, each illumination The positive terminal 2 of the diode wafer 20 is disposed in the direction of the positive terminal 2 of the adjacent LED chip 20; [in contrast, the wire is connected in series and through the wire and the positive electrode is electrically conductive. The track 1 2 is electrically connected. The seventh embodiment of the present invention is a block diagram of the third embodiment of the structure of the light-emitting diode chip, and the second embodiment is shown in the figure. The biggest difference between the example and the second embodiment is that... in the S4〇5 The positive terminal 2 0 1 of the polar body wafer 20 is arranged in the same direction. The electrical connection is made in series and through the wire and the positive electrode 1 and the negative electrode conductive M327089 track 1 2 . In summary, the illumination of the present invention The package structure of the diode chip is overcome by a conventional die mold or printing method, and a wire-bounding or flip chip process: The problem of the dark light band is, and the package structure of the light-emitting diode is simplified, and the process time thereof is shortened. ^ , As described above, it is only a detailed description of the specific embodiment of the present invention and the formula However, the thief of this creation is not limited to this = this creation 'All the scope of this creation should be the following application = the general spirit of the scope of the patent application and the similar changes, should be included in this creation Among the materials, any (10) and (4) ς匕 在 在 以下 杨 杨 杨 杨 杨 杨 杨 杨 杨 杨 杨 杨 杨 杨 杨 杨 杨 杨 杨 杨 杨 杨 杨 杨 杨 杨 杨 杨 杨 杨 杨 杨 杨 杨 杨 杨 杨 杨 杨 杨 杨 杨 杨 杨 杨Structure front view; first The second A=舄 知 发光 发光 发光 发光 发光 ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; The D-picture of Guan is the light-emitting diode structure of the creation-arrangement and combination; the M327089 of the brother-in-law is the second generation of the light-emitting diode package of the light-emitting diode package: Figure 2 The top view of the arrangement structure of the second embodiment of the diode-enclosed structure; the second generation of the diode D _ is the arrangement of the light-emitting diodes of the solution; the first two-pole body of the 爻 一 贝 y yoke Figure; top view of the diode structure of the diode; the fourth embodiment of the fourth structure of the polar structure, the fourth figure of the third implementation of the first diode structure, the dynasty creation of the light-emitting diode W County The step-by-step block diagram of the method of the fund-raising method; the sixth figure of the second part of the book is the step-by-step block diagram of the (IV) embodiment of the Creative Diode chip; and / the seventh figure of the brother-in-law, the creative light-emitting diode A step-by-step block diagram of a package structure of a wafer. Brother 1 [Main component symbol description] [Learn J substrate structure 1 a light-emitting diode 2 a positive electrode region i work a negative electrode region 2 a positive electrode region 2 1 a M327089 negative electrode region 22a wire 3 a ' Fluorescent colloid 4 a • [This creation] Substrate unit 1 Light-emitting unit 2 Colloidal unit 3 Substrate body Metal layer Bakelite positive conductive track Negative conductive trace Light-emitting diode wafer Positive terminal Negative end AB ο ο ο ο 2 ο ο 14

Claims (1)

M327089 九、申請專利範圍: 1種毛光一極體晶片之封裝結構,其特徵在於,包括: 一基材單元; =光單70 ’其具有複數個電性連接地設置於該基材 單元上之發光二極體晶片;以及 膠體單元,其覆著於該基材單元與該發光單元上; 精此 Μ '"亥餐光早元被通電而產生光線時,該光線係 透過該膠體單元之導引而於該膠體單元上形成一連 續之發光區域。 2 '如申請專利範圍第1項所述之發光二極體晶片之封裝 結構,其特徵在於:該基材單元係為印刷電路板、軟 基板、鋁基板或陶瓷基板。 3、 如申請專利範圍第1項所述之發光二極體晶片之封裝 結構’其特徵在於:該基材單元係具有一基材本體、 及分別形成於該基材本體之正極導電軌跡(electr〇n trace)與負極導電軌跡。 4、 如申請專利範圍第3項所述之發光二極體晶片之封裝 、、口構’其知'徵在於:該基材本體係包括一金屬層(metai hyer )及一成形在該金屬層上之電木層(bakelite layer ) 〇 5、 如申請專利範圍第3項所述之發光二極體晶片之封裝 結構,其特徵在於:每一個發光二極體晶片係具有二 正極端與一負極端,並且該等發光二極體晶片之正、 負極端係分別與該正、負極導電軌跡產生電性連接。 15 M327089 6 請專利範圍第5項所述之發光二極體晶片之封穿 . 二t其特徵在於:該等發光二極體晶片之正、負極 _ 而糸透過相對應之導線並以打線的方式,以與誃 7負極導電執跡產生電性連接。 人 =申請專利範圍第5項所述之發光二極體晶片之封裝 二構,其特徵在於··該等發光二極體晶片之正、負= 令而係透過相對應之錫球並以覆晶的方式,以與該正、 鲁 8負極導電轨跡產生電性連接。 、2申請專利範圍第5項所述之發光二極體晶片之封裝 1構,其特徵在於··該等發光二極體晶片之正、負極 2係以並聯的方式與該正、負極導電軌跡產生電性連 9 2申睛專利範圍第5項所述之發光二極體晶片之封裝 f構’其特徵在於:該等發光二極體晶片之正、負極 端係以串聯的方式與該正、負極導電軌跡產生電性遠 一 接。 逆 • 1 \如申請專利範圍第1項所述之發光二極體晶片之封 襄結構,其特徵在於:該等發光二極體晶片係以—直 線排列的方式設置於該基材單元上。 11二如申請專利範圍第1項所述之發光二極體晶片之封 褒結構’其特徵在於:該等發光二極體晶片係以複數 條直線排列的方式設置於該基材單元上。 1 2、如申請專利範圍第1項所述之發光二極體晶片之封 . 裝結構,其特徵在於:每一個發光二極體晶片係為— 16 M327089 藍光發先二極體’並且該膠體单元係為一螢光膠體。 1 3、如申請專利範圍第1項所述之發光二極體晶片之封 裝結構,其特徵在於:該膠體單元係為環氧樹脂 (Epoxy) 〇M327089 IX. Patent Application Range: A package structure of a matte-pole wafer, comprising: a substrate unit; a light sheet 70' having a plurality of electrical connections disposed on the substrate unit a light-emitting diode wafer; and a colloid unit covering the substrate unit and the light-emitting unit; wherein the light is transmitted through the gel unit when the light is energized to generate light Guided to form a continuous light-emitting area on the gel unit. The package structure of the light-emitting diode wafer according to claim 1, wherein the substrate unit is a printed circuit board, a flexible substrate, an aluminum substrate or a ceramic substrate. 3. The package structure of the light-emitting diode chip according to claim 1, wherein the substrate unit has a substrate body and a positive conductive track formed on the substrate body (electr) 〇n trace) and the negative conductive track. 4. The package of the light-emitting diode chip according to item 3 of the patent application scope, and the structure of the mouth structure are: the substrate comprises a metal layer (metai hyer) and a metal layer formed thereon. The package structure of the light-emitting diode chip according to claim 3, wherein each of the light-emitting diode chips has two positive terminals and one negative Extremely, the positive and negative ends of the LED chips are electrically connected to the positive and negative conductive tracks, respectively. 15 M327089 6 Please block the light-emitting diode wafer according to item 5 of the patent scope. The second feature is characterized in that the positive and negative electrodes of the light-emitting diode chip pass through the corresponding wires and are wired. The way is to make an electrical connection with the 誃7 negative electrode conductive trace. The package structure of the light-emitting diode chip according to the fifth aspect of the invention is characterized in that: the positive and negative of the light-emitting diode chips are transmitted through the corresponding solder balls The crystal is electrically connected to the positive and negative 8 negative conductive traces. The package structure of the light-emitting diode chip according to the fifth aspect of the invention is characterized in that: the positive and negative electrodes 2 of the light-emitting diode chips are connected in parallel with the positive and negative conductive tracks. The package structure of the light-emitting diode chip according to the fifth aspect of the invention is characterized in that: the positive and negative ends of the light-emitting diode chips are connected in series and the positive The negative conductive track generates electrical continuity. The sealing structure of the light-emitting diode wafer according to the first aspect of the invention is characterized in that the light-emitting diode chips are arranged on the substrate unit in a line-aligned manner. The sealing structure of the light-emitting diode wafer according to the first aspect of the invention is characterized in that the light-emitting diode chips are arranged on the substrate unit in a plurality of linear alignments. The package structure of the light-emitting diode chip according to claim 1, wherein each of the light-emitting diode chips is - 16 M327089 blue light-emitting diode ' and the colloid The unit is a fluorescent colloid. The package structure of the light-emitting diode chip according to claim 1, wherein the colloidal unit is epoxy resin (Epoxy). 1717
TW096214234U 2007-08-27 2007-08-27 LED chip package structure TWM327089U (en)

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JP2007008249U JP3138582U (en) 2007-08-27 2007-10-26 Light emitting diode chip package
DE202007015174U DE202007015174U1 (en) 2007-08-27 2007-10-31 Packaging structure of LED chips

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US9366390B2 (en) 2013-10-25 2016-06-14 Lextar Electronics Corporation Light emitting diode device and light emitting diode lamp

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DE102013206342B4 (en) 2012-05-18 2017-04-13 Atex Co., Ltd LED mounting circuit board, belt-type flexible LED light and LED lighting device taking advantage of these
DE102016109951A1 (en) * 2016-05-31 2017-11-30 Valeo Schalter Und Sensoren Gmbh Light generating device for a head-up display of a motor vehicle
JP7009207B2 (en) * 2017-12-28 2022-01-25 シーシーエス株式会社 Manufacturing method of LED light source unit, LED light emitting device and LED light source unit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9366390B2 (en) 2013-10-25 2016-06-14 Lextar Electronics Corporation Light emitting diode device and light emitting diode lamp

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