TWI840405B - Systems and methods of control for plasma processing - Google Patents
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Abstract
Description
本發明大致關於電漿處理，在特定實施例中，關於電漿處理之控制系統及方法。 [相關申請案之交互參照]The present invention generally relates to plasma processing and, in certain embodiments, to control systems and methods for plasma processing. [CROSS-REFERENCE TO RELATED APPLICATIONS]
本申請案主張於2018年8月14日提出之美國臨時專利申請案第62/718,454號、於2018年8月30日提出之美國臨時專利申請案第62/724,879號、於2018年12月17日提出之美國專利申請案第16/221,971號之優先權，其完整內容係併入本申請案中之參考資料。This application claims priority to U.S. Provisional Patent Application No. 62/718,454 filed on August 14, 2018, U.S. Provisional Patent Application No. 62/724,879 filed on August 30, 2018, and U.S. Patent Application No. 16/221,971 filed on December 17, 2018, the entire contents of which are incorporated herein by reference.
微電子工作件內之元件形成可能涉及一系列製造技術，包括基板上之許多材料層之形成、圖案化及去除。為了達成當前及下一代半導體元件之物理及電性規格，對於各種圖案化處理，能夠縮小特徵部尺寸同時保持結構完整之處理流程是令人期待的。The formation of components within a microelectronic workpiece may involve a range of manufacturing techniques, including the formation, patterning, and removal of many layers of material on a substrate. In order to achieve the physical and electrical specifications of current and next-generation semiconductor components, it is desirable to have a process flow that can shrink feature sizes while maintaining structural integrity for various patterning processes.
電漿處理通常用於在微電子工作件中形成元件。例如，電漿蝕刻及電漿沉積是半導體元件製造期間常見的處理步驟。在電漿處理期間，可使用來源功率及偏壓功率之組合來產生及引導電漿。圖18顯示出在電漿處理期間施加來源功率及偏壓功率之習知時序圖。在上方的圖中，來源功率或偏壓功率沒有明顯的脈衝。在中間的圖中，施加連續偏壓功率而沒有脈衝，並施加來源脈衝。在下方的圖中，施加連續來源功率而沒有脈衝，及施加偏壓脈衝。Plasma processing is commonly used to form components in microelectronic workpieces. For example, plasma etching and plasma deposition are common processing steps during semiconductor device manufacturing. During plasma processing, a combination of source power and bias power can be used to generate and guide the plasma. Figure 18 shows a known timing diagram for applying source power and bias power during plasma processing. In the top figure, there is no obvious pulse in the source power or bias power. In the middle figure, continuous bias power is applied without pulses, and source pulses are applied. In the bottom figure, continuous source power is applied without pulses, and bias pulses are applied.
根據本發明之一實施例，電漿處理方法包括：產生複數來源功率脈衝之一第一序列；產生複數偏壓功率脈衝之一第二序列；結合該第二序列之該等偏壓功率脈衝及該第一序列之該等來源功率脈衝，以形成交替的複數來源功率脈衝及複數偏壓功率脈衝之一組合序列；及使用該組合序列，產生包含複數離子之一電漿及藉由傳送該等離子至一基板之一主表面而處理該基板。According to an embodiment of the present invention, a plasma processing method includes: generating a first sequence of a plurality of source power pulses; generating a second sequence of a plurality of bias power pulses; combining the bias power pulses of the second sequence and the source power pulses of the first sequence to form a combined sequence of alternating plurality of source power pulses and plurality of bias power pulses; and using the combined sequence to generate a plasma comprising a plurality of ions and process the substrate by transmitting the plasma to a major surface of the substrate.
根據另一實施例，電漿處理方法包括：提供來源功率至一電漿處理腔室以產生電漿。該來源功率包括複數來源功率脈衝。該方法更包括：提供包括複數偏壓功率脈衝之偏壓功率至該電漿處理腔室。該複數來源功率脈衝及該複數偏壓功率脈衝被結合以形成一脈衝序列。該脈衝序列之每一脈衝包括該複數來源功率脈衝其中之一來源功率脈衝、該複數偏壓功率脈衝其中之一偏壓功率脈衝、及一時間間隔，在該時間間隔中該SP脈衝之一部分或該BP脈衝之一部分處於高幅度狀態。According to another embodiment, a plasma processing method includes: providing source power to a plasma processing chamber to generate plasma. The source power includes a plurality of source power pulses. The method further includes: providing bias power including a plurality of bias power pulses to the plasma processing chamber. The plurality of source power pulses and the plurality of bias power pulses are combined to form a pulse sequence. Each pulse of the pulse sequence includes one of the plurality of source power pulses, one of the plurality of bias power pulses, and a time interval during which a portion of the SP pulse or a portion of the BP pulse is in a high amplitude state.
根據本發明之又一實施例，電漿處理系統包括一控制器，用以產生複數來源功率脈衝之一第一序列及複數偏壓功率脈衝之一第二序列。該控制器更用以結合該第二序列之該等偏壓功率脈衝及該第一序列之該等來源功率脈衝，以形成交替的複數來源功率脈衝及複數偏壓功率脈衝之一組合序列。該電漿處理系統更包括一電漿處理腔室，耦接至該控制器並用以產生電漿，該電漿包括使用該組合序列所產生的複數離子。該電漿處理腔室用以支撐用於接收所產生的該等離子之一基板。According to another embodiment of the present invention, a plasma processing system includes a controller for generating a first sequence of a plurality of source power pulses and a second sequence of a plurality of bias power pulses. The controller is further configured to combine the bias power pulses of the second sequence with the source power pulses of the first sequence to form a combined sequence of alternating source power pulses and bias power pulses. The plasma processing system further includes a plasma processing chamber coupled to the controller and configured to generate plasma, the plasma including a plurality of ions generated using the combined sequence. The plasma processing chamber is configured to support a substrate for receiving the generated plasma.
以下詳細討論各種實施例之製造及使用。然而，應當理解，本文中所述之各種實施例可應用於各式各樣的特定情況。所討論之特定實施例僅用於說明製造及使用各種實施例之特定方式，不應以受限的範圍加以解釋。The making and using of various embodiments are discussed in detail below. However, it should be understood that the various embodiments described herein can be applied to a wide variety of specific situations. The specific embodiments discussed are only used to illustrate specific ways to make and use the various embodiments and should not be interpreted in a limited scope.
離子能量及離子角度可能影響各種電漿處理之品質、均勻性、選擇性及可預測性。例如，為了達成高深寬比特徵部之非等向性蝕刻，可能希望產生完全單方向的垂直離子束。此外，使用受控的離子角度分佈以調整、校正及控制這些定向離子之能力可能也是令人期望的。這種受控的角度離子分佈，例如，可能對於形成接觸窗（contact）、鰭（fin）、柵極線、其它前段或後段處理及一般的圖案化步驟以及其它處理是有幫助的。Ion energy and ion angle may affect the quality, uniformity, selectivity, and predictability of various plasma processes. For example, to achieve anisotropic etching of high depth and width features, it may be desirable to produce a completely unidirectional vertical ion beam. In addition, the ability to adjust, correct, and control these directional ions using a controlled ion angle distribution may also be desirable. Such a controlled angle ion distribution, for example, may be helpful for forming contacts, fins, grid lines, other front-end or back-end processing, and general patterning steps, as well as other processing.
然而，一般相信，在本領域中不存在主動控制機制來控制在電漿處理期間入射在微電子元件之形貌特徵部上之離子之角度。將絕對垂直或實質垂直的離子傳送至基板表面可能是有幫助的。此外，在考慮及∕或校正圖案化結構側壁上之散射時，控制傳送至結構中之離子束之角度可能也是有幫助的。例如，離子分佈角度之控制對於高深寬比接觸窗（HARC）型蝕刻及圖案化應用還有其它蝕刻∕沉積處理可能是有幫助的。However, it is generally believed that there is no active control mechanism in the art to control the angle of ions incident on topographical features of microelectronic devices during plasma processing. It may be helpful to deliver ions absolutely perpendicular or substantially perpendicular to the substrate surface. In addition, it may be helpful to control the angle of the ion beam delivered into the structure when considering and/or correcting for scattering on the sidewalls of the patterned structure. For example, control of the ion distribution angle may be helpful for high aspect ratio contact (HARC) type etching and patterning applications as well as other etch/deposition processes.
如本文中所述，提出了控制離子角度分佈以用於微電子工作件（或基板）之電漿處理之實施例。在電漿處理期間，所揭示的實施例控制施加至微電子工作件（例如，半導體晶圓）之交流（AC）功率及∕或脈衝式直流（DC）功率。藉由這些技術，所揭示的實施例可提供各種優點，包括被傳送至微電子工作件之離子之角度分佈之控制。根據以下描述，其它實施方式及優點對於所屬領域技術者而言亦可為顯而易見的。As described herein, embodiments of controlling the angular distribution of ions for plasma processing of microelectronic workpieces (or substrates) are presented. During plasma processing, the disclosed embodiments control the alternating current (AC) power and/or pulsed direct current (DC) power applied to the microelectronic workpiece (e.g., semiconductor wafer). Through these techniques, the disclosed embodiments can provide various advantages, including control of the angular distribution of ions delivered to the microelectronic workpiece. Based on the following description, other embodiments and advantages may also be apparent to those skilled in the art.
在各種實施例中，處理微電子工作件之方法包括提供來源功率至電漿處理腔室以產生電漿。例如，電漿可用於電漿處理，例如蝕刻、沉積、清潔、灰化等。提供至電漿處理腔室之來源功率是脈衝式的。具體而言，至電漿處理腔室之脈衝功率可包括在開啟狀態與關閉狀態之間之交替功率，從而形成一系列在時間上不同的脈衝。該方法更包括提供偏壓功率至電漿處理腔室。偏壓功率可使所產生的電漿中之帶電粒子加速朝向放置在電漿處理腔室中之微電子工作件。提供至電漿處理腔室之偏壓功率也是脈衝式的。然而，來源功率脈衝及偏壓功率脈衝在時間上至少部分不重疊。In various embodiments, a method for processing a microelectronic workpiece includes providing source power to a plasma processing chamber to generate plasma. For example, the plasma can be used for plasma processing, such as etching, deposition, cleaning, ashing, etc. The source power provided to the plasma processing chamber is pulsed. Specifically, the pulsed power to the plasma processing chamber may include alternating power between an on state and an off state, thereby forming a series of pulses that are different in time. The method further includes providing bias power to the plasma processing chamber. The bias power can accelerate charged particles in the generated plasma toward the microelectronic workpiece placed in the plasma processing chamber. The bias power provided to the plasma processing chamber is also pulsed. However, the source power pulse and the bias power pulse do not overlap at least partially in time.
本文中所述之各種實施例提出了系統及方法，以控制離子角度分佈以及離子能量，用於將離子傳送至表面以進行電漿處理，例如反應性離子蝕刻或電漿沉積。這些用於離子角度分佈之控制技術對於原子級蝕刻（ALE）及原子級沉積（ALD）還有空間ALE∕ALD及∕或其它處理可能也是有幫助的。本文中所述之各種實施例提供反相、反同步及∕或不同相的來源功率與偏壓功率脈衝。此外，藉由結合用於控制電漿電位之一或更多額外機制，可進一步增強這些技術。這些額外機制也可為脈衝式的，與來源電漿於相同的時間或以與來源電漿具有延遲之方式。可使用本文中所述之實施例來調變及控制各種電漿特性，例如離子溫度（Ti ）、電子溫度（Te ）、電子密度（ne ）、鞘電壓降（Vs ）等。Various embodiments described herein provide systems and methods for controlling ion angular distribution and ion energy for delivering ions to a surface for plasma processing, such as reactive ion etching or plasma deposition. These control techniques for ion angular distribution may also be helpful for atomic level etching (ALE) and atomic level deposition (ALD) as well as spatial ALE/ALD and/or other processes. Various embodiments described herein provide source power and bias power pulses that are in opposite phase, anti-synchronous, and/or out of phase. In addition, these techniques can be further enhanced by incorporating one or more additional mechanisms for controlling the plasma potential. These additional mechanisms may also be pulsed, at the same time as the source plasma or in a delayed manner relative to the source plasma. Various plasma properties such as ion temperature (T i ), electron temperature (T e ), electron density ( ne ), sheath voltage drop (V s ), etc. may be modulated and controlled using the embodiments described herein.
以下提供之實施例描述了操作電漿處理系統之各種系統及方法，尤其是包括來源功率脈衝及偏壓功率脈衝之電漿處理之控制方法。以下敘述說明了該等實施例。使用圖1以描述用於電漿處理之實施例控制方法之示例性概要時序圖及定性圖，電漿處理之實施例控制方法包括來源功率脈衝及偏壓功率脈衝。使用圖2以描述實施例電漿處理系統，包括來源脈衝調變電路及脈衝調變時序電路。使用圖3以描述用於電漿處理之實施例控制方法之二示例性概要時序圖，包括反同步偏壓功率脈衝。使用圖4至7以描述用於電漿處理之實施例控制方法之數個示例性概要時序圖，其顯示出包括一來源功率脈衝及一偏壓功率脈衝之單一週期。 使用圖8及9以描述包括電漿電位耦合元件之實施例電漿處理系統及實施例方法之相應概要時序圖。使用圖10及11以描述包括電子束來源之實施例電漿處理系統及實施例方法之相應概要時序圖。使用圖12及13以描述包括導電格柵之實施例電漿處理系統及實施例方法之相應概要時序圖。使用圖14以描述產生控制法則之實施例方法之示例性流程圖，該控制法則可用於在電漿處理期間主動控制離子角度分佈函數（IADF）。使用圖15以描述電漿處理之前饋控制之實施例方法之示例性流程圖。使用圖16及17以描述二實施例方法。The embodiments provided below describe various systems and methods for operating a plasma processing system, and in particular, control methods for plasma processing including source power pulses and bias power pulses. The embodiments are described below. Figure 1 is used to describe an exemplary summary timing diagram and qualitative diagram of an embodiment control method for plasma processing, and the embodiment control method for plasma processing includes a source power pulse and a bias power pulse. Figure 2 is used to describe an embodiment plasma processing system, including a source pulse modulation circuit and a pulse modulation timing circuit. Figure 3 is used to describe two exemplary summary timing diagrams of an embodiment control method for plasma processing, including an anti-synchronous bias power pulse. Figures 4 to 7 are used to describe several exemplary schematic timing diagrams of an embodiment control method for plasma processing, which show a single cycle including a source power pulse and a bias power pulse. Figures 8 and 9 are used to describe corresponding schematic timing diagrams of an embodiment plasma processing system and embodiment method including a plasma potential coupling element. Figures 10 and 11 are used to describe corresponding schematic timing diagrams of an embodiment plasma processing system and embodiment method including an electron beam source. Figures 12 and 13 are used to describe corresponding schematic timing diagrams of an embodiment plasma processing system and embodiment method including a conductive grid. Figure 14 is used to describe an exemplary flow chart of an embodiment method for generating a control law that can be used to actively control the ion angle distribution function (IADF) during plasma processing. An exemplary flow chart of an embodiment method of plasma processing feedforward control is described using Figure 15. Two embodiment methods are described using Figures 16 and 17.
圖1顯示出根據本發明實施例之用於電漿處理之示例性控制方法之脈衝序列之概要時序圖及相應的定性圖，電漿處理之示例性控制方法包括來源功率脈衝及偏壓功率脈衝。來源功率耦合至電漿處理系統之電漿處理腔室，並用於產生電漿以處理微電子工作件。偏壓功率亦耦合至電漿處理腔室，除了其它功能以外，亦可用於使離子加速朝向微電子工作件之表面。FIG. 1 shows a schematic timing diagram and corresponding qualitative diagram of a pulse sequence for an exemplary control method for plasma processing according to an embodiment of the present invention, the exemplary control method for plasma processing including source power pulses and bias power pulses. The source power is coupled to a plasma processing chamber of a plasma processing system and is used to generate plasma to process a microelectronic workpiece. The bias power is also coupled to the plasma processing chamber and can be used, among other functions, to accelerate ions toward the surface of the microelectronic workpiece.
參考圖1，時序圖100包括脈衝式的來源功率1及偏壓功率2，以產生及傳送離子至微電子工作件（例如，半導體晶圓）。具體而言，時序圖100包括具有在時間上至少部分不重疊之一或更多來源功率（SP）脈衝11及偏壓功率（BP）脈衝12之脈衝序列。例如，來源功率1可為在開啟狀態與關閉狀態之間切換之AC功率，以產生SP脈衝11（AC功率之頻率高於SP脈衝11之頻率）。類似地，偏壓電源2亦可為AC功率。例如，偏壓功率2可實施為RF功率並且可具有DC自偏壓。或者，來源功率1及偏壓功率2其中一或二者可為DC功率。Referring to FIG. 1 , a timing diagram 100 includes a
在各種實施例中，脈衝序列是週期性的，具有脈衝調變週期5，並且包括複數SP脈衝11及BP脈衝12。然而，在某些例子中，脈衝序列可指單一SP脈衝及單一BP脈衝。此外，儘管週期性可能是有益的，但是沒有嚴格要求脈衝序列是週期性的、或者SP脈衝具有與BP脈衝相同的週期。In various embodiments, the pulse sequence is periodic, has a
如曲線圖102所示，所產生的電漿之溫度曲線31及密度曲線32根據時序圖100之施加的來源功率1而變化。SP脈衝11產生電漿輝光階段，其特徵在於各種電漿參數（例如電子密度ne
、電子溫度Te
及離子溫度Ti
）之增加。 SP脈衝11之初始施加可導致電漿溫度（例如，Te
及Ti
）之尖峰21，其在SP脈衝之其餘部分會鬆弛到偽平衡狀態23。在SP脈衝結束後，電漿進入餘輝階段，在餘輝階段期間離子及電子可能冷卻下來，導致Te
、Ti
之降低。電子及離子藉由雙極擴散而擴散到壁上，導致ne
之降低。在各種實施例中，在餘輝階段期間，施加BP脈衝以使離子加速朝向微電子工作件之表面。As shown in
如曲線圖102所示，在餘輝階段，Te
及Ti
之降低可能比ne
之降低更快。因為電子密度ne
與可利用的離子有關，所以在餘輝階段施加BP脈衝可能特別有效，以便使低溫離子加速至微電子工作件之表面。在餘輝階段，電漿電流亦可能減少。當施加偏壓功率時（例如，使用BP脈衝），此電流降可允許餘輝階段中橫跨電漿鞘VDC
（RF DC自偏壓）之大電壓差Vp
。增大的電壓差Vp
及時間平均DC電壓降VDC
以及較低的離子溫度可改善離子通量之方向性。As shown in
因此，SP脈衝及BP脈衝在時間上至少部分不重疊。在各種實施例中，如時序圖100所示，SP脈衝及BP脈衝完全不同相。在其它實施例中，SP脈衝及BP脈衝可部分重疊。因此，該方法之實施例包括施加來源功率1但不施加偏壓功率2之非零時間間隔，也包括施加偏壓功率2但不施加來源功率1之非零時間間隔。Thus, the SP pulse and the BP pulse do not overlap in time at least partially. In various embodiments, as shown in timing diagram 100, the SP pulse and the BP pulse are completely out of phase. In other embodiments, the SP pulse and the BP pulse may overlap partially. Thus, embodiments of the method include non-zero time intervals when
在某些例子中，傳送實質垂直的離子至被處理表面可視為是有利的。離子在表面處之入射角之平均偏差可稱為角擴展（angular spread）。角擴展可能是由於在電漿鞘中之離子之散射、以及在電漿中之離子在加速通過電漿鞘朝向表面之前之隨機熱運動所引起。雖然隨機熱運動可能導致角擴展之變寬，但可藉由存在於電漿鞘中之電場所得到之方向性來達成角擴展之變窄。在電漿鞘中產生電場之方法可為施加偏壓功率。通常，特定離子角度分佈之角擴展〈θ〉可藉由下列比例方程式加以描述：（1）In certain instances, it may be considered advantageous to deliver substantially normal ions to the surface being treated. The average deviation of the angle of incidence of the ions at the surface may be referred to as the angular spread. The angular spread may be caused by scattering of the ions in the plasma sheath, as well as random thermal motion of the ions in the plasma before being accelerated through the plasma sheath toward the surface. Although random thermal motion may result in a widening of the angular spread, a narrowing of the angular spread may be achieved by the directionality obtained by the electric field present in the plasma sheath. The electric field may be generated in the plasma sheath by applying a bias power. In general, the angular spread 〈θ〉 of a particular ion angular distribution may be described by the following proportional equation: (1)
由方程式（1）可看出，當離子溫度Ti
升高時，角擴展〈θ〉增大，導致較少的垂直離子。類似地，根據方程式（1），當偏壓電壓VDC
增加時，角擴展〈θ〉減小，導致較多的垂直離子。因此，當Ti
相對較低時，將偏壓功率2施加至電漿處理腔室可能是有利的，以便增加在工作件表面處之離子之垂直性。應當注意，在方程式（1）中，離子溫度Ti
通常以電子伏特（eV）表示，而偏壓電壓VDC
以伏特（V）表示，此方便地允許從方程式（1）之分母中省略離子之電荷（+1）。As can be seen from equation (1), as the ion temperature Ti increases, the angular spread 〈θ〉 increases, resulting in fewer vertical ions. Similarly, according to equation (1), as the bias voltage V DC increases, the angular spread 〈θ〉 decreases, resulting in more vertical ions. Therefore, it may be advantageous to apply a
仍然參考圖1，時序圖100之脈衝序列可由脈衝調變處理參數加以定義。脈衝調變處理參數可包括與來源功率1序列相對應之SP脈衝寬度3及SP脈衝幅度4、以及與偏壓功率2序列相對應之前緣偏壓偏移6、BP脈衝寬度7、BP脈衝幅度8及後緣偏壓偏移9。具體而言，每一SP脈衝11包括SP脈衝寬度3及SP脈衝幅度4，而每一BP脈衝12包括BP脈衝寬度7及BP脈衝幅度8。應該指出，除非另有說明，否則本文中所使用之幅度表示特定脈衝之平均峰至峰幅度。Still referring to FIG. 1 , the pulse sequence of the timing diagram 100 may be defined by pulse modulation processing parameters. The pulse modulation processing parameters may include
如圖1所示，SP脈衝11及BP脈衝12可在時間上完全不重疊。在此特定例子中，SP脈衝寬度3為一時間間隔，在其中施加來源功率1做為SP脈衝而無偏壓功率2，BP脈衝寬度7為一時間間隔，在其中施加偏壓功率2做為BP脈衝而無來源功率1。在SP脈衝11及BP脈衝12部分不重疊之實施例中，不重疊的時間間隔可包括SP脈衝寬度3及∕或BP脈衝寬度7之部分。As shown in FIG1 , the
對於SP脈衝11及BP脈衝12兩者，可藉由選擇給定脈衝調變週期5之工作週期（%）來實現特定的脈衝寬度。例如，如果將脈衝調變週期設定為150 µs，則56%來源功率工作週期（%）及28%偏壓功率工作週期（%）將導致84 µs之SP脈衝寬度及42 µs之BP脈衝寬度。在一實施例中，來源功率1及偏壓功率2具有相同的脈衝調變週期。或者，來源功率1及偏壓功率2可以不同的脈衝調變週期來操作。For both the
使用SP脈衝11之關閉時間，可有利地控制離子及∕或其它自由基至微電子工作件表面之通量。例如，本案發明人發現，當SP關閉時間（6/7/9）設定為小於L2
∕sD時，可維持固定的自由基通量，其中L是電漿處理腔室之關鍵尺寸，D是維持固定通量之物種之擴散係數，而s是該物種之黏附係數。例如，L可為產生離子∕自由基之位置與最近的壁之間之距離。在一實施例中，L為來源區域（亦即，離子∕自由基所生成之位置）與SP耦合元件之間之距離。在各種實施例中，SP關閉時間之調整可增加或減少離子及∕或其它自由基至工作件表面之通量。The off time of the
如圖1所示，SP脈衝11與BP脈衝12之間之延遲可稱為前緣偏壓偏移6。前緣偏壓偏移6可以脈衝調變週期5之百分比加以實施。例如，前緣偏壓偏移可在脈衝調變週期5之 -10%至 +10%之間變化。或者，前緣偏壓偏移6可設定為特定時間值。例如，繼續上述例子（其中來源功率1及偏壓功率2具有設定為150 µs之相同脈衝調變週期），則10%的前緣偏壓偏移將導致15 µs之延遲在SP脈衝之後緣與BP脈衝之間。在上述範例中，前緣偏壓偏移6係設定為正。然而，前緣偏壓偏移6亦可為零或負。As shown in FIG1 , the delay between the
類似地，在BP脈衝12與SP脈衝11之間之延遲可稱為後緣偏壓偏移9，並且可藉由SP脈衝寬度3、前緣偏壓偏移6及BP脈衝寬度7之組合加以實施。繼續上述範例，56%來源功率工作週期（%）、10%前緣偏壓偏移及28%偏壓功率工作週期（%）佔整個脈衝調變週期之94%。因此，在此特定範例中，在BP脈衝之後緣與SP脈衝之前緣之間之延遲等於脈衝調變週期之6%。因為脈衝調變週期為150 µs，所以該延遲（即後緣偏壓偏移9）等於9 µs。類似於前緣偏壓偏移6，後緣偏壓偏移9不需要為正，而亦可為零或負。Similarly, the delay between the
脈衝幅度可由相對應的高及低幅度狀態加以定義。例如，高及低幅度可為電壓位準。具體而言，每一SP脈衝11可在SP低幅度狀態13與SP高幅度狀態14之間振盪，而每一BP脈衝12可在BP低幅度狀態17與BP高幅度狀態18之間振盪。可施加正或負DC偏壓至來源功率1或偏壓功率2之一或兩者，使得各別的高及低幅度達到期望的位準。The pulse amplitudes may be defined by corresponding high and low amplitude states. For example, the high and low amplitudes may be voltage levels. Specifically, each
應當指出，溫度曲線31及密度曲線32兩者在本質上是定性的。因此，儘管兩者皆可表示與脈衝序列對電漿參數（例如Te
，Ti
及ne
）之影響相關之重要現象，但其皆未打算以特定比例繪製或定量上準確的。此外，為了清楚起見，可能已經進行簡化。例如，電子溫度Te
及離子溫度Ti
在曲線圖102中係以單一曲線加以表示，因為即使在冷電漿中Te
至少比Ti
大一個數量級，但曲線之形狀是類似的。It should be noted that both the
圖2顯示出根據本發明實施例之示例性電漿處理系統之方塊圖，包括來源脈衝調變電路及脈衝調變時序電路。圖2之電漿處理系統可用於執行本文中所述之任何實施例方法，例如圖1之方法。FIG2 shows a block diagram of an exemplary plasma processing system according to an embodiment of the present invention, including a source pulse modulation circuit and a pulse modulation timing circuit. The plasma processing system of FIG2 can be used to perform any of the embodiments described herein, such as the method of FIG1.
參考圖2，電漿處理系統200包括耦合至電漿處理腔室210之SP耦合元件15。SP耦合元件可允許將來源功率施加至電漿處理腔室210，導致電漿60之產生。在各種實施例中，SP耦合元件15是位於電漿處理腔室210周圍之導電線圈，在一實施例中是四分之一波長螺旋狀諧振器。在另一實施例中，SP耦合元件15是半波長螺旋狀諧振器，其可以被實現為位於電漿處理腔室210上方之平面螺旋形線圈。或者，例如，可採用其它SP耦合元件，例如天線、板狀電極、或波導。2, a
電漿處理系統200更包括耦合至電漿處理腔室210之BP耦合元件19。BP耦合元件19可使偏壓功率施加至被處理之微電子工作件。在各種實施例中，BP耦合元件19是基板固持器，在一實施例中是靜電夾盤。The
可使用SP控制路徑201以將來源功率耦合至電漿處理腔室210，SP控制路徑201包括SP脈衝調變電路51。SP脈衝調變電路51可調變來源信號於SP高幅度狀態14與SP低幅度狀態13之間。例如，已調變的來源信號可對應於SP脈衝11，如參考圖1所述。已調變的來源信號可由SP函數產生器20接收，SP函數產生器20可將波形疊加至已調變的來源信號上。SP函數產生器20亦可可選地包括放大電路，放大電路用於增加已調變的來源信號之幅度。The
被疊加的波形之頻率可高於脈衝調變頻率。在各種實施例中，被疊加的波形之頻率可為RF頻率，在一實施例中約為13.56 MHz。因此，所產生的SP脈衝每一者可包括被疊加的波形之數個週期。波形形狀可包括週期性波形，例如正弦波、方波、鋸齒波等。或者，波形形狀可包括非週期性波（例如複數不同頻率之正弦波之疊加），以產生任意波形形狀。The frequency of the superimposed waveform may be higher than the pulse modulation frequency. In various embodiments, the frequency of the superimposed waveform may be an RF frequency, approximately 13.56 MHz in one embodiment. Thus, each of the generated SP pulses may include several cycles of the superimposed waveform. The waveform shape may include a periodic waveform, such as a sine wave, a square wave, a sawtooth wave, etc. Alternatively, the waveform shape may include a non-periodic wave (e.g., a superposition of multiple sine waves of different frequencies) to generate an arbitrary waveform shape.
SP控制路徑201可包括可選的SP阻抗匹配網路25。在藉由SP耦合元件15以耦合至電漿處理腔室210之前，由SP函數產生器20所產生之SP脈衝可先通過可選的SP阻抗匹配網路25。在某些電漿處理系統中，例如當SP耦合元件15是感應耦合至電漿60之諧振結構時，可省略可選的SP阻抗匹配網路25。相反地，當SP耦合元件15是非諧振時，可包括可選的SP阻抗匹配網路25。藉由將負載之阻抗與供應端之阻抗進行匹配，可選的SP阻抗匹配網路25可用於確保來源功率被有效地耦合至電漿60。The
仍然參考圖2，可使用BP控制路徑202以將偏壓功率耦合至電漿處理腔室210。可經由脈衝調變時序電路252將BP控制路徑202耦合至SP控制路徑201。脈衝調變時序電路252可判定BP脈衝之時序（相對於由SP控制路徑201所產生之SP脈衝之時序）。脈衝調變時序電路252可從SP脈衝調變電路51接收信號，並引入由SP脈衝之前緣或後緣所觸發之延遲。例如，如果前緣偏壓偏移參數被設定為脈衝調變週期之8%，則脈衝調變時序電路252可在被SP脈衝之後緣觸發之後引入等於脈衝調變週期之8%之延遲。或者，如果脈衝調變時序電路252係設置為由SP脈衝之前緣所觸發，則來源功率工作週期（%）加上脈衝調變週期之8%之延遲可由脈衝調變時序電路252引入。或者，脈衝調變時序電路252可判定SP脈衝之時序（相對於由BP控制路徑202所產生之BP脈衝之時序）。Still referring to FIG. 2 , the
類似於SP控制路徑201，BP控制路徑202可包括由脈衝調變時序電路252觸發之可選的BP脈衝調變電路53。可選的BP脈衝調變電路53可調變偏壓信號於BP高幅度狀態與BP低幅度狀態之間。例如，已調變的偏壓信號可對應於BP脈衝12，如參考圖1所述。或者，可省略可選的BP脈衝調變電路53，且延遲的已調變的來源信號可與BP脈衝相對應。Similar to the
已調變的偏壓信號可由可選的BP函數產生器30接收。可選的BP函數產生器30可將波形疊加至已調變的偏壓信號上。該波形可能類似或不同於疊加至已調變的來源信號上之波形，並且可具有如先前所述之任何期望的波形形狀。可選的BP函數產生器30亦可可選地包括放大電路，以增加已調變的偏壓信號之幅度。在一實施例中，傳送至電漿處理腔室210之偏壓功率為DC功率。在此例子中，可省略可選的BP函數產生器30。在一些需要放大、但不需要函數產生之例子中，可包括放大電路來代替可選的BP函數產生器30。The modulated bias signal may be received by an optional
在BP控制路徑202中，在可選的BP函數產生器30與BP耦合元件19之間亦包括BP阻抗匹配網路35。藉由將負載之阻抗與供應端之阻抗進行匹配，BP阻抗匹配網路可用於確保偏壓功率有效地耦合至電漿處理腔室210。A BP
上述之一或更多元件可包含在控制器中。例如，如圖2所示，SP脈衝調變電路51、脈衝調變時序電路252及可選的BP脈衝調變電路53可包含在控制器250中。控制器250可位於相對於電漿處理腔室210之本地。或者，控制器250可位於相對於電漿處理腔室210之遠端。控制器250可能能夠與SP控制路徑201及BP控制路徑202中之一或更多元件交換數據。每一阻抗匹配網路可由控制器250所控制、或可包括單獨的控制器。One or more of the above elements may be included in a controller. For example, as shown in FIG. 2 , the SP
控制器250可用以設定、監視及∕或控制與產生電漿及傳送離子至微電子工作件表面相關之各種控制參數。控制參數可包括，但不限於，來源功率及偏壓功率兩者之功率位準、頻率及工作週期（%）還有偏壓偏移百分比。亦可使用其它控制參數集。例如，可直接輸入SP脈衝及BP脈衝之脈衝寬度以及偏壓偏移，而不是將其定義為脈衝調變週期之工作週期（%）。The
圖3顯示出根據本發明實施例之電漿處理之示例性控制方法之概要時序圖，包括反同步偏壓功率脈衝。圖3之時序圖可為其它實施例時序圖（例如，圖1之時序圖100）之特定實行例。類似標示的元件可如以上所述。FIG3 shows a schematic timing diagram of an exemplary control method for plasma processing according to an embodiment of the present invention, including an anti-synchronous bias power pulse. The timing diagram of FIG3 may be a specific implementation of other embodiment timing diagrams (e.g., timing diagram 100 of FIG1). Similar labeled elements may be as described above.
參考圖3，時序圖300包括脈衝式產生的來源功率1及偏壓功率2，以產生及傳送離子至微電子工作件。具體而言，時序圖300包括週期性脈衝序列，具有對於一系列50% SP脈衝311及50% BP脈衝312之共享脈衝調變週期305。50% SP脈衝311及50% BP脈衝312兩者為脈衝式產生，而達到對應於100%工作週期（%）之共享脈衝調變週期305之一半。亦即，50% SP脈衝311具有50%工作週期（%）之50% SP脈衝寬度303，而50% BP脈衝312具有50%工作週期（%）之50% BP脈衝寬度307。3, a timing diagram 300 includes a
在一實施例中，共享脈衝調變週期305為大約200 μs。因此，在該實施例中，50% SP脈衝寬度303為大約100 μs，而50% BP脈衝寬度307為大約100 μs。在其它實施例中，共享脈衝調變週期305可為任何期望的長度。例如，共享脈衝調變週期305可小於或大於200 μs。在各種實施例中，共享脈衝調變週期305為微秒（μs）之數量級。在其它實施例中，共享脈衝調變週期305可為毫秒（ms）或秒（s）之數量級。在一實施例中，共享脈衝調變週期305大約為1s。In one embodiment, the shared
仍然參考圖3，時序圖320類似於時序圖300，包括脈衝式產生的來源功率1及偏壓功率2，具有共享脈衝調變週期305。然而，在時序圖320中，在50% SP脈衝311與>50% BP脈衝322之間包含一非零前緣偏壓偏移326。因為50% SP脈衝311之關閉時間等於50%工作週期（%），所以>50% BP脈衝322具有>50% BP脈衝寬度327，>50% BP脈衝寬度327等於小於50%之工作週期（%）。具體而言，>50% BP脈衝寬度327等於50%工作週期（%）減去該非零前緣偏壓偏移326。Still referring to FIG. 3 , timing diagram 320 is similar to timing diagram 300 , including
在一實施例中，共享脈衝調變週期305為大約200 μs，非零前緣偏壓偏移326為大約20 μs，且>50% BP脈衝寬度327為大約80 μs。因此，在此實施例中，50% SP脈衝寬度303為大約100 μs。此對應於大約10%工作週期（%）之非零前緣偏壓偏移326、及大約40%工作週期（%）之＜50% BP脈衝寬度327。在其它實施例中，非零前緣偏壓偏移326可為小於共享脈衝調變週期305之任何期望的長度。例如，非零前緣偏壓偏移326可小於或大於20 μs。In one embodiment, the shared
因為50% SP脈衝311及50% BP脈衝312在時間上完全不重疊並且共用著共享脈衝調變週期305，所以50% SP脈衝311及50% BP脈衝312是反同步的。亦即，因為當50% BP脈衝312處於低幅度狀態時，50% SP脈衝311僅處於高幅度狀態，所以50% SP脈衝311與50% BP脈衝312不同相。此外，在它們共用相同的調變週期之意義上，50% SP脈衝311與50% BP脈衝312是同步的。這種不同相的同步關係可稱為反同步關係。類似地，50% SP脈衝311與>50% BP脈衝322也彼此為反同步的。Because the 50
將反同步BP脈衝傳送至電漿處理腔室可有益地增加BP脈衝之效率。例如，在SP脈衝之高幅度狀態期間，能量被耦合至電漿以產生離子。離子之熱能正在增加，此可增加熱運動。平均而言，離子之隨機熱運動可能將水平速度分量引入由偏壓功率所賦予之垂直速度。另外，在SP脈衝之高幅度狀態期間，流至處理中基板之電流可能很大，此在固定功率時可能減少至基板之電壓。因此，與在SP脈衝之低幅度狀態期間施加BP脈衝相比，在SP脈衝之高幅度狀態期間施加偏壓功率可能在產生垂直或接近垂直的離子方面效率較低。Delivering anti-synchronous BP pulses to a plasma processing chamber can beneficially increase the efficiency of the BP pulses. For example, during the high amplitude state of the SP pulse, energy is coupled to the plasma to generate ions. The thermal energy of the ions is increasing, which can increase thermal motion. On average, the random thermal motion of the ions may introduce a horizontal velocity component into the vertical velocity imparted by the bias power. In addition, during the high amplitude state of the SP pulse, the current flowing to the substrate being processed may be large, which may reduce the voltage to the substrate at a fixed power. Therefore, applying the bias power during the high amplitude state of the SP pulse may be less efficient in generating vertical or near-vertical ions than applying the BP pulse during the low amplitude state of the SP pulse.
除了其它因素之外，還可以基於電漿之冷卻速率來判定非零前緣偏壓偏移326。例如，因為在SP脈衝與BP脈衝之間之延遲期間來源功率1是關閉的，所以產生的電漿可能會喪失功率，且帶電粒子之溫度及密度可能會降低。因此，非零前緣偏壓偏移326可有利地允許離子溫度Ti
為低（相較於由隨後的BP脈衝所引起之鞘電壓VS
）。The non-zero leading edge bias offset 326 may be determined based on, among other factors, the cooling rate of the plasma. For example, because the
時序圖300及時序圖320是如前所述之時序圖100之特定例子。例如，時序圖300對應於SP脈衝寬度3等於50%工作週期（%）、及前緣偏壓偏移6及後緣偏壓偏移9兩者等於零之情況。類似地，時序圖320對應於SP脈衝寬度3等於50%工作週期（%）、前緣偏壓偏移6為非零且為正、及後緣偏壓偏移9等於零之情況。鑑於本文中所述之實施例，藉由改變脈衝調變處理參數，許多其它時序圖對於本領域技術人員將是顯而易見的。亦即，可使用不同的偏移、脈衝寬度及脈衝調變週期，但仍然利用本文中所述之技術。Timing diagram 300 and timing diagram 320 are specific examples of timing diagram 100 as described above. For example, timing diagram 300 corresponds to the case where
圖4顯示出根據本發明實施例之用於電漿處理之示例性控制方法之概要時序圖，包括高頻RF來源功率脈衝及低頻RF偏壓功率脈衝。圖4之時序圖可為其它實施例時序圖（例如，圖1之時序圖100或圖3之時序圖320）之特定實行例。類似標示的元件可如以上所述。FIG4 shows a schematic timing diagram of an exemplary control method for plasma processing according to an embodiment of the present invention, including a high frequency RF source power pulse and a low frequency RF bias power pulse. The timing diagram of FIG4 may be a specific implementation of the timing diagrams of other embodiments (e.g., the timing diagram 100 of FIG1 or the timing diagram 320 of FIG3). Similar labeled elements may be as described above.
參考圖4，時序圖400包括脈衝式產生的來源功率1及偏壓功率2，以產生及傳送離子至微電子工作件。具體而言，時序圖400包括脈衝調變週期5，具有一或更多SP脈衝11及一或更多BP脈衝12，具有SP脈衝寬度3、前緣偏壓偏移6及BP脈衝寬度7。每一SP脈衝11包括具有SP頻率fSP
之週期性波形，其可由函數產生器疊加在SP脈衝11上。在一實施例中，週期性波形可為正弦波，且來源功率可為AC功率。然而，亦可能是其它波形，如前所述。每一BP脈衝12亦可包括具有BP頻率fBP
之週期性波形，其可與SP脈衝11之週期性波形相似或不同。Referring to FIG. 4 , a timing diagram 400 includes a
本案發明人發現，在某些情況下，在餘輝階段中施加高頻脈衝可能導致非期望的電子加熱及電漿產生（例如，在鹵素電漿中），其有可能會降低及∕或消除如本文中所述之脈衝序列之效率。藉由在餘輝階段期間施加低頻AC功率、DC功率或交替極性DC電壓，可減輕此潛在問題。如上所述，餘輝間隔可在來源功率處於低幅度狀態時開始。因此，包括低頻AC功率、DC功率或交替極性DC電壓之BP脈衝可有利地減少或消除在餘輝階段中非期望的電子加熱及電漿產生。The inventors of the present invention have discovered that, in certain circumstances, applying a high frequency pulse during the afterglow phase may result in undesirable electron heating and plasma generation (e.g., in a halogen plasma), which may reduce and/or eliminate the efficiency of the pulse sequence as described herein. This potential problem may be mitigated by applying a low frequency AC power, DC power, or alternating polarity DC voltage during the afterglow phase. As described above, the afterglow interval may begin when the source power is at a low amplitude state. Therefore, a BP pulse including a low frequency AC power, DC power, or alternating polarity DC voltage may advantageously reduce or eliminate undesirable electron heating and plasma generation during the afterglow phase.
因此，在各種實施例中，fBP 小於fSP 。在一實施例中，fBP 小於20 MHz。在另一實施例中，fBP 小於400 kHz。在一實施例中，fSP 大約為13.56 MHz，且fBP 小於400 kHz。SP頻率fSP 可為任何頻率，例如RF、特高頻（VHF）、微波（MW）等。在一實施例中，fSP 大於10 MHz，且fBP 小於5 MHz。在另一實施例中，fSP 大於50 MHz，且fBP 小於5 MHz。在又一實施例中，fSP 在大約50 MHz與大約150 MHz之間，而fBP 在大約1 MHz與大約5 MHz之間。Therefore, in various embodiments, f BP is less than f SP . In one embodiment, f BP is less than 20 MHz. In another embodiment, f BP is less than 400 kHz. In one embodiment, f SP is approximately 13.56 MHz and f BP is less than 400 kHz. The SP frequency f SP may be any frequency, such as RF, very high frequency (VHF), microwave (MW), etc. In one embodiment, f SP is greater than 10 MHz and f BP is less than 5 MHz. In another embodiment, f SP is greater than 50 MHz and f BP is less than 5 MHz. In yet another embodiment, f SP is between approximately 50 MHz and approximately 150 MHz, and f BP is between approximately 1 MHz and approximately 5 MHz.
圖5顯示出根據本發明實施例之用於電漿處理之示例性控制方法之概要時序圖，包括高頻RF來源功率脈衝及低頻方波偏壓功率脈衝。圖5之時序圖可為其它實施例時序圖（例如，圖1之時序圖100或圖3之時序圖320）之特定實行例。類似標示的元件可如以上所述。FIG5 shows a schematic timing diagram of an exemplary control method for plasma processing according to an embodiment of the present invention, including a high frequency RF source power pulse and a low frequency square wave bias power pulse. The timing diagram of FIG5 may be a specific implementation of other embodiment timing diagrams (e.g., timing diagram 100 of FIG1 or timing diagram 320 of FIG3). Similar labeled elements may be as described above.
參考圖5，時序圖500包括脈衝式產生的來源功率1及偏壓功率2，以產生及傳送離子至微電子工作件。具體而言，時序圖500包括脈衝調變週期5，具有一或更多SP脈衝11及一或更多BP脈衝12，具有SP脈衝寬度3、前緣偏壓偏移6及BP脈衝寬度7。除了每一BP脈衝12包括具有方波頻率fSW
及方波脈衝寬度517之週期性方波之外，時序圖500類似於圖4之時序圖400。方波頻率fSW
可小於fSP
，且可與上述之時序圖400之BP頻率fBP
有類似的大小。在各種實施例中，可藉由函數產生器由諧波正弦波形之疊加來產生週期性方波。Referring to FIG5, a timing diagram 500 includes a
圖6顯示出根據本發明實施例之用於電漿處理之示例性控制方法之概要時序圖，包括高頻RF來源功率脈衝及脈衝式DC偏壓功率脈衝。圖6之時序圖可為其它實施例時序圖（例如，圖1之時序圖100或圖3之時序圖320）之特定實行例。類似標示的元件可如以上所述。FIG6 shows a schematic timing diagram of an exemplary control method for plasma processing according to an embodiment of the present invention, including a high frequency RF source power pulse and a pulsed DC bias power pulse. The timing diagram of FIG6 may be a specific implementation of the timing diagrams of other embodiments (e.g., the timing diagram 100 of FIG1 or the timing diagram 320 of FIG3). Similar labeled elements may be as described above.
參考圖6，時序圖600包括脈衝式產生的來源功率1及偏壓功率2，以產生及傳送離子至微電子工作件。具體而言，時序圖600包括脈衝調變週期5，具有一或更多SP脈衝11及一或更多BP脈衝12，具有SP脈衝寬度3、前緣偏壓偏移6及BP脈衝寬度7。除了每一BP脈衝12包括具有DC頻率fDC
及DC脈衝寬度617之一或更多DC脈衝之外，時序圖600類似於圖4之時序圖400。除了可藉由關閉及打開DC電壓而產生每一DC脈衝612之外，DC頻率fDC
類似於方波頻率fSW
。DC頻率fDC
可小於fSP
，且可與上述的時序圖400之BP頻率fBP
具有類似的大小。6 , a timing diagram 600 includes a
SP脈衝11可包括用於電漿產生之AC功率，而處理中的微電子工作件（例如，晶圓）可用包括DC電壓之BP脈衝12來施加脈衝。每一BP脈衝12中包括之DC脈衝612之數量可相當小。因此，在各種實施例中，DC頻率fDC
遠小於SP頻率fSP
。例如，在一實施例中，每一BP脈衝12可僅包括一連續DC脈衝612。或者，在每一BP脈衝12中包括之DC脈衝612可少於五。然而，在每一BP脈衝12中可包括任何合適數量之DC脈衝612。The
圖7顯示出根據本發明實施例之用於電漿處理之示例性控制方法之概要時序圖，包括高頻RF來源功率脈衝及交替極性脈衝式DC偏壓功率脈衝。圖7之時序圖可為其它實施例時序圖（例如，圖1之時序圖100或圖3之時序圖320）之特定實行例。類似標示的元件可如以上所述。FIG. 7 shows a schematic timing diagram of an exemplary control method for plasma processing according to an embodiment of the present invention, including a high frequency RF source power pulse and an alternating polarity pulsed DC bias power pulse. The timing diagram of FIG. 7 may be a specific implementation of the timing diagrams of other embodiments (e.g., the timing diagram 100 of FIG. 1 or the timing diagram 320 of FIG. 3). Similar labeled elements may be as described above.
參考圖7，時序圖700包括脈衝式產生的來源功率1及偏壓功率2，以產生及傳送離子至微電子工作件。具體而言，時序圖700包括脈衝調變週期5，具有一或更多SP脈衝11及一或更多BP脈衝12，具有SP脈衝寬度3、前緣偏壓偏移6及BP脈衝寬度7。除了每一BP脈衝12包括具有AP頻率fAP
之交替極性（AP）DC脈衝712之外，時序圖700類似於圖6之時序圖600。AP DC脈衝712類似於圖6之DC脈衝612，但AP DC脈衝712係配置為相對於參考電位、在正電壓位準與負電壓位準之間交替。7 , a timing diagram 700 includes a
例如，當處理中的基板包括可能累積電荷（其可能導致非期望的電弧放電）之介電層時，交替極性DC電壓是有用的。在一些實施例中，正AP DC脈衝712之寬度及高度可能不同於負AP DC脈衝712之寬度及高度。例如，正DC脈衝可將離子吸引至工作件表面。然而，隨後的負DC脈衝可能排斥離子而使其離開表面。因此，較長的正DC脈衝及較大的負DC脈衝可能是有利的。在一實施例中，正DC脈衝之寬度大於負DC脈衝之寬度。For example, alternating polarity DC voltages are useful when the substrate being processed includes a dielectric layer that may accumulate charge, which may cause undesirable arc discharges. In some embodiments, the width and height of the positive
在一實施例中，正DC脈衝之高度小於負DC脈衝之高度。在一實施例中，正DC脈衝之寬度大於負DC脈衝之寬度，且正DC脈衝之高度小於負DC脈衝之高度。在其它實施例中，正及負DC脈衝之高度及∕或寬度可以相同。在各種實施例中，每一BP脈衝12包括單一正AP DC脈衝及單一負AP DC脈衝。在一實施例中，單一正AP DC脈衝出現在來源功率關閉（即，低幅度狀態）時，且單一負AP DC脈衝出現在來源功率開啟（即，與隨後的SP脈衝之高幅度狀態在時間上重疊）時。In one embodiment, the height of the positive DC pulse is less than the height of the negative DC pulse. In one embodiment, the width of the positive DC pulse is greater than the width of the negative DC pulse, and the height of the positive DC pulse is less than the height of the negative DC pulse. In other embodiments, the height and/or width of the positive and negative DC pulses can be the same. In various embodiments, each
圖8顯示出根據本發明之實施例之示例性電漿處理系統之方塊圖，示例性電漿處理系統除了包括來源脈衝調變電路及脈衝調變時序電路之外還包括電漿電位耦合元件。圖8之電漿處理系統可為其它實施例電漿處理系統（例如，圖2之電漿處理系統200）之特定實行例。圖8之電漿處理系統可用於執行本文中所述之任何實施例方法，例如圖9之方法。類似標示的元件可如上所述。FIG8 shows a block diagram of an exemplary plasma processing system according to an embodiment of the present invention, the exemplary plasma processing system including a plasma potential coupling element in addition to a source pulse modulation circuit and a pulse modulation timing circuit. The plasma processing system of FIG8 may be a specific implementation of other embodiment plasma processing systems (e.g., the
參考圖8，電漿處理系統800包括使用BP時序電路52耦接至SP控制路徑801之BP控制路徑802，BP時序電路52提供來源功率及偏壓功率至電漿處理腔室810。SP控制路徑801及BP控制路徑802可類似於圖2之SP控制路徑201及BP控制路徑202。此外，電漿處理系統800亦包括電位控制功率（PCP）控制路徑803。PCP控制路徑803使用電漿電位耦合元件816將功率耦合至電漿60。在一實施例中，電漿電位耦合元件816是板電極。然而，可使用任何上述的耦合元件。8, the
PCP控制路徑803可經由可選的PCP時序電路854而耦接至SP控制路徑801。可選的PCP時序電路854可耦接至SP脈衝調變電路51及∕或BP時序電路52。類似於BP時序電路52，可選的PCP時序電路854可相對於由SP控制路徑801及BP控制路徑802所傳送之SP脈衝及∕或BP脈衝來控制將電位控制功率施加至電漿處理腔室810之時序。PCP控制路徑803可經由可選的PCP脈衝調變電路855而提供PCP脈衝至電漿電位耦合元件816。The
在各種實施例中，SP脈衝調變電路51、BP時序電路52、可選的BP脈衝調變電路53、可選的PCP時序電路854及可選的PCP脈衝調變電路855其中一或多者可包含在控制器850中。如同先前所述的控制器一般，控制器850可位於電漿處理腔室810之本地或遠端。In various embodiments, one or more of the SP
使用電漿電位耦合元件816耦合至電漿之功率可有利地在SP脈衝之高幅度狀態期間降低電漿之電位。在一實施例中，在SP脈衝期間提供負DC（-VPCP
）脈衝。在此例子中，-VPCP
脈衝可降低電漿60之主體電位。例如，在電漿電位耦合元件816處之負電位可將電子從電漿鞘排斥至電漿主體中。此負電荷注入可降低主體電位，其接著可降低電漿溫度（例如，Te
及Ti
）。因此，相較於僅利用施加的來源功率來產生電漿，在電漿產生間隔期間施加負DC電位至電漿可有利地允許電漿產生具有降低的電漿溫度增益。The power coupled to the plasma using the plasma
使用電漿電位耦合元件816而耦合至電漿之功率可提供額外的好處，在BP脈衝期間增加至微電子工作件表面之離子速度。在一實施例中，在BP脈衝期間提供正DC（+VPCP
）脈衝。+VPCP
脈衝可將離子排斥朝向工作件，從而增加了離子相對於工作件表面之垂直速度。因此，在BP脈衝之高幅度狀態期間將正DC電位施加至電漿可有利地增加離子之垂直性以及至工作件表面之離子能量。應當注意，雖然可在同一脈衝序列中使用-VPCP
及+VPCP
脈衝，但是在一些實施例中可省略其中一者或兩者。The power coupled to the plasma using the plasma
圖9顯示出根據本發明實施例之用於電漿處理之示例性控制方法之概要時序圖，除了包括來源功率脈衝及偏壓功率脈衝之外，亦包括電位控制功率脈衝。圖9之時序圖可為其它實施例時序圖（例如，圖1之時序圖100）之特定實行例。類似標示的元件可如以上所述。FIG. 9 shows a schematic timing diagram of an exemplary control method for plasma processing according to an embodiment of the present invention, including a potential control power pulse in addition to a source power pulse and a bias power pulse. The timing diagram of FIG. 9 may be a specific implementation of the timing diagram of other embodiments (e.g., the timing diagram 100 of FIG. 1 ). Similar labeled elements may be as described above.
參考圖9，時序圖900包括脈衝式產生的來源功率1、偏壓功率2及電位控制功率903，以產生及傳送離子至微電子工作件。時序圖900包括一額外脈衝序列，包括-VPCP
脈衝911及+VPCP
脈衝912。如同BP脈衝12，-VPCP
脈衝911及+VPCP
脈衝912相對於SP脈衝11具有利用各種偏移參數之延遲。例如，-VPCP
脈衝911包括前緣-PCP偏移916、-VPCP
脈衝寬度917及後緣-PCP偏移918，其允許控制-VPCP
脈衝911之時序及持續時間。類似地，+VPCP
脈衝912包括前緣+PCP偏移926、+VPCP
脈衝寬度927及後緣+PCP偏移928，其允許控制+VPCP
脈衝912之時序及持續時間。9, a timing diagram 900 includes a
如同先前所述的脈衝一般，-VPCP 脈衝911及+VPCP 脈衝912可根據需要而包含任何合適的脈衝寬度及偏移，以在工作件表面之電漿處理期間對所產生之電漿進行期望的控制。然而，-VPCP 脈衝911及+VPCP 脈衝912必須在時間上不重疊。亦可控制-VPCP 脈衝911及+VPCP 脈衝912兩者之脈衝高度。在一實施例中，-VPCP 脈衝911及+VPCP 脈衝912之脈衝高度之大小是實質相同的。然而，在其它實施例中，-VPCP 脈衝911及+VPCP 脈衝912之脈衝高度之大小可能是不同的。As with the pulses previously described, -V PCP pulse 911 and +V PCP pulse 912 may include any suitable pulse width and offset as needed to provide desired control of the plasma generated during plasma treatment of the workpiece surface. However, -V PCP pulse 911 and +V PCP pulse 912 must not overlap in time. The pulse height of both -V PCP pulse 911 and +V PCP pulse 912 may also be controlled. In one embodiment, the pulse heights of -V PCP pulse 911 and +V PCP pulse 912 are substantially the same. However, in other embodiments, the pulse heights of the -V PCP pulse 911 and the +V PCP pulse 912 may be different.
圖10顯示出根據本發明之實施例之示例性電漿處理系統之方塊圖，除了包括來源脈衝調變電路及脈衝調變時序電路之外，亦包括電子束來源。圖10之電漿處理系統可為其它實施例電漿處理系統（例如，圖2之電漿處理系統200）之特定實行例。圖10之電漿處理系統可用於執行本文中所述之任何實施例方法，例如圖11之方法。類似標示的元件可如以上所述。FIG. 10 shows a block diagram of an exemplary plasma processing system according to an embodiment of the present invention, including an electron beam source in addition to a source pulse modulation circuit and a pulse modulation timing circuit. The plasma processing system of FIG. 10 may be a specific implementation of other embodiment plasma processing systems (e.g., the
參考圖10，電漿處理系統1000包括使用BP時序電路52耦接至SP控制路徑1001之BP控制路徑1002，BP時序電路52提供來源功率及偏壓功率至電漿處理腔室1010。SP控制路徑1001及BP控制路徑1002可類似於圖2之SP控制路徑201及BP控制路徑202。此外，電漿處理系統1000亦包括電子束（e束）控制功率（eCP）控制路徑1004。利用電子束來源1017，eCP控制路徑1004產生電子1065並將其引入電漿處理腔室1010中之電漿60處或附近。在各種實施例中，電子束來源1017產生電子之定向流。在一實施例中，由電子束來源1017所產生之電子定向流被引導朝向電漿60，例如，在垂直於離子通量方向之方向上朝內。10 , the
eCP控制路徑1004可經由可選的eCP時序電路1056而耦接至SP控制路徑1001。可選的eCP時序電路1056可耦接至SP脈衝調變電路51及∕或BP時序電路52。 類似於BP時序電路52，可選的eCP時序電路1056可相對於由SP控制路徑1001及BP控制路徑1002所傳送之SP脈衝及∕或BP脈衝來控制時序電子束控制功率。利用由可選的eCP時序電路1056所接收之信號，eCP控制路徑1004可藉由可選的eCP脈衝調變電路1057而使電子束來源1017在開啟狀態與關閉狀態之間進行切換。The
在各種實施例中，SP脈衝調變電路51、BP時序電路52、可選的BP脈衝調變電路53、可選的eCP時序電路1056及可選的eCP脈衝調變電路1057其中一或多者可包含在控制器1050中。如同先前所述的控制器一般，控制器1050可位於電漿處理腔室1010之本地或遠端。In various embodiments, one or more of the SP
類似於以上參考圖8及圖9所述之-VPCP
脈衝911，藉由電子1065注入電漿60中之負電荷可有利地降低電漿60之主體電位及溫度。因為電子1065係直接提供至電漿處理腔室1010中之電漿60，所以相較於其它方法，eCP控制路徑1004可有利地實現對Te
及Ti
之增強控制。可在SP脈衝及∕或BP脈衝期間提供電子1065。在一實施例中，在SP脈衝期間提供電子1065。在各種實施例中，可在SP脈衝與BP脈衝之間提供電子1065。或者，可脈衝式產生電子1065，使得它們僅與SP脈衝之尾端之一小部分重疊，而不與BP脈衝重疊。Similar to the -V PCP pulse 911 described above with reference to FIGS. 8 and 9, the negative charge injected into the
圖11顯示出根據本發明實施例之用於電漿處理之示例性控制方法之概要時序圖，除了包括來源功率脈衝及偏壓功率脈衝之外，亦包括電子束功率脈衝。圖11之時序圖可為其它實施例時序圖（例如，圖1之時序圖100）之特定實行例。類似標示的元件可如以上所述。FIG. 11 shows a schematic timing diagram of an exemplary control method for plasma processing according to an embodiment of the present invention, including electron beam power pulses in addition to source power pulses and bias power pulses. The timing diagram of FIG. 11 may be a specific implementation of the timing diagrams of other embodiments (e.g., the timing diagram 100 of FIG. 1 ). Similar labeled elements may be as described above.
參考圖11，時序圖1100包括脈衝式產生的來源功率1、偏壓功率2及電子束控制功率1104，以產生及傳送離子至微電子工作件。時序圖1100包括具有eCP脈衝1111之額外脈衝序列。如同BP脈衝12，eCP脈衝1111相對於SP脈衝11具有利用各種偏移參數之延遲。例如，eCP脈衝1111包括前緣eCP偏移1116、eCP脈衝寬度1117及後緣eCP偏移1118，其允許控制eCP脈衝1111之時序及持續時間。如同先前所述的脈衝一般，eCP脈衝1111可根據需要而包含任何合適的脈衝寬度及偏移，以在工作件表面之電漿處理期間對所產生之電漿進行期望的控制。雖然時序圖1100顯示出同步eCP脈衝1111，但亦可施加反同步eCP脈衝以代替同步脈衝或與同步脈衝一起施加。Referring to FIG. 11 , a timing diagram 1100 includes a
圖12顯示出根據本發明實施例之示例性電漿處理系統之方塊圖，除了包括來源脈衝調變電路及脈衝調變時序電路之外，亦包括導電格柵。圖12之電漿處理系統可為其它實施例電漿處理系統（例如，圖2之電漿處理系統200）之特定實行例。圖12之電漿處理系統可用於執行本文中所述之任何實施例方法，例如圖13之方法。類似標示的元件可如以上所述。FIG. 12 shows a block diagram of an exemplary plasma processing system according to an embodiment of the present invention, including a source pulse modulation circuit and a pulse modulation timing circuit, and also includes a conductive grid. The plasma processing system of FIG. 12 can be a specific implementation of other embodiment plasma processing systems (e.g.,
參考圖12，電漿處理系統1200包括使用BP時序電路52耦接至SP控制路徑1201之BP控制路徑1202，BP時序電路52提供來源功率及偏壓功率至電漿處理腔室1210。SP控制路徑1201及BP控制路徑1202可類似於圖2之SP控制路徑201及BP控制路徑202。此外，電漿處理系統1200亦包括格柵控制功率（GCP）控制路徑1205。GCP控制路徑1205使用導電格柵1218而提供功率至電漿60。12, the
在一實施例中，導電格柵1218是導電板之網狀物，其主要尺寸實質上垂直於待處理之工作件表面。在一實施例中，導電格柵1218係用以增加傳送至工作件表面之離子之垂直性。在一些實施例中，導電格柵可為孔板、帶電粒子過濾器或導管。在一些實施例中，導電格柵1218係用以濾除遠端電漿之帶電粒子。In one embodiment, the
GCP控制路徑1205可經由可選的GCP時序電路1258而耦接至SP控制路徑1201。可選的GCP時序電路1258可耦接至SP脈衝調變電路51及∕或BP時序電路52。 類似於BP時序電路52，可選的GCP時序電路1258可相對於由SP控制路徑1201及BP控制路徑1202所傳送之SP脈衝及∕或BP脈衝來控制將格柵控制功率施加至電漿處理腔室1210之時序。GCP控制路徑1205可經由可選的GCP脈衝調變電路1259而提供GCP脈衝至導電格柵1218。The
在各種實施例中，SP脈衝調變電路51、BP時序電路52、可選的BP脈衝調變電路53、可選的GCP時序電路1258及可選的GCP脈衝調變電路1259其中一或多者可包含在控制器1250中。如同先前所述的控制器一般，控制器1250可位於電漿處理腔室1210之本地或遠端。In various embodiments, one or more of the SP
類似於以上參考圖8及圖9所述之-VPCP
脈衝911，在電漿60附近之負電位可有利地降低電漿60之主體電位及溫度。不同於圖8之電漿電位耦合元件816，導電格柵1218可位於電漿60與工作件表面之間。因此，與BP耦合元件19之電位相比，在BP脈衝期間施加至導電格柵1218之任何電位可保持為小，使得對於離子之主導力係朝向工作件表面。Similar to the -V PCP pulse 911 described above with reference to Figures 8 and 9, the negative potential near the
圖13顯示出根據本發明實施例之用於電漿處理之示例性控制方法之概要時序圖，除了包括來源功率脈衝及偏壓功率脈衝之外，亦包括格柵控制脈衝。圖13之時序圖可為其它實施例時序圖（例如，圖1之時序圖100）之特定實行例。類似標示的元件可如以上所述。FIG. 13 shows a schematic timing diagram of an exemplary control method for plasma processing according to an embodiment of the present invention, including a grid control pulse in addition to a source power pulse and a bias power pulse. The timing diagram of FIG. 13 may be a specific implementation of the timing diagram of other embodiments (e.g., the timing diagram 100 of FIG. 1 ). Similar labeled elements may be as described above.
參考圖13，時序圖1300包括脈衝式產生的來源功率1、偏壓功率2及格柵控制功率1305，以產生及傳送離子至微電子工作件。時序圖1300包括具有SP GCP脈衝1311及BP GCP脈衝1312之額外脈衝序列。如同BP脈衝12，SP GCP脈衝1311及BP GCP脈衝1312相對於SP脈衝11具有利用各種偏移參數之延遲。例如，SP GCP脈衝1311包括前緣SP GCP偏移1316、SP GCP脈衝寬度1317及後緣SP GCP偏移1318，其允許控制SP GCP脈衝1311之時序及持續時間。類似地，BP GCP脈衝1312包括前緣BP GCP偏移1326、BP GCP脈衝寬度1327及後緣BP GCP偏移1328，其允許控制BP GCP脈衝1312之時序及持續時間。13, timing diagram 1300 includes pulsed
SP GCP脈衝1311包括SP GCP脈衝幅度1304，而BP GCP脈衝1312包括BP GCP脈衝幅度1314。SP GCP脈衝幅度1304及BP GCP脈衝幅度1314相對於參考電位可為正或負。在一實施例中，SP GCP脈衝幅度1304及BP GCP脈衝幅度1314皆為負。或者，SP GCP脈衝幅度1304為負，且BP GCP脈衝幅度1314為正。
SP GCP脈衝幅度1304之大小比BP GCP脈衝幅度1314大可能是有利的。例如，在SP脈衝期間，SP GCP脈衝可用於降低電漿之主體電位。因此，可使SP GCP脈衝幅度1304足夠大，以影響電漿之主體。相反地，在BP脈衝期間，可使用BP GCP脈衝，以對於通過導電格柵之離子相對於工作件表面在垂直方向之速度進行小調整。因此，可使BP GCP脈衝幅度1314足夠小，從而不會使離子反射回電漿。在一實施例中，SP GCP脈衝幅度1304之大小比BP GCP脈衝幅度1314大，且符號相反。It may be advantageous to have the SP
如同先前所述的脈衝一般，SP GCP脈衝1311及BP GCP脈衝1312可根據需要而包含任何合適的脈衝寬度及偏移，以在工作件表面之電漿處理期間對所產生之電漿進行期望的控制。As with the pulses previously described, the
圖14顯示出根據本發明實施例之產生控制法則之示例性方法之流程圖，控制法則可用於在電漿處理期間之離子角度分佈函數之主動控制。圖14之方法可用於判定適當的延遲及∕或偏移，以用於本文中所述之實施例方法（例如圖1之方法），以便在電漿處理期間獲得期望的角擴展。由於難以量測離子角度分佈函數（IADF），因此在線控制可能是不合適的解決方案。替代地，可實施基於模型的IADF控制做為解決方案，以實現IADF之主動控制。FIG. 14 shows a flow chart of an exemplary method for generating a control law according to an embodiment of the present invention, which can be used for active control of the ion angle distribution function during plasma processing. The method of FIG. 14 can be used to determine appropriate delays and/or offsets for use in the embodiment methods described herein (e.g., the method of FIG. 1) to obtain a desired angular spread during plasma processing. Since the ion angle distribution function (IADF) is difficult to measure, online control may not be a suitable solution. Alternatively, model-based IADF control can be implemented as a solution to achieve active control of the IADF.
參考圖14，用於產生控制法則之流程圖1400包括步驟1401，步驟1401包括，確定脈衝調變處理參數之輸入陣列。例如，輸入陣列可包括各種延遲、功率、脈衝寬度、工作週期等。輸入參數陣列可使用在步驟1402中，在步驟1402期間可進行實驗以確定給定電漿處理系統之輸入參數陣列之觀察（經驗）結果。在步驟1403中，可量測各種電漿參數。例如，電漿參數可包括在電漿處理腔室中一或更多位置處之電漿物種之最大、最小及平均能量、離子能量分佈函數（IEDF）、離子角度分佈函數（IADF）、離子角度分佈之半高寬（δθfwhm
）、顯影後臨界尺寸（DCD）、蝕刻後臨界尺寸（ECD）及其它。可藉由導入測試晶圓來進行量測，以最佳地近似實際處理條件。14, a
在步驟1404中，輸入參數陣列亦可用於電漿模型中。例如，電漿模型可為特定用於電漿處理系統之一維（1D）模型，以便根據一組輸入參數而預測電漿參數。在某些例子中，電漿模型亦可為多維模型。電漿模型可為統計的及∕或可包括在電漿腔室中之電漿之基於物理學的模型。在步驟1405中，可使用電漿模型以計算與所測得的電漿參數相對應之一組模擬電漿參數。In
在步驟1406中，可將計算出的電漿參數及測得的電漿參數進行比較，以確定電漿模型之準確性。例如，如果某些預選參數在預定範圍內，則可確定計算出的參數與測得的參數之間之一致性。預定範圍及預選參數之本體可取決於電漿處理之特定設計細節。在步驟1406中，如果確定計算出的參數與測得的參數不一致，則可在步驟1407中修改電漿模型。模型修改可包括比例常數之調整、邊界條件之改變、回歸分析以及用較複雜模型來取代簡單模型。在已經修改電漿模型之後，方法返回到步驟1404。In
如果發現所測得的與計算出的電漿參數一致，則在步驟1408中可產生控制法則。控制法則可定義在離子角度分佈δθfwhm
之變化（表示為Δδθfwhm
）為一或更多延遲參數之變化f(Δtdelay
)之函數之關係。具體而言，對於一或更多延遲參數之給定變化，控制法則可有利地允許準確地預測離子分佈之角擴展之變化。If the measured and calculated plasma parameters are found to be consistent, a control law may be generated in
圖15顯示出根據本發明實施例之電漿處理之前饋控制之示例性方法之流程圖。例如，圖15之方法可藉由電漿處理系統來執行，以藉由實施控制法則而以前饋的方式來控制電漿處理，而控制法則可，例如，藉由圖14之方法來確定。前饋控制方法可，例如，基於與期望值之預期的及∕或測得的差異（例如臨界尺寸（CD）、角度分佈等之差異）來確定新的脈衝延遲，以容許電漿處理系統之控制。FIG15 shows a flow chart of an exemplary method for feedforward control of a plasma process according to an embodiment of the present invention. For example, the method of FIG15 may be performed by a plasma process system to control the plasma process in a feedforward manner by implementing a control law, which may be determined, for example, by the method of FIG14. The feedforward control method may, for example, determine a new pulse delay based on an expected and/or measured difference from a desired value (e.g., a difference in critical dimension (CD), angular distribution, etc.) to allow control of the plasma process system.
參考圖15，前饋控制方法之流程圖1500包括量測臨界尺寸之差異ΔCD之步驟1501。例如，CD可為特定電漿處理之DCD之ECD。在一些實施例中，步驟1501可量測多個ΔCD，或者可省略步驟1501。步驟1502包括量測角度分佈之差異Δδθfwhm
。類似於步驟1501，在一些實施例中，可在步驟1502中量測多個物種之角度分佈之差異。或者，可省略步驟1502。15 , a
在步驟1503中，可使用控制法則來實施校正模型。在一實施例中，校正模型為線性校正模型。例如，可使用合適的方法（例如圖14之方法）來預先確定控制法則。基於線性校正模型之結果，可確定一或更多新的延遲參數tdelay
。In
圖16顯示出根據本發明實施例之在電漿處理期間進行控制之示例性方法。應當注意，雖然圖14及圖15之流程圖用於說明事件之特定順序，但是如圖16所示之方法並非用於將方法步驟限制於特定順序。因此，以下的方法步驟可以任何合適的順序加以執行，此對於本領域技術人員來說是顯而易見的。FIG. 16 shows an exemplary method for controlling during plasma processing according to an embodiment of the present invention. It should be noted that although the flowcharts of FIG. 14 and FIG. 15 are used to illustrate a specific sequence of events, the method shown in FIG. 16 is not intended to limit the method steps to a specific sequence. Therefore, the following method steps can be performed in any suitable order, which will be apparent to those skilled in the art.
在電漿處理期間進行控制之方法1600之步驟1601包括，產生SP脈衝之第一序列。步驟1602包括產生BP脈衝之第二序列。可根據本文中所述之任何實施例方法（例如圖1之方法），利用各種脈衝調變參數來產生SP脈衝及BP脈衝。此外，可使用本文中所述之任何實施例系統（例如圖2之系統）來形成SP脈衝及BP脈衝。在一實施例中，使用脈衝調變電路來產生SP脈衝。脈衝調變電路可包含在控制器中。
在電漿處理期間進行控制之方法1600之步驟1603包括，使第二序列之BP脈衝相對於第一序列之SP脈衝具有延遲，以形成交替的SP脈衝及BP脈衝之組合序列。例如，在每一SP脈衝之後可為BP脈衝，而在每一BP脈衝之後為SP脈衝。在一實施例中，使用時序電路來使BP脈衝延遲。時序電路可包括在控制器中。
步驟1604包括使用組合序列來產生包含離子之電漿，且步驟1605包括使用組合序列來傳送離子至工作件表面。組合序列可用於在電漿處理腔室中產生電漿。電漿可包括離子，且組合序列可進一步用於傳送離子至工作件表面。
圖17顯示出根據本發明實施例之電漿處理之示例性方法。應當注意，雖然圖14及圖15之流程圖用於說明事件之特定順序，但是如圖17所示之方法並非用於將方法步驟限制於特定順序。因此，以下的方法步驟可以任何合適的順序加以執行，此對於本領域技術人員來說是顯而易見的。FIG. 17 shows an exemplary method of plasma treatment according to an embodiment of the present invention. It should be noted that although the flow charts of FIG. 14 and FIG. 15 are used to illustrate a specific sequence of events, the method shown in FIG. 17 is not intended to limit the method steps to a specific sequence. Therefore, the following method steps can be performed in any suitable order, which is obvious to those skilled in the art.
電漿處理方法1700之步驟1701包括，提供來源功率至電漿處理腔室以產生電漿。來源功率包括複數SP脈衝。可根據本文中所述之任何實施例方法（例如圖1之方法），利用各種脈衝調變參數來產生SP脈衝。此外，可使用本文中所述之任何實施例系統（例如圖2之系統）來形成SP脈衝。
電漿處理方法1700之步驟1702包括，提供偏壓功率至電漿處理腔室。偏壓功率包括在時間上至少部分不重疊之複數BP脈衝。在各種實施例中，SP脈衝及BP脈衝在時間上完全不重疊。可根據本文中所述之任何實施例方法（例如圖1之方法），利用各種脈衝調變參數來產生BP脈衝。此外，可使用本文中所述之任何實施例系統（例如圖2之系統）來形成BP脈衝。
藉由控制來源脈衝與偏壓脈衝之間之時序，本文中所述之實施例可有利地控制離子在微電子工作件表面處之入射角。例如，給定離子抵達微電子工作件表面處之入射角是由偏壓功率所賦予離子之實質垂直速度與由於離子溫度所引起之隨機速度之組合。在電漿產生期間，離子之溫度隨著來源功率而升高，如果來源功率關閉，則離子之溫度降低。在施加來源功率及偏壓功率至電漿處理腔室時，該等實施例亦可有利地達成靈活性，俾使實質垂直的速度增加而隨機速度減小。By controlling the timing between the source pulse and the bias pulse, the embodiments described herein can advantageously control the angle of incidence of the ions at the surface of the microelectronic workpiece. For example, the angle of incidence of a given ion arriving at the surface of the microelectronic workpiece is a combination of the substantial vertical velocity imparted to the ion by the bias power and the random velocity due to the ion temperature. During plasma generation, the temperature of the ions increases with the source power, and if the source power is turned off, the temperature of the ions decreases. The embodiments can also advantageously achieve flexibility in applying source power and bias power to the plasma processing chamber so that the substantial vertical velocity is increased and the random velocity is decreased.
本文中所述之實施例亦可提供將電漿產生限制在特定時段之優點。例如，施加高頻至電漿餘輝階段可導致電子及離子加熱以及電漿產生。此外，實施例可有利地在來源功率關閉時允許偏壓功率脈衝，使得離子在餘輝階段中被加速而沒有額外的電漿產生或加熱。除了控制離子之角度分佈之外，此可有利地導致對離子能量之增強控制。Embodiments described herein may also provide the advantage of limiting plasma generation to a specific time period. For example, applying a high frequency to the plasma afterglow phase may result in heating of electrons and ions as well as plasma generation. Furthermore, embodiments may advantageously allow bias power pulses when the source power is off so that ions are accelerated in the afterglow phase without additional plasma generation or heating. This may advantageously result in enhanced control of ion energy in addition to controlling the angular distribution of the ions.
例如，所述實施例之另一優點可為偏壓功率之靈活應用，偏壓功率包括低頻RF功率（例如，> 400 kHz）、DC功率脈衝或交替極性DC電壓脈衝。由於來源功率關閉，較低頻率之偏壓功率脈衝及∕或DC偏壓功率脈衝可能具有較高的效率。交替極性DC脈衝可有利地防止電荷累積在處理中的基板上。例如，如果微電子工作件之基板包括介電層，則交替極性DC偏壓功率脈衝可減少或消除基板之非期望的電荷累積。For example, another advantage of the embodiments described may be the flexible application of bias power, including low frequency RF power (e.g., > 400 kHz), DC power pulses, or alternating polarity DC voltage pulses. Lower frequency bias power pulses and/or DC bias power pulses may have higher efficiency due to the source power being turned off. Alternating polarity DC pulses may advantageously prevent charge accumulation on the substrate being processed. For example, if the substrate of the microelectronic workpiece includes a dielectric layer, the alternating polarity DC bias power pulses may reduce or eliminate undesirable charge accumulation of the substrate.
所述實施例之另一可能優點為，維持朝向微電子工作件之固定粒子通量。例如，可選擇來源功率脈衝關閉時間，使得離子及其它期望的粒子（例如自由基）以一致的速率抵達微電子工作件之表面。在選擇來源功率關閉時間時，可考慮幾個參數，包括特定物種之擴散係數及黏滯係數以及電漿處理腔室之關鍵尺寸等等。Another possible advantage of the described embodiments is maintaining a constant particle flux toward a microelectronic workpiece. For example, the source power pulse off time can be selected so that ions and other desired particles (e.g., free radicals) arrive at the surface of the microelectronic workpiece at a consistent rate. In selecting the source power off time, several parameters can be considered, including the diffusion coefficient and viscosity coefficient of the specific species and the critical dimensions of the plasma processing chamber, etc.
本發明之示例性實施例係總結於此。根據本文中所提出之說明書整體以及申請專利範圍，亦可理解其它實施例。Exemplary embodiments of the present invention are summarized here. Other embodiments can also be understood based on the overall description and application scope proposed in this article.
示例1。一種電漿處理之方法，該方法包括：產生來源功率（SP）脈衝之第一序列；產生偏壓功率（BP）脈衝之第二序列；將BP脈衝之第二序列與SP脈衝之第一序列加以組合，以形成交替的SP脈衝及BP脈衝之組合序列；及使用該組合序列，產生包含離子之電漿，並藉由傳送離子至基板之主表面來處理基板。Example 1. A method of plasma processing, the method comprising: generating a first sequence of source power (SP) pulses; generating a second sequence of bias power (BP) pulses; combining the second sequence of BP pulses with the first sequence of SP pulses to form a combined sequence of alternating SP pulses and BP pulses; and using the combined sequence to generate a plasma containing ions and process a substrate by delivering the ions to a major surface of the substrate.
範例2。如範例1之方法，更包括：調整在SP脈衝之後緣與BP脈衝之前緣之間之偏移持續時間。Example 2. The method of Example 1 further includes: adjusting the offset duration between the trailing edge of the SP pulse and the leading edge of the BP pulse.
範例3。如範例1及2其中一者之方法，更包括：調整第二序列之BP脈衝之脈衝寬度持續時間。Example 3. The method of one of Examples 1 and 2 further comprises: adjusting the pulse width duration of the second sequence of BP pulses.
範例4。如範例1至3其中一者之方法，更包括：調整在第一序列之SP脈衝之間之關閉時間持續時間。Example 4. The method of any one of Examples 1 to 3 further comprises: adjusting the duration of the off time between the SP pulses of the first sequence.
範例5。如範例1至4其中一者之方法，更包括：產生電位控制功率（PCP）脈衝之第三序列，其中第三序列之PCP脈衝在時間上與組合序列之交替的SP脈衝及BP脈衝重疊。Example 5. The method of any one of Examples 1 to 4 further comprises: generating a third sequence of potential controlled power (PCP) pulses, wherein the PCP pulses of the third sequence overlap in time with the alternating SP pulses and BP pulses of the combined sequence.
範例6。如範例5之方法，其中PCP脈衝包括負直流（DC）脈衝，及其中在SP脈衝期間提供負DC脈衝至電漿。Example 6. The method of Example 5, wherein the PCP pulse comprises a negative direct current (DC) pulse, and wherein the negative DC pulse is provided to the plasma during the SP pulse.
範例7。如範例5之方法，其中PCP脈衝包括正直流（DC）脈衝，及其中在BP脈衝期間提供正DC脈衝至電漿。Example 7. The method of Example 5, wherein the PCP pulse comprises a positive direct current (DC) pulse, and wherein the positive DC pulse is provided to the plasma during the BP pulse.
範例8。如範例1至7其中一者之方法，更包括：在組合序列之交替SP脈衝及BP脈衝期間在電漿處提供電子流。Example 8. The method of any one of Examples 1 to 7, further comprising: providing an electron current at the plasma during the combined sequence of alternating SP pulses and BP pulses.
範例9。一種電漿處理方法，包括：提供來源功率（SP）至電漿處理腔室以產生電漿，所述SP包括複數SP脈衝；及提供包括複數BP脈衝之偏壓功率（BP）至電漿處理腔室，其中複數SP脈衝及複數BP脈衝被結合以形成脈衝序列，其中脈衝序列之每一脈衝包括複數SP脈衝其中之一SP脈衝及複數BP脈衝其中之一BP脈衝、及時間間隔，在時間間隔中SP脈衝之一部分或BP脈衝之一部分處於高幅度狀態。Example 9. A plasma processing method, comprising: providing a source power (SP) to a plasma processing chamber to generate plasma, the SP comprising a plurality of SP pulses; and providing a bias power (BP) comprising a plurality of BP pulses to the plasma processing chamber, wherein the plurality of SP pulses and the plurality of BP pulses are combined to form a pulse sequence, wherein each pulse of the pulse sequence comprises one SP pulse of the plurality of SP pulses and one BP pulse of the plurality of BP pulses, and a time interval, during which a portion of the SP pulse or a portion of the BP pulse is in a high amplitude state.
範例10。如範例9之方法，其中SP包括第一頻率之交流（AC）功率； BP包括第二頻率之AC功率；第二頻率小於第一頻率。Example 10. The method of Example 9, wherein SP comprises alternating current (AC) power of a first frequency; BP comprises AC power of a second frequency; and the second frequency is less than the first frequency.
範例11。如範例10之方法，其中第一頻率大於約10 MHz，第二頻率小於約5 MHz。Example 11. The method of Example 10, wherein the first frequency is greater than about 10 MHz and the second frequency is less than about 5 MHz.
範例12。如範例10之方法，其中第二頻率小於約400 kHz。Example 12. The method of Example 10, wherein the second frequency is less than about 400 kHz.
範例13。如範例9之方法，其中SP包括交流（AC）功率；BP包含直流（DC）功率。Example 13. The method of Example 9, wherein SP comprises alternating current (AC) power; and BP comprises direct current (DC) power.
範例14。如範例13之方法，其中提供SP及BP至電漿處理腔室包括：使複數SP脈衝中之SP脈衝與複數BP脈衝中之BP脈衝交替；及其中複數BP脈衝其中每一者包括單一DC脈衝。Example 14. The method of Example 13, wherein providing SP and BP to the plasma processing chamber comprises: alternating SP pulses in the plurality of SP pulses with BP pulses in the plurality of BP pulses; and wherein each of the plurality of BP pulses comprises a single DC pulse.
範例15。如範例13之方法，其中複數BP脈衝其中每一者包括交替極性DC脈衝。Example 15. The method of Example 13, wherein each of the plurality of BP pulses comprises alternating polarity DC pulses.
範例16。如範例9至15其中一者之方法，其中脈衝序列為週期序列，其中提供SP及BP至電漿處理腔室包括：傳送包括複數SP脈衝及複數BP脈衝之週期序列至電漿處理腔室；週期序列之每一週期恰好包括複數SP脈衝其中之一SP脈衝；及複數SP脈衝其中每一者之工作週期大約為50%。Example 16. The method of any one of Examples 9 to 15, wherein the pulse sequence is a cycle sequence, wherein providing SP and BP to the plasma processing chamber comprises: transmitting a cycle sequence including a plurality of SP pulses and a plurality of BP pulses to the plasma processing chamber; each cycle of the cycle sequence includes exactly one SP pulse of the plurality of SP pulses; and a duty cycle of each of the plurality of SP pulses is approximately 50%.
範例17。如範例16之方法，其中週期序列之每一循環恰好包括複數BP脈衝其中之一BP脈衝；及提供SP及BP至電漿處理腔室包括：使複數BP脈衝其中每一者具有延遲，以使得複數BP脈衝其中每一者之工作週期小於50%。Example 17. The method of Example 16, wherein each cycle of the cycle sequence includes exactly one BP pulse of the plurality of BP pulses; and providing SP and BP to the plasma processing chamber includes: providing each of the plurality of BP pulses with a delay so that a duty cycle of each of the plurality of BP pulses is less than 50%.
範例18。一種電漿處理系統，包括控制器，控制器用以產生來源功率（SP）脈衝之第一序列及偏壓功率（BP）脈衝之第二序列，並將第二序列之BP脈衝與第一序列之SP脈衝加以組合，以形成交替的SP脈衝及BP脈衝之組合序列；及電漿處理腔室，耦接至控制器並用以產生電漿，電漿包括使用組合序列所產生之離子，電漿處理腔室用以支撐用於接收所產生的離子之基板。Example 18. A plasma processing system includes a controller for generating a first sequence of source power (SP) pulses and a second sequence of bias power (BP) pulses, and combining the second sequence of BP pulses with the first sequence of SP pulses to form a combined sequence of alternating SP pulses and BP pulses; and a plasma processing chamber coupled to the controller and for generating plasma, the plasma including ions generated using the combined sequence, the plasma processing chamber for supporting a substrate for receiving the generated ions.
範例19。如範例18之系統，其中控制器更用以調整在SP脈衝之後緣與BP脈衝之前緣之間之偏移持續時間、調整第二序列之BP脈衝之脈衝寬度持續時間、或調整在第一序列之SP脈衝之間之關閉時間持續時間。Example 19. The system of Example 18, wherein the controller is further configured to adjust an offset duration between a trailing edge of an SP pulse and a leading edge of a BP pulse, adjust a pulse width duration of a second sequence of BP pulses, or adjust an off-time duration between SP pulses of a first sequence.
範例20。如範例18及19其中一者之系統，其中控制器更用以產生電位控制功率（PCP）脈衝之第三序列，其中第三序列之PCP脈衝在時間上與組合序列之交替的SP脈衝及BP脈衝重疊。Example 20. The system of any one of Examples 18 and 19, wherein the controller is further configured to generate a third sequence of potential controlled power (PCP) pulses, wherein the PCP pulses of the third sequence overlap in time with the alternating SP pulses and BP pulses of the combined sequence.
本文中所述之功率控制技術可由控制器進行控制。亦應注意，可使用被程式化以提供本文中所述之功能之一或更多可程式化積體電路來實現控制器。例如，一或更多處理器（例如微處理器、微控制器、中央處理單元等）、可程式化邏輯裝置（例如複雜可程式化邏輯裝置（CPLD）、場可程式閘陣列（FPGA）等）、及∕或其它可程式化積體電路可利用軟體或其它程式化指令而加以程式化，以實現本文中所述之任何功能。更應注意，軟體或其它程式化指令可儲存在一或更多非暫態電腦可讀媒體（例如記憶體儲存裝置、FLASH記憶體、DRAM記憶體、可再程式化儲存裝置、硬碟、軟碟、DVD、CD-ROM等）中，且當由可程式化積體電路執行時，軟體或其它程式化指令使得可程式化積體電路執行本文中所述之處理、功能、及∕或性能。亦可實現其它的變化。The power control techniques described herein may be controlled by a controller. It should also be noted that the controller may be implemented using one or more programmable integrated circuits that are programmed to provide the functions described herein. For example, one or more processors (e.g., microprocessors, microcontrollers, central processing units, etc.), programmable logic devices (e.g., complex programmable logic devices (CPLDs), field programmable gate arrays (FPGAs), etc.), and/or other programmable integrated circuits may be programmed using software or other programming instructions to implement any of the functions described herein. It should be further noted that the software or other programmable instructions may be stored in one or more non-transitory computer-readable media (e.g., memory storage devices, FLASH memory, DRAM memory, reprogrammable storage devices, hard disks, floppy disks, DVDs, CD-ROMs, etc.), and when executed by a programmable integrated circuit, the software or other programmable instructions cause the programmable integrated circuit to perform the processing, functions, and/or performance described herein. Other variations may also be implemented.
可使用一或更多沉積處理以形成本文中所述之材料層。例如，可使用化學氣相沉積（CVD）、電漿增強CVD（PECVD）、物理氣相沉積（PVD），原子層沉積（ALD）及∕或其它沉積處理，以進行一或更多沉積。對於電漿沉積處理，可在各種壓力、功率、流量及溫度條件下，使用前驅物氣體混合物，包括但不限於碳氫化合物、氟碳化物、或含氮碳氫化合物加上一或更多稀釋氣體（例如，氬、氮等）。可使用光微影、極紫外（EUV）微影及∕或其它微影處理來進行關於光阻（PR）層之微影處理。可使用電漿蝕刻處理、放電蝕刻處理及∕或其它期望的蝕刻處理，以進行蝕刻處理。例如，可使用包含氟碳化物、氧、氮、氫，氬及∕或其它氣體之電漿，以實施電漿蝕刻處理。此外，可控制處理步驟之操作變數，以確保在通孔形成期間達成通孔之CD目標參數。操作變數可包括，例如，腔室溫度、腔室壓力、氣體流速、在產生電漿時施加至電極組件之頻率及∕或功率、及∕或處理步驟之其它操作變數。亦可實施以上之變型，但仍然利用本文中所述之技術。One or more deposition processes may be used to form the material layers described herein. For example, chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and/or other deposition processes may be used to perform one or more depositions. For plasma deposition processes, precursor gas mixtures may be used under various pressure, power, flow, and temperature conditions, including but not limited to hydrocarbons, fluorocarbons, or nitrogen-containing hydrocarbons plus one or more diluent gases (e.g., argon, nitrogen, etc.). Photolithography, extreme ultraviolet (EUV) lithography, and/or other lithography processes may be used to perform lithography processes for photoresist (PR) layers. The etching process may be performed using a plasma etching process, a discharge etching process, and/or other desired etching processes. For example, a plasma comprising a fluorocarbon, oxygen, nitrogen, hydrogen, argon, and/or other gases may be used to perform the plasma etching process. In addition, the operating variables of the process step may be controlled to ensure that the CD target parameters of the through hole are achieved during the through hole formation. The operating variables may include, for example, chamber temperature, chamber pressure, gas flow rate, frequency and/or power applied to the electrode assembly when generating the plasma, and/or other operating variables of the process step. Variations of the above may also be implemented, but still utilize the techniques described herein.
儘管已經參考說明實施例而描述了本發明，但是該描述不意圖以限制性之意義來解釋。在參考描述之後，說明實施例及本發明之其它實施例之各種修改及組合對於本領域技術人員將是顯而易見的。例如，圖8、10及12之實施例可在進一步的實施例中加以組合。類似地，關於圖2所述之實施例，例如圖2-7，可與圖9、11或13組合。因此，所附申請專利範圍旨在涵蓋任何這樣的修改或實施例。Although the present invention has been described with reference to the illustrative embodiments, the description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments and other embodiments of the present invention will be apparent to those skilled in the art after reference to the description. For example, the embodiments of Figures 8, 10, and 12 may be combined in further embodiments. Similarly, the embodiments described with respect to Figure 2, such as Figures 2-7, may be combined with Figures 9, 11, or 13. Therefore, the appended claims are intended to cover any such modifications or embodiments.
1:來源功率 2:偏壓功率 3:來源功率（SP）脈衝寬度 4:偏壓功率（BP）脈衝幅度 5:脈衝調變週期 6:前緣偏壓偏移 7:BP脈衝寬度 8:BP脈衝幅度 9:後緣偏壓偏移 11:來源功率（SP）脈衝 12:偏壓功率（BP）脈衝 13:SP低幅度狀態 14:SP高幅度狀態 15:SP耦合元件 17:BP低幅度狀態 18:BP高幅度狀態 19:BP耦合元件 20:SP函數產生器 21:尖峰 23:偽平衡狀態 25:SP阻抗匹配網路 30:BP函數產生器 31:溫度曲線 32:密度曲線 35:BP阻抗匹配網路 51:SP脈衝調變電路 53:BP脈衝調變電路 60:電漿 100:時序圖 102:曲線圖 200:電漿處理系統 201:SP控制路徑 202:BP控制路徑 210:電漿處理腔室 250:控制器 252:脈衝調變時序電路 300:時序圖 303:SP脈衝寬度 305:脈衝調變週期 307:BP脈衝寬度 311:SP脈衝 312:BP脈衝 320:時序圖 322:BP脈衝 326:前緣偏壓偏移 327:BP脈衝寬度 400:時序圖 500:時序圖 517:方波脈衝寬度 600:時序圖 612:DC脈衝 617:DC脈衝寬度 700:時序圖 712:交替極性DC脈衝 800:電漿處理系統 801:SP控制路徑 802:BP控制路徑 803:電位控制功率（PCP）控制路徑 810:電漿處理腔室 816:電漿電位耦合元件 850:控制器 854:PCP時序電路 855:PCP脈衝調變電路 900:時序圖 903:電位控制功率 911:-VPCP脈衝 912:+VPCP脈衝 916:前緣-PCP偏移 917:-VPCP脈衝寬度 918:後緣-PCP偏移 926:前緣+PCP偏移 927:+VPCP脈衝寬度 928:後緣+PCP偏移 1000:電漿處理系統 1001:SP控制路徑 1002:BP控制路徑 1004:電子束控制功率（eCP）控制路徑 1010:電漿處理腔室 1017:電子束來源 1050:控制器 1056:eCP時序電路 1057:eCP脈衝調變電路 1065:電子 1100:時序圖 1104:電子束控制功率 1111:eCP脈衝 1116:前緣eCP偏移 1117:eCP脈衝寬度 1118:後緣eCP偏移 1200:電漿處理系統 1201:SP控制路徑 1202:BP控制路徑 1205:格柵控制功率（GCP）控制路徑 1210:電漿處理腔室 1218:導電格柵 1250:控制器 1258:GCP時序電路 1259:GCP脈衝調變電路 1300:時序圖 1304:SP GCP脈衝幅度 1305:格柵控制功率 1311:SP GCP脈衝 1312:BP GCP脈衝 1314:BP GCP脈衝幅度 1316:前緣SP GCP偏移 1317:SP GCP脈衝寬度 1318:後緣SP GCP偏移 1326:前緣SP GCP偏移 1327:SP GCP脈衝寬度 1328:後緣SP GCP偏移 1400:流程圖 1401~1408:步驟 1500:流程圖 1501~1504:步驟 1600:方法 1601~1605:步驟 1700:方法 1701~1702:步驟1: Source power 2: Bias power 3: Source power (SP) pulse width 4: Bias power (BP) pulse amplitude 5: Pulse modulation period 6: Leading edge bias offset 7: BP pulse width 8: BP pulse amplitude 9: Trailing edge bias offset 11: Source power (SP) pulse 12: Bias power (BP) pulse 13: SP low amplitude state 14: SP high amplitude state 15: SP coupling element 17: BP low amplitude state 18: BP high amplitude state 19: BP coupling element 20: SP function generator 21: spike 23: pseudo-balance state 25: SP impedance matching network 30: BP function generator 31: temperature curve 32: density curve 35: BP impedance matching network 51: SP pulse modulation circuit 53: BP pulse Pulse modulation circuit 60: Plasma 100: Timing diagram 102: Curve diagram 200: Plasma processing system 201: SP control path 202: BP control path 210: Plasma processing chamber 250: Controller 252: Pulse modulation timing circuit 300: Timing diagram 303: SP pulse width 305: Pulse modulation cycle 307: BP pulse width 311: SP pulse 312:BP pulse 320:Timing diagram 322:BP pulse 326:Leading edge bias offset 327:BP pulse width 400:Timing diagram 500:Timing diagram 517:Square wave pulse width 600:Timing diagram 612:DC pulse 617:DC pulse width 700:Timing diagram 712:Alternating polarity DC pulse 800:Plasma processing system 801: SP control path 802: BP control path 803: Potential Control Power (PCP) control path 810: Plasma processing chamber 816: Plasma potential coupling element 850: Controller 854: PCP timing circuit 855: PCP pulse modulation circuit 900: Timing diagram 903: Potential Control Power 911: -VPCP pulse 912: +V PCP pulse 916: Leading edge - PCP offset 917: -VPCP pulse width 918: Trailing edge - PCP offset 926: Leading edge + PCP offset 927: +VPCP pulse width 928: Trailing edge + PCP offset 1000: Plasma processing system 1001: SP control path 1002: BP control path 1004: Electron beam control power (eCP) Control path 1010: Plasma processing chamber 1017: Electron beam source 1050: Controller 1056: eCP timing circuit 1057: eCP pulse modulation circuit 1065: Electron 1100: Timing diagram 1104: Electron beam control power 1111: eCP pulse 1116: Leading edge eCP offset 1117: eCP pulse width 1118: Back eCP offset 1200: Plasma processing system 1201: SP control path 1202: BP control path 1205: Grid control power (GCP) control path 1210: Plasma processing chamber 1218: Conductive grid 1250: Controller 1258: GCP timing circuit 1259: GCP pulse modulation circuit 1300: Timing diagram 1304: SP GCP pulse amplitude 1305: Grid control power 1311: SP GCP pulse 1312: BP GCP pulse 1314: BP GCP pulse amplitude 1316: Leading edge SP GCP offset 1317: SP GCP pulse width 1318: Trailing edge SP GCP offset 1326: Leading edge SP GCP offset 1327: SP GCP pulse width 1328: Trailing edge SP GCP offset 1400: Flowchart 1401~1408: Steps 1500: Flowchart 1501~1504: Steps 1600: Method 1601~1605: Steps 1700: Method 1701~1702: Steps
為了更完整地理解本發明及其優點，現在參考伴隨著圖式之以下描述，其中：For a more complete understanding of the present invention and its advantages, reference is now made to the following description accompanied by the accompanying drawings, in which:
圖1顯示出根據本發明實施例之電漿處理之示例性控制方法之脈衝序列之概要時序圖及相對應的定性圖，電漿處理之示例性控制方法包括來源功率脈衝及偏壓功率脈衝；FIG. 1 shows a schematic timing diagram and a corresponding qualitative diagram of a pulse sequence of an exemplary control method for plasma processing according to an embodiment of the present invention, wherein the exemplary control method for plasma processing includes a source power pulse and a bias power pulse;
圖2顯示出根據本發明實施例之示例性電漿處理系統之方塊圖，示例性電漿處理系統包括來源脈衝調變電路及脈衝調變時序電路；FIG. 2 shows a block diagram of an exemplary plasma processing system according to an embodiment of the present invention, the exemplary plasma processing system including a source pulse modulation circuit and a pulse modulation timing circuit;
圖3顯示出根據本發明實施例之電漿處理之示例性控制方法之概要時序圖，電漿處理之示例性控制方法包括反同步偏壓功率脈衝；FIG. 3 shows a schematic timing diagram of an exemplary control method for plasma processing according to an embodiment of the present invention, the exemplary control method for plasma processing including anti-synchronous bias power pulses;
圖4顯示出根據本發明實施例之電漿處理之示例性控制方法之概要時序圖，電漿處理之示例性控制方法包括高頻射頻（RF）來源功率脈衝及低頻RF偏壓功率脈衝。FIG. 4 shows a schematic timing diagram of an exemplary control method for plasma processing according to an embodiment of the present invention, the exemplary control method for plasma processing including a high frequency radio frequency (RF) source power pulse and a low frequency RF bias power pulse.
圖5顯示出根據本發明實施例之電漿處理之示例性控制方法之概要時序圖，電漿處理之示例性控制方法包括高頻RF來源功率脈衝及低頻方波偏壓功率脈衝。FIG. 5 shows a schematic timing diagram of an exemplary control method for plasma processing according to an embodiment of the present invention, wherein the exemplary control method for plasma processing includes a high frequency RF source power pulse and a low frequency square wave bias power pulse.
圖6顯示出根據本發明實施例之電漿處理之示例性控制方法之概要時序圖，電漿處理之示例性控制方法包括高頻RF來源功率脈衝及脈衝式DC偏壓功率脈衝。FIG. 6 shows a schematic timing diagram of an exemplary control method for plasma processing according to an embodiment of the present invention, wherein the exemplary control method for plasma processing includes a high frequency RF source power pulse and a pulsed DC bias power pulse.
圖7顯示出根據本發明實施例之電漿處理之示例性控制方法之概要時序圖，電漿處理之示例性控制方法包括高頻RF來源功率脈衝及交替極性（alternating polarity）脈衝式DC偏壓功率脈衝。FIG. 7 shows a schematic timing diagram of an exemplary control method for plasma processing according to an embodiment of the present invention, the exemplary control method for plasma processing including a high frequency RF source power pulse and an alternating polarity pulsed DC bias power pulse.
圖8顯示出根據本發明實施例之示例性電漿處理系統之方塊圖，示例性電漿處理系統除了來源脈衝調變電路及脈衝調變時序電路之外，亦包括電漿電位耦合元件。FIG. 8 shows a block diagram of an exemplary plasma processing system according to an embodiment of the present invention. The exemplary plasma processing system includes a plasma potential coupling element in addition to a source pulse modulation circuit and a pulse modulation timing circuit.
圖9顯示出根據本發明實施例之電漿處理之示例性控制方法之概要時序圖，電漿處理之示例性控制方法除了來源功率脈衝及偏壓功率脈衝之外，亦包括電位控制功率脈衝。FIG. 9 shows a schematic timing diagram of an exemplary control method for plasma processing according to an embodiment of the present invention, wherein the exemplary control method for plasma processing includes a potential control power pulse in addition to a source power pulse and a bias power pulse.
圖10顯示出根據本發明實施例之示例性電漿處理系統之方塊圖，示例性電漿處理系統除了包括來源脈衝調變電路及脈衝調變時序電路之外，亦包括電子束來源。FIG. 10 shows a block diagram of an exemplary plasma processing system according to an embodiment of the present invention. The exemplary plasma processing system includes an electron beam source in addition to a source pulse modulation circuit and a pulse modulation timing circuit.
圖11顯示出根據本發明實施例之電漿處理之示例性控制方法之概要時序圖，電漿處理之示例性控制方法除了來源功率脈衝及偏壓功率脈衝之外，亦包括電子束功率脈衝。FIG. 11 is a schematic timing diagram showing an exemplary control method for plasma processing according to an embodiment of the present invention, wherein the exemplary control method for plasma processing includes an electron beam power pulse in addition to a source power pulse and a bias power pulse.
圖12顯示出根據本發明實施例之示例性電漿處理系統之方塊圖，示例性電漿處理系統除了來源脈衝調變電路及脈衝調變時序電路之外，亦包括導電格柵。FIG. 12 shows a block diagram of an exemplary plasma processing system according to an embodiment of the present invention, the exemplary plasma processing system including a conductive grid in addition to a source pulse modulation circuit and a pulse modulation timing circuit.
圖13顯示出根據本發明實施例之電漿處理之示例性控制方法之概要時序圖，電漿處理之示例性控制方法除了來源功率脈衝及偏壓功率脈衝之外，亦包括格柵控制脈衝。FIG. 13 shows a schematic timing diagram of an exemplary control method for plasma processing according to an embodiment of the present invention, wherein the exemplary control method for plasma processing includes a grid control pulse in addition to a source power pulse and a bias power pulse.
圖14顯示出根據本發明實施例之產生控制法則之示例性方法之流程圖，控制法則可用於在電漿處理期間之離子角度分佈函數之主動控制；FIG. 14 is a flow chart showing an exemplary method for generating a control law that can be used for active control of the ion angle distribution function during plasma processing according to an embodiment of the present invention;
圖15顯示出根據本發明實施例之電漿處理之示例性前饋控制方法之流程圖；FIG. 15 is a flow chart showing an exemplary feedforward control method for plasma processing according to an embodiment of the present invention;
圖16顯示出根據本發明實施例之在電漿處理期間之示例性控制方法；FIG. 16 shows an exemplary control method during plasma processing according to an embodiment of the present invention;
圖17顯示出根據本發明實施例之電漿處理之示例性方法；及FIG. 17 shows an exemplary method of plasma treatment according to an embodiment of the present invention; and
圖18顯示出數種習知時序圖，包括來源功率及偏壓功率。Figure 18 shows several learned timing diagrams, including source power and bias power.
除非另外指出，否則不同圖式中之對應數字及符號通常表示對應的部件。圖式係繪製以清楚地顯示實施例之相關態樣，且不一定按比例繪製。圖式中所顯示之特徵部之邊緣不一定表示特徵部範圍之界限。Unless otherwise indicated, corresponding numbers and symbols in the different drawings generally indicate corresponding components. The drawings are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale. The edges of features shown in the drawings do not necessarily represent the limits of the features.
300:時序圖 300: Timing diagram
303:SP脈衝寬度 303:SP pulse width
305:脈衝調變週期 305: Pulse modulation cycle
307:BP脈衝寬度 307:BP pulse width
311:SP脈衝 311:SP Pulse
312:BP脈衝 312:BP pulse
320:時序圖 320: Timing diagram
322:BP脈衝 322:BP pulse
326:前緣偏壓偏移 326: Leading edge bias offset
327:BP脈衝寬度 327:BP pulse width
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| US9257294B2 (en) | 2010-08-24 | 2016-02-09 | Micron Technology, Inc. | Methods and apparatuses for energetic neutral flux generation for processing a substrate |
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| US9257294B2 (en) | 2010-08-24 | 2016-02-09 | Micron Technology, Inc. | Methods and apparatuses for energetic neutral flux generation for processing a substrate |
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