TWI834356B - 承載結構 - Google Patents
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Abstract
一種承載結構,係於封裝基板之置晶區上定義有至少一定位區,並將至少一對位部設於該定位區上,故藉由將該定位區設於該置晶區上,以提高製作該對位部時之精準度,使該承載結構對於置晶作業時能提供更好的對位機制。
Description
本發明係有關一種半導體結構,尤指一種可提升製程可靠性之承載結構。
於半導體封裝發展中,早期使用導線架(lead frame)作為承載主動元件之承載件,其主要原因係其具有較低製造成本與較高可靠度之優點。然而,隨著電子產業的蓬勃發展,電子產品在型態上趨於輕薄短小,在功能上則朝高性能、高功能、高速化的研發方向。因此,為滿足半導體裝置之高積集度(Integration)及微型化(Miniaturization)需求,現階段封裝製程漸以具有高密度及細間距之線路的封裝基板取代導線架。
如圖1A所示,於傳統封裝製程中,係將複數封裝基板10陣列排設成一基板條(strip)1,且於該基板條1之外圍對應各該封裝基板10之角落處形成有複數定位孔100,並於該基板條1之邊緣配置複數測試墊101及至少一條碼102,以於後續封裝製程中,如圖1B所示,將複數半導體晶片30藉由該些定位孔100分別對位,以令各該複數半導體晶片30設於各該封裝基板10之置晶區D上,再以封裝膠體32包覆該些半導體晶片30,以獲取複數半導體封裝件3,之後藉由該條碼102識別各該半導體封
裝件3之批號,以讀取該封裝基板10之相關資訊。最後,進行切單製程以移除該基板條1之邊條,且一併移除該定位孔100、測試墊101及條碼102。
所述之封裝基板10包含有複數介電層10b及設於該複數介電層10b上之複數線路層10a。
所述之半導體晶片30藉由複數導電凸塊31以覆晶方式電性連接該複數線路層10a,並藉由該些測試墊101測試該半導體晶片30與該複數線路層10a之間的電性連接情況。
然而,該基板條1之版面面積極大,僅藉由少量分布於該基板條1外圍的定位孔100對位每一個半導體晶片30之置晶區D之位置,將使精準度降低,導致常常發生半導體晶片30偏移而造成該封裝基板10與該半導體晶片30之間電性連接不良之問題。
因此,如何克服上述習知技術的問題,實已成目前亟欲解決的課題。
鑑於上述習知技術之種種缺失,本發明係提供一種承載結構,係包括:封裝基板,係定義有至少一置晶區及至少一位於該置晶區上之定位區;以及對位部,係設於該定位區上。
前述之承載結構中,該封裝基板係具有介電層與設於該介電層上之線路層。例如,該封裝基板於最外側之該介電層上形成絕緣保護層。
前述之承載結構中,該置晶區係具有複數角落處,以於各該角落處形成有該定位區。
前述之承載結構中,該定位區之邊長係為該置晶區之邊長之4%~50%。例如,該定位區之邊長係為該置晶區之邊長之1/4。
前述之承載結構中,該對位部係為凹槽形式。
前述之承載結構中,該對位部係為對稱圖形。
前述之承載結構中,該定位區上係形成複數該對位部。例如,該定位區係具有複數角落處,且複數該對位部係位於該定位區之至少兩角落處。
前述之承載結構中,該對位部係包含形成於該置晶區上之虛線路,以令該封裝基板於該置晶區上形成外露該虛線路之開孔,且於該置晶區上形成外露線路層之另一開孔,該線路層係形成於該置晶區上且未電性連接該虛線路,並使該線路層之外露表面用以外接導電凸塊。
由上可知,本發明之承載結構中,主要藉由將該定位區設於該封裝基板上,以提高製作該對位部時之位置精準度及尺寸公差精準度,使該承載結構對於設置電子元件能具有更好的對位機制,故相較於習知技術,當該半導體晶片藉由該封裝基板上的對位部進行置晶區之位置之對位時,不論該承載結構之版面面積大小,該承載結構均能提供置晶作業較佳之精準度,以避免該半導體晶片發生偏移而造成該封裝基板與該半導體晶片之間電性連接不良之問題。
1:基板條
10,20:封裝基板
10a,20a:線路層
10b,20b:介電層
100:定位孔
101,201:測試墊
102,202:條碼
2:承載結構
2a:功能件
200,201:開孔
21:絕緣保護層
210,211:對位部
213:虛線路
23:連接段
3:半導體封裝件
30:半導體晶片
31:導電凸塊
32:封裝膠體
A:定位區
D:置晶區
L,L1:長度
W,W1:寬度
圖1A係為習知基板條之上視平面示意圖。
圖1B係為習知半導體封裝件之局部剖面示意圖。
圖2A係為本發明之承載結構之上視平面示意圖。
圖2B係為本發明之承載結構所製得之半導體封裝件之局部剖面示意圖。
圖3A係為圖2A之部分局部放大示意圖。
圖3B係為圖3A之部分局部放大示意圖。
以下藉由特定的具體實施例說明本發明之實施方式,熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知,本說明書所附圖式所繪示之結構、比例、大小等,均僅用以配合說明書所揭示之內容,以供熟悉此技藝之人士之瞭解與閱讀,並非用以限定本發明可實施之限定條件,故不具技術上之實質意義,任何結構之修飾、比例關係之改變或大小之調整,在不影響本發明所能產生之功效及所能達成之目的下,均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時,本說明書中所引用之如「上」、及「一」等之用語,亦僅為便於敘述之明瞭,而非用以限定本發明可實施之範圍,其相對關係之改變或調整,在無實質變更技術內容下,當亦視為本發明可實施之範疇。
圖2A係為係為本發明之承載結構的上視平面示意圖。如圖2A所示,所述之承載結構2係包括:陣列排設之複數封裝基板20、連接該複數封裝基板20之複數連接段23。
於本實施例中,該承載結構2係為整版面型式,如基板條(strip)規格,其於該連接段23上配置功能件2a,如測試墊201或條碼202,且各該封裝基板20上係定義有至少一矩形狀之置晶區D及至少一位於該置晶區D角落之定位區A,以於單一該定位區A上形成至少一對位部210,211。例如,該置晶區D係假想區域,其為半導體晶片30之垂直投影面積所覆蓋之區域,故該置晶區D係對應該半導體晶片30之輪廓。
再者,該定位區A位在對應該半導體晶片30下方的四個角落處,以令該對位部210,211作為後續封裝製程中之對位機制。例如,當置放如半導體晶片30(如圖2B所示)之電子元件於該封裝基板20之置晶區D上時,該電子元件可藉由該些對位部210,211進行對位。
又,該電子元件係依所需之數量佈設於各該封裝基板20上,其可為主動元件、被動元件或其組合等,其中,該主動元件係例如半導體晶片,且該被動元件係例如電阻、電容及電感。於本實施例中,該電子元件係為半導體晶片30,其可藉由複數導電凸塊31(如圖2B所示)以覆晶方式設於該封裝基板20之置晶區D上;或者該電子元件可藉由打線方式電性連接該封裝基板20;亦或,該電子元件可嵌埋於該封裝基板20中。應可理解地,有關該電子元件之配置及電性連接該封裝基板20之方式繁多,並不限於上述。
另外,該包覆層係為絕緣材,如聚醯亞胺(polyimide,簡稱PI)、乾膜(dry film)、環氧樹脂(epoxy)或封裝材(molding compound)或其它封裝膠體32,並無特別限制。
因此,該承載結構2係可應用於半導體封裝製程,以獲取複數半導體封裝件3。
所述之封裝基板20係為具有核心層之線路結構或無核心層(coreless)之線路結構,其具有至少一介電層20b與至少一設於該介電層20b上之線路層20a,如扇出(fan out)型重佈線路層(redistribution layer,簡稱RDL),並於最外側之介電層20b上形成一如防銲層之絕緣保護層21。
於本實施例中,該封裝基板20之版面及其置晶區D係呈矩形,使該置晶區D之每一角落處上係設有該定位區A,且形成該介電層20b之主要材質係為如聚對二唑苯(Polybenzoxazole,簡稱PBO)、聚醯亞胺(Polyimide,簡稱PI)、預浸材(Prepreg,簡稱PP)等之介電材。應可理解地,該封裝基板20可依需求選擇形成該絕緣保護層21或不形成該絕緣保護層21。然而,該封裝基板20亦可為其它承載晶片之承載件,如有機板材、半導體材、或其他具有金屬佈線(routing)之載板,故不限於上述。
再者,由於該定位區A係形成於該置晶區D內,且該置晶區D之佈線係對應該半導體晶片30之線路間距(pitch)作設計(如導電凸塊31之間距),即間距較小,故在線路密集的置晶區D中配合線路製程一併製作該對位部210,211,則該對位部210,211的位置及尺寸公差均因配合該線路層20a之圖案化製程而會更精準,因而可有效提高對位精準度。例如,該定位區A係為假想區域,其內仍具有該線路層20a之功能佈線(如對應
該半導體晶片30之導電凸塊31),而該對位部210,211僅設計於該定位區A的非功能佈線處,如角落處。
又,該定位區A係呈矩形,如圖3A所示,其長度L1係為該置晶區D之長度L之4%~50%,且其寬度W1係為該置晶區D之寬度W之4%~50%。例如,該定位區A之長度L1係為該置晶區D之長度L之1/4,且該定位區A之寬度W1係為該置晶區D之寬度W之1/4。
另外,可於該定位區A之其中一對角處上分別形成不同對稱圖形之對位部210,211,如圖3A所示之十字狀與矩形狀。例如,該些對位部210,211係為凹槽形式,可於該絕緣保護層21上形成複數開孔200,201,以於部分該開孔200處外露已形成於該介電層20b上之虛線路(dummy trace)213,如圖2B及圖3B所示,使該虛線路213外露於該絕緣保護層21之開孔200,供作為該對位部210,211,以便於對位作業中進行位置辨識,其中,該對位部210,211之虛線路213並未電性連接該線路層20a與該半導體晶片30。另外,該絕緣保護層21之其它開孔201係用以外露該線路層20a之部分表面,供後續外接導電凸塊31。
因此,配合該絕緣保護層21用以外接導電凸塊31之開孔201之製程,將該對位部210,211所配合之開孔200同步形成於該封裝基板20之置晶區D上,使得形成該對位部210,211之位置將更精準,且該對位部210,211之圖形尺寸公差也將更精準。
應可理解地,有關該對位部210,211之態樣繁多,可依需求設計,如兩對位部之形狀相同或僅一對位部具有虛線路等,並不限於上述。
所述之連接段23係環繞佈設於該封裝基板20之周緣,且該連接段23係包含至少一絕緣層,以令該功能件2a形成於該絕緣層上。
於本實施例中,該連接段23之構造係可依據該封裝基板20之製程及構造製作。例如,該絕緣層可為該介電層20b及/或該絕緣保護層21,而無需形成線路層,以令該功能件2a形成於該絕緣保護層21上。
再者,該連接段23係於各該封裝基板20之間定義為作為切單製程之切割路徑,以移除該連接段23及該測試墊201與條碼202,但保留該對位部210,211於該封裝基板20上,俾獲取複數半導體封裝件3。
因此,本發明之承載結構2主要藉由將該定位區A設於該封裝基板20之置晶區D上,以提高製作該對位部210,211時之位置精準度及尺寸公差精準度,使該承載結構2對於設置半導體晶片30能具有更好的對位機制,故相較於習知技術,當該半導體晶片30藉由該封裝基板20上置晶區D內的對位部210,211進行置晶位置之對位時,不論該承載結構2之版面面積大小,該承載結構2均能提供置晶作業較佳之精準度,以避免該半導體晶片30發生偏移而造成該封裝基板20與該半導體晶片30之間電性連接不良之問題。
再者,藉由將兩定位區A分別設於該封裝基板20之置晶區D對角線之兩角落處,以利於提升置晶作業之精準度。
又,藉由將兩對位部210,211分別設於該定位區A之對角線之兩角落處,以利於提升置晶作業之精準度。較佳地,當該兩對位部210,211之圖形不同時,更有利於提升置晶作業之精準度。
另外,藉由於該對位部210,211呈對稱圖形之設計,亦有利於提升置晶作業之精準度。
綜上所述,本發明之承載結構,係藉由將該定位區設於該封裝基板上,以提高製作該對位部時之位置精準度及尺寸公差精準度,使該承載結構對於設置電子元件能具有更好的對位機制,故該承載結構能提供置晶作業較佳之精準度,以避免該半導體晶片發生偏移而造成該封裝基板與該半導體晶片之間電性連接不良之問題,因而有利於提升半導體封裝製程之良率及產量。
上述實施例係用以例示性說明本發明之原理及其功效,而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下,對上述實施例進行修改。因此本發明之權利保護範圍,應如後述之申請專利範圍所列。
20:封裝基板
20a:線路層
210,211:對位部
A:定位區
D:置晶區
L,L1:長度
W,W1:寬度
Claims (9)
- 一種承載結構,係包括:封裝基板,係定義有至少一置晶區及至少一位於該置晶區上之定位區;以及對位部,係設於該定位區上,其中,該對位部係包含形成於該置晶區上之虛線路,以令該封裝基板於該置晶區上形成外露該虛線路之開孔,且於該置晶區上形成外露線路層之另一開孔,該線路層係形成於該置晶區上且未電性連接該虛線路,並使該線路層之外露表面用以外接導電凸塊。
- 如請求項1所述之承載結構,其中,該封裝基板係具有介電層與設於該介電層上之該線路層。
- 如請求項1所述之承載結構,其中,該置晶區係具有複數角落處,以於各該角落處形成有該定位區。
- 如請求項1所述之承載結構,其中,該定位區之邊長係為該置晶區之邊長之4%~50%。
- 如請求項4所述之承載結構,其中,該定位區之邊長係為該置晶區之邊長之1/4。
- 如請求項1所述之承載結構,其中,該對位部係為凹槽形式。
- 如請求項1所述之承載結構,其中,該對位部係為對稱圖形。
- 如請求項1所述之承載結構,其中,該定位區上係形成複數該對位部。
- 如請求項8所述之承載結構,其中,該定位區係具有複數角落處,且複數該對位部係位於該定位區之至少兩角落處。
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TW201442171A (zh) * | 2013-04-24 | 2014-11-01 | 矽品精密工業股份有限公司 | 中介板及其製法 |
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