TWI833121B

TWI833121B - Semiconductor components

Info

Publication number: TWI833121B
Application number: TW110138087A
Authority: TW
Inventors: 何焱騰; 陳乃榕
Original assignee: 瑞礱科技股份有限公司
Priority date: 2021-10-14
Filing date: 2021-10-14
Publication date: 2024-02-21
Also published as: TW202316667A

Abstract

本發明係一種半導體元件，包含有一通道層以及二金屬層，該通道層係由二維材料所形成，該通道層中具有二互相間隔之摻雜區、以及一未摻雜區介於該二摻雜區之間，該二金屬層係覆設於該二摻雜區。藉此，能有效降低二維材料與金屬之間的接觸電阻，使該二維材料能成功應用在電晶體或二極體的通道層。The invention is a semiconductor element, which includes a channel layer and two metal layers. The channel layer is formed of a two-dimensional material. The channel layer has two doped regions spaced apart from each other, and an undoped region between the two. Between the doped regions, the two metal layers are covered with the two doped regions. In this way, the contact resistance between the two-dimensional material and the metal can be effectively reduced, so that the two-dimensional material can be successfully used in the channel layer of a transistor or diode.

Description

半導體元件Semiconductor components

本發明與半導體有關，特別是指一種半導體元件。The present invention relates to semiconductors, and in particular refers to a semiconductor component.

在半導體元件尺寸越來越小的今日，矽材料已到達其先天的侷限而無法作得更小，為了能進一步縮小半導體元件的尺寸，二維材料是最有可能取代矽成為半導體通道之材料，其中又以過渡金屬二硫屬化合物(Transition Metal Dichalcogenides, TMDs) 被認為是最有可能應用於積體電路的材料，如二硫化鉬(MoS ₂)，然由於二維材料為層狀結構且無未鍵結的懸空鍵(dangling bond)，使得二維材料很難與金屬形成強的界面鍵結，再加上二維材料與金屬的接面存有蕭基能障(Schottky barrier)，使帶電載子難以通過，導致接觸電阻較高而通過電流較低。 Today, the size of semiconductor components is getting smaller and smaller. Silicon material has reached its inherent limitations and cannot be made smaller. In order to further reduce the size of semiconductor components, two-dimensional materials are the most likely material to replace silicon as the semiconductor channel. Among them, Transition Metal Dichalcogenides (TMDs) are considered to be the most likely materials to be used in integrated circuits, such as molybdenum disulfide (MoS ₂ ). However, because the two-dimensional material has a layered structure and no Unbonded dangling bonds make it difficult for two-dimensional materials to form strong interface bonds with metals. In addition, there is a Schottky barrier at the interface between two-dimensional materials and metals, making the charged It is difficult for carriers to pass through, resulting in high contact resistance and low passing current.

在某些半導體應用場合如場效電晶體(FET)，如何降低接觸電阻，達成元件應用所需之歐姆接觸，是元件能否成功應用的關鍵，惟目前尚未有任何技術能有效降低二維材料與金屬之間的接觸電阻。In some semiconductor applications such as field effect transistors (FETs), how to reduce the contact resistance and achieve the ohmic contact required for component application is the key to the successful application of the component. However, there is currently no technology that can effectively reduce the contact resistance of two-dimensional materials. Contact resistance with metal.

本發明之一目的在於提供一種半導體元件，能有效降低二維材料與金屬之間的接觸電阻，使該二維材料能成功應用在電晶體或二極體的通道層。One object of the present invention is to provide a semiconductor element that can effectively reduce the contact resistance between a two-dimensional material and a metal, so that the two-dimensional material can be successfully used in the channel layer of a transistor or a diode.

為了達成上述目的，本發明之半導體元件包含有一通道層以及二金屬層，該通道層係由二維材料所形成，該通道層中具有二互相間隔之摻雜區、以及一未摻雜區介於該二摻雜區之間，該二金屬層係覆設於該二摻雜區。藉此，能有效降低二維材料與金屬之間的接觸電阻，達成歐姆接觸，使該二維材料能成功應用在電晶體或二極體的通道層。In order to achieve the above object, the semiconductor device of the present invention includes a channel layer and two metal layers. The channel layer is formed of a two-dimensional material. The channel layer has two mutually spaced doped regions and an undoped region. Between the two doped regions, the two metal layers cover the two doped regions. In this way, the contact resistance between the two-dimensional material and the metal can be effectively reduced and ohmic contact can be achieved, so that the two-dimensional material can be successfully used in the channel layer of a transistor or diode.

以下藉由二較佳實施例配合圖式，詳細說明本發明的技術內容及特徵，如圖1所示，係本發明第一較佳實施例所提供之半導體元件10，該半導體元件10係一電晶體，包含有一基板12、一通道層14、二金屬層20、一絕緣層22以及一閘極24。The following describes the technical content and features of the present invention in detail through two preferred embodiments and drawings. As shown in FIG. 1, it is a semiconductor device 10 provided by the first preferred embodiment of the present invention. The semiconductor device 10 is a The transistor includes a substrate 12, a channel layer 14, two metal layers 20, an insulating layer 22 and a gate 24.

該基板12可採用半導體材料，如矽、鍺、金剛石或其類似者；或者，亦可使用具有其他晶體定向之化合物材料，如矽鍺、碳化矽、氧化矽、砷化鎵、砷化銦、磷化銦、矽鍺碳化物、鎵砷磷化物、鎵銦磷化物、藍寶石或其類似者。該基板12可摻雜有p型摻雜劑，如硼、鋁、鎵或其類似者，或者該基板12亦可摻雜有n型摻雜劑。該基板12之厚度可依需要選擇。The substrate 12 can be made of semiconductor materials, such as silicon, germanium, diamond or the like; or, compound materials with other crystal orientations can also be used, such as silicon germanium, silicon carbide, silicon oxide, gallium arsenide, indium arsenide, Indium phosphide, silicon germanium carbide, gallium arsenic phosphide, gallium indium phosphide, sapphire or the like. The substrate 12 may be doped with p-type dopants, such as boron, aluminum, gallium or the like, or the substrate 12 may also be doped with n-type dopants. The thickness of the substrate 12 can be selected as needed.

該通道層14係由二維材料所形成，該二維材料可為過渡金屬二硫屬化合物(Transition Metal Dichalcogenides)如二硫化鉬(MoS ₂)、二硒化鉬(MoSe ₂)、二碲化鉬(MoTe ₂)、二硫化鎢(WS ₂)、二硒化鎢(WSe ₂)、二碲化鎢(WTe ₂)、二硫化鉿(HfS ₂)、二硒化鉿(HfSe ₂)、二硫化鋯(ZrS ₂)與二硒化鋯(ZrSe ₂)，該二維材料亦可為三族硫屬化合物如硒化銦(InSe)與硒化镓(GaSe)，亦可為其他已知或未知的二維材料，於本實施例中採用的是二硫化鉬(MoS ₂)，該通道層14中具有二互相間隔之摻雜區16、以及一未摻雜區18介於該二摻雜區16之間，該摻雜區16係於二硫化鉬中添加p型摻雜劑如鈮(Nb)、鉭(Ta)或其組合，或其他合適的p型摻雜劑材料，或者添加n型摻雜劑如錸(Re)、鎝(Tc)、釕(Ru)或其組合，或其他合適的n型摻雜劑材料，使該摻雜區16成為p型半導體或n型半導體，於本實施例中係將鈮(Nb)作為摻雜劑，該未摻雜區18則為單純未摻雜的二硫化鉬。 The channel layer 14 is formed of a two-dimensional material. The two-dimensional material can be a transition metal dichalcogenide (Transition Metal Dichalcogenides) such as molybdenum disulfide (MoS ₂ ), molybdenum diselenide (MoSe ₂ ), ditelluride Molybdenum (MoTe ₂ ), tungsten disulfide (WS ₂ ), tungsten diselenide (WSe ₂ ), tungsten disulfide (WTe ₂ ), hafnium disulfide (HfS ₂ ), hafnium diselenide (HfSe ₂ ), Zirconium sulfide (ZrS ₂ ) and zirconium diselenide (ZrSe ₂ ), the two-dimensional material can also be a Group III chalcogen compound such as indium selenide (InSe) and gallium selenide (GaSe), or other known or The unknown two-dimensional material is molybdenum disulfide (MoS ₂ ) in this embodiment. The channel layer 14 has two mutually spaced doped regions 16 and an undoped region 18 between the two doped regions. Between the regions 16, the doping region 16 is made by adding p-type dopants such as niobium (Nb), tantalum (Ta) or combinations thereof, or other suitable p-type dopant materials in molybdenum disulfide, or adding n Type dopants such as rhenium (Re), phosphonium (Tc), ruthenium (Ru) or combinations thereof, or other suitable n-type dopant materials, make the doped region 16 a p-type semiconductor or an n-type semiconductor. In this embodiment, niobium (Nb) is used as a dopant, and the undoped region 18 is simply undoped molybdenum disulfide.

摻雜的實際作法如圖2a所示，首先於一該基板12上形成二硫化鉬之該通道層14，再將鈮的氧化物(NbO _x)15鍍覆於該通道層14之二側表面，沈積方式可為反應濺鍍(reactive sputtering)、電子束蒸鍍(e-beam evaporation)、熱蒸鍍(thermal evaporation)、脈衝雷射沈積(pulsed laser deposition)、原子層沉積(Atomic layer deposition)或其他適合方式；接著，利用硫粉(sulfur)、硫化氫(H ₂S) 或其他適合材料為硫源進行硫化反應，以爐管(Furnace)或快速退火(Rapid Thermal Annealing)方式，在溫度450~900°C下，時間持續1分鐘～2小時，即可將鈮摻雜於二硫化鉬中形成該二摻雜區16，如圖2b所示，該二摻雜區16的摻雜型態同為p型，於其他實施例中，該二摻雜區16的摻雜型態可同為n型。於本實施例中，是以反應濺鍍之方式沈積鈮的氧化物(NbO _x)15於該通道層14之表面，以硫化氫 (H ₂S)為硫源進行硫化反應，在爐管(Furnace)中加熱，在溫度600°C下持續30分鐘而形成該二摻雜區16。 The actual doping method is shown in Figure 2a. First, the channel layer 14 of molybdenum disulfide is formed on a substrate 12, and then niobium oxide (NbO _x ) 15 is plated on both sides of the channel layer 14. , the deposition method can be reactive sputtering, e-beam evaporation, thermal evaporation, pulsed laser deposition, atomic layer deposition or other suitable methods; then, use sulfur powder (sulfur), hydrogen sulfide (H ₂ S) or other suitable materials as the sulfur source to perform the vulcanization reaction, using furnace tube (Furnace) or rapid annealing (Rapid Thermal Annealing) method, at the temperature At 450~900°C, for 1 minute to 2 hours, niobium can be doped into molybdenum disulfide to form the second doped region 16. As shown in Figure 2b, the doping type of the second doped region 16 The doping states of the two doped regions 16 can be both n-type in other embodiments. In this embodiment, niobium oxide ₍ _NbO Furnace), the second doped region 16 was formed by heating at a temperature of 600°C for 30 minutes.

於其他實施例，該摻雜劑亦可以金屬型式沈積於該通道層14表面，沈積方式可為反應濺鍍(reactive sputtering)、電子束蒸鍍(e-beam evaporation)、熱蒸鍍(thermal evaporation) 或其他適合方式，並經硫化或硒化而摻雜於該二維材料中，形成該摻雜區16，該硒化之硒源可為硒粉(Selelinum)、硒化氫(H ₂Se) 或其他適合材料，硒化之方式如同上述之硫化方式。 In other embodiments, the dopant can also be deposited on the surface of the channel layer 14 in a metallic form, and the deposition method can be reactive sputtering, e-beam evaporation, or thermal evaporation. ) or other suitable methods, and is doped into the two-dimensional material through sulfide or selenization to form the doping region 16. The selenium source of the selenization can be selenium powder (Selelinum), hydrogen selenide (H ₂ Se ) or other suitable materials, the selenization method is the same as the vulcanization method above.

該二金屬層20覆設於該二摻雜區16之表面，分別作為源極20a與汲極20b，如圖2c所示，該金屬層之成分為鈦(Ti)、銦(In)、金(Au)、鎢(W)、鉬(Mo)、鉑(Pt)、鈀(Pd)、鉻(Cr)、鎳(Ni)、錫(Sn)、鉍(Bi)、鉭(Ta)或其合金，或其他導電材料，單層或多層均可，於本實施例中係採用鈦/金的雙層結構。The two metal layers 20 are covered on the surface of the two doped regions 16 and serve as the source electrode 20a and the drain electrode 20b respectively. As shown in FIG. 2c, the components of the metal layer are titanium (Ti), indium (In), and gold. (Au), tungsten (W), molybdenum (Mo), platinum (Pt), palladium (Pd), chromium (Cr), nickel (Ni), tin (Sn), bismuth (Bi), tantalum (Ta) or other Alloy, or other conductive materials, can be single-layer or multi-layer. In this embodiment, a titanium/gold double-layer structure is used.

該絕緣層22為氧化物，位於該閘極24與該通道層14之間，同時將該閘極24與該源極20a、該汲極20b分隔開。The insulating layer 22 is an oxide and is located between the gate electrode 24 and the channel layer 14 and separates the gate electrode 24 from the source electrode 20a and the drain electrode 20b.

由於鈮的摻雜可使二硫化鉬與金屬之間的蕭基能障降低且變窄，且該二摻雜區16與該未摻雜區18之間的屬於二維材料的側向接觸(Edge Contact)，相較於頂面接觸(Top Contact)具有較低的電阻，如此可大幅降低二維材料與金屬間的接觸電阻，舉例而言，未摻雜的二維材料與金屬之間的接觸電阻約為3.3 kΩ μm，於本實施例中該二金屬層20與該二摻雜區16之接觸電阻可低至500 Ω μm以下，達成歐姆接觸，使得二維材料應用在電晶體的通道層14具有極佳的效能，從而達成本發明的目的。Because the doping of niobium can reduce and narrow the Schottky energy barrier between molybdenum disulfide and metal, and the lateral contact between the two doped regions 16 and the undoped region 18 is a two-dimensional material ( Edge Contact) has lower resistance than Top Contact, which can greatly reduce the contact resistance between two-dimensional materials and metals. For example, the contact resistance between undoped two-dimensional materials and metals The contact resistance is about 3.3 kΩ μm. In this embodiment, the contact resistance between the two metal layers 20 and the two doped regions 16 can be as low as less than 500 Ω μm, achieving ohmic contact, so that the two-dimensional material can be used in the channel of the transistor. Layer 14 has excellent performance and thus achieves the objectives of the present invention.

本發明之架構不僅可應用在電晶體，亦可應用至二極體，如圖3所示，係本發明第二較佳實施例所提供之半導體元件30，該半導體元件30係一二極體，包含有一基板32、一通道層34以及二金屬層40。其中，該通道層34為二維材料所形成，包含有二摻雜區36與一未摻雜區38，該二摻雜區36其中之一摻雜型態為p型，與其上的金屬層40a形成p型接觸，另一摻雜區36之摻雜型態則為n型，與其上的金屬層40b形成n型接觸。藉此，可降低二維材料與金屬之間的接觸電阻達到歐姆接觸，使該二維材料能成功應用在二極體的通道層，從而達成本發明的目的。The structure of the present invention can be applied not only to transistors, but also to diodes. As shown in Figure 3, it is a semiconductor device 30 provided by the second preferred embodiment of the present invention. The semiconductor device 30 is a diode. , including a substrate 32, a channel layer 34 and two metal layers 40. Among them, the channel layer 34 is formed of a two-dimensional material and includes two doped regions 36 and an undoped region 38. One of the doping types of the two doped regions 36 is p-type, and the metal layer above it 40a forms a p-type contact, and the doping type of the other doped region 36 is n-type, forming an n-type contact with the metal layer 40b above it. In this way, the contact resistance between the two-dimensional material and the metal can be reduced to achieve ohmic contact, so that the two-dimensional material can be successfully applied to the channel layer of the diode, thereby achieving the purpose of the present invention.

基於本發明之設計精神，該半導體元件之結構可有其他變化，例如：應用至三維全包覆式之MOSFET時，無需設置該基板12。舉凡此等可輕易思及的結構變化，均應為本發明申請專利範圍所涵蓋，且本發明之基礎架構除可應用至電晶體與二極體之外，亦可應用至其他半導體元件。Based on the design spirit of the present invention, the structure of the semiconductor device can have other changes. For example, when applied to a three-dimensional fully-covered MOSFET, the substrate 12 does not need to be provided. All such easily conceivable structural changes should be covered by the patent application scope of the present invention, and the basic structure of the present invention can be applied to other semiconductor components in addition to transistors and diodes.

10:半導體元件 12:基板 14:通道層 15:氧化物 16:摻雜區 18:未摻雜區 20:金屬層 20a:源極 20b:汲極 22:絕緣層 24:閘極 30:半導體元件 32:基板 34:通道層 36:摻雜區 38:未摻雜區 40,40a,40b:金屬層 10:Semiconductor components 12: Substrate 14: Channel layer 15: Oxide 16: Doped area 18: Undoped area 20: Metal layer 20a: Source 20b: Drain 22: Insulating layer 24: Gate 30: Semiconductor component 32: Substrate 34: Channel layer 36: Doped area 38: Undoped area 40, 40a, 40b: Metal layer

圖1為本發明第一較佳實施例之半導體元件之示意圖；圖2a~c為本發明第一較佳實施例之半導體元件之製程示意圖；圖3為本發明第二較佳實施例之半導體元件之示意圖。 Figure 1 is a schematic diagram of a semiconductor device according to a first preferred embodiment of the present invention; 2a~c are schematic diagrams of the manufacturing process of the semiconductor device according to the first preferred embodiment of the present invention; FIG. 3 is a schematic diagram of a semiconductor device according to a second preferred embodiment of the present invention.

10:半導體元件 10:Semiconductor components

12:基板 12:Substrate

14:通道層 14: Channel layer

16:摻雜區 16: Doped area

18:未摻雜區 18: Undoped area

20:金屬層 20:Metal layer

20a:源極 20a: Source

20b:汲極 20b: Drainage pole

22:絕緣層 22:Insulation layer

24:閘極 24: Gate

Claims

一種半導體元件，包含有：一通道層，係由二維材料所形成，該通道層中具有二互相間隔之摻雜區、以及一未摻雜區介於該二摻雜區之間，其中該二摻雜區係於該二維材料中添加摻雜劑為鈮(Nb)、鉭(Ta)、錸(Re)、鎝(Tc)、釕(Ru)或其組合；以及二金屬層，覆設於該二摻雜區。 A semiconductor element includes: a channel layer formed of two-dimensional material, the channel layer has two doped regions spaced apart from each other, and an undoped region between the two doped regions, wherein the The second doping region is a dopant added to the two-dimensional material, which is niobium (Nb), tantalum (Ta), rhenium (Re), tonium (Tc), ruthenium (Ru) or a combination thereof; and a second metal layer, covering Located in the two doped regions.

如請求項1所述之半導體元件，其中該二維材料係過渡金屬二硫屬化合物(Transition Metal Dichalcogenides)或三族硫屬化合物。 The semiconductor device as claimed in claim 1, wherein the two-dimensional material is a transition metal dichalcogenide (Transition Metal Dichalcogenides) or a Group III chalcogenide.

如請求項2所述之半導體元件，其中該二維材料係二硫化鉬(MoS₂)、二硒化鉬(MoSe₂)、二碲化鉬(MoTe₂)、二硫化鎢(WS₂)、二硒化鎢(WSe₂)、二碲化鎢(WTe₂)、二硫化鉿(HfS₂)、二硒化鉿(HfSe₂)、二硫化鋯(ZrS₂)、二硒化鋯(ZrSe₂)、硒化銦(InSe)或硒化镓(GaSe)。 The semiconductor element according to claim 2, wherein the two-dimensional material is molybdenum disulfide (MoS ₂ ), molybdenum diselenide (MoSe ₂ ), molybdenum disulfide (MoTe ₂ ), tungsten disulfide (WS ₂ ), Tungsten diselenide (WSe ₂ ), tungsten diselenide (WTe ₂ ), hafnium disulfide (HfS ₂ ), hafnium diselenide (HfSe ₂ ), zirconium disulfide (ZrS ₂ ), zirconium diselenide (ZrSe ₂ ), indium selenide (InSe) or gallium selenide (GaSe).

如請求項1所述之半導體元件，其中該摻雜劑是以氧化物或金屬型式沈積於該通道層表面，並經硫化或硒化而摻雜於該二維材料中，形成該摻雜區。 The semiconductor device according to claim 1, wherein the dopant is deposited on the surface of the channel layer in the form of oxide or metal, and is doped into the two-dimensional material through sulfide or selenization to form the doped region. .

如請求項4所述之半導體元件，其中該氧化物是以反應濺鍍(reactive sputtering)、電子束蒸鍍(e-beam evaporation)、熱蒸鍍(thermal evaporation)、脈衝雷射沈積(pulsed laser deposition)或原子層沉積(Atomic layer deposition)之方式形成。 The semiconductor device according to claim 4, wherein the oxide is deposited by reactive sputtering, e-beam evaporation, thermal evaporation, or pulsed laser deposition. deposition) or atomic layer deposition.

如請求項4所述之半導體元件，其中該金屬是以反應濺鍍(reactive sputtering)、電子束蒸鍍(e-beam evaporation)或熱蒸鍍(thermal evaporation)之方式形成。 The semiconductor device according to claim 4, wherein the metal is formed by reactive sputtering, e-beam evaporation or thermal evaporation.

如請求項4所述之半導體元件，其中該硫化之硫源為硫粉(sulfur)或硫化氫(H₂S)，該硒化之硒源為硒粉(Selelinum)或硒化氫(H₂Se)。 The semiconductor device as described in claim 4, wherein the sulfur source for sulfide is sulfur powder (sulfur) or hydrogen sulfide (H ₂ S), and the selenium source for selenization is selenium powder (Selelinum) or hydrogen selenide (H ₂ Se).

如請求項7所述之半導體元件，其中該硫化或是硒化之方式為爐管(Furnace)或快速退火(Rapid Thermal Annealing)，溫度450~900℃，時間為1分鐘~2小時。 The semiconductor component as described in claim 7, wherein the sulfidation or selenization method is furnace tube (Furnace) or Rapid Thermal Annealing (Rapid Thermal Annealing), the temperature is 450~900°C, and the time is 1 minute to 2 hours.

如請求項1所述之半導體元件，其中該金屬層之成分為鈦(Ti)、銦(In)、金(Au)、鎢(W)、鉬(Mo)、鉑(Pt)、鈀(Pd)、鉻(Cr)、鎳(Ni)、錫(Sn)、鉍(Bi)、鉭(Ta)或其合金。 The semiconductor element according to claim 1, wherein the metal layer is composed of titanium (Ti), indium (In), gold (Au), tungsten (W), molybdenum (Mo), platinum (Pt), palladium (Pd) ), chromium (Cr), nickel (Ni), tin (Sn), bismuth (Bi), tantalum (Ta) or their alloys.

如請求項1所述之半導體元件，更包含有一基板供該通道層設於其上。 The semiconductor device according to claim 1 further includes a substrate on which the channel layer is disposed.

如請求項1所述之半導體元件，其中該二摻雜區的摻雜型態同為p型、或同為n型、或為不同型。 The semiconductor device according to claim 1, wherein the doping types of the two doped regions are the same p-type, the same n-type, or different types.

如請求項1所述之半導體元件為電晶體或二極體。The semiconductor component as claimed in claim 1 is a transistor or a diode.