JPS63199415A - Manufacture of semiconductor element - Google Patents
Manufacture of semiconductor elementInfo
- Publication number
- JPS63199415A JPS63199415A JP3155687A JP3155687A JPS63199415A JP S63199415 A JPS63199415 A JP S63199415A JP 3155687 A JP3155687 A JP 3155687A JP 3155687 A JP3155687 A JP 3155687A JP S63199415 A JPS63199415 A JP S63199415A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- indium
- substrate
- deposited
- manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 13
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 229910052738 indium Inorganic materials 0.000 claims abstract description 24
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 238000000034 method Methods 0.000 claims abstract description 13
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 12
- 229910000673 Indium arsenide Inorganic materials 0.000 claims abstract description 12
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 claims abstract description 12
- 229910052785 arsenic Inorganic materials 0.000 claims abstract description 7
- 238000000151 deposition Methods 0.000 claims abstract description 5
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims abstract 5
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims description 11
- 229910052751 metal Inorganic materials 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 9
- 238000010438 heat treatment Methods 0.000 claims description 3
- 229910000838 Al alloy Inorganic materials 0.000 claims 1
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 claims 1
- UTSDGYKWHMMTDM-UHFFFAOYSA-N alumane;tungsten Chemical group [AlH3].[W] UTSDGYKWHMMTDM-UHFFFAOYSA-N 0.000 claims 1
- 238000005245 sintering Methods 0.000 abstract description 6
- IBEFSUTVZWZJEL-UHFFFAOYSA-N trimethylindium Chemical compound C[In](C)C IBEFSUTVZWZJEL-UHFFFAOYSA-N 0.000 abstract description 5
- 229910045601 alloy Inorganic materials 0.000 abstract description 3
- 239000000956 alloy Substances 0.000 abstract description 3
- 229910001080 W alloy Inorganic materials 0.000 abstract description 2
- 229910052782 aluminium Inorganic materials 0.000 abstract description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 2
- RBFQJDQYXXHULB-UHFFFAOYSA-N arsane Chemical compound [AsH3] RBFQJDQYXXHULB-UHFFFAOYSA-N 0.000 abstract description 2
- 239000012535 impurity Substances 0.000 abstract description 2
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 abstract 2
- 239000002994 raw material Substances 0.000 abstract 1
- 238000007493 shaping process Methods 0.000 abstract 1
- 238000004544 sputter deposition Methods 0.000 abstract 1
- 238000000137 annealing Methods 0.000 description 11
- 229910000927 Ge alloy Inorganic materials 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 4
- 239000013078 crystal Substances 0.000 description 2
- RCJVRSBWZCNNQT-UHFFFAOYSA-N dichloridooxygen Chemical compound ClOCl RCJVRSBWZCNNQT-UHFFFAOYSA-N 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000005275 alloying Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
(産業上の利用分野〕
本発明は半導体素子の製造方法、特にガリウムヒ素基板
を用いる半導体素子におけるオーミック接触の形成に関
するものである。DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a method of manufacturing a semiconductor device, and particularly to the formation of ohmic contacts in a semiconductor device using a gallium arsenide substrate.
(従来の技術)
ガリウムヒ素(Ga AS )を用いたFET (電界
効果トランジスタ)はシリコンに比べて電子の速度が同
じ電圧で5〜6倍も速いことから相互コンダクタンスg
mが小ざくなり動作速度が速く、また消費電力も小さい
という特徴を有しており、製造技術の進歩により今後増
々頻繁に使用されることが期待されている。(Prior technology) FETs (field effect transistors) using gallium arsenide (Ga AS ) have a high mutual conductance g because the electron speed is 5 to 6 times faster than that of silicon at the same voltage.
It has the characteristics of small m, high operating speed, and low power consumption, and is expected to be used more frequently in the future as manufacturing technology advances.
ガリウムヒ素(Ga As )基板を用いたFETにお
いては通常ゲートについては金属と半導体の接触による
ショツ1〜キー接触を、ソース、ドレインについてはオ
ーミック接触を用いる。このオーミック接触を形成しよ
うとする場合、n型Ga AS基板に対しては通常Au
−Ge合金が用いられる。そしてこのAu−(3a合金
を用いた場合、ALI−Ge合金をGaAs基板上に堆
積した後シンタリングと称される加熱処理による合金化
が行なわれている。しかしこのシンタリングによりAu
−Ge合金がボールアップする(球状塊となる)ことお
よびAU−Ge合金を用いて形成されたオーミック接触
は500℃以下では接触抵抗が著しく増加するという問
題を有している。In an FET using a gallium arsenide (GaAs) substrate, normally a short-key contact is used for the gate, which is a contact between a metal and a semiconductor, and an ohmic contact is used for the source and drain. When attempting to form this ohmic contact, typically Au is used for n-type Ga AS substrate.
-Ge alloy is used. When this Au-(3a alloy is used, the ALI-Ge alloy is deposited on the GaAs substrate and then alloyed by heat treatment called sintering. However, this sintering
-Ge alloy balls up (becomes a spherical mass), and ohmic contacts formed using AU-Ge alloys have problems in that contact resistance increases significantly at temperatures below 500°C.
これを解決するために(3a AS基板の上にInAs
層および金属層を順次堆積させることが提案されている
。金属とInAsはシンタリングを行なわなくても容易
に低接触抵抗のオーミック接触を形成する。To solve this problem (3a)
It has been proposed to deposit layers and metal layers sequentially. Metal and InAs easily form an ohmic contact with low contact resistance without sintering.
しかしこのような構造を採用した場合、Ga As上に
InAs層を単に形成したのでは、両者の間にバリヤが
形成され良好なオーミック接触が得られない。However, when such a structure is adopted, if an InAs layer is simply formed on GaAs, a barrier is formed between the two, and good ohmic contact cannot be obtained.
これに対しJ、W、Woodall et、al、:J
、Vac、Sci。On the other hand, J, W, Woodall et al, :J
, Vac, Sci.
Technol、Vo119.No、3.p、626〜
p、627(1981)特にそのp、627のFig、
1 (d)に示されているようにG at−X I
nXA SをGa AS側よりx=Qから1へ連続的に
変化するように(グレイデッド)結晶成長してバリヤの
発生を抑制する技術が提案されている。Technol, Vol.119. No, 3. p, 626~
p, 627 (1981) especially that p, 627 Fig.
1 (d) as shown in G at-X I
A technique has been proposed for suppressing the generation of barriers by growing crystals of nXA S so that x=Q changes continuously from 1 to 1 (graded) from the Ga AS side.
しかしながら、このようなGa1−xInxASのグレ
イデッド層を形成するには3元の混晶成長を必要とし、
所望の層を得るための条件設定が非常に困難であるとい
う問題があった。特にGa 1−XInXAs層が薄い
場合には製造が一層困難である。However, forming such a graded layer of Ga1-xInxAS requires ternary mixed crystal growth;
There was a problem in that it was very difficult to set conditions to obtain a desired layer. In particular, when the Ga 1-XInXAs layer is thin, manufacturing is more difficult.
本発明はこのような問題を解決するもので、グレイデッ
ド層を成長させることなくシンタリングを必要としない
ノンアロイオーミック接触を形成することができる半導
体素子の製造方法を提供することを目的とする。The present invention solves these problems, and aims to provide a method for manufacturing a semiconductor device that can form a non-alloy ohmic contact that does not require sintering without growing a graded layer. .
本発明はGa As基板表面にまずinを堆積し続いて
InとAsとを主体とする層を堆積しさらにその上に金
属層を形成するようにしたものである。In the present invention, in is first deposited on the surface of a GaAs substrate, then a layer mainly composed of In and As is deposited, and a metal layer is further formed thereon.
本発明の方法によればGa AS基板およびInとAS
とを主体とする層の間にまずIn層が形成される。この
ため1nASと(3a Asとの間にバリヤが発生しに
くくなるのでシンタリングを行なわなくても低抵抗のオ
ーミック接触が得られる。According to the method of the present invention, Ga AS substrate and In and AS
First, an In layer is formed between the layers mainly composed of. Therefore, a barrier is less likely to occur between 1nAs and (3aAs), so that a low-resistance ohmic contact can be obtained without sintering.
第1図は本発明に係る半導体素子の製造方法を示す工程
別素子断面図である。なおここではソース、ドレイン部
について示す。FIG. 1 is a cross-sectional view of a semiconductor device according to each step, showing a method of manufacturing a semiconductor device according to the present invention. Note that the source and drain portions are shown here.
まずn型不純物を多量(例えばキャリア密度1×101
8cm−3)に含むnGaA3基板1の表面にインジウ
ム層2を例えば公知のMOCVD (有機金属化学的気
相成長)法により堆積させる。すなわち、トリメチルイ
ンジウム(丁MI)を原料ガスとして450℃の雰囲気
で成長させる。これにより数人〜1ooXの厚さのイン
ジウム層が形成される(第1図(a))。First, add a large amount of n-type impurity (for example, carrier density 1×101
An indium layer 2 is deposited on the surface of an nGaA3 substrate 1 containing a thickness of 8 cm -3 by, for example, a known MOCVD (metal-organic chemical vapor deposition) method. That is, the growth is performed in an atmosphere of 450° C. using trimethylindium (di-MI) as a source gas. As a result, an indium layer with a thickness of several to 10X is formed (FIG. 1(a)).
次にTMIおよびアルシン(As H3)を用いて同様
に基板温度450℃でMOCVD法によりIn As
l1J3を堆積させる(第1図(b))。Next, using TMI and arsine (As H3), InAs was formed using the MOCVD method at a substrate temperature of 450°C.
11J3 is deposited (FIG. 1(b)).
次にその上にタングステンおよびアルミニウムの合金で
なる配線層4をスパッタンリグ等の方法で形成する(第
1図(C))。Next, a wiring layer 4 made of an alloy of tungsten and aluminum is formed thereon by a method such as a sputter rig (FIG. 1(C)).
このようにして形成されたソース、ドレイン電極におけ
る接触抵抗は2x1o−6Ω/d以下であり、良好な値
が得られた。The contact resistance of the source and drain electrodes formed in this manner was 2x1o-6 Ω/d or less, which was a good value.
尚■n As層形成後例えばW−A I電極の形成後に
600〜800℃の温度でアニールを行なうこととして
も抵抗を低下させることができる。第2図はW−A I
電極形成後の横軸はW−AI電極形成後に行なったアニ
ールの温度を、縦軸はその結果得られた接触抵抗をそれ
ぞれ示している。試料1は予め、即ちこのアニールには
インジウム層を7Aの厚さで堆積後700℃で1分間の
アニールを行ないInAs層を堆積したもの、試料2は
予めインジウム層を7Aの厚さで堆積後■n Asの堆
積したもの、試料3はインジウム層を30犬の厚さで堆
積後InA3層を堆積したものである。Note that the resistance can also be lowered by performing annealing at a temperature of 600 to 800° C. after forming the As layer, for example, after forming the W-A I electrode. Figure 2 shows W-A I
The horizontal axis after forming the electrode shows the temperature of annealing performed after forming the W-AI electrode, and the vertical axis shows the contact resistance obtained as a result. For sample 1, an InAs layer was deposited beforehand, that is, for this annealing, an indium layer was deposited to a thickness of 7A, and then annealing was performed at 700°C for 1 minute to deposit an InAs layer. Sample 3 is a sample in which As was deposited, and three InA layers were deposited after an indium layer was deposited to a thickness of 30 mm.
試料2と試料3の比較からIn層の厚さが厚い方が、接
触抵抗が低いことが分かる。また、試料1と試料2の比
較から、In層の堆積後いったんアニールを行ない、さ
らにW−AI電極の形成後にアニールを行なった方が接
触抵抗がより低くなることが分かる。そしてそれぞれの
資料をさらに600℃,700℃,750℃,800℃
でそれぞれ20分間アニールを行なった場合にはアニー
ル温度か高い程接触抵抗が低下することがわかる。Comparing Samples 2 and 3, it can be seen that the thicker the In layer, the lower the contact resistance. Further, from a comparison between Sample 1 and Sample 2, it can be seen that the contact resistance is lowered by performing annealing once after depositing the In layer and further performing annealing after forming the W-AI electrode. Then, each material was further heated to 600℃, 700℃, 750℃, and 800℃.
It can be seen that the higher the annealing temperature, the lower the contact resistance when annealing is performed for 20 minutes in each case.
さらに本発明により形成されたオーミック接触は800
′Cl2O分のアニールに対しても安定で十分な耐熱性
を有することがわかる。Furthermore, the ohmic contact formed by the present invention is 800
It can be seen that it is stable and has sufficient heat resistance even against annealing of Cl2O.
以上の実施例においてはオーミック接触を取るべきソー
ス、ドレイン領域についてのみ示しているが、適当なパ
ターニングを行なってその大ぎさを自由に定めることが
でき、また、ソースとトレインの間のQa As基板上
に直接金属電極を形成し、ショットキー接続を行なうこ
とによってグー1〜を形成することができる。In the above embodiments, only the source and drain regions that should be in ohmic contact are shown, but their size can be freely determined by performing appropriate patterning. Groups 1 to 1 can be formed by directly forming a metal electrode thereon and making a Schottky connection.
ざらにGa As基板上にシリコン酸化膜等の絶縁膜を
選択的に形成してあき、Qa As基板の露出部のみに
インジウム層およびInAs層を選択的に成長させるこ
とも可能である。例えばインジウム層の膜厚を20Aと
しこのインジウム層の堆積後700℃,1分間のアニー
ルを行なった後に450℃の基板温度でInAsを成長
させる。これにより接触抵抗値は2X10’Ω/ at
tの値が得られ、これをさらに800℃,15分のアニ
ールを行なってもほとんど接触抵抗値に変化はなく、選
択成長法を用いる場合でも本発明が有効であることがわ
かる。It is also possible to selectively form an insulating film such as a silicon oxide film on a GaAs substrate, and selectively grow an indium layer and an InAs layer only on the exposed portion of the QaAs substrate. For example, the thickness of the indium layer is 20A, and after the indium layer is deposited, annealing is performed at 700.degree. C. for 1 minute, and then InAs is grown at a substrate temperature of 450.degree. As a result, the contact resistance value is 2X10'Ω/at
Even when the value of t was obtained and this was further annealed at 800° C. for 15 minutes, there was almost no change in the contact resistance value, indicating that the present invention is effective even when selective growth is used.
なお、InAsはほとんどすべての金属についてオーミ
ック接触が可能であるので本発明は上述したW−A、l
l以外の金属についても適用することができる。Note that since InAs is capable of making ohmic contact with almost all metals, the present invention is applicable to the above-mentioned W-A, l
It can also be applied to metals other than l.
以上のように本発明によればGa As基板およびIn
As層との間にインジウム層を堆積するようにしている
のでGa AS 基板上にInAsを形成する際に生じ
るバリヤを低減でき、低抵抗で耐熱性にすぐれたオーミ
ック接触を合金化を要することなく実現することができ
る。As described above, according to the present invention, GaAs substrate and In
Since the indium layer is deposited between the As layer and the As layer, the barrier that occurs when forming InAs on the Ga AS substrate can be reduced, and an ohmic contact with low resistance and excellent heat resistance can be created without the need for alloying. It can be realized.
第1図は本発明の一実施例を示す工程別素子断面図、第
2図は本発明を用いて形成されたオーミック接触の特性
を示すグラフである。
1・・・n GaAs基板、2・・・インジウム層、3
・・・InAs層、4・・・W−Aρ層。
= 10 −
2:インジウム層
(−/¥)
(C)
ル
J
し アニール逼度乙辣触抵抗
第 2 図
一実 方絞、イ列
茶 l 図FIG. 1 is a cross-sectional view of a step-by-step device showing an embodiment of the present invention, and FIG. 2 is a graph showing characteristics of an ohmic contact formed using the present invention. 1...n GaAs substrate, 2... Indium layer, 3
...InAs layer, 4...W-Aρ layer. = 10-2: Indium layer (-/¥) (C) Annealing strength and contact resistance No. 2
Claims (1)
堆積形成する工程と、 その上にインジウムおよびヒ素を主体とする層を堆積形
成する工程と、 その上に配線金属層を必要に応じ形成する工程とを備え
た半導体素子の製造方法。 2、インジウム層の形成工程の後600℃以上の温度で
の加熱処理を行なうことを特徴とする特許請求の範囲第
1項記載の半導体素子の製造方法。 3、インジウムおよびヒ素を主体とする層の成長工程の
後600℃以上の温度での加熱処理を行なうことを特徴
とする特許請求の範囲第1項または第2項記載の半導体
素子の製造方法。 4、インジウムおよびヒ素を主体とする層 がInAs層またはInGaAs層であることを特徴と
する特許請求の範囲第1項記載の半導体素子の製造方法
。 5、配線金属層がタングステン−アルミニウム合金層で
ある特許請求の範囲第1項記載の半導体素子の製造方法
。 6、インジウム層並びにインジウムおよびヒ素を主体と
する層の形成がガリウムヒ素基板上で選択的に行われる
ものである特許請求の範囲第1項記載の半導体素子の製
造方法。[Claims] 1. A step of depositing an indium layer on a gallium arsenide (GaAs) substrate, a step of depositing a layer mainly composed of indium and arsenic thereon, and a wiring metal layer thereon. A method for manufacturing a semiconductor element, comprising a step of forming as necessary. 2. The method for manufacturing a semiconductor device according to claim 1, wherein a heat treatment is performed at a temperature of 600° C. or higher after the step of forming the indium layer. 3. The method for manufacturing a semiconductor device according to claim 1 or 2, wherein a heat treatment is performed at a temperature of 600° C. or higher after the step of growing the layer mainly containing indium and arsenic. 4. The method for manufacturing a semiconductor device according to claim 1, wherein the layer mainly containing indium and arsenic is an InAs layer or an InGaAs layer. 5. The method of manufacturing a semiconductor device according to claim 1, wherein the wiring metal layer is a tungsten-aluminum alloy layer. 6. The method of manufacturing a semiconductor device according to claim 1, wherein the indium layer and the layer mainly composed of indium and arsenic are selectively formed on the gallium arsenide substrate.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3155687A JPS63199415A (en) | 1987-02-16 | 1987-02-16 | Manufacture of semiconductor element |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3155687A JPS63199415A (en) | 1987-02-16 | 1987-02-16 | Manufacture of semiconductor element |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63199415A true JPS63199415A (en) | 1988-08-17 |
Family
ID=12334455
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3155687A Pending JPS63199415A (en) | 1987-02-16 | 1987-02-16 | Manufacture of semiconductor element |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63199415A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63237470A (en) * | 1987-03-16 | 1988-10-03 | インターナシヨナル・ビジネス・マシーンズ・コーポレーション | Semiconductor device |
US5346852A (en) * | 1993-02-25 | 1994-09-13 | The United States Of America As Represented By The Secretary Of The Navy | Low temperature process for producing indium-containing semiconductor materials |
-
1987
- 1987-02-16 JP JP3155687A patent/JPS63199415A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63237470A (en) * | 1987-03-16 | 1988-10-03 | インターナシヨナル・ビジネス・マシーンズ・コーポレーション | Semiconductor device |
US5346852A (en) * | 1993-02-25 | 1994-09-13 | The United States Of America As Represented By The Secretary Of The Navy | Low temperature process for producing indium-containing semiconductor materials |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US4186410A (en) | Nonalloyed ohmic contacts to n-type Group III(a)-V(a) semiconductors | |
JP3512659B2 (en) | Nitride III-V compound semiconductor device | |
US5124779A (en) | Silicon carbide semiconductor device with ohmic electrode consisting of alloy | |
Moazed et al. | Ohmic contacts to semiconducting diamond | |
Anderson et al. | Development ot ohmic contacts for GaAs devices using epitaxial Ge films | |
WO1997008744A1 (en) | Laminate for forming ohmic electrode and ohmic electrode | |
JPS63199415A (en) | Manufacture of semiconductor element | |
JPH0296374A (en) | Semiconductor device and manufacture thereof | |
JPS6362313A (en) | Manufacture of semiconductor device | |
JP3439597B2 (en) | Ohmic electrode for n-type SiC and manufacturing method thereof | |
O'connor et al. | Gold-germanium-based ohmic contacts to the two-dimensional electron gas at selectively doped semiconductor heterointerfaces | |
JP2750330B2 (en) | Method for manufacturing compound semiconductor device | |
KR102394975B1 (en) | Method for Manufacturing Semiconductor Device and Semiconductor Device Manufactured Thereby | |
JPH0945635A (en) | Manufacture of semiconductor device and semiconductor device | |
JPS62143461A (en) | N-type gaas ohmic electrodes | |
JPH06326051A (en) | Ohmic electrode and formation thereof | |
JP3768348B2 (en) | Semiconductor device and manufacturing method thereof | |
JPS61241972A (en) | Compound semiconductor device | |
JPH05275467A (en) | Manufacture of compound semiconductor device | |
JP2929084B2 (en) | Method of forming compound semiconductor low contact resistance electrode | |
JPS61161760A (en) | Manufacture of semiconductor device | |
JPH02219244A (en) | Field effect trensistor and its manufacture | |
JPH03236224A (en) | Manufacture of semiconductor device | |
JP2987405B2 (en) | Method for manufacturing compound semiconductor device | |
JPH02170417A (en) | Manufacture of electrode of compound semiconductor device |