TWI832508B - 電子封裝件 - Google Patents
電子封裝件 Download PDFInfo
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- TWI832508B TWI832508B TW111140085A TW111140085A TWI832508B TW I832508 B TWI832508 B TW I832508B TW 111140085 A TW111140085 A TW 111140085A TW 111140085 A TW111140085 A TW 111140085A TW I832508 B TWI832508 B TW I832508B
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- 229910000679 solder Inorganic materials 0.000 claims abstract description 56
- 239000010410 layer Substances 0.000 claims description 122
- 239000011229 interlayer Substances 0.000 claims description 52
- 239000000463 material Substances 0.000 claims description 34
- 238000004806 packaging method and process Methods 0.000 description 25
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 19
- 229910052802 copper Inorganic materials 0.000 description 18
- 239000010949 copper Substances 0.000 description 18
- 239000004642 Polyimide Substances 0.000 description 15
- 229920001721 polyimide Polymers 0.000 description 15
- 239000004065 semiconductor Substances 0.000 description 15
- 238000005253 cladding Methods 0.000 description 12
- 239000011247 coating layer Substances 0.000 description 8
- 229920002577 polybenzoxazole Polymers 0.000 description 7
- 239000000758 substrate Substances 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000012792 core layer Substances 0.000 description 4
- 239000003989 dielectric material Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000005538 encapsulation Methods 0.000 description 4
- 239000004593 Epoxy Substances 0.000 description 3
- 239000004698 Polyethylene Substances 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 3
- 150000001875 compounds Chemical class 0.000 description 3
- 239000011810 insulating material Substances 0.000 description 3
- 238000000465 moulding Methods 0.000 description 3
- 239000005022 packaging material Substances 0.000 description 3
- -1 polyethylene Polymers 0.000 description 3
- 229920000573 polyethylene Polymers 0.000 description 3
- 235000012431 wafers Nutrition 0.000 description 3
- 238000010521 absorption reaction Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
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- 150000002466 imines Chemical class 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000001568 sexual effect Effects 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
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- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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Abstract
一種電子封裝件,係將第一電子模組藉由複數第一導電結構與第二導電結構堆疊一第二電子模組,且該第一導電結構之銲錫量係多於該第二導電結構之銲錫量,使該電子封裝件可依據其翹曲程度進行第一導電結構與第二導電結構之配置,以有效分散應力而避免發生翹曲之問題。
Description
本發明係有關一種半導體裝置,尤指一種堆疊複數電子模組之電子封裝件。
隨著電子產業的蓬勃發展,電子產品也逐漸邁向多功能、高性能的趨勢。目前應用於晶片封裝領域之技術,包含有例如晶片尺寸構裝(Chip Scale Package,簡稱CSP)、晶片直接貼附封裝(Direct Chip Attached,簡稱DCA)、封裝堆疊(package on package,簡稱PoP)或多晶片模組封裝(Multi-Chip Module,簡稱MCM)等封裝型態。
圖1係為習知半導體封裝件1之剖面示意圖。如圖1所示,該半導體封裝件1係將兩封裝模組1a,1b藉由複數銲錫凸塊13相互堆疊,且各該封裝模組1a,1b係包含一線路結構10a,10b、設於該線路結構10a,10b上且電性連接該線路結構10a,10b之電子元件11a,11b、一包覆該電子元件11a,11b之封裝層12a,12b,以令該些銲錫凸塊13電性連接該線路結構10a,10b,其中,下方封裝模組1a係於該封裝層12a之相對兩側均佈設該線路結構10a,因而於該封裝層12a中佈設有複數用以電性連接兩線路結構10a之銅柱體17。
前述半導體封裝件1主要以下方線路結構10a藉由複數導電凸塊191與銲球190接置於一電路板19上。
惟,習知半導體封裝件1中,該兩封裝模組1a,1b因其線路結構10a,10b之層數及/或佈線不同,或電子元件11a,11b之規格、數量及/或尺寸不同,亦或封裝層12a,12b之用量及/或材質不同等種種因素,而使所產生之應力無法平均分佈,導致該兩封裝模組1a,1b之間的區域空間S的應力分佈不同,如角落處之應力遠大於其它處,致使該半導體封裝件1容易發生變形的情況(即翹曲),造成該銲錫凸塊13或銲球190發生脫離,進而導致該半導體封裝件1之信賴性不佳。
因此,如何克服上述習知技術之問題,實已成為目前業界亟待克服之難題。
鑑於上述習知技術之種種缺失,本發明係提供一種電子封裝件,係包括:第一電子模組,係具有相對之第一側與第二側;第二電子模組,係堆疊於該第一電子模組之第一側上,其中,該第一電子模組之第一側與該第二電子模組之間的區域係定義為第一層間,且該第一電子模組之第二側向外之區域係定義為第二層間;包含銲錫材料之複數第一導電結構,係配置於該第一層間中;以及包含銲錫材料之複數第二導電結構,係配置於該第一層間中,其中,該複數第一導電結構之銲錫量係多於該複數第二導電結構之銲錫量。
前述之電子封裝件中,各該第一導電結構係為銲錫球。
前述之電子封裝件中,各該第二導電結構係包含導電柱及形成於該導電柱端面上之銲錫材料。
前述之電子封裝件中,該複數第一導電結構與該複數第二導電結構係依據該第一層間中之應力大小進行配置,以令該複數第一導電結構於該第一層間所分佈之位置上之應力係大於該複數第二導電結構於該第一層間所分佈之位置上之應力。
前述之電子封裝件中,該複數第一導電結構係環繞圍住該複數第二導電結構。
前述之電子封裝件中,該複數第一導電結構復配置於該第二層間中,且該第一層間的複數第一導電結構之數量係少於該第二層間的複數第一導電結構之數量。
前述之電子封裝件中,該複數第二導電結構復配置於該第二層間中,且該第一層間的複數第二導電結構之數量係多於該第二層間的複數第二導電結構之數量。
前述之電子封裝件中,復包括配置於該第一層間中之複數第三導電結構,其無銲錫量。例如,各該第三導電結構係包含相互堆疊之第一導電柱與第二導電柱,以令該第一導電柱立設於該第一電子模組上,且該第二導電柱立設於該第二電子模組上,使該第一導電柱之端面與該第二導電柱之端面相互接觸於該第一層間中。
進一步,該複數第一、第二與第三導電結構係依據該第一層間中之應力大小進行配置,以令該複數第一導電結構於該第一層間所分佈之位置上之應力係大於該複數第二導電結構於該第一層間所分佈之位置上之應力,且該
複數第二導電結構於該第一層間所分佈之位置上之應力係大於該複數第三導電結構於該第一層間所分佈之位置上之應力。
或者,該複數第一導電結構、第二導電結構及第三導電結構係於該第一層間中以對稱方式由外向內依序排設。例如,該複數第二導電結構係環繞圍住該複數第三導電結構。
另外,該複數第三導電結構復配置於該第二層間中,且該第一層間的複數第三導電結構之數量係等於該第二層間的複數第三導電結構之數量。
由上可知,本發明之電子封裝件中,主要藉由該第一層間可依據該電子封裝件的翹曲程度配置銲錫量不同之第一導電結構與第二導電結構,以有效分散應力而避免發生應力集中之問題,故相較於習知技術,本發明之電子封裝件可避免發生翹曲之問題,以提高後續將該電子封裝件接置於電路板上的良率。
1:半導體封裝件
1a,1b,2c:封裝模組
10a,10b:線路結構
11a,11b:電子元件
12a,12b,28:封裝層
13:銲錫凸塊
17:銅柱體
19,9:電路板
190:銲球
191:導電凸塊
2:電子封裝件
2a:第一電子模組
2b:第二電子模組
20:第一承載結構
20a:第一側
20b:第二側
21:第一電子元件
22:第二電子元件
23,33:佈線結構
24:第一包覆層
25:第二包覆層
26:第二承載結構
27:第三電子元件
29a:第一導電元件
29b:第二導電元件
290,310,320:銲錫材料
291:銅凸塊
30:第三承載結構
31a,31b:第一導電結構
311:電性接觸墊
32a,32b:第二導電結構
321:導電柱
33a,33b:第三導電結構
331:第一導電柱
332:第二導電柱
L1:第一層間
L2:第二層間
L3:第三層間
S:區域空間
圖1係為習知半導體封裝件之剖視示意圖。
圖2係為本發明之電子封裝件之剖視示意圖。
圖3A及圖3B係為圖2之不同層間之上視示意圖。
以下藉由特定的具體實施例說明本發明之實施方式,熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知,本說明書所附圖式所繪示之結構、比例、大小等,均僅用以配合說明書所揭示之內容,以供熟悉此技藝之人士之瞭解與閱讀,並非用以限定本發明可實施之限定條件,故不具技術上之實質意義,任何結構之修飾、比例關係之改變或大小之調整,在不影響本發明所能產生之功效及所能達成之目的下,均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時,本說明書中所引用之如「上」、「第一」、「第二」、「第三」、「一」等之用語,亦僅為便於敘述之明瞭,而非用以限定本發明可實施之範圍,其相對關係之改變或調整,在無實質變更技術內容下,當亦視為本發明可實施之範疇。
圖2係為本發明之電子封裝件2之剖面示意圖。如圖2所示,該電子封裝件2包括:第一電子模組2a、第二電子模組2b、複數第一導電結構31a,31b、複數第二導電結構32a,32b以及複數第三導電結構33a,33b,其中,該些第一導電結構31a,31b、第二導電結構32a,32b及第三導電結構33a,33b之構件係互不相同。
所述之第一電子模組2a係包含一第一包覆層24、至少一嵌埋於該第一包覆層24中之第一電子元件21、一設於該第一包覆層24其中一側以電性連接該第一電子元件21之第一承載結構20、及設於該第一包覆層24另一側之佈線結構23。
於本實施例中,該第一承載結構20係定義有相對之第一側20a與第二側20b,且該第一承載結構20可例如為具有核心層與線路結構之封裝基板、無核心層(coreless)形式線路結構之封裝基板、具導電矽穿孔(Through-silicon via,簡稱TSV)之矽中介板(Through Silicon interposer,簡稱TSI)或其它板型,其包含至少一介電層(圖略)及至少一結合該介電層之線路層(圖略)。例如,透過線
路重佈層(redistribution layer,簡稱RDL)之製作方式形成該線路層,其材質係為銅,且形成該介電層之材質係為如聚對二唑苯(Polybenzoxazole,簡稱PBO)、聚醯亞胺(Polyimide,簡稱PI)、預浸材(Prepreg,簡稱PP)等之介電材。應可理解地,該第一承載結構20亦可為其它承載晶片之板材,如導線架(lead frame)、晶圓(wafer)、或其它具有金屬佈線(routing)之板體等,並不限於上述。
再者,該第一電子元件21係設於該第一承載結構20之第一側20a上並電性連接該第一承載結構20之線路層,且該第一電子元件21係為主動元件、被動元件或其二者組合等,其中,該主動元件係例如半導體晶片,且該被動元件係例如電阻、電容及電感。於本實施例中,該第一電子元件21係為半導體晶片,且於該第一承載結構20上配置複數個(如圖2所示之兩個)第一電子元件21。應可理解地,有關該第一電子元件21電性連接該第一承載結構20之方式繁多,如打線、覆晶、嵌埋或其它等,並無特別限制。
又,該第一包覆層24係形成於該第一承載結構20之第一側20a上以包覆該第一電子元件21,且該第一包覆層24係為絕緣材,如聚醯亞胺(Polyimide,簡稱PI)、乾膜(dry film)、環氧樹脂(epoxy)、封裝膠體(molding compound)或其它封裝材。
另外,該佈線結構23係包括至少一絕緣層(圖略)與設於該絕緣層上之線路重佈層(RDL)(圖略)。例如,形成該線路重佈層之材質係為銅,且形成該絕緣層之材質係為如聚對二唑苯(PBO)、聚醯亞胺(PI)、預浸材(PP)之介電材。應可理解地,該佈線結構23與該第一承載結構20之間可藉由至少一形成於該第一包覆層24中之導電結構(如圖1所示之銅柱體17)相互電性連接。
所述之第二電子模組2b係包含一第二包覆層25、至少一嵌埋於該第二包覆層25中之第二電子元件22、及一設於該第二包覆層25上以電性連接該第二電子元件22之第二承載結構26,以令該些第一導電結構31a、第二導電結構32a及第三導電結構33a連接於該第二承載結構26與該佈線結構23之間,使該第二電子模組2b藉由該些第一導電結構31a、第二導電結構32a及第三導電結構33a堆疊於該第一電子模組2a上,其中,該第一電子模組2a與該第二電子模組2b之間的區域係定義為第一層間L1,而該第一電子模組2a之第一承載結構20的第二側20b向外的區域係定義有第二層間L2。
應可理解地,該第一電子模組2a之構造與該第二電子模組2b之構造可相同或相異,且該第一電子模組2a之尺寸(如體積或寬度)可大於、等於或小於該第二電子模組2b之尺寸。
於本實施例中,該第二承載結構26係例如為具有核心層與線路結構之封裝基板、無核心層(coreless)形式線路結構之封裝基板、具導電矽穿孔(TSV)之矽中介板(TSI)或其它板型,其包含至少一介電層(圖略)及至少一結合該介電層之線路層(圖略)。於本實施例中,透過線路重佈層(RDL)之製作方式形成該線路層,其材質係為銅,且形成該介電層之材質係為如聚對二唑苯(PBO)、聚醯亞胺(PI)、預浸材(PP)等之介電材。應可理解地,該第二承載結構26亦可為其它承載晶片之板材,如導線架(lead frame)、晶圓(wafer)、或其它具有金屬佈線(routing)之板體等,並不限於上述。
再者,該第二電子元件22係設於該第二承載結構26上並電性連接該第二承載結構26之線路層,且該第二電子元件22係為主動元件、被動元件或其二者組合等,其中,該主動元件係例如半導體晶片,且該被動元件係例如電
阻、電容及電感。於本實施例中,該第二電子元件22係為半導體晶片,且於該第二承載結構26上配置複數個(如圖2所示之兩個)第二電子元件22。應可理解地,有關該第二電子元件22電性連接該第二承載結構26之方式繁多,如打線、覆晶、嵌埋或其它等,並無特別限制。
又,該第二包覆層25係形成於該第二承載結構26上以包覆該些第二電子元件22。於本實施例中,該第二包覆層25為絕緣材,如聚醯亞胺(PI)、乾膜(dry film)、環氧樹脂(epoxy)、封裝膠體(molding compound)或其它封裝材。應可理解地,該第一包覆層24與該第二包覆層25之材質可相同或相異。
所述之第一導電結構31a,31b係包含銲錫材料310,如規格為C4型之銲錫球,其配置於該第一層間L1(即該第二承載結構26與該佈線結構23之間)及該第二層間L2(即該第一承載結構20之第二側20b上)中。
於本實施例中,該第一導電結構31a,31b復包含用以結合該銲錫材料310之電性接觸墊311,其分別配置於該第二層間L2之第一承載結構20與該第一層間L1之第二承載結構26上。例如,該第二承載結構26上形成有該電性接觸墊311,以令該銲錫材料310形成於該電性接觸墊311上而結合該佈線結構23之線路重佈層;或者,該第一承載結構20之第二側20b上形成有該電性接觸墊311,以令該銲錫材料310形成於該電性接觸墊311上而外接如封裝模組2c之其它元件。
再者,該第一層間L1的第一導電結構31a之數量係少於該第二層間L2的第一導電結構31b之數量。例如,該第一層間L1與該第二層間L2均為矩形區域,且該第一層間L1的第一導電結構31a係沿該矩形區域之邊緣佈設
兩圈,如圖3A所示,而該第二層間L2的第一導電結構31b係沿該矩形區域之邊緣佈設三圈,如圖3B所示。
又,該第一層間L1與該第二層間L2均為矩形區域,以令該第一導電結構31a、31b位於該第一層間L1與該第二層間L2之邊緣(特別是角落處),如圖3A及圖3B所示。
所述之第二導電結構32a,32b係包含如銲錫凸塊之銲錫材料320與如規格為微凸塊(u-bump)型之導電柱321,其配置於該第一層間L1(即該第二承載結構26與該佈線結構23之間)及該第二層間L2(即該第一承載結構20之第二側20b與該封裝模組2c之間)中。
於本實施例中,該導電柱321係為如銅柱之金屬柱,且該銲錫材料320係形成於該導電柱321之端部上。例如,該導電柱321係立設於該第二承載結構26上,使該銲錫材料320結合該佈線結構23之線路重佈層;或者,該導電柱321可立設於該第一承載結構20之第二側20b上,使該銲錫材料320外接如封裝模組2c之其它元件。
再者,該第一層間L1的第二導電結構32a之數量係多於該第二層間L2的第二導電結構32b之數量。例如,該第一層間L1的第二導電結構32a係對應該第一層間L1的矩形區域之邊緣佈設三圈,如圖3A所示,而該第二層間L2的第二導電結構32b係對應該第二層間L2的矩形區域之邊緣佈設兩圈,如圖3B所示。
又,該第一導電結構31a,31b係環繞圍住該第二導電結構32a,32b,如圖3A及圖3B所示。
另外,該第一導電結構31a,31b之銲錫量係多於該第二導電結構32a,32b之銲錫量。
所述之第三導電結構33a,33b係包含相互堆疊之第一導電柱331與第二導電柱332,如金屬柱,其配置於該第一層間L1(即該第二承載結構26與該佈線結構23之間)及該第二層間L2(即該第一承載結構20之第二側20b與該封裝模組2c之間)中。
於本實施例中,第一導電柱331與第二導電柱332均為銅柱,兩者之銅材端面係相互接觸。例如,該第一導電柱331係立設於該佈線結構23上,且該第二導電柱332係立設於該第二承載結構26上,使第一導電柱331與第二導電柱332(兩銅柱)之端面相互接觸於該第一層間L1中以形成該第三導電結構33a;或者,該第一導電柱331可立設於如封裝模組2c之其它元件上,且該第二導電柱332可立設於該第一承載結構20之第二側20b上,使第一導電柱331與第二導電柱332(兩銅柱)之端面相互接觸於該第二層間L2中以形成該第三導電結構33b。
再者,該第一層間L1的第三導電結構33a之數量係等於該第二層間L2的第三導電結構33b之數量。例如,該第一層間L1的第三導電結構33a係於該第一層間L1的矩形區域之中間處對稱佈設九組,如圖3A所示,而該第二層間L2的第三導電結構33b係於該第二層間L2的矩形區域之中間處亦對稱佈設九組,如圖3B所示。
又,該第二導電結構32a,32b之銲錫量係多於該第三導電結構33a,33b之銲錫量,且該第二導電結構32a,32b係環繞圍住該第三導電結構33a,33b,如圖3A及圖3B所示。
另外,該第一、第二與第三導電結構31a,32a,33a係依據該第一層間L1中之應力大小進行配置,以令該第一導電結構31a於該第一層間L1所分佈之位置上之應力係大於該第二導電結構32a於該第一層間L1所分佈之位置上之應力,且該第二導電結構32a於該第一層間L1所分佈之位置上之應力係大於該第三導電結構33a於該第一層間L1所分佈之位置上之應力。同理地,該第二層間L2亦可採用上述配置方式。換言之,各層間的導電結構之佈設可基於銲錫量之多寡進行配置,以令銲錫量最多之第一導電結構31a,31b、銲錫量次多之第二導電結構32a,32b及無銲錫量之第三導電結構33a,33b於各層間中以對稱方式由外向內依序排設,如圖3A及圖3B所示。
因此,本發明之電子封裝件2中,主要藉由不同構造之第一導電結構31a、第二導電結構32a及第三導電結構33a堆疊第一電子模組2a與第二電子模組2b,並於該第一層間L1越靠近外圍之區域上佈設越多應力吸收效果較好的銲錫材料310,320,即於該第一層間L1中係由外向內依序排設銲錫量最多之第一導電結構31a、銲錫量次多之第二導電結構32a及無銲錫量之第三導電結構33a,以有效分散應力而避免發生應力集中之問題,故相較於習知技術,本發明之電子封裝件2能避免發生翹曲之問題。
再者,由於銅柱接合態樣之結構尺寸較小,且電阻值低,以利於應用在高接點(I/O)數、高訊號傳輸及小電流等需求,故於各層間中可依需求配置該第三導電結構33a,33b。
又,該第一層間L1之角落處的應力係小於該第二層間L2之角落處的應力,故藉由該第一層間L1於角落處的銲錫量少於該第二層間L2於角落處的銲錫量(即該第一層間L1於角落處的第一導電結構31a之數量少於該第二
層間L2於角落處的第一導電結構31b之數量)的設計,不僅能分散應力而避免發生應力集中之問題,且能節省銲錫材料310之成本。
另一方面,前述之封裝模組2c係包含一封裝層28、至少一嵌埋於該封裝層28中之第三電子元件27、一設於該封裝層28其中一側以電性連接該第三電子元件27之第三承載結構30、及設於該封裝層28另一側之佈線結構33。
於本實施例中,該第三承載結構30係例如為具有核心層與線路結構之封裝基板、無核心層(coreless)形式線路結構之封裝基板、具導電矽穿孔(TSV)之矽中介板(TSI)或其它板型,其包含至少一介電層(圖略)及至少一結合該介電層之線路層(圖略)。例如,透過線路重佈層(RDL)之製作方式形成該線路層,其材質係為銅,且形成該介電層之材質係為如聚對二唑苯(PBO)、聚醯亞胺(PI)、預浸材(PP)等之介電材。應可理解地,該第三承載結構30亦可為其它承載晶片之板材,如導線架(lead frame)、晶圓(wafer)、或其它具有金屬佈線(routing)之板體等,並不限於上述。
再者,該第三電子元件27係設於該第三承載結構30上並電性連接該第三承載結構30之線路層,且該第三電子元件27係為主動元件、被動元件或其二者組合等,其中,該主動元件係例如半導體晶片,且該被動元件係例如電阻、電容及電感。於本實施例中,該第三電子元件27係為半導體晶片,且於該第三承載結構30上配置複數個(如圖2所示之三個)第三電子元件27。應可理解地,有關該第三電子元件27電性連接該第三承載結構30之方式繁多,如打線、覆晶、嵌埋或其它等,並無特別限制。
又,該封裝層28係形成於該第三承載結構30上以包覆該些第三電子元件27,且該封裝層28係為絕緣材,如聚醯亞胺(PI)、乾膜(dry film)、環氧樹脂(epoxy)、封裝膠體(molding compound)或其它封裝材。該第一包覆層24、第二包覆層25與封裝層28之材質可相同或相異。
另外,該佈線結構33係包括至少一絕緣層(圖略)與設於該絕緣層上之線路重佈層(redistribution layer,簡稱RDL)(圖略)。例如,形成該線路重佈層之材質係為銅,且形成該絕緣層之材質係為如聚對二唑苯(Polybenzoxazole,簡稱PBO)、聚醯亞胺(Polyimide,簡稱PI)、預浸材(Prepreg,簡稱PP)之介電材。應可理解地,該佈線結構33與該第三承載結構30之間可藉由至少一形成於該封裝層28中之導電結構(如圖1所示之銅柱體17)相互電性連接。
因此,於該第一電子模組2a之第二側20b上可依需求配置多個相互堆疊之封裝模組2c,且於最外側之封裝模組2c上可藉由複數態樣不同之第一導電元件29a與第二導電元件29b設於一電路板9上,其中,可將該最外側之封裝模組2c與該電路板9之間的區域係定義為第三層間L3,且該第三層間L3於角落處之應力係大於該第二層間L2於角落處之應力。例如,該第一導電元件29a係為外接規格之錫球(其銲錫量多於該第一導電結構31a,31b之銲錫量),且該第二導電元件29b係為銅核心球(copper core ball),其由銲錫材料290包覆銅凸塊291。
應可理解地,由於錫球之銲錫量較多而具有較佳之應力吸收能力,故將該第一導電元件29a設於該第三層間L3之應力較大處(如外圍或角落處),而將銲錫量較少之第二導電元件29b設於該第三層間L3之應力較小處(如
中間處)。例如,該第一導電元件29a之分佈方式係環繞該第二導電元件29b之位置。
綜上所述,本發明之電子封裝件,係藉由該第一層間能依據該電子封裝件的翹曲程度進行該第一導電結構與第二導電結構(具不同銲錫量之導電結構)之配置,以有效分散應力而避免發生應力集中之問題,故本發明之電子封裝件能避免發生翹曲之問題,因而可提高後續將該電子封裝件接置於電路板上的良率。
上述實施例係用以例示性說明本發明之原理及其功效,而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下,對上述實施例進行修改。因此本發明之權利保護範圍,應如後述之申請專利範圍所列。
2:電子封裝件
2a:第一電子模組
2b:第二電子模組
2c:封裝模組
20:第一承載結構
20a:第一側
20b:第二側
21:第一電子元件
22:第二電子元件
23,33:佈線結構
24:第一包覆層
25:第二包覆層
26:第二承載結構
27:第三電子元件
28:封裝層
29a:第一導電元件
29b:第二導電元件
290,310,320:銲錫材料
291:銅凸塊
30:第三承載結構
31a,31b:第一導電結構
311:電性接觸墊
32a,32b:第二導電結構
321:導電柱
33a,33b:第三導電結構
331:第一導電柱
332:第二導電柱
9:電路板
L1:第一層間
L2:第二層間
L3:第三層間
Claims (12)
- 一種電子封裝件,係包括:第一電子模組,係具有相對之第一側與第二側;第二電子模組,係堆疊於該第一電子模組之第一側上,其中,該第一電子模組之第一側與該第二電子模組之間的區域係定義為第一層間,且該第一電子模組之第二側向外之區域係定義為第二層間;包含銲錫材料之複數第一導電結構,係配置於該第一層間中;以及包含銲錫材料之複數第二導電結構,係配置於該第一層間中,其中,該複數第一導電結構之銲錫量係多於該複數第二導電結構之銲錫量;各該第二導電結構係包含導電柱及形成於該導電柱端面上之銲錫材料。
- 如請求項1所述之電子封裝件,其中,各該第一導電結構係為銲錫球。
- 如請求項1所述之電子封裝件,其中,該複數第一導電結構與複數第二導電結構係依據該第一層間中之應力大小進行配置,以令該複數第一導電結構於該第一層間所分佈之位置上之應力係大於該複數第二導電結構於該第一層間所分佈之位置上之應力。
- 如請求項1所述之電子封裝件,其中,該複數第一導電結構係環繞圍住該複數第二導電結構。
- 如請求項1所述之電子封裝件,其中,該複數第一導電結構復配置於該第二層間中,且該第一層間的複數第一導電結構之數量係少於該第二層間的複數第一導電結構之數量。
- 如請求項1所述之電子封裝件,其中,該複數第二導電結構復配置於該第二層間中,且該第一層間的複數第二導電結構之數量係多於該第二層間的複數第二導電結構之數量。
- 如請求項1所述之電子封裝件,復包括配置於該第一層間中之複數第三導電結構,其無銲錫量。
- 如請求項7所述之電子封裝件,其中,各該第三導電結構係包含相互堆疊之第一導電柱與第二導電柱,以令該第一導電柱立設於該第一電子模組上,且該第二導電柱立設於該第二電子模組上,使該第一導電柱之端面與該第二導電柱之端面相互接觸於該第一層間中。
- 如請求項7所述之電子封裝件,其中,該複數第一導電結構、該複數第二導電結構與該複數第三導電結構係依據該第一層間中之應力大小進行配置,以令該複數第一導電結構於該第一層間所分佈之位置上之應力係大於該複數第二導電結構於該第一層間所分佈之位置上之應力,且該複數第二導電結構於該第一層間所分佈之位置上之應力係大於該複數第三導電結構於該第一層間所分佈之位置上之應力。
- 如請求項7所述之電子封裝件,其中,該複數第一導電結構、該複數第二導電結構及該複數第三導電結構係於該第一層間中以對稱方式由外向內依序排設。
- 如請求項7所述之電子封裝件,其中,該複數第二導電結構係環繞圍住該複數第三導電結構。
- 如請求項7所述之電子封裝件,其中,該複數第三導電結構復配置於該第二層間中,且該第一層間的該複數第三導電結構之數量係等於該第二層間的該複數第三導電結構之數量。
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US20110248398A1 (en) * | 2010-04-07 | 2011-10-13 | Maxim Integrated Products, Inc. | Wafer-level chip-scale package device having bump assemblies configured to mitigate failures due to stress |
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US20110248398A1 (en) * | 2010-04-07 | 2011-10-13 | Maxim Integrated Products, Inc. | Wafer-level chip-scale package device having bump assemblies configured to mitigate failures due to stress |
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