TWI740305B - 電子封裝件及其製法 - Google Patents
電子封裝件及其製法 Download PDFInfo
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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Abstract
一種電子封裝件及其製法,係提供一設有複數支撐柱之上承載結構及一設有電子元件之下承載結構,再將該上承載結構以複數支撐柱結合至該下承載結構上,之後形成封裝層於該上承載結構與該下承載結構之間,以令該封裝層包覆該些支撐柱與該電子元件,俾藉由該支撐柱取代習知銲球,以避免發生銲球橋接之問題。
Description
本發明係有關一種半導體封裝製程,尤指一種堆疊形式之電子封裝件及其製法。
隨著半導體封裝技術的演進,半導體裝置(Semiconductor device)已開發出不同的封裝型態,其中,為提升電性功能及節省封裝空間,業界遂發展出堆疊複數封裝結構以形成封裝堆疊結構(Package on Package,簡稱POP)之封裝型態,此種封裝型態能發揮系統封裝(SiP)異質整合特性,可將不同功用之電子元件,例如:記憶體、中央處理器、繪圖處理器、影像應用處理器等,藉由堆疊設計達到系統的整合,而適用於各種輕薄短小型電子產品。
第1圖係為習知封裝堆疊結構1之剖面示意圖。如第1圖所示,該封裝堆疊結構1係包含有第一半導體元件10、第一封裝基板11、第二封裝基板12、複數銲球13、第二半導體元件14以及封裝膠體15。該第一封裝基板11具有核心層110與複數線路層111,且該第二封裝基板12具有核心層120與複數線路層121。該第一半導體元件10以覆晶方式設於
該第一封裝基板11上,且該第二半導體元件14亦以覆晶方式設於該第二封裝基板12上。該些銲球13係用以連結且電性耦接該第一封裝基板11與該第二封裝基板12。該封裝膠體15係包覆該些銲球13與該第一半導體元件10。可選擇性地,形成底膠16於該第一半導體元件10與該第一封裝基板11之間。
惟,習知封裝堆疊結構1之製法中,由於第一封裝基板11與第二封裝基板12間係以該銲球13作為支撐與電性連接之元件,且該銲球13具有一定的寬度,故隨著電子產品的接點(即I/O)數量愈來愈多,在封裝件的尺寸大小不變的情況下,各該銲球13間的間距需縮小,致使容易發生橋接(bridge)的現象,而造成產品良率過低及可靠度不佳等問題,亦即,該銲球13無法達到細間距(fine pitch)的需求。
再者,該銲球13係以植球或網印(screen printing)的方式形成於該第一封裝基板11上,且於回銲後之體積及高度之公差大,不僅接點容易產生缺陷,導致電性連接品質不良,而且該銲球13所排列成之柵狀陣列(grid array)容易產生共面性(coplanarity)不良,導致接點應力(stress)不平衡而容易造成該第一封裝基板11與第二封裝基板12之間呈傾斜接置,甚至產生接點偏移之問題。
因此,如何克服上述習知技術之種種問題,實已成為目前業界亟待克服之難題。
鑑於上述習知技術之缺失,本發明提供一種電子封裝件,係
包括:下承載結構;上承載結構,係設有複數導電柱;複數支撐柱,係設於該複數導電柱上,以令該上承載結構藉由該複數支撐柱結合該下承載結構;封裝層,係設於該下承載結構上以包覆該複數支撐柱;以及包覆層,係形成於該封裝層與該上承載結構之間,以包覆該複數導電柱。
本發明亦提供一種電子封裝件之製法,係包括:提供一設有複數導電柱之上承載結構及一下承載結構,其中,對應該複數導電柱上分別形成有複數支撐柱,並於該上承載結構形成有一包覆該複數導電柱之包覆層,且令該複數支撐柱凸出該包覆層;將該上承載結構以該支撐柱結合至該下承載結構上;以及形成封裝層於該包覆層與該下承載結構之間,以令該封裝層包覆該複數支撐柱。
前述之製法中,該支撐柱的製程係包含:提供一導電架,其包含一板體及分離設於該板體上之該複數導電柱;將該導電架以該複數導電柱設於該上承載結構上;於該上承載結構與該板體之間形成該包覆層以包覆該複數導電柱;以及移除該板體之部分材質,使該板體之保留材質作為複數該支撐柱。進一步,於形成該支撐柱之前,形成阻層於該板體上,以移除未為該阻層所覆蓋之該板體之部分材質。
前述之製法中,該封裝層係採用射出成形或點膠方式形成。
前述之電子封裝件及其製法中,復包括設置電子元件於該下承載結構上,且該封裝層復包覆該電子元件。
前述之電子封裝件及其製法中,該支撐柱與該導電柱係一體成形。
前述之電子封裝件及其製法中,該封裝層與該包覆層的材質
係相同或不相同。
前述之電子封裝件及其製法中,復包括設置電子元件於該上承載結構上。
前述之電子封裝件及其製法中,該上承載結構係配置有第一接地層,且該下承載結構係配置有第二接地層,以令該第一接地層與該第二接地層電性連接該導電柱與支撐柱。
由上可知,本發明之電子封裝件及其製法,主要藉由該導電柱與支撐柱所構成之柱體取代習知銲錫球,以依需求調整各該柱體之間的間距,故相較於習知技術,該些柱體之間不會發生橋接之問題,因而能有效提高產品良率及可靠度,以達到細間距的需求。
1‧‧‧封裝堆疊結構
10‧‧‧第一半導體元件
11‧‧‧第一封裝基板
110,120‧‧‧核心層
111,121‧‧‧線路層
12‧‧‧第二封裝基板
13‧‧‧銲球
14‧‧‧第二半導體元件
15‧‧‧封裝膠體
16‧‧‧底膠
2‧‧‧電子封裝件
2a‧‧‧第一封裝模組
2b‧‧‧第二封裝模組
20‧‧‧導電架
20’‧‧‧板體
20”‧‧‧柱體
20a‧‧‧第一表面
20b‧‧‧第二表面
200‧‧‧支撐柱
201‧‧‧導電柱
21‧‧‧上承載結構
210‧‧‧線路層
211‧‧‧絕緣層
212‧‧‧電性接觸墊
22‧‧‧包覆層
23‧‧‧下承載結構
230‧‧‧介電層
231‧‧‧佈線層
232‧‧‧電性連接墊
233‧‧‧銲錫材
24,34‧‧‧電子元件
24a‧‧‧作用面
24b‧‧‧非作用面
240‧‧‧電極墊
25‧‧‧導電凸塊
26‧‧‧封裝層
27‧‧‧導電元件
29‧‧‧阻層
290‧‧‧開口區
3a‧‧‧屏蔽結構
310‧‧‧第一接地層
330‧‧‧第二接地層
S,L‧‧‧切割路徑
第1圖係為習知封裝堆疊結構之剖面示意圖。
第2A至2F圖係為本發明之電子封裝件之製法之剖視示意圖。
第3圖係為本發明之電子封裝件之另一實施例之剖視示意圖。
以下藉由特定的具體實施例說明本發明之實施方式,熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知,本說明書所附圖式所繪示之結構、比例、大小等,均僅用以配合說明書所揭示之內容,以供熟悉此技藝之人士之瞭解與閱讀,並非用以限定本發明可實施之限定條件,故不具技術上之實質意義,任何結構之修飾、比例關係之改變或大小之調整,在不影響本發明所能產生之功效及所能達成之目的下,均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時,本說明書中所引用之如“第一”、“第二”、“上”、及“一”等之用語,亦僅為便於敘述之明瞭,而非用以限定本發明可實施之範圍,其相對關係之改變或調整,在無實質變更技術內容下,當亦視為本發明可實施之範疇。
請參閱第2A至2F圖,係為本發明之電子封裝件2之製法之剖視示意圖。
如第2A圖所示,將一導電架20接合至少一上承載結構21上。
於本實施例中,該導電架20包含一板體20’及複數分離設於該板體20’上之導電柱201,其中,該導電柱201之周面係相對兩端面呈內凹弧形,且該板體20’與導電柱201係一體成形。具體地,以蝕刻、雷射或其它方式移除一如銅材之金屬板之部分材質,以在該板體20’上形成複數相互間隔之導電柱201。
再者,該板體20’係具有相對之第一表面20a與第二表面20b,其中,於該第一表面20a上形成該些導電柱201,而於該第二表面20b上形成一圖案化阻層29,使該阻層29具有複數開口區290,以令該板體20’之部分第二表面20b外露於該開口區290。
又,該上承載結構21係例如具有核心層與線路部之已切單封裝基板(substrate)或具有線路部之無核心層(coreless)式之已切單封裝基板,其線路部具有至少一絕緣層211與設於該絕緣層211上之線路層210,該線路層210例如為扇出型(fan out)重佈線路層(redistribution layer,簡稱RDL),且最外側之線路層210具有複數電性接觸墊212,以結合該導電柱201之端面,使該導電柱201電性連接該線路層210。
另外,形成該線路層210之材質係例如為銅,且形成該絕緣層211之材質係例如為聚對二唑苯(Polybenzoxazole,簡稱PBO)、聚醯亞胺(Polyimide,簡稱PI)、預浸材(Prepreg,簡稱PP)等之介電材。應可理解地,該上承載結構21亦可為其它可供承載如晶片等電子元件之承載單元,例如導線架(lead frame)或矽中介板(silicon interposer),並不限於上述。
如第2B圖所示,形成一包覆層22於該板體20’之第一表面20a與該上承載結構21之間,以令該包覆層22包覆該些導電柱201及該上承載結構21之側面。
於本實施例中,該包覆層22係為絕緣材,如聚醯亞胺(polyimide,簡稱PI)、乾膜(dry film)、如環氧樹脂(epoxy)之封裝膠體或封裝材(molding compound)。例如,該包覆層22之製程可選擇液態封膠(liquid compound)、噴塗(injection)、壓合(lamination)或模壓(compression molding)等方式形成。
如第2C圖所示,圖案化該板體20’,以形成複數支撐柱200。之後,移除該阻層29,以形成第一封裝模組2a,其包含該上承載結構21、
支撐柱200、導電柱201及包覆層22。
於本實施例中,以蝕刻方式移除外露於該阻層29之開口區290中之板體20’之材質,保留該阻層29遮蓋之板體20’之材質,供作為該些支撐柱200,使該支撐柱200對應位於該導電柱201之端面上。例如,該阻層29係作為蝕刻止蝕層,其為金屬材或導電材,如Ni/Au、Ni/Pd/Au或其它適當材質。
再者,該支撐柱200之外觀構造類似該導電柱201之外觀構造。例如,該支撐柱200之周面係相對其兩端面呈內凹弧形,使該支撐柱200之兩端面之寬度大於其周面之寬度。
如第2D圖所示,沿如第2C圖所示之切割路徑L進行切單製程,以獲取複數第一封裝模組2a,再將該複數第一封裝模組2a以其支撐柱200設於一第二封裝模組2b上。
於本實施例中,該第二封裝模組2b係包含一用以結合該支撐柱200之下承載結構23及至少一設於該下承載結構23上之電子元件24。
再者,該下承載結構23係為整版面(panel)形式之具有核心層或無核心層之線路結構,如封裝基板,其具有如扇出型(fan out)重佈線路層(RDL)之線路配置。例如,該下承載結構23係具有至少一介電層230、及設於該介電層230上之佈線層231。具體地,形成該介電層230之材質如預浸材(prepreg)、封裝膠體(molding compound)或感光型介電材,但不限於此,且該佈線層231係具有複數電性連接墊232,以利用銲錫材233透過該阻層29結合該支撐柱200,使該導電柱201電性連接該佈線層
231。應可理解地,該下承載結構23亦可為其它承載晶片之板材,如導線架、晶圓(wafer)、矽中介板、或其它具有金屬佈線(routing)之載板等,並不限於上述。
又,該電子元件24係為主動元件、被動元件或其二者組合,其中,該主動元件係例如半導體晶片,且該被動元件係例如電阻、電容及電感。例如,該電子元件24係為半導體晶片,其具有相對之作用面24a與非作用面24b,該作用面24a具有複數電極墊240,且該電子元件24以覆晶方式藉由其電極墊240透過複數如銲錫材之導電凸塊25設於該下承載結構23上並電性連接該佈線層231。或者,該電子元件24可藉由複數銲線(圖略)以打線方式電性連接該下承載結構23;亦或,該電子元件24可直接接觸該下承載結構23之線路,如該電子元件24嵌埋於該下承載結構23中。應可理解地,有關該電子元件24電性連接該下承載結構23之方式繁多,並不限於上述。
如第2E圖所示,形成一封裝層26於該下承載結構23與該包覆層22之間,以令該封裝層26包覆該些支撐柱200與該電子元件24(甚至包覆該些導電凸塊25;或者,該些導電凸塊25亦可先被底膠(underfill)(圖未示)包覆)。
於本實施例中,該封裝層26係為絕緣材,如聚醯亞胺(polyimide,簡稱PI)、乾膜(dry film)、如環氧樹脂(epoxy)之封裝膠體或封裝材(molding compound),其可用射出成形或點膠方式形成。應可理解地,形成該封裝層26之材質可相同或不相同該包覆層22之材質。
如第2F圖所示,沿如第2E圖所示之切割路徑S進行切單
製程,以獲取複數電子封裝件2。
於本實施例中,該下承載結構23下側進行植球製程以形成複數如銲球之導電元件27,俾供於後續製程中,該電子封裝件2可藉其導電元件27設於一電路板(圖略)上。
再者,該上承載結構21上側可接置另一如半導體晶片之電子元件34或其它電子裝置,使該電子元件34電性連接該上承載結構21。例如,該電子元件34係為主動元件、被動元件或其二者組合,其中,該主動元件係例如半導體晶片,且該被動元件係例如電阻、電容及電感。應可理解地,有關該電子元件34電性連接該上承載結構21之方式繁多,並無特別限制。
又,如第3圖所示,該上承載結構21可配置有第一接地層310,且該下承載結構23亦可配置有第二接地層330,以令該第一接地層310與該第二接地層330電性連接該些導電柱201與支撐柱200而形成一屏蔽結構3a,故藉由該屏蔽結構3a之設計,以避免該電子元件24受外界的電磁干擾(Electromagnetic Interference,簡稱EMI)。
本發明之製法係主要藉由該導電柱201與支撐柱200所構成之一體成形之柱體20”取代習知銲錫球,因而可依需求調整各該柱體20”之間的間距,故相較於習知技術,該些柱體20”之間不易發生橋接之問題,因而能有效提高產品良率及可靠度,以達到細間距(fine pitch)的需求。
再者,由於該導電架20的材料及製作成本低,故可有效降低該電子封裝件2之整體製程之成本
又,藉由該第一封裝模組2a與第二封裝模組2b分開製作,
以獨立進行功能測試作業,故能於形成該封裝層26之前,先檢測出該電子元件24之良率,以提升該電子封裝件2之良率。
另外,該第一封裝模組2a藉由該包覆層22之設計,以產生強化結構(stiffener)的效果,避免該第一封裝模組2a發生翹曲(warpage),且可依據該第二封裝模組2b之翹曲狀態即時調整該包覆層22之材料及參數(如形成該包覆層22後之warpage moire參數)。應可理解地,可依據該第一封裝模組2a與第二封裝模組2b堆疊後之翹曲狀態,調整該封裝層26之材料及參數。
本發明復提供一種電子封裝件2,係包括:上承載結構21、複數支撐柱200、一包覆層22、下承載結構23以及一封裝層26。
所述之上承載結構21係設有複數導電柱201。
所述之支撐柱200係設於該複數導電柱201上,以令該上承載結構21藉由該複數支撐柱200結合該下承載結構23。
所述之封裝層26係設於該下承載結構23上以包覆該複數支撐柱200。
所述之包覆層22係形成於該封裝層26與該上承載結構21之間,以包覆該複數導電柱201。
於一實施例中,所述之電子封裝件2復包括一設於該下承載結構23上之電子元件24,且該封裝層26復包覆該電子元件24。
於一實施例中,該支撐柱200與該導電柱201係一體成形。
於一實施例中,該封裝層26與該包覆層22的材質係相同或不相同。
於一實施例中,所述之電子封裝件2復包括至少一設於該上承載結構21上之電子元件34。
於一實施例中,該上承載結構21係配置有一第一接地層310,且該下承載結構23係配置有一第二接地層330,以令該第一接地層310與該第二接地層330電性連接該導電柱201與支撐柱200而形成一屏蔽結構3a。
綜上所述,本發明之電子封裝件及其製法,主要藉由該導電柱與支撐柱所構成之柱體,以依需求調整各該支撐柱之間的間距,而不易發生橋接之問題,且能有效提高產品良率及可靠度,以達到細間距的需求。
上述實施例係用以例示性說明本發明之原理及其功效,而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下,對上述實施例進行修改。因此本發明之權利保護範圍,應如後述之申請專利範圍所列。
2‧‧‧電子封裝件
20”‧‧‧柱體
200‧‧‧支撐柱
201‧‧‧導電柱
21‧‧‧上承載結構
22‧‧‧包覆層
23‧‧‧下承載結構
24,34‧‧‧電子元件
26‧‧‧封裝層
27‧‧‧導電元件
29‧‧‧阻層
Claims (15)
- 一種電子封裝件,係包括:下承載結構;上承載結構,係設有複數導電柱;複數支撐柱,係設於該複數導電柱上,以令該上承載結構藉由該複數支撐柱結合該下承載結構,其中,該支撐柱與該導電柱係一體成形;封裝層,係設於該下承載結構上以包覆該複數支撐柱;以及包覆層,係形成於該封裝層與該上承載結構之間,以包覆該複數導電柱。
- 如申請專利範圍第1項所述之電子封裝件,復包括設於該下承載結構上之電子元件,且該封裝層復包覆該電子元件。
- 如申請專利範圍第1項所述之電子封裝件,其中,該封裝層與該包覆層的材質係相同。
- 如申請專利範圍第1項所述之電子封裝件,其中,該封裝層與該包覆層的材質係不相同。
- 如申請專利範圍第1項所述之電子封裝件,復包括設於該上承載結構上之電子元件。
- 如申請專利範圍第1項所述之電子封裝件,其中,該上承載結構係配置有第一接地層,且該下承載結構係配置有第二接地層,以令該第一接地層與該第二接地層電性連接該導電柱與支撐柱。
- 一種電子封裝件之製法,係包括:提供一設有複數導電柱之上承載結構及一下承載結構,其中,對應該複數導電柱上分別形成有複數支撐柱,該支撐柱與該導電柱係一體成形, 並於該上承載結構形成有一包覆該複數導電柱之包覆層,且令該複數支撐柱凸出該包覆層;將該上承載結構以該支撐柱結合至該下承載結構上;以及形成封裝層於該包覆層與該下承載結構之間,以令該封裝層包覆該複數支撐柱。
- 如申請專利範圍第7項所述之電子封裝件之製法,其中,該支撐柱的製程係包含:提供一導電架,其包含一板體及分離設於該板體上之該複數導電柱;將該導電架以該複數導電柱設於該上承載結構上;於該上承載結構與該板體之間形成該包覆層以包覆該複數導電柱;以及移除該板體之部分材質,使該板體之保留材質作為該複數支撐柱。
- 如申請專利範圍第8項所述之電子封裝件之製法,復包括於形成該支撐柱之前,形成阻層於該板體上,以移除未為該阻層所覆蓋之該板體之部分材質。
- 如申請專利範圍第7項所述之電子封裝件之製法,復包括設置電子元件於該下承載結構上,且該封裝層復包覆該電子元件。
- 如申請專利範圍第7項所述之電子封裝件之製法,其中,該封裝層與該包覆層的材質係相同。
- 如申請專利範圍第7項所述之電子封裝件之製法,其中,該封裝層與該包覆層的材質係不相同。
- 如申請專利範圍第7項所述之電子封裝件之製法,復包括設置電子元件於該上承載結構上。
- 如申請專利範圍第7項所述之電子封裝件之製法,其中,該上承載結構係配置有第一接地層,且該下承載結構係配置有第二接地層,以令該第一接地層與該第二接地層電性連接該導電柱與支撐柱。
- 如申請專利範圍第7項所述之電子封裝件之製法,其中,該封裝層係採用射出成形或點膠方式形成。
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US20170271272A1 (en) * | 2016-03-15 | 2017-09-21 | Samsung Electro-Mechanics Co., Ltd. | Fan-out semiconductor package and method of manufacturing same |
US20180096941A1 (en) * | 2016-09-30 | 2018-04-05 | Samsung Electro-Mechanics Co., Ltd. | Fan-out semiconductor package |
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WO2019209394A1 (en) * | 2018-04-23 | 2019-10-31 | Sandisk Technologies Llc | Three-dimensional memory device containing self-aligned interlocking bonded structure and method of making the same |
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US20170271272A1 (en) * | 2016-03-15 | 2017-09-21 | Samsung Electro-Mechanics Co., Ltd. | Fan-out semiconductor package and method of manufacturing same |
US20180096941A1 (en) * | 2016-09-30 | 2018-04-05 | Samsung Electro-Mechanics Co., Ltd. | Fan-out semiconductor package |
TW201926605A (zh) * | 2017-11-22 | 2019-07-01 | 矽品精密工業股份有限公司 | 電子封裝件及其製法 |
WO2019209394A1 (en) * | 2018-04-23 | 2019-10-31 | Sandisk Technologies Llc | Three-dimensional memory device containing self-aligned interlocking bonded structure and method of making the same |
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