TWI830830B - 訊號發送及接收裝置、其操作方法、記憶體元件以及其操作方法 - Google Patents
訊號發送及接收裝置、其操作方法、記憶體元件以及其操作方法 Download PDFInfo
- Publication number
- TWI830830B TWI830830B TW108144444A TW108144444A TWI830830B TW I830830 B TWI830830 B TW I830830B TW 108144444 A TW108144444 A TW 108144444A TW 108144444 A TW108144444 A TW 108144444A TW I830830 B TWI830830 B TW I830830B
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- Taiwan
- Prior art keywords
- die
- circuit
- signal
- pin
- terminal
- Prior art date
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- 238000000034 method Methods 0.000 title claims description 32
- 230000015654 memory Effects 0.000 claims description 161
- 230000001360 synchronised effect Effects 0.000 claims description 6
- 238000004891 communication Methods 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 19
- 238000012545 processing Methods 0.000 description 8
- 230000015556 catabolic process Effects 0.000 description 5
- 238000006731 degradation reaction Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- 230000004044 response Effects 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 102100035964 Gastrokine-2 Human genes 0.000 description 1
- 101001075215 Homo sapiens Gastrokine-2 Proteins 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 238000012805 post-processing Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
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- Memory System (AREA)
- Logic Circuits (AREA)
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2018-0167576 | 2018-12-21 | ||
KR20180167576 | 2018-12-21 | ||
KR10-2019-0049826 | 2019-04-29 | ||
KR1020190049826A KR20200078294A (ko) | 2018-12-21 | 2019-04-29 | 신호를 송수신 하기 위한 장치, 그것의 동작 방법, 메모리 장치 및 그것의 동작 방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
TW202030993A TW202030993A (zh) | 2020-08-16 |
TWI830830B true TWI830830B (zh) | 2024-02-01 |
Family
ID=71601649
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW108144444A TWI830830B (zh) | 2018-12-21 | 2019-12-05 | 訊號發送及接收裝置、其操作方法、記憶體元件以及其操作方法 |
Country Status (2)
Country | Link |
---|---|
KR (1) | KR20200078294A (ko) |
TW (1) | TWI830830B (ko) |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20100109704A1 (en) * | 2008-10-30 | 2010-05-06 | Dennis Carr | Differential on-line termination |
US20130002291A1 (en) * | 2011-06-30 | 2013-01-03 | Joon-Young Park | Semiconductor memory device, memory controller and memory system having on die termination and on die termination controlling method |
TW201709065A (zh) * | 2015-05-29 | 2017-03-01 | 英特爾公司 | 記憶體裝置特定之自我更新進入與退出技術 |
US20170288634A1 (en) * | 2016-03-31 | 2017-10-05 | Dae-Woon Kang | Nonvolatile memory device, memory system including the same and method of operating the same |
US20180026634A1 (en) * | 2016-07-21 | 2018-01-25 | Samsung Electronics Co., Ltd. | On-die termination circuit, a memory device including the on-die termination circuit, and a memory system including the memory device |
US20180039588A1 (en) * | 2016-08-04 | 2018-02-08 | Samsung Electronics Co ., Ltd. | Memory system including on-die termination and method of controlling on-die termination thereof |
-
2019
- 2019-04-29 KR KR1020190049826A patent/KR20200078294A/ko not_active Application Discontinuation
- 2019-12-05 TW TW108144444A patent/TWI830830B/zh active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20100109704A1 (en) * | 2008-10-30 | 2010-05-06 | Dennis Carr | Differential on-line termination |
US20130002291A1 (en) * | 2011-06-30 | 2013-01-03 | Joon-Young Park | Semiconductor memory device, memory controller and memory system having on die termination and on die termination controlling method |
TW201709065A (zh) * | 2015-05-29 | 2017-03-01 | 英特爾公司 | 記憶體裝置特定之自我更新進入與退出技術 |
US20170288634A1 (en) * | 2016-03-31 | 2017-10-05 | Dae-Woon Kang | Nonvolatile memory device, memory system including the same and method of operating the same |
US20180026634A1 (en) * | 2016-07-21 | 2018-01-25 | Samsung Electronics Co., Ltd. | On-die termination circuit, a memory device including the on-die termination circuit, and a memory system including the memory device |
US20180039588A1 (en) * | 2016-08-04 | 2018-02-08 | Samsung Electronics Co ., Ltd. | Memory system including on-die termination and method of controlling on-die termination thereof |
Also Published As
Publication number | Publication date |
---|---|
KR20200078294A (ko) | 2020-07-01 |
TW202030993A (zh) | 2020-08-16 |
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