TWI827019B - 電子封裝件及其製法 - Google Patents

電子封裝件及其製法 Download PDF

Info

Publication number
TWI827019B
TWI827019B TW111115641A TW111115641A TWI827019B TW I827019 B TWI827019 B TW I827019B TW 111115641 A TW111115641 A TW 111115641A TW 111115641 A TW111115641 A TW 111115641A TW I827019 B TWI827019 B TW I827019B
Authority
TW
Taiwan
Prior art keywords
electronic component
electronic
support member
spacer
package
Prior art date
Application number
TW111115641A
Other languages
English (en)
Other versions
TW202343734A (zh
Inventor
葉昱成
林怡馨
陳紹華
紀伊真
蘇文偉
陳國宜
Original Assignee
矽品精密工業股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 矽品精密工業股份有限公司 filed Critical 矽品精密工業股份有限公司
Priority to TW111115641A priority Critical patent/TWI827019B/zh
Priority to CN202210475102.3A priority patent/CN116995033A/zh
Priority to US17/845,302 priority patent/US20230343751A1/en
Publication of TW202343734A publication Critical patent/TW202343734A/zh
Application granted granted Critical
Publication of TWI827019B publication Critical patent/TWI827019B/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
    • H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
    • H01L2225/06537—Electromagnetic shielding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06575—Auxiliary carrier between devices, the carrier having no electrical connection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
    • H01L2225/06586—Housing with external bump or bump-like connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06589—Thermal management, e.g. cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Dispersion Chemistry (AREA)
  • Wire Bonding (AREA)

Abstract

一種電子封裝件，係於承載結構上設置第一電子元件及至少一支撐件，再將間隔件設於該第一電子元件上，以將第二電子元件設於該至少一支撐件與該間隔件上，避免該第二電子元件於進行打線製程時發生傾倒問題。

Description

電子封裝件及其製法
本發明係有關一種半導體封裝製程，尤指一種具有多晶片堆疊結構之電子封裝件及其製法。
隨著半導體技術的演進，半導體產品已開發出不同封裝產品型態。早期多晶片封裝結構係為採用並排式(side-by-side)多晶片封裝結構，其係將兩個以上之晶片彼此並排地安裝於一共同基板之主要安裝面。多晶片與共同基板上導電線路之間的連接一般係藉由導線銲接方式(wire bonding)達成。然而並排式多晶片封裝構造之缺點為封裝成本太高及封裝結構尺寸太大，因該共同基板之面積會隨著晶片數目的增加而增加。
為解決上述習知問題，近年來為使用垂直式之堆疊方法來安裝所增加的晶片，其堆疊的方式按照其晶片之設計，打線製程各有不同。
如圖1所示，習知半導體封裝件1係將一第一半導體晶片11安裝於一封裝基板10上，再將第二半導體晶片12藉由間隔件13堆疊於該第一半導體晶片11上，並以打線方式藉由複數金屬線110,120將該第一半導體晶片11及第二半導體晶片12電性連接至該封裝基板10。
一般而言，該第二半導體晶片12之平面尺寸係大於該第一半導體晶片11之平面尺寸，故該第二半導體晶片12需相對該第一半導體晶片11之位置偏移放置，使得該第二半導體晶片12凸出該第一半導體晶片11，以利於該第二半導體晶片12進行打線製程，即該第二半導體晶片12上之金屬線120之打線路徑能避開該第一半導體晶片11上之已佈設之金屬線110。
惟，該第二半導體晶片12若凸出該第一半導體晶片11過多尺寸，則會發生傾斜(如圖1所示之傾倒方向N)，導致無法進行後續製程(如該第二半導體晶片12之打線製程)，甚至該第二半導體晶片12會撞擊該封裝基板10而損壞。
因此，如何克服上述習知技術的問題，實已成目前亟欲解決的課題。
鑑於上述習知技術之種種缺失，本發明係提供一種電子封裝件，係包括：承載結構，係具有相對之第一側與第二側；第一電子元件，係設於該承載結構之第一側上且電性連接該承載結構；至少一支撐件，係設於該承載結構之第一側上；間隔件，係設於該第一電子元件上；以及第二電子元件，係設於該至少一支撐件與該間隔件上且電性連接該承載結構，其中，該第二電子元件之平面尺寸係大於該第一電子元件之平面尺寸。
本發明復提供一種電子封裝件之製法，係包括：提供一承載結構，其具有相對之第一側與第二側；將第一電子元件與至少一支撐件設於該承載結構之第一側上，且令該第一電子元件係電性連接該承載結構； 將間隔件設於該第一電子元件上；以及將第二電子元件設於該至少一支撐件與間隔件上，且令該第二電子元件電性連接該承載結構，其中，該第二電子元件之平面尺寸係大於該第一電子元件之平面尺寸。
前述之電子封裝件及其製法中，該第一電子元件係藉由複數第一銲線電性連接該承載結構。
前述之電子封裝件及其製法中，該第二電子元件係藉由複數第二銲線電性連接該承載結構。
前述之電子封裝件及其製法中，該間隔件之平面尺寸係小於該第一電子元件之平面尺寸。
前述之電子封裝件及其製法中，該支撐件係包含半導體材或金屬材。
前述之電子封裝件及其製法中，該支撐件係為虛晶片。
前述之電子封裝件及其製法中，該支撐件之熱膨脹係數與該第一電子元件之熱膨脹係數屬於同一等級。
前述之電子封裝件及其製法中，復包括形成封裝層於該承載結構上，以令該封裝層包覆該第一電子元件與第二電子元件、間隔件及支撐件。
前述之電子封裝件及其製法中，復包括形成複數導電元件於該承載結構之第二側上，以令該複數導電元件電性連接該承載結構。
由上可知，本發明之電子封裝件及其製法中，主要藉由該支撐件與該間隔件一同支撐該第二電子元件，故相較於習知技術，該第二電子元件於進行打線製程時不會傾倒，因而可順利進行打線製程，且可避免該第二電子元件碰撞該承載結構而造成碎裂之問題。
1:半導體封裝件
10:封裝基板
11:第一半導體晶片
12:第二半導體晶片
13,23:間隔件
110,120:金屬線
2:電子封裝件
20:承載結構
20a:第一側
20b:第二側
201,202:電性接觸墊
21:第一電子元件
21a,22a:作用面
21b,22b:非作用面
21c:側面
210:第一銲線
211,221:電極墊
22,42:第二電子元件
220:第二銲線
24,34a,34b,34c:支撐件
25:封裝層
26:導電元件
A:凸出部分
P1,P2,P3:平面尺寸
h,h1,h2:高度
N:傾倒方向
圖1係為習知半導體封裝件之側視示意圖。
圖2A至圖2D係為本發明之電子封裝件之製法之側視示意圖。
圖2A-1至圖2C-1係為圖2A至圖2C之上視示意圖。
圖3A、圖3B及圖3C係為圖2A-1之其它不同態樣之上視示意圖。
圖4係為圖2C-1之另一態樣之上視示意圖。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如「上」、「第一」、「第二」及「一」等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
圖2A至圖2C係為本發明之電子封裝件2之製法的剖面示意圖。
如圖2A所示，提供一承載結構20，其具有相對之第一側20a與第二側20b，再將至少一第一電子元件21與至少一支撐件24設於該承載結構20之第一側20a上(圖2A-1係顯示設置有兩個支撐件24)，以令該第一電子元件21電性連接該承載結構20。
於本實施例中，該承載結構20可為具有核心層與線路結構之封裝基板(substrate)或無核心層(coreless)之線路構造，且其構成係於介電材上形成複數線路層，如線路重佈層(redistribution layer，簡稱RDL)，且於最外層之線路層具有複數電性接觸墊201,202。然而，於其它實施例中，該承載結構20亦可為具有複數導電矽穿孔(Through-silicon via，簡稱TSV)之半導體基板，以作為矽中介板(Through Silicon interposer，簡稱TSI)。因此，該承載結構20可為任何其它可供承載如晶片等電子元件之承載單元，如導線架(lead frame)，但並不限於上述。
再者，該第一電子元件21係為主動元件、被動元件或其二者組合，且該主動元件係例如半導體晶片，而該被動元件係例如電阻、電容及電感。於本實施例中，該第一電子元件21係為矩形半導體晶片，其具有相對之作用面21a與非作用面21b，該第一電子元件21係以其非作用面21b藉由一結合層(圖略)黏固於該承載結構20上，而該作用面21a具有複數電極墊211，如圖2A-1所示，以藉由打線方式將複數第一銲線210電性連接該電極墊211與該電性接觸墊201。
又，該支撐件24係為半導體材(如矽)之塊體，如柱狀或牆狀，其未電性連接該承載結構20及該第一電子元件21，並與該第一電子元件21間隔排設。例如，該支撐件24係為虛晶片(dummy die)或玻璃片。 或者，該支撐件24可為金屬塊體，其熱膨脹係數(coefficient of thermal expansion，簡稱CTE)接近該第一電子元件21之熱膨脹係數，使該支撐件24之熱膨脹係數與該第一電子元件21之熱膨脹係數屬於同一等級。
另外，該支撐件24之高度h係大於該第一電子元件21之高度h1。
如圖2B所示，將至少一間隔件23設於該第一電子元件21之作用面21a上。
於本實施例中，該間隔件23可為緩衝晶片(buffer die)、屏蔽物、散熱片或絕緣體，甚至功能性晶片，且該支撐件24之高度h係等於該第一電子元件21之高度h1與該間隔件23之高度h2之總和。
再者，該間隔件23係為矩形體，如圖2B-1所示，其平面尺寸P3(或底面積)係小於該第一電子元件21之平面尺寸P1(或該作用面21a之面積)，以避免該間隔件23干涉該第一銲線210之佈設位置。或者，該間隔件23亦可為結合膜，其利用膠膜包線(Film over Wire，簡稱FOW)之方式形成於全部該作用面21a上，以包覆該第一銲線210之局部線段。
應可理解地，有關該間隔件23之種類繁多，只要能於其上堆疊元件即可，並無特別限制。
如圖2C所示，將至少一第二電子元件22設於該間隔件23與該支撐件24上，使該第二電子元件22完全遮蓋該第一電子元件21，且該支撐件24未電性連接該第二電子元件22。
於本實施例中，該第二電子元件22係為主動元件、被動元件或其二者組合，且該主動元件係例如半導體晶片，而該被動元件係例如電阻、電容及電感。例如，該第二電子元件22係為半導體晶片，其具有相對之作用面22a與非作用面22b，該第二電子元件22係以其非作用面22b設 於該間隔件23與該支撐件24上，而該作用面22a具有複數電極墊221，如圖2C-1所示，以藉由打線方式將複數第二銲線220電性連接該電極墊221與該電性接觸墊202。
再者，該第二電子元件22之平面尺寸P2係大於該第一電子元件21之平面尺寸P1，使該第二電子元件22凸伸出該第一電子元件21之側面21c，以令該第二電子元件22之凸出部分A之非作用面22b遮蓋及抵靠該支撐件24。例如，該第二電子元件22係為矩形體，以令該支撐件24係位於該第二電子元件22之凸出部分A之非作用面22b之邊緣處，如圖2C-1所示之角落處。
又，該第二電子元件22相對該第一電子元件21之位置朝一方向(如圖2C所示)偏移放置而非置中放置，使該第二電子元件22凸伸出該第一電子元件21之側面21c，以利於該第二電子元件22進行打線製程，即該第二銲線220之打線路徑能避開已佈設之第一銲線210。
另外，藉由該間隔件23之設計，使該第二電子元件22於置放時不會干涉該第一電子元件21上之第一銲線210之佈設。
如圖2D所示，形成一封裝層25於該承載結構20之第一側20a上，以包覆該第一電子元件21與第二電子元件22、間隔件23、支撐件24、第一銲線210與第二銲線220，且形成複數如銲球之導電元件26於該承載結構之第二側20b上，以令該導電元件26電性連接該承載結構20。
於本實施例中，該封裝層25係為絕緣材，如聚醯亞胺(Polyimide，簡稱PI)、乾膜(dry film)、環氧樹脂(epoxy)環氧樹脂之封裝膠體或封裝材(molding compound)，其可用壓合(lamination)或模壓(molding)之方式形成於該承載結構20上。
因此，本發明之製法主要藉由該支撐件24之配置，以支撐該第二電子元件22之凸出部分A，故相較於習知技術，該第二電子元件22於進行打線製程時不會傾倒，因而能順利進行第二銲線220之製作，且能避免該第二電子元件22碰撞該承載結構20而造成碎裂之問題。
應可理解地，該支撐件24係用以防止該第二電子元件22傾倒，故該支撐件24之數量、形狀與位置可依需求配置，如圖3A所示之三個支撐件34a、如圖3B所示之四個支撐件34b，甚至如圖3C所示之一個牆狀支撐件34c，係以穩固支撐該第二電子元件22(或該凸出部分A)為配置基礎進行調整，並無特別限制。
再者，該第二電子元件42亦可未完全遮蓋該第一電子元件21，如圖4所示之錯位狀態，但仍可藉由該支撐件24之配置，有效支撐該第二電子元件42，以防止該第二電子元件42於進行打線製程時傾倒。
本發明亦提供一種電子封裝件2，其包括：一承載結構20、一第一電子元件21、至少一支撐件24,34a,34b,34c、一間隔件23以及一第二電子元件22,42。
所述之承載結構20係具有相對之第一側20a與第二側20b。
所述之第一電子元件21係設於該承載結構20之第一側20a上且電性連接該承載結構20。
所述之支撐件24,34a,34b,34c係設於該承載結構20之第一側20a上。
所述之間隔件23係設於該第一電子元件21上。
所述之第二電子元件22,42係設於該支撐件23與間隔件24,34a,34b,34c上且電性連接該承載結構20，其中，該第二電子元件22,42之平面尺寸P2係大於該第一電子元件21之平面尺寸P1。
於一實施例中，該第一電子元件21係藉由複數第一銲線210電性連接該承載結構20。
於一實施例中，該第二電子元件22係藉由複數第二銲線220電性連接該承載結構20。
於一實施例中，該間隔件23之平面尺寸P3係小於該第一電子元件21之平面尺寸P1。
於一實施例中，該支撐件24,34a,34b,34c係包含半導體材或金屬材。
於一實施例中，該支撐件24,34a,34b,34c係為虛晶片。
於一實施例中，該支撐件24,34a,34b,34c之熱膨脹係數與該第一電子元件21之熱膨脹係數屬於同一等級。
於一實施例中，所述之電子封裝件2復包括一形成於該承載結構20上之封裝層25，其包覆該第一電子元件21與第二電子元件22,42、間隔件23及支撐件24,34a,34b,34c。
於一實施例中，所述之電子封裝件2復包括形成於該承載結構20第二側20b上之複數導電元件26，其電性連接該承載結構20。
綜上所述，本發明之電子封裝件及其製法，係藉由該支撐件支撐該第二電子元件，使該第二電子元件於進行打線製程時不會傾倒，故本發明能不僅能順利進行打線製程，且能避免該第二電子元件碰撞該承載結構而造成碎裂之問題。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
2:電子封裝件
20:承載結構
20a:第一側
20b:第二側
21:第一電子元件
210:第一銲線
22:第二電子元件
220:第二銲線
23:間隔件
24:支撐件
25:封裝層
26:導電元件

Claims (18)

  1. 一種電子封裝件，係包括：承載結構，係具有相對之第一側與第二側；第一電子元件，係設於該承載結構之第一側上且電性連接該承載結構；高於該第一電子元件之至少一支撐件，係設於該承載結構之第一側上；作為間隔件之屏蔽物或散熱片，係設於該第一電子元件上；以及第二電子元件，係同時設在高於該第一電子元件之該至少一支撐件與作為該間隔件之該屏蔽物或散熱片兩者上，且該第二電子元件電性連接該承載結構，其中，該第二電子元件之平面尺寸係大於該第一電子元件之平面尺寸，且作為該間隔件之該屏蔽物或散熱片係位在低於該至少一支撐件之該第一電子元件與高於該至少一支撐件之該第二電子元件兩者之間。
  2. 如請求項1所述之電子封裝件，其中，該第一電子元件係藉由複數第一銲線電性連接該承載結構。
  3. 如請求項1所述之電子封裝件，其中，該第二電子元件係藉由複數第二銲線電性連接該承載結構。
  4. 如請求項1所述之電子封裝件，其中，該間隔件之平面尺寸係小於該第一電子元件之平面尺寸。
  5. 如請求項1所述之電子封裝件，其中，該至少一支撐件係包含半導體材或金屬材。
  6. 如請求項1所述之電子封裝件，其中，該至少一支撐件係為虛晶片。
  7. 如請求項1所述之電子封裝件，其中，該至少一支撐件之熱膨脹係數與該第一電子元件之熱膨脹係數屬於同一等級。
  8. 如請求項1所述之電子封裝件，復包括形成於該承載結構上之封裝層，其包覆該第一電子元件、第二電子元件、間隔件及至少一支撐件。
  9. 如請求項1所述之電子封裝件，復包括形成於該承載結構第二側上之複數導電元件，其電性連接該承載結構。
  10. 一種電子封裝件之製法，係包括：提供一承載結構，其具有相對之第一側與第二側；將第一電子元件與高於該第一電子元件之至少一支撐件設於該承載結構之第一側上，且令該第一電子元件係電性連接該承載結構；將作為間隔件之屏蔽物或散熱片設於該第一電子元件上；以及將第二電子元件同時設在高於該第一電子元件之該至少一支撐件與作為該間隔件之該屏蔽物或散熱片兩者上，且令該第二電子元件電性連接該承載結構，其中，該第二電子元件之平面尺寸係大於該第一電子元件之平面尺寸，且作為該間隔件之該屏蔽物或散熱片係位在低於該至少一支撐件之該第一電子元件與高於該至少一支撐件之該第二電子元件兩者之間。
  11. 如請求項10所述之電子封裝件之製法，其中，該第一電子元件係藉由複數第一銲線電性連接該承載結構。
  12. 如請求項10所述之電子封裝件之製法，其中，該第二電子元件係藉由複數第二銲線電性連接該承載結構。
  13. 如請求項10所述之電子封裝件之製法，其中，該間隔件之平面尺寸係小於該第一電子元件之平面尺寸。
  14. 如請求項10所述之電子封裝件之製法，其中，該至少一支撐件係包含半導體材或金屬材。
  15. 如請求項10所述之電子封裝件之製法，其中，該至少一支撐件係為虛晶片。
  16. 如請求項10所述之電子封裝件之製法，其中，該至少一支撐件之熱膨脹係數與該第一電子元件之熱膨脹係數屬於同一等級。
  17. 如請求項10所述之電子封裝件之製法，復包括形成封裝層於該承載結構上，以令該封裝層包覆該第一電子元件、第二電子元件、間隔件及至少一支撐件。
  18. 如請求項10所述之電子封裝件之製法，復包括形成複數導電元件於該承載結構之第二側上，以令該複數導電元件電性連接該承載結構。
TW111115641A 2022-04-25 2022-04-25 電子封裝件及其製法 TWI827019B (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
TW111115641A TWI827019B (zh) 2022-04-25 2022-04-25 電子封裝件及其製法
CN202210475102.3A CN116995033A (zh) 2022-04-25 2022-04-29 电子封装件及其制法
US17/845,302 US20230343751A1 (en) 2022-04-25 2022-06-21 Electronic package and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW111115641A TWI827019B (zh) 2022-04-25 2022-04-25 電子封裝件及其製法

Publications (2)

Publication Number Publication Date
TW202343734A TW202343734A (zh) 2023-11-01
TWI827019B true TWI827019B (zh) 2023-12-21

Family

ID=88415864

Family Applications (1)

Application Number Title Priority Date Filing Date
TW111115641A TWI827019B (zh) 2022-04-25 2022-04-25 電子封裝件及其製法

Country Status (3)

Country Link
US (1) US20230343751A1 (zh)
CN (1) CN116995033A (zh)
TW (1) TWI827019B (zh)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200629503A (en) * 2005-02-02 2006-08-16 Siliconware Precision Industries Co Ltd Chip-stacked semiconductor package and fabrication method thereof
TW200703607A (en) * 2005-05-31 2007-01-16 Stats Chippac Ltd Epoxy bump for overhang die
TW201446089A (zh) * 2013-05-28 2014-12-01 矽品精密工業股份有限公司 半導體封裝件及其製法
TW202215617A (zh) * 2020-10-12 2022-04-16 南韓商愛思開海力士有限公司 包括支撐件的堆疊封裝件

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200629503A (en) * 2005-02-02 2006-08-16 Siliconware Precision Industries Co Ltd Chip-stacked semiconductor package and fabrication method thereof
TW200703607A (en) * 2005-05-31 2007-01-16 Stats Chippac Ltd Epoxy bump for overhang die
TW201446089A (zh) * 2013-05-28 2014-12-01 矽品精密工業股份有限公司 半導體封裝件及其製法
TW202215617A (zh) * 2020-10-12 2022-04-16 南韓商愛思開海力士有限公司 包括支撐件的堆疊封裝件

Also Published As

Publication number Publication date
TW202343734A (zh) 2023-11-01
CN116995033A (zh) 2023-11-03
US20230343751A1 (en) 2023-10-26

Similar Documents

Publication Publication Date Title
US9972605B2 (en) Method for fabricating fan-out wafer level package and fan-out wafer level package fabricated thereby
TWI426591B (zh) 多晶片封裝系統
US7224070B2 (en) Plurality of semiconductor die in an assembly
TWI520232B (zh) 具有經封包之通孔的積體電路封裝系統及其製造方法
TWI415201B (zh) 多晶片堆疊結構及其製法
US10002853B2 (en) Stacked semiconductor package having a support and method for fabricating the same
TW201939696A (zh) 電子封裝件及其製法
KR101368793B1 (ko) 반도체 패키지 및 그 제조 방법
KR20200102928A (ko) 브리지 다이를 포함한 시스템 인 패키지 및 반도체 패키지
TWI733569B (zh) 電子封裝件及其製法
CN113921477A (zh) 包括底部填料的半导体封装件
TWI734651B (zh) 電子封裝件及其製法
TWI467731B (zh) 半導體封裝件及其製法
US11881459B2 (en) Electronic package and fabrication method thereof
TW202110298A (zh) 電子封裝件及其組合式基板與製法
TW201806039A (zh) 電子堆疊結構及其製法
TW202230711A (zh) 半導體封裝
US20210280530A1 (en) Electronic package
TWI455280B (zh) 半導體封裝件
TWI827019B (zh) 電子封裝件及其製法
TWI481002B (zh) 具堆疊結構之封裝件及其製法
CN116153873A (zh) 电子封装件及其制法
US20240162101A1 (en) Electronic package and manufacturing method thereof
US20230141318A1 (en) Redistribution substrate and semiconductor package including the same
TWI837021B (zh) 電子封裝件