TWI826072B - Power supply device with high output stability - Google Patents
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Description
本發明係關於一種電源供應器,特別係關於一種高輸出穩定度之電源供應器。The present invention relates to a power supply, and in particular to a power supply with high output stability.
電源供應器為筆記型電腦領域中不可或缺之元件。然而,若電源供應器之輸出穩定度不足,則很容易造成相關筆記型電腦之整體操作性能下滑。有鑑於此,勢必要提出一種全新之解決方案,以克服先前技術所面臨之困境。The power supply is an indispensable component in the notebook computer field. However, if the output stability of the power supply is insufficient, it will easily cause the overall operating performance of the related notebook computer to decline. In view of this, it is necessary to propose a new solution to overcome the difficulties faced by previous technologies.
在較佳實施例中,本發明提出一種高輸出穩定度之電源供應器,包括:一橋式整流器,根據一第一輸入電位和一第二輸入電位來產生一整流電位;一變壓器,包括一主線圈和一副線圈,其中該主線圈係用於接收該整流電位,而該副線圈係用於輸出一感應電位;一功率切換器,根據一時脈電位來選擇性地將該主線圈耦接至一接地電位;一輸出級電路,根據該感應電位來產生一輸出電位;一回授補償電路,根據該輸出電位來產生一分壓電位和一電容電位;以及一偵測及控制電路,根據該電容電位來產生該時脈電位;其中該偵測及控制電路更監控該分壓電位,而若該分壓電位低於或等於一臨界電位,則該偵測及控制電路將會提升及更新該回授補償電路之該電容電位。In a preferred embodiment, the present invention proposes a power supply with high output stability, including: a bridge rectifier that generates a rectified potential based on a first input potential and a second input potential; a transformer including a main A coil and a secondary coil, wherein the primary coil is used to receive the rectified potential, and the secondary coil is used to output an induced potential; a power switch selectively couples the primary coil to the A ground potential; an output stage circuit, which generates an output potential based on the induced potential; a feedback compensation circuit, which generates a divided voltage potential and a capacitor potential based on the output potential; and a detection and control circuit, based on The capacitor potential is used to generate the clock potential; the detection and control circuit further monitors the divided voltage potential, and if the divided voltage potential is lower than or equal to a critical potential, the detection and control circuit will increase and updating the capacitor potential of the feedback compensation circuit.
為讓本發明之目的、特徵和優點能更明顯易懂,下文特舉出本發明之具體實施例,並配合所附圖式,作詳細說明如下。In order to make the purpose, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are listed below and described in detail with reference to the accompanying drawings.
在說明書及申請專利範圍當中使用了某些詞彙來指稱特定的元件。本領域技術人員應可理解,硬體製造商可能會用不同的名詞來稱呼同一個元件。本說明書及申請專利範圍並不以名稱的差異來作為區分元件的方式,而是以元件在功能上的差異來作為區分的準則。在通篇說明書及申請專利範圍當中所提及的「包含」及「包括」一詞為開放式的用語,故應解釋成「包含但不僅限定於」。「大致」一詞則是指在可接受的誤差範圍內,本領域技術人員能夠在一定誤差範圍內解決所述技術問題,達到所述基本之技術效果。此外,「耦接」一詞在本說明書中包含任何直接及間接的電性連接手段。因此,若文中描述一第一裝置耦接至一第二裝置,則代表該第一裝置可直接電性連接至該第二裝置,或經由其它裝置或連接手段而間接地電性連接至該第二裝置。Certain words are used in the specification and patent claims to refer to specific components. Those skilled in the art will understand that hardware manufacturers may use different names to refer to the same component. This specification and the patent application do not use differences in names as a way to distinguish components, but differences in functions of components as a criterion for distinction. The words "include" and "include" mentioned throughout the specification and the scope of the patent application are open-ended terms, and therefore should be interpreted as "include but not limited to." The term "approximately" means that within an acceptable error range, those skilled in the art can solve the technical problem and achieve the basic technical effect within a certain error range. In addition, the word "coupling" in this specification includes any direct and indirect electrical connection means. Therefore, if a first device is coupled to a second device, it means that the first device can be directly electrically connected to the second device, or indirectly electrically connected to the second device via other devices or connections. Two devices.
第1圖係顯示根據本發明一實施例所述之電源供應器100之示意圖。例如,電源供應器100可應用於桌上型電腦、筆記型電腦,或一體成形電腦。如第1圖所示,電源供應器100包括:一橋式整流器110、一變壓器120、一功率切換器130、一輸出級電路140、一回授補償電路150,以及一偵測及控制電路160。必須注意的是,雖然未顯示於第1圖中,但電源供應器100更可包括其他元件,例如:一穩壓器或(且)一負回授電路。Figure 1 is a schematic diagram of a
橋式整流器110可根據一第一輸入電位VIN1和一第二輸入電位VIN2來產生一整流電位VR,其中第一輸入電位VIN1和第二輸入電位VIN2之間可形成具有任意頻率和任意振幅之一交流電壓。例如,交流電壓之頻率可約為50Hz或60Hz,而交流電壓之方均根值(Root Mean Square,RMS)可約由90V至264V,但亦不僅限於此。變壓器120包括一主線圈121和一副線圈122,其中主線圈121可位於變壓器120之一側,而副線圈122則可位於變壓器120之相對另一側。主線圈121可用於接收整流電位VR,而回應於整流電位VR,副線圈122則可用於輸出一感應電位VS。功率切換器130可根據一時脈電位VA來選擇性地將主線圈121耦接至一接地電位VSS(例如:0V)。例如,若時脈電位VA為一高邏輯位準(亦即,邏輯「1」),則功率切換器130可將主線圈121耦接至接地電位VSS(亦即,功率切換器130可近似於一短路路徑);反之,若時脈電位VA為一低邏輯位準(亦即,邏輯「0」),則功率切換器130不會將主線圈121耦接至接地電位VSS(亦即,功率切換器130可近似於一開路路徑)。輸出級電路140可根據感應電位VS來產生一輸出電位VOUT。例如,輸出電位VOUT可為一直流電位,其電位位準可介於18V至20V之間,但亦不僅限於此。回授補償電路150可根據輸出電位VOUT來產生一分壓電位VD和一電容電位VT。偵測及控制電路160可根據電容電位VT來產生時脈電位VA。偵測及控制電路160更可監控分壓電位VD。若分壓電位VD低於或等於一臨界電位VTH,則偵測及控制電路160將會提升及更新回授補償電路150之電容電位VT。在本發明之設計下,偵測及控制電路160可根據分壓電位VD來判斷回授補償電路150之電容電位VT是否存有一誤差值。若是,則偵測及控制電路160將會適當地調整回授補償電路150之電容電位VT,從而可有效提升電源供應器100之輸出穩定度。The
以下實施例將介紹電源供應器100之詳細結構及操作方式。必須理解的是,這些圖式和敘述僅為舉例,而非用於限制本發明之範圍。The following embodiments will introduce the detailed structure and operation of the
第2圖係顯示根據本發明一實施例所述之電源供應器200之電路圖。在第2圖之實施例中,電源供應器200具有一第一輸入節點NIN1、一第二輸入節點NIN2,以及一輸出節點NOUT,並包括一橋式整流器210、一變壓器220、一功率切換器230、一輸出級電路240、一回授補償電路250,以及一偵測及控制電路260。電源供應器200之第一輸入節點NIN1和第二輸入節點NIN2可分別用於接收一第一輸入電位VIN1和一第二輸入電位VIN2。電源供應器200之輸出節點NOUT則可用於輸出一輸出電位VOUT。Figure 2 is a circuit diagram of a
橋式整流器210包括一第一二極體D1、一第二二極體D2、一第三二極體D3,以及一第四二極體D4。第一二極體D1具有一陽極和一陰極,其中第一二極體D1之陽極係耦接至第一輸入節點NIN1,而第一二極體D1之陰極係耦接至一第一節點N1以輸出一整流電位VR。第二二極體D2具有一陽極和一陰極,其中第二二極體D2之陽極係耦接至第二輸入節點NIN2,而第二二極體D2之陰極係耦接至第一節點N1。第三二極體D3具有一陽極和一陰極,其中第三二極體D3之陽極係耦接至一接地電位VSS,而第三二極體D3之陰極係耦接至第一輸入節點NIN1。第四二極體D4具有一陽極和一陰極,其中第四二極體D4之陽極係耦接至接地電位VSS,而第四二極體D4之陰極係耦接至第二輸入節點NIN2。The
變壓器220包括一主線圈221和一副線圈222,其中變壓器220更可內建一激磁電感器LM。激磁電感器LM可為變壓器220製造時所附帶產生之一固有元件,其並非一外部獨立元件。主線圈221和激磁電感器LM皆可位於變壓器220之同一側(例如:一次側),而副線圈222則可位於變壓器220之相對另一側(例如:二次側,其可與一次側互相隔離開來)。詳細而言,主線圈221具有一第一端和一第二端,其中主線圈221之第一端係耦接至第一節點N1以接收整流電位VR,而主線圈221之第二端係耦接至一第二節點N2。激磁電感器LM具有一第一端和一第二端,其中激磁電感器LM之第一端係耦接至第一節點N1,而激磁電感器LM之第二端係耦接至第二節點N2。副線圈222具有一第一端和一第二端,其中副線圈222之第一端係耦接至一第三節點N3以輸出一感應電位VS,而副線圈222之第二端係耦接至一共同節點NCM。例如,共同節點NCM可視為另一接地電位,其可與前述之接地電位VSS相同或相異。The
功率切換器230包括一第一電晶體M1。例如,第一電晶體M1可為一N型金氧半場效電晶體(N-type Metal-Oxide-Semiconductor Field-Effect Transistor,NMOSFET)。第一電晶體M1具有一控制端(例如:一閘極)、一第一端(例如:一源極),以及一第二端(例如:一汲極),其中第一電晶體M1之控制端係用於接收一時脈電位VA,第一電晶體M1之第一端係耦接至接地電位VSS,而第一電晶體M1之第二端係耦接至第二節點N2。功率切換器230更可內建一寄生電容器CP。詳細而言,寄生電容器CP具有一第一端和一第二端,其中寄生電容器CP之第一端係耦接至第二節點N2,而寄生電容器CP之第二端係耦接至接地電位VSS。必須理解的是,第一電晶體M1之第一端和第二端之間之總寄生電容可模擬為前述之寄生電容器CP,其並非一外部獨立元件。The
輸出級電路240包括一第五二極體D5和一第一電容器C1。第五二極體D5具有一陽極和一陰極,其中第五二極體D5之陽極係耦接至第三節點N3以接收感應電位VS,而第五二極體D5之陰極係耦接至輸出節點NOUT。第一電容器C1具有一第一端和一第二端,其中第一電容器C1之第一端係耦接至輸出節點NOUT,而第一電容器C1之第二端係耦接至共同節點NCM。The
在一些實施例中,回授補償電路250包括一線性光耦合器252、一穩壓器254、一第二電容器C2、一第三電容器C3、一第一電阻器R1,以及一第二電阻器R2。In some embodiments, the
第一電阻器R1具有一第一端和一第二端,其中第一電阻器R1之第一端係耦接至輸出節點NOUT以接收輸出電位VOUT,而第一電阻器R1之第二端係耦接至一第四節點N4以輸出一分壓電位VD。第二電阻器R2具有一第一端和一第二端,其中第二電阻器R2之第一端係耦接至第四節點N4,而第二電阻器R2之第二端係耦接至共同節點NCM。第二電容器C2具有一第一端和一第二端,其中第二電容器C2之第一端係耦接至一第五節點N5,而第二電容器C2之第二端係耦接至第四節點N4。The first resistor R1 has a first terminal and a second terminal, wherein the first terminal of the first resistor R1 is coupled to the output node NOUT to receive the output potential VOUT, and the second terminal of the first resistor R1 is Coupled to a fourth node N4 to output a divided voltage potential VD. The second resistor R2 has a first terminal and a second terminal, wherein the first terminal of the second resistor R2 is coupled to the fourth node N4, and the second terminal of the second resistor R2 is coupled to the common node N4. Node NCM. The second capacitor C2 has a first terminal and a second terminal, wherein the first terminal of the second capacitor C2 is coupled to a fifth node N5, and the second terminal of the second capacitor C2 is coupled to the fourth node. N4.
在一些實施例中,線性光耦合器252係由一PC817電子元件來實施。線性光耦合器252包括一發光二極體DL和一雙載子接面電晶體Q1(例如:NPN型)。發光二極體DL具有一陽極和一陰極,其中發光二極體DL之陽極係耦接至輸出節點NOUT,而發光二極體DL之陰極係耦接至第五節點N5。雙載子接面電晶體Q1具有一集極和一射極,其中雙載子接面電晶體Q1之集極係用於輸出一回授電位VF至偵測及控制電路260,而雙載子接面電晶體Q1之射極係耦接至一第六節點N6。In some embodiments,
在一些實施例中,穩壓器254係由一TL431電子元件來實施。穩壓器254具有一陽極、一陰極,以及一參考端,其中穩壓器254之陽極係耦接至共同節點NCM,穩壓器254之陰極係耦接至第五節點N5,而穩壓器254之參考端係耦接至第四節點N4。In some embodiments,
另外,第三電容器C3具有一第一端和一第二端,其中第三電容器C3之第一端係耦接至第六節點N6以提供一電容電位VT,而第三電容器C3之第二端係耦接至接地電位VSS。必須注意的是,回授電位VF係與電容電位VT相關聯。因此,偵測及控制電路260亦可藉由分析回授電位VF來取得電容電位VT之相關資訊。In addition, the third capacitor C3 has a first terminal and a second terminal, wherein the first terminal of the third capacitor C3 is coupled to the sixth node N6 to provide a capacitance potential VT, and the second terminal of the third capacitor C3 is coupled to ground potential VSS. It must be noted that the feedback potential VF is related to the capacitor potential VT. Therefore, the detection and
偵測及控制電路260包括一微控制器(Microcontroller Unit,MCU)262、一誤差放大器(Error Amplifier)266、一第二電晶體M2、一第三電晶體M3、一第四電容器C4,以及一第三電阻器R3。例如,第二電晶體M2和第三電晶體M3可各自為一N型金氧半場效電晶體。The detection and
微控制器262可接收分壓電位VD和回授電位VF,並可根據回授電位VF(或電容電位VT)來產生時脈電位VA和一反相時脈電位VB,其中時脈電位VA和反相時脈電位VB兩者可具有互補(Complementary)之邏輯位準。另外,微控制器262更可持續地監控分壓電位VD,其中微控制器262儲存有一對照表264。若分壓電位VD低於或等於一臨界電位VTH(例如:2.5V),則微控制器262將可根據分壓電位VD來查詢對照表264,以產生對應之一目標電位VG。在一些實施例中,微控制器262之對照表264可如下列所述:
例如,若分壓電位VD變低,則微控制器262所產生之目標電位VG將會隨之變高,從而可拉升時脈電位VA之目標責任週期。在一些實施例中,分壓電位VD與對應之目標電位VG兩者之總和可為一恆定值(例如:5.6V),但亦不僅限於此。For example, if the divided voltage potential VD becomes low, the target potential VG generated by the
第二電晶體M2具有一控制端(例如:一閘極)、一第一端(例如:一源極),以及一第二端(例如:一汲極),其中第二電晶體M2之控制端係用於接收反相時脈電位VB,第二電晶體M2之第一端係耦接至一第七節點N7,而第二電晶體M2之第二端係耦接至第二節點N2。第三電阻器R3具有一第一端和一第二端,其中第三電阻器R3之第一端係耦接至一第八節點N8,而第三電阻器R3之第二端係耦接至第七節點N7。第四電容器C4具有一第一端和一第二端,其中第四電容器C4之第一端係耦接至第八節點N8,而第四電容器C4之第二端係耦接至接地電位VSS。The second transistor M2 has a control terminal (for example, a gate), a first terminal (for example, a source), and a second terminal (for example, a drain), wherein the control terminal of the second transistor M2 The terminal is used to receive the inverted clock potential VB, the first terminal of the second transistor M2 is coupled to a seventh node N7, and the second terminal of the second transistor M2 is coupled to the second node N2. The third resistor R3 has a first terminal and a second terminal, wherein the first terminal of the third resistor R3 is coupled to an eighth node N8, and the second terminal of the third resistor R3 is coupled to The seventh node N7. The fourth capacitor C4 has a first terminal and a second terminal, wherein the first terminal of the fourth capacitor C4 is coupled to the eighth node N8, and the second terminal of the fourth capacitor C4 is coupled to the ground potential VSS.
誤差放大器266具有一正輸入端、一負輸入端,以及一輸出端,其中誤差放大器266之正輸入端係用於接收目標電位VG,誤差放大器266之負輸入端係用於接收電容電位VT,而誤差放大器266之輸出端係用於輸出一控制電位VC。第三電晶體M3具有一控制端(例如:一閘極)、一第一端(例如:一源極),以及一第二端(例如:一汲極),其中第三電晶體M3之控制端係用於接收控制電位VC,第三電晶體M3之第一端係耦接至第六節點N6,而第三電晶體M3之第二端係耦接至第八節點N8。The
第3圖係顯示根據本發明一實施例所述之電源供應器200之電位波形圖,其中橫軸代表時間,而縱軸代表各個電位位準。請一併參考第2、3圖以理解電源供應器200之操作原理。Figure 3 shows a potential waveform diagram of the
當時脈電位VA具有高邏輯位準時,第一電晶體M1將被致能,而第二電晶體M2將被禁能。此時,電磁能量會儲存於變壓器220之激磁電感器LM當中,而功率切換器230之寄生電容器CP則會進行充電。When the clock potential VA has a high logic level, the first transistor M1 will be enabled, and the second transistor M2 will be disabled. At this time, electromagnetic energy will be stored in the magnetizing inductor LM of the
反之,當時脈電位VA具有低邏輯位準時,第一電晶體M1將被禁能,而第二電晶體M2將被致能。此時,第一電容器C1會間接地由激磁電感器LM來進行充電,而第四電容器C4則會間接地由寄生電容器CP來進行充電。必須注意的是,第四電容器C4可大致儲存一平均電位,其即等同於第八節點N8處之電位V8。On the contrary, when the pulse potential VA has a low logic level, the first transistor M1 will be disabled and the second transistor M2 will be enabled. At this time, the first capacitor C1 is indirectly charged by the magnetizing inductor LM, and the fourth capacitor C4 is indirectly charged by the parasitic capacitor CP. It should be noted that the fourth capacitor C4 can approximately store an average potential, which is equal to the potential V8 at the eighth node N8.
第4圖係顯示根據本發明一實施例所述之電源供應器200之電位波形圖,其中橫軸代表時間,而縱軸代表各個電位位準。請一併參考第2、4圖以理解電源供應器200之操作原理。Figure 4 shows a potential waveform diagram of the
若分壓電位VD低於或等於臨界電位VTH,則代表輸出電位VOUT之電位位準過低。這可能是因第三電容器C3發生劣化且其電容電位VT不足所導致。如前所述,微控制器262將可根據分壓電位VD來產生目標電位VG。此時,誤差放大器266會比較目標電位VG和電容電位VT,以產生控制電位VC。必須注意的是,若目標電位VG和電容電位VT之間之一電位差變大,則控制電位VC將會逐漸提升。第三電晶體M3可根據控制電位VC來將儲存於第四電容器C4中之能量傳送至第三電容器C3,從而能補償第三電容器C3之電容電位VT。在一些實施例中,第三電晶體M3可操作於三極管模式(Triode Mode)(其亦可稱為「線性區(Linear Region)」)。亦即,若控制電位VC變高,則第三電晶體M3將可傳送更多能量至第三電容器C3。If the divided voltage potential VD is lower than or equal to the critical potential VTH, it means that the potential level of the output potential VOUT is too low. This may be caused by the third capacitor C3 deteriorating and its capacitance potential VT being insufficient. As mentioned above, the
根據第4圖之量測結果,若電容電位VT由一較低位準VL1提升至一較高位準VL2,則微控制器262將會增加時脈電位VA之一責任週期(Duty Cycle),使得電源供應器200之輸出電位VOUT隨之提高。因此,即使第三電容器C3因高溫而老化,電源供應器200之輸出電位VOUT仍能重新回到一可接受範圍內。According to the measurement results in Figure 4, if the capacitor potential VT is raised from a lower level VL1 to a higher level VL2, the
本發明提出一種新穎之電源供應器,其可根據即時之輸出條件來自動調整其內部電路。根據實際量測結果,使用前述設計之電源供應器將可大幅改善整體之輸出穩定度,故其很適合應用於各種各式之裝置當中。The present invention proposes a novel power supply that can automatically adjust its internal circuit according to real-time output conditions. According to the actual measurement results, using the power supply designed as mentioned above can greatly improve the overall output stability, so it is very suitable for use in various devices.
值得注意的是,以上所述之電位、電流、電阻值、電感值、電容值,以及其餘元件參數均非為本發明之限制條件。設計者可以根據不同需要調整這些設定值。本發明之電源供應器並不僅限於第1-43圖所圖示之狀態。本發明可以僅包括第1-4圖之任何一或複數個實施例之任何一或複數項特徵。換言之,並非所有圖示之特徵均須同時實施於本發明之電源供應器當中。雖然本發明之實施例係使用金氧半場效電晶體為例,但本發明並不僅限於此,本技術領域人士可改用其他種類之電晶體,例如:接面場效電晶體,或是鰭式場效電晶體等等,而不致於影響本發明之效果。It is worth noting that the above-mentioned potential, current, resistance value, inductance value, capacitance value, and other component parameters are not limiting conditions of the present invention. Designers can adjust these settings according to different needs. The power supply of the present invention is not limited to the state shown in Figures 1-43. The present invention may only include any one or multiple features of any one or multiple embodiments of Figures 1-4. In other words, not all features shown in the figures need to be implemented in the power supply of the present invention at the same time. Although the embodiment of the present invention uses a metal oxide semi-field effect transistor as an example, the present invention is not limited thereto. Those skilled in the art can use other types of transistors, such as junction field effect transistors or fins. type field effect transistor, etc., without affecting the effect of the present invention.
在本說明書以及申請專利範圍中的序數,例如「第一」、「第二」、「第三」等等,彼此之間並沒有順序上的先後關係,其僅用於標示區分兩個具有相同名字之不同元件。The ordinal numbers in this specification and the scope of the patent application, such as "first", "second", "third", etc., have no sequential relationship with each other. They are only used to distinguish two items with the same Different components with names.
本發明雖以較佳實施例揭露如上,然其並非用以限定本發明的範圍,任何熟習此項技藝者,在不脫離本發明之精神和範圍內,當可做些許的更動與潤飾,因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。Although the present invention is disclosed above in terms of preferred embodiments, they are not intended to limit the scope of the present invention. Anyone skilled in the art can make slight changes and modifications without departing from the spirit and scope of the present invention. Therefore, The protection scope of the present invention shall be determined by the appended patent application scope.
100,200:電源供應器 110,210:橋式整流器 120,220:變壓器 121,221:主線圈 122,222:副線圈 130,230:功率切換器 140,240:輸出級電路 150,250:回授補償電路 160,260:偵測及控制電路 252:線性光耦合器 254:穩壓器 262:微控制器 264:對照表 266:誤差放大器 C1:第一電容器 C2:第二電容器 C3:第三電容器 C4:第四電容器 CP:寄生電容器 D1:第一二極體 D2:第二二極體 D3:第三二極體 D4:第四二極體 D5:第五二極體 DL:發光二極體 LM:激磁電感器 M1:第一電晶體 M2:第二電晶體 M3:第三電晶體 M4:第四電晶體 N1:第一節點 N2:第二節點 N3:第三節點 N4:第四節點 N5:第五節點 N6:第六節點 N7:第七節點 N8:第八節點 NCM:共同節點 NIN1:第一輸入節點 NIN2:第二輸入節點 NOUT:輸出節點 Q1:雙載子接面電晶體 R1:第一電阻器 R2:第二電阻器 R3:第三電阻器 V8:電位 VA:時脈電位 VB:反相時脈電位 VC:控制電位 VD:分壓電位 VF:回授電位 VG:目標電位 VIN1:第一輸入電位 VIN2:第二輸入電位 VL1:較低位準 VL2:較高位準 VOUT:輸出電位 VR:整流電位 VS:感應電位 VSS:接地電位 VT:電容電位 VTH:臨界電位 100,200:Power supply 110,210: Bridge rectifier 120,220:Transformer 121,221: Main coil 122,222: Secondary coil 130,230:Power switcher 140,240: Output stage circuit 150,250: Feedback compensation circuit 160,260: Detection and control circuit 252:Linear Optocoupler 254:Voltage regulator 262:Microcontroller 264: Comparison table 266: Error amplifier C1: first capacitor C2: Second capacitor C3: The third capacitor C4: The fourth capacitor CP: parasitic capacitor D1: first diode D2: Second diode D3: The third diode D4: The fourth diode D5: The fifth diode DL: light emitting diode LM: Magnetizing inductor M1: the first transistor M2: Second transistor M3: The third transistor M4: The fourth transistor N1: first node N2: second node N3: The third node N4: fourth node N5: fifth node N6: The sixth node N7: The seventh node N8: The eighth node NCM: common node NIN1: first input node NIN2: second input node NOUT: output node Q1: Bicarrier junction transistor R1: first resistor R2: second resistor R3: The third resistor V8:potential VA: clock potential VB: reverse clock potential VC: control potential VD: voltage dividing potential VF: feedback potential VG: target potential VIN1: first input potential VIN2: second input potential VL1: lower level VL2: higher level VOUT: output potential VR: rectifier potential VS: induced potential VSS: ground potential VT: capacitor potential VTH: critical potential
第1圖係顯示根據本發明一實施例所述之電源供應器之示意圖。 第2圖係顯示根據本發明一實施例所述之電源供應器之電路圖。 第3圖係顯示根據本發明一實施例所述之電源供應器之電位波形圖。 第4圖係顯示根據本發明一實施例所述之電源供應器之電位波形圖。 Figure 1 is a schematic diagram of a power supply according to an embodiment of the present invention. Figure 2 is a circuit diagram showing a power supply according to an embodiment of the present invention. Figure 3 shows a potential waveform diagram of a power supply according to an embodiment of the present invention. Figure 4 shows a potential waveform diagram of a power supply according to an embodiment of the present invention.
100:電源供應器 100:Power supply
110:橋式整流器 110: Bridge rectifier
120:變壓器 120:Transformer
121:主線圈 121: Main coil
122:副線圈 122: Secondary coil
130:功率切換器 130:Power switcher
140:輸出級電路 140:Output stage circuit
150:回授補償電路 150:Feedback compensation circuit
160:偵測及控制電路 160: Detection and control circuit
VA:時脈電位 VA: clock potential
VD:分壓電位 VD: voltage dividing potential
VIN1:第一輸入電位 VIN1: first input potential
VIN2:第二輸入電位 VIN2: second input potential
VOUT:輸出電位 VOUT: output potential
VR:整流電位 VR: rectifier potential
VS:感應電位 VS: induced potential
VSS:接地電位 VSS: ground potential
VT:電容電位 VT: capacitor potential
VTH:臨界電位 VTH: critical potential
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TW201206034A (en) * | 2010-07-29 | 2012-02-01 | Tpv Electronics Fujian Co Ltd | Over power protection (OPP) compensation circuit and flyback power supply |
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TW202213917A (en) * | 2020-09-24 | 2022-04-01 | 宏碁股份有限公司 | Power supply capable of stabilizing compensation current |
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TW201206034A (en) * | 2010-07-29 | 2012-02-01 | Tpv Electronics Fujian Co Ltd | Over power protection (OPP) compensation circuit and flyback power supply |
WO2012164613A1 (en) * | 2011-05-31 | 2012-12-06 | パナソニック株式会社 | Switching power supply and semiconductor device |
TW201340573A (en) * | 2012-03-12 | 2013-10-01 | Linear Techn Inc | Isolated flyback converter with sleep mode for light load operation |
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