TWI818268B

TWI818268B - Vcsel with carrier recycling

Info

Publication number: TWI818268B
Application number: TW110120424A
Authority: TW
Inventors: 黃朝興; 金宇中; 文長戴; 何肇杭; 蕭鴻齊
Original assignee: 全新光電科技股份有限公司
Priority date: 2019-06-11
Filing date: 2020-06-08
Publication date: 2023-10-11
Also published as: TW202139552A

Abstract

Provided is a semiconductor laser diode. Although the materials used in the conventional technology can reduce the strain, the selections of materials are relatively limited and the carrier confinement ability is not good. To solve the above-mentioned problems, a phosphorus-containing semiconductor layer is provided in a laser diode. As such, it can effectively reduce the strain of the active region or the total strain of the laser diode, and improve the carrier confinement capability of the active region. Therefore, it can effectively reduce the total strain or significantly improve carrier confinement under appropriate conditions of laser diode. In some cases, it has the aforesaid effects. The phosphorus-containing semiconductor layer is suitable for an active region with one or more active layers. The active layer has a quantum well structure or a quantum dot structure. Especially after the phosphorus-containing semiconductor layer is provided in the active region with multiple active layers, high temperature performance are significantly improved or enhanced.

Description

具有載子再利用機制的垂直共振腔表面放射雷射二極體Vertical resonant cavity surface emitting laser diode with carrier reuse mechanism

一種垂直共振腔表面放射雷射二極體，尤其是一種具有載子再利用機制的垂直共振腔表面放射雷射二極體。 A vertical resonant cavity surface emitting laser diode, in particular, a vertical resonant cavity surface emitting laser diode with a carrier reuse mechanism.

半導體雷射二極體例如垂直共振腔表面放射雷射二極體(Vertical Cavity Surface Emitting Laser Diode,VCSEL)或邊射型雷射二極體(Edge Emitting Laser Diode,EEL)可以用來做為3D感測、LiDAR或光通訊的光源之一。 Semiconductor laser diodes such as Vertical Cavity Surface Emitting Laser Diode (VCSEL) or Edge Emitting Laser Diode (EEL) can be used as 3D One of the light sources for sensing, LiDAR or optical communication.

VCSEL通常包括一對高反射率的膜層，習稱為分散式布拉格反射器層(Distributed Bragg Reflector Layer,DBR Layer)。在一對DBR層之間會具有共振腔，共振腔通常包括間隔層(Spacer Layer)及主動層(Active Layer)，主動層通常包含量子井結構或量子點結構，其中量子井結構主要是由障壁層(Barrier Layer)及井層(Well Layer)構成。DBR層通常是由兩種或兩種以上不同折射率的材料經重覆堆疊並準確控制厚度以達到高反射率的效果。EEL則是在元件的相對的兩外側鍍上一對不同反射率的膜層來形成共振腔，主動層通常包含量子井結構或量子點結構，EEL的量子井結構跟VCSEL一樣也是主要由障壁層及井層構成，主動層之上與之下通常形成上光電侷限層與下光電侷限層。 VCSEL usually includes a pair of high-reflectivity film layers, commonly known as Distributed Bragg Reflector Layer (DBR Layer). There will be a resonant cavity between a pair of DBR layers. The resonant cavity usually includes a spacer layer and an active layer. The active layer usually includes a quantum well structure or a quantum dot structure. The quantum well structure is mainly composed of barrier walls. It is composed of Barrier Layer and Well Layer. The DBR layer is usually made of two or more materials with different refractive indexes that are repeatedly stacked and the thickness is accurately controlled to achieve high reflectivity. EEL is to coat a pair of film layers with different reflectivities on the opposite sides of the element to form a resonant cavity. The active layer usually contains a quantum well structure or a quantum dot structure. The quantum well structure of EEL, like VCSEL, is mainly composed of barrier layers. And the well layer is composed of an upper photoelectric control layer and a lower photoelectric control layer above and below the active layer.

半導體雷射二極體的主動層若是量子井結構時，井層通常是由較低能隙的半導體材料形成，且障壁層是由能隙比井層更大的材料組成，因此藉由障壁層及井層之間的能帶差距會形成量子井。當雷射二極體受到順向偏壓時，電子及電洞則會注入並侷限於量子井結構中，而被注入的電子及電洞等載子會在量子井內產生複合而發射特定波長的光，且光在共振腔內產生建設性干涉，進而發出雷射光。根據雷射光發出的方向，雷射二極體可區分為面射型雷射二極體(VCSEL)及邊射型雷射二極體(EEL)，而面射型雷射二極體也可根據雷射光發出的方向進一步區分為正面出光型雷射二極體(Top Emitting VCSEL)及背面出光型雷射二極體(Bottom Emitting VCSEL)。 If the active layer of a semiconductor laser diode has a quantum well structure, the well layer is usually made of a semiconductor material with a lower energy gap, and the barrier layer is composed of a material with a larger energy gap than the well layer. Therefore, the barrier layer And the energy band gap between well layers will form quantum wells. When the laser diode is forward biased, electrons and holes will be injected and confined in the quantum well structure, and the injected electrons, holes and other carriers will recombine in the quantum well and emit specific wavelengths The light generates constructive interference in the resonant cavity, and then emits laser light. According to the direction in which the laser light is emitted, the laser diode The body can be divided into surface-emitting laser diodes (VCSEL) and edge-emitting laser diodes (EEL), and surface-emitting laser diodes can also be further divided into front-emitting diodes according to the direction in which the laser light is emitted. Type laser diode (Top Emitting VCSEL) and back-emitting laser diode (Bottom Emitting VCSEL).

VCSEL具備下列優點：(1)窄線寬、圓錐形雷射光束易與光纖耦合；(2)在低電流準位可具有快速調變功能，適用於高速傳輸之應用領域；(3)可單模輸出；(4)低驅動電流(threshold current)，功耗小；(5)高輸出功率；(6)正面或背面發光的特性可設計1D或2D矩陣；(7)晶片在封裝前即可進行測試，可大幅降低成本。 VCSEL has the following advantages: (1) narrow linewidth, conical laser beam is easy to couple with optical fiber; (2) can have fast modulation function at low current level, suitable for high-speed transmission applications; (3) can be used alone Mode output; (4) Low drive current (threshold current), low power consumption; (5) High output power; (6) Front or back light-emitting characteristics can be designed with 1D or 2D matrix; (7) The chip can be processed before packaging Testing can significantly reduce costs.

在基板上進行磊晶成長而形成雷射二極體結構，若所成長的磊晶層材料與基板的晶格有不匹配時就會在磊晶層產生應力(Stress)，磊晶層累積過大的應力總和將可能導致雷射二極體結構中的磊晶層產生缺陷(Defect)或差排(Dislocation)，進而影響雷射元件的可靠度(Reliability)或功率轉換效率(Power Conversion Efficiency,PCE)。雷射二極體的主動層若為量子井結構，井層常使用的材料例如有InGaAs或InAlGaAs，選用上述材料的主要目的在於提升雷射二極體的發光效率(optical gain)、提升操作頻寬(frequency response)或用於達到發出特定的雷射波長，然而InGaAs或InAlGaAs磊晶層材料與GaAs基板的晶格不匹配偏大，因而導致主動層產生較大的壓縮應力並於雷射二極體的磊晶層產生壓縮應力累積。 Epitaxial growth is performed on the substrate to form a laser diode structure. If the grown epitaxial layer material does not match the crystal lattice of the substrate, stress will be generated in the epitaxial layer and the accumulation of the epitaxial layer will be too large. The sum of stresses may cause defects or dislocations in the epitaxial layer in the laser diode structure, thereby affecting the reliability or power conversion efficiency (PCE) of the laser element. ). If the active layer of the laser diode has a quantum well structure, commonly used materials for the well layer include InGaAs or InAlGaAs. The main purpose of selecting the above materials is to improve the luminous efficiency (optical gain) of the laser diode and increase the operating frequency. Wide (frequency response) or used to emit a specific laser wavelength. However, the lattice mismatch between the InGaAs or InAlGaAs epitaxial layer material and the GaAs substrate is relatively large, which causes the active layer to generate large compressive stress and causes damage to the laser. The epitaxial layer of the polar body generates compressive stress accumulation.

井層的材料與基板的材料晶格不匹配時會在主動層產生應力累積，且導致雷射二極體結構中磊晶層的應力總和快速累積，導致可靠度不佳。另一方面，高溫操作時主動層載子侷限不佳也是必須克服的問題。 When the material lattice of the well layer does not match the material lattice of the substrate, stress accumulation will occur in the active layer, and the sum of stresses in the epitaxial layer in the laser diode structure will rapidly accumulate, resulting in poor reliability. On the other hand, poor active layer carrier localization during high-temperature operation is also a problem that must be overcome.

在半導體雷射元件引入本說明書所提出的含磷的半導體層時，能減少多層結構的缺陷或差排，或提高主動層的載子侷限能力，甚至在一些情形下兼具以上兩種功效。 When the phosphorus-containing semiconductor layer proposed in this specification is introduced into a semiconductor laser element, defects or dislocations in the multilayer structure can be reduced, or the carrier confinement capability of the active layer can be improved, or even both of the above effects can be achieved in some cases.

本說明書的第一實施例是關於一種半導體雷射二極體，該半導體雷射二極體包含一GaAs基板與在該GaAs基板之上的一多層結構；該多層結構包含一主動區與一第一半導體層；該主動區包含一或複數主動層，該或該等主動層之至少一者包含至少一井層，該至少一井層是包含選自由InGaAs、InAlGaAs、GaAsSb、GaAs、AlGaAs、AlGaAsSb、GaAsP及InGaAsP所組成的群組；該第一半導體層係設於該主動區之內或之外，其中該第一半導體層包含選自由AlGaAsP、AlGaAsPN、AlGaAsPSb、AlGaAsPBi、InAlGaP、InAlGaPN、InAlGaPSb、InAlGaPBi、InGaAsP、InGaAsPN、InGaAsPSb、InGaAsPBi、InGaP、InGaPN、InGaPSb、InGaPBi及InAlGaAsP所組成的群組。 The first embodiment of this specification relates to a semiconductor laser diode. The semiconductor laser diode includes a GaAs substrate and a multi-layer structure on the GaAs substrate; the multi-layer structure includes an active region and an a first semiconductor layer; the active region includes one or a plurality of active layers, the or At least one of the active layers includes at least one well layer, the at least one well layer being selected from the group consisting of InGaAs, InAlGaAs, GaAsSb, GaAs, AlGaAs, AlGaAsSb, GaAsP and InGaAsP; the first semiconductor layer Disposed within or outside the active region, wherein the first semiconductor layer is selected from the group consisting of AlGaAsP, AlGaAsPN, AlGaAsPSb, AlGaAsPBi, InAlGaP, InAlGaPN, InAlGaPSb, InAlGaPBi, InGaAsP, InGaAsPN, InGaAsPSb, InGaAsPBi, InGaP, InGaPN, InGaPSb, The group consisting of InGaPBi and InAlGaAsP.

本說明書的第二實施例是關於一種半導體雷射二極體，該半導體雷射二極體包含一GaAs基板與在該GaAs基板之上的一多層結構；該多層結構包含一主動區、一第二半導體層與一中間層；該主動區包含一或複數主動層，該或該等主動層之至少一者包含至少一障壁層與至少一井層，該至少一井層是包含選自由InGaAs、InAlGaAs、GaAsSb、GaAs、AlGaAs、AlGaAsSb、GaAsP及InGaAsP所組成的群組；該第二半導體層設置於該至少一障壁層之中，其中該第二半導體層是GaAsP；該中間層設置於該至少一障壁層之中及/或該至少一障壁層及該至少一井層之間，該中間層選自由AlGaAsP、AlGaAsPN、AlGaAsPSb、AlGaAsPBi、InAlGaP、InAlGaPN、InAlGaPSb、InAlGaPBi、InGaAsP、InGaAsPN、InGaAsPSb、InGaAsPBi、InGaP、InGaPN、InGaPSb、InGaPBi、InAlGaAsP、GaAs及AlGaAs所組成之群組，其中，該至少一井層的能隙是小於該至少一障壁層的能隙與該中間層的能隙。 The second embodiment of this specification relates to a semiconductor laser diode. The semiconductor laser diode includes a GaAs substrate and a multi-layer structure on the GaAs substrate; the multi-layer structure includes an active region, a The second semiconductor layer and an intermediate layer; the active region includes one or a plurality of active layers, and at least one of the active layers includes at least one barrier layer and at least one well layer, and the at least one well layer is selected from InGaAs. , a group consisting of InAlGaAs, GaAsSb, GaAs, AlGaAs, AlGaAsSb, GaAsP and InGaAsP; the second semiconductor layer is disposed in the at least one barrier layer, wherein the second semiconductor layer is GaAsP; the intermediate layer is disposed in the at least one barrier layer Among at least one barrier layer and/or between the at least one barrier layer and the at least one well layer, the intermediate layer is selected from the group consisting of AlGaAsP, AlGaAsPN, AlGaAsPSb, AlGaAsPBi, InAlGaP, InAlGaPN, InAlGaPSb, InAlGaPBi, InGaAsP, InGaAsPN, InGaAsPSb, The group consisting of InGaAsPBi, InGaP, InGaPN, InGaPSb, InGaPBi, InAlGaAsP, GaAs and AlGaAs, wherein the energy gap of the at least one well layer is smaller than the energy gap of the at least one barrier layer and the energy gap of the intermediate layer.

本說明書的第三實施例是關於一種半導體雷射二極體，該半導體雷射二極體包含一GaAs基板與在該GaAs基板之上的一多層結構；該多層結構包含一下磊晶區、一主動區、一上磊晶區與至少一載子侷限層；該下磊晶區位於該GaAs基板之上，該主動區位於該下磊晶區之上，該上磊晶區位於該主動區之上；該至少一載子侷限層是位於該主動區、該下磊晶區或該上磊晶區之中，該至少一載子侷限層包含選自由AlGaAsP、AlGaAsPN、AlGaAsPSb、AlGaAsPBi、InAlGaP、InAlGaPN、InAlGaPSb、InAlGaPBi、InGaAsP、InGaAsPN、InGaAsPSb、InGaAsPBi、InGaP、InGaPN、InGaPSb、InGaPBi及InAlGaAsP所組成的群組。 The third embodiment of this specification relates to a semiconductor laser diode. The semiconductor laser diode includes a GaAs substrate and a multi-layer structure on the GaAs substrate; the multi-layer structure includes an epitaxial region, An active region, an upper epitaxial region and at least one carrier localization layer; the lower epitaxial region is located on the GaAs substrate, the active region is located on the lower epitaxial region, and the upper epitaxial region is located on the active region above; the at least one carrier confinement layer is located in the active region, the lower epitaxial region or the upper epitaxial region, and the at least one carrier confinement layer includes selected from the group consisting of AlGaAsP, AlGaAsPN, AlGaAsPSb, AlGaAsPBi, InAlGaP, The group consisting of InAlGaPN, InAlGaPSb, InAlGaPBi, InGaAsP, InGaAsPN, InGaAsPSb, InGaAsPBi, InGaP, InGaPN, InGaPSb, InGaPBi and InAlGaAsP.

本說明書的第四實施例是關於一種半導體雷射二極體，該半導體雷射二極體包含一GaAs基板與在該GaAs基板之上的一多層結構；該多層結構包含一主動區，該主動區包含一或複數量子點結構，該或該等量子點結構之至少一者包含一量子點、一浸潤層及一覆蓋層；其中，該量子點或該浸潤層是包含選自由InGaAs、InAlGaAs、GaAsSb、GaAs、AlGaAs、AlGaAsSb、GaAsP及InGaAsP所組成的群組；該覆蓋層是包含選自由AlGaAsP、AlGaAsPN、AlGaAsPSb、AlGaAsPBi、InAlGaP、InAlGaPN、InAlGaPSb、InAlGaPBi、InGaAsP、InGaAsPN、InGaAsPSb、InGaAsPBi、InGaP、InGaPN、InGaPSb、InGaPBi及InAlGaAsP所組成的群組。 The fourth embodiment of this specification relates to a semiconductor laser diode. The semiconductor laser diode includes a GaAs substrate and a multi-layer structure on the GaAs substrate; the multi-layer structure includes an active region, and the The active region includes one or a plurality of quantum dot structures, and at least one of the or the quantum dot structures includes a quantum dot, a wetting layer and a covering layer; wherein the quantum dot or the wetting layer is selected from the group consisting of InGaAs, InAlGaAs , GaAsSb, GaAs, AlGaAs, AlGaAsSb, GaAsP and InGaAsP; the covering layer is selected from the group consisting of AlGaAsP, AlGaAsPN, AlGaAsPSb, AlGaAsPBi, InAlGaP, InAlGaPN, InAlGaPSb, InAlGaPBi, InGaAsP, InGaAsPN, InGaAsPSb, InGaAsPBi, InGaP , InGaPN, InGaPSb, InGaPBi and InAlGaAsP.

本說明書的第五實施例是關於一種半導體雷射二極體，該半導體雷射二極體包含一InP基板與在該InP基板之上的一多層結構；該多層結構包含一下磊晶區、一主動區、一上磊晶區與至少一載子侷限層；該下磊晶區位於該InP基板之上，該主動區位於該下磊晶區之上，其中該主動區包含一主動層或複數主動層，該上磊晶區位於該主動區之上；該至少一載子侷限層是位於該主動區、該下磊晶區或該上磊晶區之中，該至少一載子侷限層係選自由InGaP、InAlGaP、InP、InAlAsP、AlAsSb、AlAsBi、AlGaAsSb、AlGaAsBi、AlPSb、AlPBi、InGaAsP所組成的群組。 The fifth embodiment of this specification relates to a semiconductor laser diode. The semiconductor laser diode includes an InP substrate and a multi-layer structure on the InP substrate; the multi-layer structure includes an epitaxial region, An active region, an upper epitaxial region and at least one carrier confinement layer; the lower epitaxial region is located on the InP substrate, and the active region is located on the lower epitaxial region, wherein the active region includes an active layer or A plurality of active layers, the upper epitaxial region is located above the active region; the at least one carrier confinement layer is located in the active region, the lower epitaxial region or the upper epitaxial region, and the at least one carrier confinement layer The system is selected from the group consisting of InGaP, InAlGaP, InP, InAlAsP, AlAsSb, AlAsBi, AlGaAsSb, AlGaAsBi, AlPSb, AlPBi, and InGaAsP.

1’:半導體雷射元件 1’:Semiconductor laser element

10’:基板 10’:Substrate

20’、21’:主動層 20’, 21’: active layer

30’:下磊晶區 30’: Lower epitaxial area

40’:上磊晶區 40’: Upper epitaxial area

100’:多層結構 100’:Multi-layer structure

A’:主動區 A’: Active area

S1’:半導體層 S1’: semiconductor layer

CF’:載子侷限層 CF’: carrier confinement layer

J1:第一面 J1: Side one

J2:第二面 J2: Side two

J3:第三面 J3: The third side

J4:第四面 J4: The fourth side

CF’:載子侷限層 CF’: carrier confinement layer

1:VCSEL 1:VCSEL

10:基板、GaAs基板 10: Substrate, GaAs substrate

100:多層結構 100:Multi-layer structure

101:緩衝層 101:Buffer layer

102:下DBR層 102: Lower DBR layer

103:下間隔層 103: Lower compartment layer

20、21:主動層 20, 21: Active layer

104:上間隔層 104: Upper spacer layer

105:上DBR層 105: Go to DBR layer

106:歐姆接觸層 106: Ohmic contact layer

201:井層 201:Well layer

203:障壁層 203: Barrier layer

205:中間層 205:Middle layer

24:氧化層 24:Oxide layer

25:穿隧接面層 25: Tunnel junction layer

261、262、263:間隔層 261, 262, 263: Spacer layer

S1:第一半導體層 S1: first semiconductor layer

S2:第二半導體層 S2: second semiconductor layer

CF:載子侷限層 CF: carrier confinement layer

3:EEL 3:EEL

300:多層結構 300:Multi-layer structure

301:下披覆層 301: Lower covering layer

302:下光電侷限層 302: Lower photoelectric control layer

303:上光電侷限層 303: Upper photoelectric control layer

304:披覆層 304:Coating layer

305:歐姆接觸層 305: Ohmic contact layer

CF1、CF2:載子侷限層 CF1, CF2: carrier confinement layer

圖1a~1c是顯示含磷的半導體層設置於主動區內的一些代表性實施例的簡單示意圖。 1a to 1c are simple schematic diagrams showing some representative embodiments in which a phosphorus-containing semiconductor layer is disposed in an active region.

圖1d~1g是顯示含磷的半導體層設置於主動區外的一些代表性實施例的簡單示意圖。 1d to 1g are simple schematic diagrams showing some representative embodiments in which the phosphorus-containing semiconductor layer is disposed outside the active region.

圖2是顯示一種現有VCSEL的示意圖。 Figure 2 is a schematic diagram showing a conventional VCSEL.

圖3a是顯示圖2的主動層為量子井結構的一實施例示意圖。 FIG. 3a is a schematic diagram showing an embodiment in which the active layer in FIG. 2 is a quantum well structure.

圖3b是顯示圖3a的障壁層與井層的能帶關係示意圖。 Figure 3b is a schematic diagram showing the energy band relationship between the barrier layer and the well layer in Figure 3a.

圖4a是顯示障壁層的一部分或障壁層的全部是第一半導體層的示意圖。 FIG. 4a is a schematic diagram showing that a part of the barrier layer or the entire barrier layer is a first semiconductor layer.

圖4b是顯示各障壁層皆形成第一半導體層的一實施例示意圖。 FIG. 4b is a schematic diagram showing an embodiment in which each barrier layer forms a first semiconductor layer.

圖5a是顯示障壁層跟井層之間具有中間層之一實施例的示意圖。 Figure 5a is a schematic diagram showing an embodiment of an intermediate layer between the barrier layer and the well layer.

圖5b是顯示圖5a的障壁層、中間層與井層的能帶關係示意圖。 Figure 5b is a schematic diagram showing the energy band relationship between the barrier layer, the intermediate layer and the well layer in Figure 5a.

圖6a是顯示障壁層中***GaAsP中間層之一實施例的示意圖。 Figure 6a is a schematic diagram showing an embodiment of inserting a GaAsP intermediate layer into the barrier layer.

圖6b是顯示圖6a的障壁層、中間層與井層的能帶關係示意圖。 Figure 6b is a schematic diagram showing the energy band relationship between the barrier layer, the intermediate layer and the well layer in Figure 6a.

圖7a是顯示障壁層中***AlGaAsP中間層之一實施例的示意圖。 Figure 7a is a schematic diagram showing an embodiment of inserting an AlGaAsP intermediate layer into the barrier layer.

圖7b是顯示圖7a的障壁層、中間層與井層的能帶關係示意圖。 Figure 7b is a schematic diagram showing the energy band relationship between the barrier layer, the intermediate layer and the well layer in Figure 7a.

圖8a為顯示以第二半導體層作為障壁層，中間層是位於第二半導體層與井層之間的一實施例示意圖。 FIG. 8a is a schematic diagram showing an embodiment in which the second semiconductor layer is used as a barrier layer and the intermediate layer is located between the second semiconductor layer and the well layer.

圖8b為顯示以第二半導體層作為障壁層，中間層***於障壁層之中的一實施例示意圖。 FIG. 8b is a schematic diagram showing an embodiment in which the second semiconductor layer is used as the barrier layer and the intermediate layer is inserted into the barrier layer.

圖9為顯示具有多主動層的主動區的VCSEL的一實施例示意圖。 FIG. 9 is a schematic diagram showing an embodiment of a VCSEL with an active region having multiple active layers.

圖10a是同時顯示第一半導體層形成於主動層之上及之下的一實施例的示意圖。 FIG. 10a is a schematic diagram showing an embodiment in which the first semiconductor layer is formed above and below the active layer at the same time.

圖10b顯示第一半導體層形成於主動層與下間隔層之間的一實施例的示意圖。 FIG. 10b shows a schematic diagram of an embodiment in which the first semiconductor layer is formed between the active layer and the lower spacer layer.

圖11a是顯示載子侷限層在主動區內的一實施例示意圖。 FIG. 11a is a schematic diagram showing an embodiment of the carrier confinement layer in the active region.

圖11b是顯示載子侷限層在主動區內的另一實施例示意圖。 Figure 11b is a schematic diagram showing another embodiment of the carrier confinement layer in the active region.

圖11c是顯示載子侷限層在主動區外的一實施例示意圖。 FIG. 11c is a schematic diagram showing an embodiment of the carrier confinement layer outside the active region.

圖11d是顯示載子侷限層在主動區外的另一實施例示意圖。 Figure 11d is a schematic diagram showing another embodiment of the carrier confinement layer outside the active region.

圖12a是顯示載子侷限層設置在下間隔層的一部份的一實施例的示意圖。 FIG. 12a is a schematic diagram showing an embodiment in which the carrier confinement layer is disposed on a portion of the lower spacer layer.

圖12b是顯示載子侷限層設置在上間隔層的全部的一實施例的示意圖。 FIG. 12b is a schematic diagram showing an embodiment in which the carrier confinement layer is entirely disposed on the upper spacer layer.

圖12c是顯示主動層的各障壁層均設置一載子侷限層的示意圖。 FIG. 12c is a schematic diagram showing that each barrier layer of the active layer is provided with a carrier confinement layer.

圖13是顯示主動層之下及之上均設置一載子侷限層的一實施例的示意圖。 FIG. 13 is a schematic diagram showing an embodiment in which a carrier confinement layer is disposed below and above the active layer.

圖14a~圖14c是顯示當主動區包含二主動層，載子侷限層設置於兩主動層之間的一些代表性實施例的簡單示意圖。 Figures 14a to 14c are simple schematic diagrams showing some representative embodiments in which the active region includes two active layers and the carrier confinement layer is disposed between the two active layers.

圖14d是顯示當主動區包含二主動層，兩載子侷限層設置於兩主動層之間的磊晶區中之一實施例的簡單示意圖。 FIG. 14d is a simple schematic diagram showing an embodiment when the active region includes two active layers and two carrier localization layers are disposed in the epitaxial region between the two active layers.

圖14e~圖14h是顯示當主動區包含二主動層，載子侷限層設置於主動區外的一些代表性實施例的簡單示意圖。 Figures 14e to 14h are simple schematic diagrams showing some representative embodiments in which the active area includes two active layers and the carrier localization layer is disposed outside the active area.

圖15是顯示兩主動層間設置一載子侷限層的一較佳實施例示意圖。 FIG. 15 is a schematic diagram showing a preferred embodiment in which a carrier confinement layer is disposed between two active layers.

圖16是顯示兩主動層間設置一載子侷限層的另一較佳實施例示意圖。 FIG. 16 is a schematic diagram showing another preferred embodiment in which a carrier confinement layer is disposed between two active layers.

圖17a是顯示兩主動層之間設置兩載子侷限層的一實施例示意圖。 FIG. 17a is a schematic diagram showing an embodiment in which two carrier confinement layers are disposed between two active layers.

圖17b是顯示主動區之上與之下皆設置一載子侷限層的一實施例示意圖。 FIG. 17b is a schematic diagram showing an embodiment in which a carrier confinement layer is disposed above and below the active region.

圖17c是顯示每一主動層之上及之下皆設置一載子侷限層的一實施例示意圖。 FIG. 17c is a schematic diagram showing an embodiment in which a carrier confinement layer is disposed above and below each active layer.

圖18是顯示現有EEL的一種多層結構的示意圖。 Figure 18 is a schematic diagram showing a multi-layer structure of a conventional EEL.

圖19a是顯示EEL的主動層之上與之下皆設有第一半導體層之一實施例的示意圖。 FIG. 19a is a schematic diagram showing an embodiment of an EEL with a first semiconductor layer both above and below the active layer.

圖19b是顯示EEL的主動層之上與之下皆設有載子侷限層之一實施例的示意圖。 Figure 19b is a schematic diagram showing an embodiment of an EEL with carrier confinement layers both above and below the active layer.

圖20a為比較例1的XRT顯像示意圖。 Figure 20a is a schematic diagram of XRT imaging of Comparative Example 1.

圖20b為實施例20的XRT顯像示意圖。 Figure 20b is a schematic diagram of XRT imaging in Example 20.

圖20c為實施例21的XRT顯像示意圖。 Figure 20c is a schematic diagram of XRT imaging in Example 21.

圖21是實施例21、22與比較例2在不同溫度下最大功率轉換效率的比較圖。 Figure 21 is a comparison diagram of the maximum power conversion efficiency at different temperatures between Examples 21 and 22 and Comparative Example 2.

圖22是實施例23與比較例3在不同溫度下最大功率轉換效率的比較圖。 Figure 22 is a comparison diagram of the maximum power conversion efficiency at different temperatures between Example 23 and Comparative Example 3.

圖23是實施例24與比較例4在室溫下測得的L-I-V曲線圖。 Figure 23 is a L-I-V curve graph measured at room temperature in Example 24 and Comparative Example 4.

圖24是實施例24與比較例4在高溫下測得的L-I-V曲線圖。 Figure 24 is a L-I-V curve graph measured at high temperature in Example 24 and Comparative Example 4.

以下配合圖式及元件符號對本發明的實施方式作更詳細的說明，俾使熟習該項技藝者在研讀本說明書後能據以實施。圖式中各膜層之間的厚度比例也非實際比例，應根據實際需要而調整各膜層的厚度。 The embodiments of the present invention are described in more detail below with reference to drawings and component symbols, so that those skilled in the art can implement them after reading this specification. The thickness ratio between the film layers in the diagram is not the actual ratio, and the thickness of each film layer should be adjusted according to actual needs.

以下描述具體的元件及其排列的例子以簡化本發明。當然這些僅是例子且不該以此限定本發明的範圍。例如，在描述中提及一層於另一層之上時，其可能包括該層與該另一層層直接接觸的實施例，也可能包括兩者之間有其他元件或磊晶層形成而沒有直接接觸的實施例。此外，在不同實施例中可能使用重複的標號及/或符號，這些重複僅為了簡單清楚地敘述一些實施例，不代表所討論的不同實施例及/或結構之間有特定關聯。 Examples of specific elements and their arrangements are described below to simplify the present invention. Of course these are only examples and should not limit the scope of the invention. For example, when a description refers to one layer being on top of another, it may include embodiments in which the layer is in direct contact with the other layer, or may include other components or epitaxial layers formed between the two without direct contact. Embodiments. In addition, repeated reference numbers and/or symbols may be used in different embodiments. These repetitions are only for the purpose of describing some embodiments simply and clearly, and do not represent a specific relationship between the different embodiments and/or structures discussed.

此外，其中可能用到與空間相關的用詞，像是“在...下方”、“下方”、“較低的”、“上方”、“較高的”及類似的用詞，這些關係詞係為了便於描述圖式中一個(些)元件或特徵與另一個(些)元件或特徵之間的關係。這些空間關係詞包括使用中或操作中的裝置之不同方位，以及圖式中所描述的方位。 In addition, words related to space may be used, such as "below", "below", "lower", "above", "higher" and similar words. These relationships The word system is used to describe the diagram easily. The relationship between one element or feature in the formula and another element or feature. These spatial relative terms include the various orientations of a device in use or operation, as well as the orientation depicted in the diagrams.

本發明說明書提供不同的實施例來說明不同實施方式的技術特徵。舉例而言，全文說明書中所指的“一些實施例”意味著在實施例中描述到的特定特徵、結構、或特色至少包含在一實施例中。因此，全文說明書不同地方所出現的片語“在一些實施例中”所指不一定為相同的實施例。 The specification of the present invention provides different examples to illustrate the technical features of different implementations. For example, reference throughout this specification to "some embodiments" means that a particular feature, structure, or characteristic described in the embodiments is included in at least one embodiment. Therefore, the phrase "in some embodiments" appearing in different places throughout this specification does not necessarily refer to the same embodiment.

此外，特定的特徵、結構、或特色可在一或多個的實施例中透過任何合適的方法結合。進一步地，對於在此所使用的用語“包括”、“具有”、“有”、“其中”或前述之變換，這些語意類似於用語“包括”來包含相應的特徵。 Additionally, specific features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. Furthermore, for the terms "include", "have", "have", "wherein" or changes in the foregoing used herein, these semantics are similar to the term "comprising" to include corresponding features.

此外，”層”可以是單一層或者包含是多層；而一磊晶層的”一部分”可能是該磊晶層的一層或互為相鄰的複數層。 In addition, a "layer" may be a single layer or include multiple layers; and a "part" of an epitaxial layer may be one layer of the epitaxial layer or a plurality of adjacent layers.

現有技術中，雷射二極體可依據實際需求而選擇性的設置緩衝層，且在一些實例中，緩衝層與基板在材質可以是相同的。且緩衝層設置與否，跟以下實施例所欲講述的技術特點與所欲提供的效果並無實質相關，因此為了簡要示例說明，以下實施例僅以具有緩衝層的雷射二極體來做為說明用的示例，而不另贅述沒有設置緩衝層的雷射二極體，也就是以下實施例如置換無緩衝層的雷射二極體也能一體適用。 In the prior art, a laser diode can be selectively provided with a buffer layer according to actual needs, and in some examples, the material of the buffer layer and the substrate can be the same. In addition, whether the buffer layer is provided or not has nothing to do with the technical features and effects to be described in the following embodiments. Therefore, for the sake of brief illustration, the following embodiments only use a laser diode with a buffer layer. For the sake of illustration, the laser diode without a buffer layer will not be described in detail. That is, the following embodiments can also be applied to replace the laser diode without a buffer layer.

半導體雷射元件主要包含基板與多層結構，多層結構是形成於基板之上，眾所周知的是，應用目的或工作原理不同的半導體雷射元件，所使用的多層結構甚至基板材料也會有所不同；本說明書所提出的含磷的半導體層應用在半導體雷射元件時，能減少多層結構的缺陷、差排或提高載子侷限能力，甚至在一些情形下兼具以上兩種功效。本說明書的半導體雷射元件是涉及VCSEL或EEL等其他適當雷射元件，但排除發光波長未達700nm的雷射二極體。 Semiconductor laser components mainly include a substrate and a multi-layer structure. The multi-layer structure is formed on the substrate. It is well known that semiconductor laser components with different application purposes or working principles will use different multi-layer structures and even substrate materials; When the phosphorus-containing semiconductor layer proposed in this specification is applied to a semiconductor laser element, it can reduce defects and dislocations in the multilayer structure or improve carrier confinement capabilities, and even achieve both of the above effects in some cases. The semiconductor laser components in this specification refer to other suitable laser components such as VCSEL or EEL, but exclude laser diodes whose emission wavelength does not reach 700nm.

參閱圖1a，本說明書的半導體雷射元件1’主要包含基板10’與多層結構100’，多層結構100’是形成於基板10’之上，多層結構100’包含主動區A’與含磷的半導體層S1’。參閱圖1a及圖1b~1c所示，含磷的半導體層S1’能位於主動區A’之內的不同位置；或者，如圖1d~1e所示，半導體層S1’是位於主動區之上或之下，且半導體層S1’與主動區A’直接接觸；或者，如圖1f~1g所示，半導體層S1’也是位於主動區A’之上或之下，但半導體層S1’是間接接觸於主動區A’，也就是半導體層S1’與主動區A’之間還具有磊晶層；具體的實施方式說明如下。 Referring to Figure 1a, the semiconductor laser element 1' of this specification mainly includes a substrate 10' and a multi-layer structure 100'. The multi-layer structure 100' is formed on the substrate 10'. The multi-layer structure 100' includes an active region A' and a phosphorus-containing region. Semiconductor layer S1'. Referring to Figures 1a and 1b~1c, the phosphorus-containing semiconductor layer S1' can be located at different positions within the active area A'; or, as shown in Figures 1d~1e, the semiconductor layer S1' is located above the active area. or below, and the semiconductor layer S1' is in direct contact with the active region A'; or, as shown in Figure 1f~1g, the semiconductor layer S1' is also located above or below the active region A', but the semiconductor layer S1' is indirectly catch In contact with the active region A', that is, there is an epitaxial layer between the semiconductor layer S1' and the active region A'; the specific implementation is described below.

[實施例1] [Example 1]

參考圖2~圖4a~圖4b，圖2是顯示一種現有VCSEL的示意圖。圖3a是顯示圖2的主動層為量子井結構的一實施例示意圖；圖3b是顯示圖3a的障壁層與井層的能階(energy band level)示意圖；圖4a是顯示障壁層的一部分或障壁層的全部是第一半導體層的示意圖，圖4b則是顯示各障壁層皆形成第一半導體層的一實施例示意圖。 Referring to Figures 2 to 4a to 4b, Figure 2 is a schematic diagram showing an existing VCSEL. Figure 3a is a schematic diagram showing an embodiment in which the active layer in Figure 2 is a quantum well structure; Figure 3b is a schematic diagram showing the energy band levels of the barrier layer and the well layer in Figure 3a; Figure 4a is a diagram showing a part of the barrier layer or The entire barrier layer is a schematic diagram of the first semiconductor layer, and FIG. 4b is a schematic diagram showing an embodiment in which each barrier layer forms the first semiconductor layer.

圖1a至1b的含磷的半導體層S1’在實施例1中稱為第一半導體層S1。圖2~圖3a、圖3b是關於現有VCESL的結構，以及主動層為量子井結構；而關於第一半導體層應用於VCSEL的具體實施例，則請參閱圖4a、圖4b及其相關內容。 The phosphorus-containing semiconductor layer S1' of Figures 1a to 1b is referred to as the first semiconductor layer S1 in Embodiment 1. Figures 2 to 3a and 3b are about the structure of the existing VCESL, and the active layer is a quantum well structure. For specific embodiments of the first semiconductor layer applied to VCSEL, please refer to Figure 4a, 4b and related content.

圖2所示的半導體雷射元件是VCSEL1，如圖2所示，VCSEL1包含GaAs基板10與多層結構100，多層結構100的主動區A包含一主動層20(多主動層的實施例參後文)，多層結構100由下而上依序包括緩衝層101、下DBR層102、下間隔層103、主動層20、上間隔層104、上DBR層105以及歐姆接觸層106，主動層20是位於下間隔層103與上間隔層104之間。 The semiconductor laser element shown in Figure 2 is VCSEL1. As shown in Figure 2, VCSEL1 includes a GaAs substrate 10 and a multi-layer structure 100. The active area A of the multi-layer structure 100 includes an active layer 20 (for the embodiment of multiple active layers, please refer to the following text). ), the multi-layer structure 100 sequentially includes a buffer layer 101, a lower DBR layer 102, a lower spacer layer 103, an active layer 20, an upper spacer layer 104, an upper DBR layer 105 and an ohmic contact layer 106 from bottom to top. The active layer 20 is located between the lower spacer layer 103 and the upper spacer layer 104 .

緩衝層101、下DBR層102、下間隔層103、上間隔層104、上DBR層105以及歐姆接觸層106，這些磊晶層的材料可以是習知常用的半導體材料；根據實際需要，在下DBR層102及/或上DBR層105中能選擇性的設置一或一些磊晶層，例如氧化層、歐姆接觸層、間隔層或其他適當的磊晶層。 Buffer layer 101, lower DBR layer 102, lower spacer layer 103, upper spacer layer 104, upper DBR layer 105 and ohmic contact layer 106. The materials of these epitaxial layers can be commonly used semiconductor materials; according to actual needs, the lower DBR One or more epitaxial layers, such as an oxide layer, an ohmic contact layer, a spacer layer or other appropriate epitaxial layers, can be selectively provided in the layer 102 and/or the upper DBR layer 105 .

如圖3a所示，主動層20的一實施例中包含二層井層201與三層障壁層203，二層井層201與三層障壁層203是相互交錯堆疊，但其結構不限於此。亦即，主動層20可以包含n層井層201與n+1層障壁層203，如主動層20是此種配置方式，則主動層20的最上層與最下層皆為障壁層203。在一些實施例中，在主動層20的最上層與最下層的障壁層20可充當下間隔層103或上間隔層104。 As shown in Figure 3a, one embodiment of the active layer 20 includes two well layers 201 and three barrier layer 203. The two well layers 201 and the three barrier layers 203 are staggered and stacked with each other, but their structure is not limited to this. That is, the active layer 20 may include n well layers 201 and n+1 barrier layers 203. If the active layer 20 is configured in this way, the uppermost layer and the lowermost layer of the active layer 20 are both barrier layers 203. In some embodiments, the barrier layer 20 at the uppermost layer and the lowermost layer of the active layer 20 may serve as the lower spacer layer 103 or the upper spacer layer 104 .

在未圖示的一實施例中，主動層20也可以包含n層井層201與n-1層障壁層203，如主動層20是此種配置方式，則主動層20的最上層或最下層的其中之一是井層201，或者主動層20的最上層與最下層都是井層201。較佳地，n為1至5的整數(即，主動層20至少包含一層井層)，更佳地，n為2至5的整數，可提升VCSEL的發光效率(optical gain)或高溫特性(high temperture performance)。 In an embodiment not shown, the active layer 20 may also include n well layers 201 and n-1 barrier layers 203. If the active layer 20 is configured in this way, the uppermost layer or the lowermost layer of the active layer 20 One of them is the well layer 201, or the uppermost layer and the lowermost layer of the active layer 20 are both the well layer 201. better Specifically, n is an integer from 1 to 5 (that is, the active layer 20 includes at least one well layer). More preferably, n is an integer from 2 to 5, which can improve the luminous efficiency (optical gain) or high temperature characteristics (high temperature) of the VCSEL. performance).

當主動層20的最上層或最下層均為井層201時，與該井層201鄰接的下間隔層103或上間隔層104充當障壁層。當主動層20的最上層與最下層皆為井層201時，與該些井層201鄰接的下間隔層103及上間隔層104皆充當障壁層。 When the uppermost layer or the lowermost layer of the active layer 20 is the well layer 201, the lower spacer layer 103 or the upper spacer layer 104 adjacent to the well layer 201 acts as a barrier layer. When the uppermost layer and the lowermost layer of the active layer 20 are both well layers 201, the lower spacer layer 103 and the upper spacer layer 104 adjacent to the well layers 201 both serve as barrier layers.

又，如圖3b的能帶示意圖所示，障壁層203為導電帶能階(E_c)較高的半導體材料，且井層201為導電帶能階較低的半導體材料，於是產生導電帶不連續(△E_c)而形成所謂的量子井。類似地，在價電帶能階(E_v)也會產生價電帶不連續(△E_v)。當VCSEL1受到順向偏壓時，電子及電洞則會注入並侷限於量子井中，而被注入的電子及電洞等載子會在量子井內複合而發光。 In addition, as shown in the energy band diagram of Figure 3b, the barrier layer 203 is a semiconductor material with a higher conductive band energy level (E _c ), and the well layer 201 is a semiconductor material with a lower conductive band energy level, resulting in a conductive band insufficiency. Continuously (ΔE _c ) to form a so-called quantum well. Similarly, valence band discontinuity (ΔE _v ) will also occur at the valence band energy level (E _v ). When VCSEL1 is forward biased, electrons and holes will be injected and confined in the quantum well, and the injected electrons, holes and other carriers will recombine in the quantum well and emit light.

在本文的大多數實施例中，井層201的優選材料是InGaAs、InAlGaAs、GaAsSb、GaAs、AlGaAs、AlGaAsSb、GaAsP、InGaAsP或以上材料的配合，經由改變井層201的成分或厚度能夠調整VCSEL1的雷射波長，因此半導體雷射元件的雷射波長容易達到700nm或800nm以上。 In most embodiments of this article, the preferred material of the well layer 201 is InGaAs, InAlGaAs, GaAsSb, GaAs, AlGaAs, AlGaAsSb, GaAsP, InGaAsP or a combination of the above materials. The VCSEL1 can be adjusted by changing the composition or thickness of the well layer 201 Laser wavelength, so the laser wavelength of semiconductor laser components can easily reach 700nm or above 800nm.

然而，作為井層201的一些材料晶格並不匹配於GaAs基板10，尤其，InGaAs、InAlGaAs、GaAsSb、AlGaAs與AlGaAsSb這些材料的晶格常數大於GaAs基板，因此井層在磊晶成長後，井層是產生壓縮應力(Compressive Strain)，且即使改變這些材料的成份，晶格常數仍然還是會大於GaAs基板；而晶格常數小於GaAs基板則有GaAsP，因此井層在進行磊晶成長後，井層是產生拉伸應力，同樣的，即使透過改變GaAsP的材料成分，GaAsP的晶格常數還是會小於GaAs基板；若主動層中的一些井層或各井層產生壓縮應力或拉伸應力，則主動層20或VCSEL1中累積的應力就會變大，一旦VCSEL中累積的應力過大，會致使VCSEL的磊晶層產生缺陷或差排。 However, the lattice of some materials used as the well layer 201 does not match the GaAs substrate 10. In particular, the lattice constants of InGaAs, InAlGaAs, GaAsSb, AlGaAs, and AlGaAsSb are larger than those of the GaAs substrate. Therefore, after the epitaxial growth of the well layer, The layer generates compressive stress (Compressive Strain), and even if the composition of these materials is changed, the lattice constant will still be larger than the GaAs substrate; while the lattice constant is smaller than the GaAs substrate, there will be GaAsP, so after the epitaxial growth of the well layer, the well layer will The layer generates tensile stress. Similarly, even by changing the material composition of GaAsP, the lattice constant of GaAsP will still be smaller than the GaAs substrate; if some well layers or each well layer in the active layer generates compressive stress or tensile stress, then The accumulated stress in the active layer 20 or VCSEL 1 will become larger. Once the accumulated stress in the VCSEL is too large, it will cause defects or misalignment in the epitaxial layer of the VCSEL.

因此，在多層結構中提供含磷的第一半導體層S1，作為第一半導體層的較佳材料有17種如表1所示，作為第一半導體層S1的優選材料包含表1的17種材料的至少一材料或至少二材料以上的組合。 Therefore, a first semiconductor layer S1 containing phosphorus is provided in a multilayer structure. There are 17 preferred materials for the first semiconductor layer as shown in Table 1. The preferred materials for the first semiconductor layer S1 include the 17 materials in Table 1. At least one material or a combination of at least two materials.

【表1】

【Table 1】

以上列舉的材料的晶格常數能被改變，比如透過調整材料中的成份多寡而決定晶格常數是要匹配於、小於或大於GaAs基板，因此第一半導體層可以根據井層的應力而決定是產生拉伸應力、產生壓縮應力或甚至不產生明顯應力，如此井層的應力能被第一半導體層有效補償，而使得主動層所累積的應力變小，從而降低VCSEL的磊晶層的缺陷或差排發生機率，因而提高VCSEL的可靠度。 The lattice constant of the materials listed above can be changed. For example, by adjusting the amount of ingredients in the material, the lattice constant must match, be smaller than, or be larger than the GaAs substrate. Therefore, the first semiconductor layer can be determined according to the stress of the well layer. Tensile stress, compressive stress, or even no obvious stress is generated, so that the stress in the well layer can be effectively compensated by the first semiconductor layer, so that the accumulated stress in the active layer becomes smaller, thereby reducing defects or defects in the epitaxial layer of the VCSEL. The probability of differential dislocation occurs, thus improving the reliability of VCSEL.

應力總和的計算方式為：先將每一層的應力值乘以其厚度而得到乘積值，接著將所有拉伸應力的乘積值減去所有壓縮應力的乘積值而得到應力總和(為絕對值)。 The calculation method of the stress sum is: first multiply the stress value of each layer by its thickness to obtain the product value, and then subtract the product value of all compressive stresses from the product value of all tensile stresses to obtain the stress sum (as an absolute value).

若只考量主動層本身的應力，原則上只要主動層本身應力總和變小即可；一般而言，主動層本身應力總和變小，VCSEL的應力總和也會降低；不過，若主動層外的磊晶層會提供相當的應力，則可透過適當選擇井層及/或第一半導體層的材料、材料成分比例、層數與其厚度，使主動層產生適當的應力與應力大小，如此主動層也能適度補償主動層外的磊晶層的應力。 If only the stress of the active layer itself is considered, in principle, as long as the sum of the stresses of the active layer itself becomes smaller; generally speaking, when the sum of the stresses of the active layer itself becomes smaller, the sum of the stresses of the VCSEL will also reduce; however, if the Lei outside the active layer The crystal layer will provide considerable stress. By appropriately selecting the materials of the well layer and/or the first semiconductor layer, the proportion of material components, the number of layers, and their thickness, the active layer can generate appropriate stress and stress magnitude. In this way, the active layer can also Moderately compensates the stress of the epitaxial layer outside the active layer.

以表1的InGaP而言，假設莫耳數比在In：Ga=51：49的情形下，InGaP會剛好晶格匹配於GaAs基板；若要使InGaP的晶格常數大於GaAs基板，則須把In的含量再提高(Ga含量變少)，如此第一半導體層就能產生壓縮應力；若要使InGaP的晶格常數小於GaAs基板，則須把Ga的含量再提高(In含量變少)，如此第一半導體層就能產生拉伸應力。 Taking InGaP in Table 1 as an example, assuming that the molar ratio is In:Ga=51:49, InGaP will just lattice match the GaAs substrate; if you want to make the lattice constant of InGaP larger than the GaAs substrate, you must If the In content is further increased (Ga content becomes less), the first semiconductor layer can generate compressive stress; if the lattice constant of InGaP is smaller than the GaAs substrate, the Ga content must be increased (In content becomes less), In this way, the first semiconductor layer can generate tensile stress.

原則上障壁層203的一部分或全部設置第一半導體層S1。例如，在圖4a中顯示了兩種設置第一半導體層S1於障壁層中的方式，一種是在障壁層203內的一部分形成第一半導體層S1，如圖4a中鄰近於上間隔層104的障壁層203；另一種是在障壁層203的全部形成第一半導體層S1，如圖4a中鄰近於下間隔層103的障壁層203；以上提到的第一半導體層部分形成或整體形成於障壁層的方式能擇一運用於一障壁層或多個障壁層中，比如一些的障壁層是以其一部分形成第一半導體層，其他的障壁層是以其整體作為第一半導體層；也可如圖4b所示，在各障壁層皆設置第一半導體層；要注意的是，第一半導體層的設置數目、設置方式與設置處視井層應力的產生位置與應力大小而定，不限於本實施例所述的數目與位置。 In principle, part or all of the barrier layer 203 is provided with the first semiconductor layer S1. For example, Figure 4a shows two ways of arranging the first semiconductor layer S1 in the barrier layer. One is to form the first semiconductor layer S1 in a part of the barrier layer 203, such as adjacent to the upper spacer layer 104 in Figure 4a. Barrier layer 203; the other is to form the first semiconductor layer S1 on the entire barrier layer 203, as shown in Figure 4a The barrier layer 203 is close to the lower spacer layer 103; the above-mentioned method of partially forming or entirely forming the first semiconductor layer in the barrier layer can be applied to one barrier layer or multiple barrier layers. For example, some barrier layers are A part of the first semiconductor layer is formed, and the other barrier layers are formed as a whole as the first semiconductor layer; as shown in Figure 4b, the first semiconductor layer can also be provided on each barrier layer; it should be noted that the first semiconductor layer The number, manner and location of the layers depend on the location and magnitude of stress in the well layer, and are not limited to the number and location described in this embodiment.

在此實施例中，藉由在障壁層203中***含磷的第一半導體層S1，障壁層203可對井層201進行應力補償，例如井層201是產生壓縮應力時，則使障壁層203中的第一半導體S1產生拉伸應力(Tensile Strain)，如此主動層20所累積的應力總和變小；此外，障壁層203因***含磷的第一半導體層S1，能進一步擴大對井層的能帶差距，從而增加主動層的載子侷限性(Carrier Confinement)，當在高溫操作時，也能將具有較高能量的載子侷限在量子井中，因此在高溫操作時，VCSEL的發光效率變得更好。 In this embodiment, by inserting the first semiconductor layer S1 containing phosphorus into the barrier layer 203, the barrier layer 203 can perform stress compensation on the well layer 201. For example, when the well layer 201 generates compressive stress, the barrier layer 203 The first semiconductor S1 in the layer generates tensile stress (Tensile Strain), so that the total stress accumulated in the active layer 20 becomes smaller; in addition, the barrier layer 203 can further expand the impact on the well layer due to the insertion of the phosphorus-containing first semiconductor layer S1. The energy band gap increases the carrier confinement (Carrier Confinement) of the active layer. When operating at high temperature, it can also confine carriers with higher energy in the quantum well. Therefore, when operating at high temperature, the luminous efficiency of VCSEL becomes Better.

要注意的是，井層會產生壓縮應力或拉伸應力是由井層材料、井層材料成份或基板的材料決定，也就是若井層產生的是拉伸應力情形中，第一半導體層則應產生壓縮應力；同樣的，若井層產生的是壓縮應力，則第一半導體層則須提供拉伸應力；若第一半導體層的能隙較大，還能增進VCSEL的載子侷限能力。 It should be noted that whether the well layer will produce compressive stress or tensile stress is determined by the well layer material, the well material composition or the material of the substrate. That is, if the well layer produces tensile stress, the first semiconductor layer should produce Compressive stress; similarly, if the well layer generates compressive stress, the first semiconductor layer must provide tensile stress; if the energy gap of the first semiconductor layer is larger, it can also improve the carrier confinement capability of the VCSEL.

在一些實施例中，井層的厚度可為1nm~30nm，較佳可為2nm~15nm或3nm~10nm，其中井層的厚度可根據井層材料、井層材料成份或井層所需波長而調整。 In some embodiments, the thickness of the well layer may be 1 nm ~ 30 nm, preferably 2 nm ~ 15 nm or 3 nm ~ 10 nm, wherein the thickness of the well layer may be determined according to the well layer material, the well layer material composition or the required wavelength of the well layer. adjust.

如上所述，障壁層203不僅能對井層201做應力補償，而且障壁層203對井層201做應力補償的程度還能被調整，具體而言，當障壁層203的材料、材料成份或厚度被改變時，井層201被障壁層203應力補償的程度也會改變；其中障壁層203的厚度可為1nm~30nm，較佳可為2nm~15nm或3nm~10nm，以減少或消除主動層20的應力。 As mentioned above, the barrier layer 203 can not only perform stress compensation on the well layer 201, but the degree of stress compensation of the barrier layer 203 on the well layer 201 can also be adjusted. Specifically, when the material, material composition or thickness of the barrier layer 203 When being changed, the degree of stress compensation of the well layer 201 by the barrier layer 203 will also change; the thickness of the barrier layer 203 can be 1nm~30nm, preferably 2nm~15nm or 3nm~10nm, to reduce or eliminate the active layer 20 stress.

[實施例2] [Example 2]

圖5a是顯示障壁層跟井層之間具有中間層之一實施例的示意圖，圖5b是顯示圖5a的障壁層、中間層與井層的能帶關係示意圖；圖6a是顯示障壁層中***GaAsP中間層之一實施例的示意圖，圖6b是顯示圖6a的障壁層、中間層與井層的能帶關係示意圖；圖7a是顯示障壁層中***AlGaAsP中間層之一實施例的示意圖，圖7b是顯示圖7a的障壁層、中間層與井層的能帶關係示意圖。 Figure 5a is a schematic diagram showing an embodiment of having an intermediate layer between the barrier layer and the well layer; Figure 5b is a schematic diagram showing the energy band relationship between the barrier layer, the intermediate layer and the well layer in Figure 5a; Figure 6a is a diagram showing the insertion in the barrier layer A schematic diagram of an embodiment of the GaAsP interlayer. Figure 6b shows the barrier layer of Figure 6a. Schematic diagram of the energy band relationship between the intermediate layer and the well layer; Figure 7a is a schematic diagram showing an embodiment of inserting an AlGaAsP intermediate layer into the barrier layer; Figure 7b is a schematic diagram showing the energy band relationship between the barrier layer, the intermediate layer and the well layer in Figure 7a.

相較於圖3a，圖5a是在井層201與障壁層203之間更***中間層205，障壁層203不會與井層201直接接觸。或者圖6a所示，在主動層20的障壁層203中設置中間層205，換言之，就是依序形成障壁層203、中間層205與障壁層203的層狀結構；其中，中間層205的優選材料參表2共計20種，當作中間層的材料是表2所列的至少一種材料或兩種以上材料的適當配合。較佳的，實施例2能與實施例1結合運用，也就是中間層包含表2的至少一種材料，且障壁層則是表1的至少1種材料。 Compared with Fig. 3a, in Fig. 5a, an intermediate layer 205 is inserted between the well layer 201 and the barrier layer 203. The barrier layer 203 will not be in direct contact with the well layer 201. Or as shown in Figure 6a, an intermediate layer 205 is provided in the barrier layer 203 of the active layer 20. In other words, a layered structure of the barrier layer 203, the intermediate layer 205 and the barrier layer 203 is formed in sequence; wherein, the preferred material of the intermediate layer 205 Refer to Table 2 for a total of 20 materials. The material used as the middle layer is at least one material listed in Table 2 or an appropriate combination of two or more materials. Preferably, Embodiment 2 can be used in combination with Embodiment 1, that is, the middle layer includes at least one material in Table 2, and the barrier layer is at least one material in Table 1.

表2逐一列舉的材料的晶格常數能被改變成小於、大於或等於GaAs的晶格常數，因此中間層可以被決定是產生拉伸應力、壓縮應力或甚至不產生應力。 The lattice constants of the materials listed in Table 2 can be changed to be less than, greater than or equal to the lattice constant of GaAs, so the intermediate layer can be determined to produce tensile stress, compressive stress or even no stress.

在一些實施例中，障壁層203及中間層205的材料可為相同或者不同，兩者的材料較佳為不同。即使障壁層203及中間層205的材料為相同的情況下，則兩者材料的成份比例亦不同，例如障壁層203及中間層205的材料為AlGaAsP時，則在鋁、鎵、砷或磷的成份比例為不同。 In some embodiments, the materials of the barrier layer 203 and the intermediate layer 205 may be the same or different. The materials of the barrier layer 203 and the intermediate layer 205 are preferably different. Even if the materials of the barrier layer 203 and the intermediate layer 205 are the same, the composition ratios of the two materials are also different. For example, when the materials of the barrier layer 203 and the intermediate layer 205 are AlGaAsP, the proportions of aluminum, gallium, arsenic or phosphorus will be different. Ingredient ratios vary.

雖然圖5a顯示了主動層20的最上層與最下層為障壁層203的實施方式，但主動層20的最上層及/或最下層也可以是井層201；主動層20的最上層或最下層是井層201時，該井層201可以實質接觸於下間隔層103或上間隔層104；當主動層20的最上層與最下層皆為井層201時，井層201可以實質接觸於下間隔層103及上間隔層104。 Although FIG. 5 a shows an embodiment in which the uppermost layer and the lowermost layer of the active layer 20 are barrier layers 203 , the uppermost layer and/or the lowermost layer of the active layer 20 can also be the well layer 201 ; the uppermost layer or the lowermost layer of the active layer 20 When it is the well layer 201, the well layer 201 can be in substantial contact with the lower spacer layer 103 or the upper spacer layer 104; when the uppermost layer and the lowermost layer of the active layer 20 are both the well layer 201, the well layer 201 can be in substantial contact with the lower spacer. layer 103 and upper spacer layer 104.

在一實施例中，如圖5b所示，中間層205為GaAsP時，中間層205的導電帶能階是位於井層201與障壁層203的導電帶能階之間。中間層因不含鋁故不易氧化，且能補償井層的應力；例如，井層是具有壓縮應力時，令中間層具有拉伸應力，以降低在主動層的應力總和。 In one embodiment, as shown in FIG. 5 b , when the intermediate layer 205 is made of GaAsP, the conductive band energy level of the intermediate layer 205 is located between the conductive band energy levels of the well layer 201 and the barrier layer 203 . The middle layer is not Because it contains aluminum, it is not easily oxidized and can compensate for the stress in the well layer; for example, when the well layer has compressive stress, the middle layer has tensile stress to reduce the total stress in the active layer.

在一些實施例中，如圖6a、圖7a所示，當中間層205的材料分別是GaAsP或AlGaAsP，則對應圖6a、7a的能帶示意圖分別顯示於圖6b、圖7b所示；中間層205不限於是提供拉伸應力的材料，還可根據量子井的能帶差距及應力補償程度等而使用提供壓縮應力或無明顯應力的材料。 In some embodiments, as shown in Figures 6a and 7a, when the material of the intermediate layer 205 is GaAsP or AlGaAsP respectively, the energy band diagrams corresponding to Figures 6a and 7a are shown in Figures 6b and 7b respectively; the intermediate layer 205 is not limited to materials that provide tensile stress. Materials that provide compressive stress or no obvious stress can also be used based on the energy band gap of the quantum well and the degree of stress compensation.

中間層205的厚度可為1nm~30nm，較佳可為2nm~15nm或3nm~10nm，且在兩相鄰的井層51之間的中間層205與障壁層203的厚度總和可介於1nm~30nm，較佳介於2nm~15nm或介於3nm~10nm。 The thickness of the middle layer 205 can be 1nm~30nm, preferably 2nm~15nm or 3nm~10nm, and the total thickness of the middle layer 205 and the barrier layer 203 between two adjacent well layers 51 can be between 1nm~ 30nm, preferably between 2nm~15nm or between 3nm~10nm.

原則上，主動層的井層、障壁層與中間層經應力補償後的應力總和會低於未補償時的應力總和，因此中間層能根據井層與障壁層的應力種類與大小來決定是要產生壓縮應力或拉伸應力或不產生應力。應力總和可根據障壁層、中間層、井層等的材料、材料成份比例、層數或厚度而有改變，故在此不作限制。 In principle, the sum of the stresses of the well layer, barrier layer and intermediate layer of the active layer after stress compensation will be lower than the sum of uncompensated stress. Therefore, the intermediate layer can be determined based on the type and magnitude of stress in the well layer and barrier layer. Generate compressive stress or tensile stress or no stress. The total stress can change according to the materials, material composition ratio, number of layers or thickness of the barrier layer, intermediate layer, well layer, etc., so there is no limit here.

實施例2雖是以中間層設置在單一主動層(VCSEL)內來作為示例，而在多主動層(VCSEL)的實施例中，實施例2亦能使用於多主動層中一層、一些主動層或各主動層之中。 Although Embodiment 2 takes the middle layer being arranged in a single active layer (VCSEL) as an example, in the embodiment of multiple active layers (VCSEL), Embodiment 2 can also be used in one or some active layers in multiple active layers. Or in each active layer.

[實施例3] [Example 3]

參閱圖8a，圖8a為顯示以第二半導體層作為障壁層，中間層是位於第二半導體層與井層之間的一實施例示意圖，參閱圖8b，圖8b為顯示以第二半導體層作為障壁層，中間層***於障壁層之中的一實施例示意圖。 Refer to FIG. 8a. FIG. 8a is a schematic diagram showing an embodiment in which the second semiconductor layer is used as the barrier layer and the intermediate layer is located between the second semiconductor layer and the well layer. Refer to FIG. 8b. FIG. 8b is a schematic diagram showing that the second semiconductor layer is used as the barrier layer. Barrier layer, a schematic diagram of an embodiment in which the intermediate layer is inserted into the barrier layer.

在實施例3中，是以VCSEL為例，實施例3在結構方面，能比照實施例1~2於多層結構100與主動層20的量子井結構的各實施例。 In Embodiment 3, a VCSEL is taken as an example. In terms of structure, Embodiment 3 can be compared with Embodiments 1 to 2 in terms of the quantum well structure of the multilayer structure 100 and the active layer 20 .

材料方面，實施例3的第二半導體層S2與中間層205則有別於實施例1的第一半導體層S1與中間層；具體而言，第二半導體層S2的含磷材料是僅限定於GaAsP一種，第二半導體層S2是障壁層203的至少一部分或全部；中間層205的材料則是表3所列的19種材料的至少一種材料或兩種材料以上的配合。井層201則與實施例1的優選材料相同，當作井層的優選材料是InGaAs、InAlGaAs、GaAsSb、GaAs、AlGaAs、AlGaAsSb、GaAsP、InGaAsP或以上材料的配合。 In terms of materials, the second semiconductor layer S2 and the intermediate layer 205 of Embodiment 3 are different from the first semiconductor layer S1 and the intermediate layer of Embodiment 1; specifically, the phosphorus-containing material of the second semiconductor layer S2 is limited to One kind of GaAsP, the second semiconductor layer S2 is at least part or all of the barrier layer 203; the material of the intermediate layer 205 is at least one of the 19 materials listed in Table 3 or a combination of two or more materials. The preferred material of the well layer 201 is the same as that of Embodiment 1. The preferred material of the well layer 201 is InGaAs, InAlGaAs, GaAsSb, GaAs, AlGaAs, AlGaAsSb, GaAsP, InGaAsP or a combination of the above materials.

上表3所列舉的材料中，除了AlGaAs只能產生壓縮應力與GaAs不產生應力之外，其餘的材料的晶格常數能被改變成小於、大於或甚至等於GaAs基板的晶格常數，因此中間層可以被決定是產生拉伸應力、壓縮應力或甚至不產生應力。 Among the materials listed in Table 3 above, except for AlGaAs which can only produce compressive stress and GaAs which does not produce stress, the lattice constants of the other materials can be changed to be less than, greater than or even equal to the lattice constant of the GaAs substrate, so the middle Layers can be determined to produce tensile stress, compressive stress or even no stress.

在一些實施例，井層201是選用InGaAs或InAlGaAs時，能更進一步增進VCSEL的發光效率或頻寬。且藉由在障壁層203***GaAsP層(第二半導體層)，且基板是GaAs基板，則晶格常數小於GaAs基板的GaAsP層會產生拉伸應力，藉以對井層201進行應力補償，從而減少或消除主動層20中的應力總和，而提升雷射二極體的可靠度。 In some embodiments, when the well layer 201 is made of InGaAs or InAlGaAs, the luminous efficiency or bandwidth of the VCSEL can be further improved. And by inserting a GaAsP layer (second semiconductor layer) in the barrier layer 203, and the substrate is a GaAs substrate, the GaAsP layer with a lattice constant smaller than the GaAs substrate will generate tensile stress, thereby compensating the stress of the well layer 201, thereby reducing Or the total stress in the active layer 20 can be eliminated to improve the reliability of the laser diode.

在一實施例中，當中間層205的導電帶能階高於材質是GaAsP的障壁層203的導電帶能階，中間層205與井層201的能帶差距則會大於GaAsP障壁層203與井層201之間的能帶差距，如此能提高量子井侷限載子的能力，增進半導體雷射二極體的高溫特性或可靠度。 In one embodiment, when the conductive band energy level of the intermediate layer 205 is higher than the conductive band energy level of the barrier layer 203 made of GaAsP, the energy band gap between the intermediate layer 205 and the well layer 201 will be greater than the energy band gap between the GaAsP barrier layer 203 and the well layer. The energy band gap between the layers 201 can improve the ability of the quantum well to confine carriers and improve the high-temperature characteristics or reliability of the semiconductor laser diode.

實施例3雖是以單一主動層中的井層、障壁層與中間層作為示例，而在多主動層的實施例中，實施例3亦能使用於多主動層中的一主動層、一些主動層或各主動層之中。 Although Embodiment 3 takes the well layer, barrier layer and intermediate layer in a single active layer as an example, in the embodiment of multiple active layers, Embodiment 3 can also be used in one active layer, some active layers in multiple active layers. layer or active layer.

[實施例4] [Example 4]

井層、中間層與障壁層是InGaAs、AlGaAs與GaAsP，且AlGaAs中間層設置於GaAsP障壁層之中；GaAsP能提供拉伸應力，減少主動層及半導體雷射中的應力總和，並且減少半導體雷射中磊晶層的差排或者缺陷。AlGaAs則能提高與井層之間的能帶差距，藉此提高量子井侷限載子的能力以增進半導體雷射二極體的高溫特性。 The well layer, intermediate layer and barrier layer are InGaAs, AlGaAs and GaAsP, and the AlGaAs intermediate layer is set in the GaAsP barrier layer; GaAsP can provide tensile stress, reduce the total stress in the active layer and semiconductor laser, and reduce the semiconductor laser Hit dislocations or defects in the epitaxial layer. AlGaAs can increase the energy band gap between the quantum well and the well layer, thereby improving the ability of the quantum well to confine carriers to improve the high-temperature characteristics of the semiconductor laser diode.

[實施例5] [Example 5]

井層與障壁層是InGaAs與AlGaAsP(無設置中間層)；AlGaAsP障壁層能提供拉伸應力，減少主動層或半導體雷射二極體中的應力總和，能減少半導體雷射二極體中磊晶層的缺陷或差排。AlGaAsP障壁層則能提高與InGaAs井層之間的能帶差距，藉此提高量子井侷限載子的能力以增進半導體雷射二極體的高溫特性。或者，當不需再把與量子井的能帶差距調大時，AlGaAsP障壁層中鋁的含量可被適當調低，半導體雷射二極體的主動層被氧化的機率則也隨之變低，進而增進半導體雷射二極體的可靠度。 The well layer and barrier layer are InGaAs and AlGaAsP (no intermediate layer is provided); the AlGaAsP barrier layer can provide tensile stress and reduce the total stress in the active layer or semiconductor laser diode. It can reduce defects or misalignment in the epitaxial layer in semiconductor laser diodes. The AlGaAsP barrier layer can increase the energy band gap with the InGaAs well layer, thereby improving the ability of the quantum well to confine carriers to improve the high-temperature characteristics of the semiconductor laser diode. Alternatively, when there is no need to increase the energy band gap between the quantum well and the quantum well, the aluminum content in the AlGaAsP barrier layer can be appropriately reduced, and the probability of the active layer of the semiconductor laser diode being oxidized will also be reduced. , thereby improving the reliability of semiconductor laser diodes.

[實施例6] [Example 6]

參閱圖9，圖9為顯示具有多主動層的主動區的VCSEL(多接面VCSEL)的一實施例示意圖。 Referring to FIG. 9 , FIG. 9 is a schematic diagram showing an embodiment of a VCSEL (multi-junction VCSEL) with an active region having multiple active layers.

如圖9所示，主動區A包含主動層20、21，其中，各主動層20及/或21本身能套用實施例1之關於第一半導體層S1的各實施例、實施例2之關於中間層的各實施例及實施例3之關於第二半導體層S2的各實施例的至少其中之一，相關內容請參前文所述；要注意的是，在多主動層(多接面)的實施例中，如表4所示，第一半導體層的材料除了表1所列的17種材料之外更包含GaAsP。 As shown in FIG. 9 , the active area A includes active layers 20 and 21 , wherein each active layer 20 and/or 21 itself can apply the various embodiments of Embodiment 1 regarding the first semiconductor layer S1 and the methods of Embodiment 2 regarding the intermediate layer. For each embodiment of the layer and at least one of the embodiments of the second semiconductor layer S2 in Embodiment 3, please refer to the above description for relevant content; it should be noted that in the implementation of multiple active layers (multiple junctions) In this example, as shown in Table 4, the material of the first semiconductor layer includes GaAsP in addition to the 17 materials listed in Table 1.

多主動層的設置數目不限於兩層，也能在三層、四層或五層以上，其中在兩相鄰的主動層或每兩相鄰的主動層之間具有磊晶區；在一些實施例中，磊晶區中至少設置穿隧接面層25；多主動層有助於提高發光功率及功率轉換效率(power conversion efficiency)，但主動層的設置數目越多，應力也越容易累積，而透過適當決定井層、第一半導體層S1或第二半導體層S2的材料、材料成分比例、層數或厚度，能降低主動層或VCSEL的應力總和。 The number of multi-active layers is not limited to two, but can also be three, four or five layers, where there is an epitaxial region between two adjacent active layers or between every two adjacent active layers; in some implementations In this example, at least a tunnel junction layer 25 is provided in the epitaxial region; multiple active layers help to improve the luminous power and power conversion efficiency (power conversion efficiency), but the more active layers are provided, the easier it is for stress to accumulate. By appropriately determining the materials, material composition ratios, number of layers, or thicknesses of the well layer, the first semiconductor layer S1 or the second semiconductor layer S2, the total stress of the active layer or VCSEL can be reduced.

雖然圖9還顯示了磊晶區中更設置氧化層24與間隔層261~263，但氧化層24或間隔層261~263是根據實際需求而選擇性的配置，比如間隔層261~263通常是用來調整光的相位(optical phase)或當作光的侷限層或載子的侷限層；圖9是顯示氧化層24與間隔層261~263的較佳實施例，其中，間隔層261、262、263能分別***主動層20與氧化層24之間、氧化層24與穿隧接面層25之間、穿隧接面層25與主動層21之間之間。在三層以上的主動層的情形下，任兩相鄰的主動層之間也能選擇性或進一步形成氧化層及/或間隔層，氧化層及/或間隔層的具體實施方式除可參照前述，也能根據實據需求做改變。 Although FIG. 9 also shows that the oxide layer 24 and the spacer layers 261 ~ 263 are further provided in the epitaxial region, the oxide layer 24 or the spacer layers 261 ~ 263 are selectively configured according to actual needs. For example, the spacer layers 261 ~ 263 are usually Used to adjust the optical phase of light or as a confinement layer of light or a confinement layer of carriers; Figure 9 shows a preferred embodiment of the oxide layer 24 and the spacer layers 261~263, where the spacer Layers 261, 262, and 263 can be respectively inserted between the active layer 20 and the oxide layer 24, between the oxide layer 24 and the tunnel junction layer 25, and between the tunnel junction layer 25 and the active layer 21. In the case of three or more active layers, an oxide layer and/or a spacer layer can also be selectively or further formed between any two adjacent active layers. In addition to the specific implementation of the oxide layer and/or spacer layer, please refer to the above. , and can also be changed according to actual needs.

在一些實施例中，在與主動層20及/或主動層21相鄰的間隔層261、263中設置第一半導體層；或者在主動層中也設置第一半導體層，第一半導體層的具體實施方式參照實施例1或2或3所述。 In some embodiments, the first semiconductor layer is provided in the spacer layers 261 and 263 adjacent to the active layer 20 and/or the active layer 21; or the first semiconductor layer is also provided in the active layer. The specific details of the first semiconductor layer The implementation mode is described with reference to Embodiment 1, 2 or 3.

現有技術中，障壁層的常用材料是AlGaAs、GaAsP、GaAs。相較於GaAsP、GaAs，因AlGaAs與井層的能帶差距較大，較能增加載子侷限性(Carrier Confinement)，因而在高溫操作時，AlGaAs障壁層也較能將載子侷限在量子井中，從而使VCSEL的光特性變得更好。但障壁層是AlGaAs時卻會具有壓縮應力，若井層也具有壓縮應力，於是在主動層中會累積過大的壓縮應力，導致VCSEL的磊晶層容易產生缺陷或差排，如此導致VCSEL的可靠度變差，當缺陷或差排過多時會導致VCSEL的光特性變差。提高障壁層中鋁的含量時雖能更擴大能帶差距以提升量子井的載子侷限性，但隨著鋁含量的增加，主動層被氧化的機率也易隨之提高。主動層中鋁發生氧化後會使主動層中產生缺陷，進而易使VCSEL的光特性或可靠度下降。 In the prior art, commonly used materials for barrier layers are AlGaAs, GaAsP, and GaAs. Compared with GaAsP and GaAs, because the energy band gap between AlGaAs and the well layer is large, it can increase carrier confinement (Carrier Confinement). Therefore, during high-temperature operation, the AlGaAs barrier layer is also better at confining carriers in the quantum well. , thereby making the optical characteristics of VCSEL better. However, when the barrier layer is AlGaAs, it will have compressive stress. If the well layer also has compressive stress, excessive compressive stress will accumulate in the active layer, causing the epitaxial layer of the VCSEL to easily produce defects or dislocations, thus affecting the reliability of the VCSEL. Deterioration. When there are too many defects or dislocations, the optical characteristics of VCSEL will deteriorate. Although increasing the aluminum content in the barrier layer can further expand the energy band gap to improve the carrier confinement of the quantum well, as the aluminum content increases, the probability of the active layer being oxidized also increases. The oxidation of aluminum in the active layer will cause defects in the active layer, which will easily reduce the optical characteristics or reliability of the VCSEL.

當障壁層是AlGaAsP(表1所列的一材料)時，相較於障壁層是AlGaAs，當AlGaAsP障壁層與AlGaAs障壁層的鋁含量相同，且井層材料也相同時，AlGaAsP的障壁層對井層的能帶差距會較大，載子侷限性也隨之增加。 When the barrier layer is AlGaAsP (a material listed in Table 1), compared to the barrier layer being AlGaAs, when the aluminum content of the AlGaAsP barrier layer and the AlGaAs barrier layer are the same, and the well layer materials are also the same, the barrier layer of AlGaAsP is The energy band gap of the well layer will be larger, and the carrier limitation will also increase.

當障壁層是AlGaAs時，只能透過提高AlGaAs的鋁含量來擴大其對井層的能帶差距，但鋁含量越高則障壁層也越容易被氧化；而在障壁層設置含磷的第一半導體層S1後，在鋁含量相同的情況下，含磷的障壁層的氧化速率會比未含磷的障壁層來得慢；此外，在鋁含量相同的情況，AlGaAsP對井層的能帶差距比AlGaAs與井層的能帶差距還要大，因此AlGaAsP的鋁的含量不需跟AlGaAs的鋁含量一樣多，此外AlGaAsP還能透過提高含磷量來擴大對井層的能帶差距，如此又能進一步減少鋁含量，因此能進一步降低VCSEL1的主動層20被氧化的機率，減少主動層或VCSEL的缺陷發生機率，降低VCSEL於磊晶層的缺陷有助於增進VCSEL1的可靠度。磷以及鋁的使用量可根據量子井的能帶差距及應力補償程度等考量而有所調整，故在此不作限制。 When the barrier layer is AlGaAs, the energy band gap to the well layer can only be widened by increasing the aluminum content of AlGaAs. However, the higher the aluminum content, the easier it is for the barrier layer to be oxidized; and a first layer containing phosphorus is provided in the barrier layer. After the semiconductor layer S1, under the same aluminum content, the oxidation rate of the barrier layer containing phosphorus will be slower than that of the barrier layer without phosphorus; in addition, under the same aluminum content, the energy band gap of AlGaAsP to the well layer is smaller than that of the barrier layer without phosphorus. The energy band gap between AlGaAs and the well layer is even larger, so the aluminum content of AlGaAsP does not need to be as much as that of AlGaAs. In addition, AlGaAsP can also expand the energy band gap of the well layer by increasing the phosphorus content, which can Further reducing the aluminum content can further reduce the probability of the active layer 20 of the VCSEL 1 being oxidized and reduce the occurrence of defects in the active layer or VCSEL. The efficiency and reducing the defects of VCSEL in the epitaxial layer will help improve the reliability of VCSEL1. The usage amounts of phosphorus and aluminum can be adjusted based on considerations such as the energy band gap of the quantum well and the degree of stress compensation, so there is no limit here.

同樣地，當形成於障壁層203的第一半導體層是使用表1所列的其他任一的含磷材料，也具有增加VCSEL1的可靠度的效果。 Similarly, when the first semiconductor layer formed in the barrier layer 203 is made of any other phosphorus-containing material listed in Table 1, it also has the effect of increasing the reliability of the VCSEL 1 .

[實施例7] [Example 7]

圖10a是同時顯示第一半導體層形成於主動層之上及之下的一實施例的示意圖。圖10b顯示第一半導體層形成於主動層與下間隔層之間的一實施例的示意圖。 FIG. 10a is a schematic diagram showing an embodiment in which the first semiconductor layer is formed above and below the active layer at the same time. FIG. 10b shows a schematic diagram of an embodiment in which the first semiconductor layer is formed between the active layer and the lower spacer layer.

圖10a與圖10b是以VCSEL為例。如圖10a所示，於主動區之上及之下皆設置第一半導體層S1；在主動區之上及/或之下的第一半導體層的材料為表5所列的20種材料的至少一種材料或至少兩種材料以上的配合；表5所列的20種材料是包含表1的17種材料以及GaAsP、AlGaAs及GaAs。 Figures 10a and 10b take VCSEL as an example. As shown in Figure 10a, a first semiconductor layer S1 is disposed above and below the active region; the material of the first semiconductor layer above and/or below the active region is at least one of the 20 materials listed in Table 5. One material or a combination of at least two or more materials; the 20 materials listed in Table 5 include the 17 materials in Table 1 as well as GaAsP, AlGaAs and GaAs.

在一些實施例中，如圖10a所示，上間隔層104的全部為第一半導體層S1，第一半導體層S1的一面並實質接觸於主動層20；或者，下間隔層103的其中一部分是第一半導體層S1，第一半導體層S1可以非實質接觸於主動層20，也就是第一半導體層S1與主動層20之間是下間隔層103的一部分。下間隔層103或上間隔層104是直接或間接接觸於主動層20是根據實施需要而定。當第一半導體層S1在下間隔層103或上間隔層104中時，第一半導體層S1是直接或間接接觸於主動層20是根據實施需要而定。 In some embodiments, as shown in Figure 10a, the entire upper spacer layer 104 is the first semiconductor layer S1, and one side of the first semiconductor layer S1 is substantially in contact with the active layer 20; or, a part of the lower spacer layer 103 is The first semiconductor layer S1 may be in non-substantial contact with the active layer 20 , that is, a part of the lower spacer layer 103 is between the first semiconductor layer S1 and the active layer 20 . Whether the lower spacer layer 103 or the upper spacer layer 104 is in direct or indirect contact with the active layer 20 depends on implementation requirements. When the first semiconductor layer S1 is in the lower spacer layer 103 or the upper spacer layer 104, whether the first semiconductor layer S1 is in direct or indirect contact with the active layer 20 depends on implementation requirements.

在一些實施例中，「上間隔層跟第一半導體層」或「下間隔層跟第一半導體層」的材料可為相同或者不同；即使「上間隔層跟第一半導體層」或「下間隔層跟第一半導體層」的材料為相同的情況下，則兩者材料的成份比例亦可不同。 In some embodiments, the materials of the "upper spacer layer and the first semiconductor layer" or the "lower spacer layer and the first semiconductor layer" can be the same or different; even if the "upper spacer layer and the first semiconductor layer" or the "lower spacer When the materials of the "layer and the first semiconductor layer" are the same, the composition ratios of the two materials may also be different.

在一些實施例中，如圖10b所示，第一半導體層S1是形成於下間隔層103與主動層20之間，但並不限於此，第一半導體層S1也能形成於上間隔層104與主動層20之間(圖未示)。 In some embodiments, as shown in FIG. 10b , the first semiconductor layer S1 is formed between the lower spacer layer 103 and the active layer 20 , but is not limited thereto. The first semiconductor layer S1 can also be formed on the upper spacer layer 104 and active layer 20 (not shown).

在第一半導體層S1與主動層為間接接觸的情形下；雖然原則上，第一半導體層S1越接近於主動層20，提高主動層20的載子侷限能力或應力補償的效果越明顯，不過並不限定第一半導體層S1必須設置在接觸於或鄰近於主動層的磊晶層中如上述的上間隔層或下間隔層。因為上間隔層或下間隔層若較薄或第一半導體層能提供足夠的應力，即使第一半導體層與主動層之間還相隔有磊晶層，第一半導體層還是能對主動層提供一定的載子侷限能力或對降低主動層或VCSEL的應力總和。 In the case where the first semiconductor layer S1 is in indirect contact with the active layer; although in principle, the closer the first semiconductor layer S1 is to the active layer 20, the more obvious the effect of improving the carrier confinement capability or stress compensation of the active layer 20 will be. It is not limited that the first semiconductor layer S1 must be disposed in the epitaxial layer that is in contact with or adjacent to the active layer, such as the above-mentioned upper spacer layer or lower spacer layer. Because if the upper spacer layer or the lower spacer layer is thin or the first semiconductor layer can provide sufficient stress, even if there is an epitaxial layer between the first semiconductor layer and the active layer, the first semiconductor layer can still provide a certain amount of stress to the active layer. The carrier confinement capability or the stress summation that reduces the active layer or VCSEL.

值得說明的是，當第一半導體層S1是設置於主動層20之外，主動層的障壁層或中間層可以使用習知的材料，或於主動層之中設置另一第一半導體層，另一第一半導體層的具體實施方式參實施例1~3的第一半導體層。 It is worth noting that when the first semiconductor layer S1 is disposed outside the active layer 20, the barrier layer or the intermediate layer of the active layer can use conventional materials, or another first semiconductor layer can be disposed in the active layer. For a specific implementation of the first semiconductor layer, refer to the first semiconductor layer in Embodiments 1 to 3.

當井層或雷射元件的磊晶層會產生相當的應力時，透過在雷射元件中應用以上的任一實施例或一些實施例的結合，將主動層或雷射元件的應力總和控制在一定的範圍中；在上述的實施例，比如表1的一些材料在適當條件下會有明顯的載子侷限效應，前文雖有提到關於載子侷限的一些內容，不過分散於前文不同處，因此後文會以一些載子侷限的較佳實施例進行詳細說明。 When the well layer or the epitaxial layer of the laser element will generate considerable stress, by applying any of the above embodiments or a combination of some embodiments in the laser element, the total stress of the active layer or the laser element is controlled to Within a certain range; in the above-mentioned embodiments, for example, some materials in Table 1 will have obvious carrier confinement effects under appropriate conditions. Although some content about carrier confinement has been mentioned in the previous article, it is scattered in different places in the previous article. Therefore, some preferred embodiments of carrier confinement will be described in detail below.

[實施例8] [Example 8]

圖11a是顯示載子侷限層在主動區內的一實施例示意圖，圖11b是顯示載子侷限層在主動區內的另一實施例示意圖，圖11c是顯示載子侷限層在主動區外的一實施例示意圖，圖11d是顯示載子侷限層在主動區外的另一實施例示意圖。 Figure 11a is a schematic diagram showing a carrier confinement layer within the active area. Figure 11b is a schematic diagram showing another embodiment of the carrier confinement layer within the active area. Figure 11c is a schematic diagram showing the carrier confinement layer outside the active area. A schematic diagram of an embodiment. FIG. 11d is a schematic diagram of another embodiment showing the carrier confinement layer outside the active region.

圖11a~11d與圖1b至1e大致相同，其中，含磷的半導體層S1’在實施例8與圖11a~11d中一律稱為載子侷限層CF’，並且圖11a~11d的主動區A’是包含一主動層；多主動層的實施例請參後文的實施例12~15。 Figures 11a to 11d are roughly the same as Figures 1b to 1e. The phosphorus-containing semiconductor layer S1' is uniformly called the carrier confinement layer CF' in Embodiment 8 and Figures 11a to 11d, and the active region A in Figures 11a to 11d ' contains an active layer; for embodiments of multiple active layers, please refer to Embodiments 12 to 15 below.

如圖11a~11d所示，多層結構包含主動區A’、下磊晶區30’與上磊晶區40’，下磊晶區30’與上磊晶區40’位於主動區A’之下及之上；主動區A’ 之面向於下磊晶區30’的一面定義為第一面J1，主動區A’之面向於上磊晶區40’的一面定義為第二面J2，而後文中若單獨稱「主動層的一面」，則代表為第一面及/或第二面；在多主動層的實施例，則還會包含第三面、第四面至第N面，則「主動層的一面」亦是代表第一面至第N面的一者、二者或多者。 As shown in Figures 11a to 11d, the multilayer structure includes an active region A', a lower epitaxial region 30' and an upper epitaxial region 40'. The lower epitaxial region 30' and the upper epitaxial region 40' are located under the active region A'. and above; active area A' The side facing the lower epitaxial region 30' is defined as the first side J1, and the side of the active region A' facing the upper epitaxial region 40' is defined as the second side J2. In the following text, it is referred to as "the side of the active layer" alone. ”, it represents the first side and/or the second side; in the embodiment with multiple active layers, it also includes the third side, the fourth side to the Nth side, then the “side of the active layer” also represents the One, two or more from one side to the Nth side.

當載子侷限層CF’是設置於主動區A’之中，在此設置方式，載子侷限層CF’不論是實質接觸於或靠近於下磊晶區30”，載子侷限層CF’會有載子侷限效果；在一些實施例，載子侷限層CF’甚至能設置於主動層的每一或一些障壁層中。 When the carrier confinement layer CF' is disposed in the active region A', in this arrangement, whether the carrier confinement layer CF' is actually in contact with or close to the lower epitaxial region 30", the carrier confinement layer CF' will There is a carrier confinement effect; in some embodiments, the carrier confinement layer CF' can even be disposed in each or some barrier layers of the active layer.

當載子侷限層CF’是設置於下磊晶區30’或上磊晶區40’之中，在此設置方式，原則上載子侷限層CF’離主動區A’越近，則載子侷限效果較明顯。在一些實施例，載子侷限層的一面可被視為第一面J1或第二面J2，也就是載子侷限層是構成為下磊晶區的最上側部分或構成為上磊晶區的最下側部分；或者，載子侷限層是構成主動區最下側或最上側的部分，換言之，載子侷限層是設置於下磊晶區與主動區之間或設置於於主動區與上磊晶區之間。 When the carrier confinement layer CF' is disposed in the lower epitaxial region 30' or the upper epitaxial region 40', in this arrangement, in principle, the closer the carrier confinement layer CF' is to the active region A', the higher the carrier confinement The effect is more obvious. In some embodiments, one side of the carrier confinement layer can be regarded as the first side J1 or the second side J2, that is, the carrier confinement layer is formed as the uppermost part of the lower epitaxial region or is formed as the upper epitaxial region. The lowermost part; alternatively, the carrier confinement layer is the lowermost or uppermost part of the active region. In other words, the carrier confinement layer is disposed between the lower epitaxial region and the active region or between the active region and the upper between epitaxial regions.

在一些實施例，載子侷限層與第一面J1之間或載子侷限層與第二面J2之間還具有一磊晶層的一部分、一磊晶層或一些磊晶層；較佳的，載子侷限層CF’是表6的17種材料之至少一材料或二材料以上的配合。 In some embodiments, there is also a part of an epitaxial layer, an epitaxial layer or some epitaxial layers between the carrier confinement layer and the first surface J1 or between the carrier confinement layer and the second surface J2; preferably , the carrier confinement layer CF' is at least one material or a combination of two or more materials among the 17 materials in Table 6.

[實施例9] [Example 9]

圖11a~圖11d屬於原則性的實施例示意圖，而具體應用於VCSEL的實施例請參考圖12a~12c。圖12a是顯示載子侷限層設置在下間隔層的一部份的一實施例的示意圖，圖12b是顯示載子侷限層設置在上間隔層的全部的一實施例的示意圖，圖12c是顯示主動層的各障壁層均設置一載子侷限層的示意圖。 Figures 11a to 11d are schematic diagrams of principle embodiments, and for specific embodiments applied to VCSEL, please refer to Figures 12a to 12c. Figure 12a is a schematic diagram showing an embodiment in which the carrier confinement layer is disposed on a part of the lower spacer layer. Figure 12b is a schematic diagram showing an embodiment in which the carrier confinement layer is disposed entirely in the upper spacer layer. Figure 12c is a schematic diagram showing an active A schematic diagram showing that each barrier layer is provided with a carrier confinement layer.

參考圖12a並請配合圖11d所示，圖12a的下間隔層103可視為在圖11d的下磊晶區30’中；如圖12a所示，載子侷限層CF為形成於下間隔層103的一部分，其中載子侷限層CF與第一面J1須處於能將載子侷限於主動層中的一有效距離中，因此不一定要形成實質接觸；在一些實施例中，上間隔層104的全部形成載子侷限層CF，如圖12b所示；而雖圖12c顯示載子侷限層CF設置在各障壁層203的其中一部分，但並不限於此，載子侷限層CF亦能設置於一些障壁層的全部或各障壁層的全部。 Referring to Figure 12a and please cooperate with Figure 11d, the lower spacer layer 103 of Figure 12a can be regarded as being in the lower epitaxial region 30' of Figure 11d; as shown in Figure 12a, the carrier confinement layer CF is formed in the lower spacer layer 103 A part of the carrier confinement layer CF and the first surface J1 must be in an effective distance that can confine the carriers in the active layer, and therefore do not necessarily need to form substantial contact; in some embodiments, the upper spacer layer 104 The carrier confinement layer CF is entirely formed, as shown in FIG. 12b; and although FIG. 12c shows that the carrier confinement layer CF is disposed in a part of each barrier layer 203, it is not limited to this, and the carrier confinement layer CF can also be disposed in some parts of the barrier layer 203. All of the barrier layers or all of each barrier layer.

綜上所述，實施例9是在主動層的一面的附近形成載子侷限層，且當載子侷限層是表6中的至少一材料時，載子侷限層對主動層的導電帶不連續或價電帶不連續變大，因此當電洞或電子注入主動層內，尤其在高溫操作時，電洞或電子會受到載子侷限層的侷限，載子侷限能力變好則VCSEL的光特性也會變好。 To sum up, Embodiment 9 forms a carrier confinement layer near one side of the active layer, and when the carrier confinement layer is at least one of the materials in Table 6, the conductive band of the carrier confinement layer to the active layer is discontinuous. Or the valence band becomes discontinuous, so when holes or electrons are injected into the active layer, especially when operating at high temperatures, the holes or electrons will be confined by the carrier confinement layer. The optical characteristics of the VCSEL will improve as the carrier confinement ability becomes better. It will also get better.

[實施例10] [Example 10]

在實施例10中，主動層的一面之附近形成載子侷限層CF，載子侷限層CF能選自表7或表8所列出的至少一材料或至少二材料的配合，其中表7的材料對電洞的位障(barrier height)大，因此對電洞的侷限效果佳，後文稱載子侷限層(電洞侷限層)。表8的材料對電子的位障(barrier height)大，因此對電子的侷限效果佳，後文稱載子侷限層(電子侷限層)。 In Embodiment 10, a carrier confinement layer CF is formed near one side of the active layer. The carrier confinement layer CF can be selected from at least one material or a combination of at least two materials listed in Table 7 or Table 8, wherein the ones in Table 7 The material has a large barrier height to the holes, so it has a good hole confinement effect, which is hereinafter referred to as the carrier confinement layer (hole confinement layer). The materials in Table 8 have a large barrier height for electrons, so they have a good confinement effect on electrons. They are hereinafter referred to as carrier confinement layers (electron confinement layers).

以圖12a為例，在電洞是經上DBR層105及第二面J2而注入於主動層20的情形，當靠近第一面J1的載子侷限層CF是使用表7的任一材料，由於載子侷限層(電洞侷限層)CF對電洞的位障大，因此電洞繼續往GaAs基板方向移動時，電洞就會受到載子侷限層(電洞侷限層)CF的侷限，因而提升主動層的電洞侷限性；值得一提的是，在上述情形中，當靠近第一面J1的載子侷限層是選用表7的InGaP或AlGaInP，且鄰近於載子侷限層的磊晶層是選用AlGaAs或其他適當材料，由於InGaP與AlGaAs間或AlGaInP與AlGaAs間的介面的電子位障相對小或幾乎沒有位障，因此電子能較不受阻的注入於主動層中，因此雷射元件中的電阻不容易變大。在此情形中，上DBR層105主要是P型，下DBR層102主要是N型。 Taking Figure 12a as an example, in the case where holes are injected into the active layer 20 through the upper DBR layer 105 and the second surface J2, when the carrier confinement layer CF close to the first surface J1 uses any material in Table 7, Since the carrier confinement layer (hole confinement layer) CF has a large potential barrier to the holes, when the holes continue to move toward the GaAs substrate, the holes will be confined by the carrier confinement layer (hole confinement layer) CF. thus promoted Hole limitation of the active layer; it is worth mentioning that in the above case, when the carrier confinement layer close to the first surface J1 is selected from InGaP or AlGaInP in Table 7, and the epitaxial layer adjacent to the carrier confinement layer AlGaAs or other appropriate materials are used. Since the electron barrier at the interface between InGaP and AlGaAs or between AlGaInP and AlGaAs is relatively small or almost non-existent, electrons can be injected into the active layer without hindrance. Therefore, in laser components The resistance is not easy to increase. In this case, the upper DBR layer 105 is mainly P-type and the lower DBR layer 102 is mainly N-type.

同樣也以圖12a為例，在電子是經上DBR層105及第二面J2而注入於主動層20的情形，當靠近第一面J1的載子侷限層CF是使用表8的任一材料，由於載子侷限層CF對電子的位障大(電子侷限層)，因此電子繼續往GaAs基板方向移動時，電子會受到載子侷限層(電子侷限層)CF的侷限，因而提升主動層的電子侷限性。值得一提的是，在上述情形中，當靠近第一面J1的載子侷限層是選用表8的AlGaAsP，且鄰近於載子侷限層的磊晶層是選用AlGaAs或其他適當材料，對電洞而言，由於AlGaAsP與AlGaAs的介面的電洞位障相對小，因此電洞能較不受阻的注入於主動層中，因此雷射元件中的電阻不容易變大。在此情形中，上DBR層105主要是N型，下DBR層102主要是P型。 Also taking Figure 12a as an example, in the case where electrons are injected into the active layer 20 through the upper DBR layer 105 and the second surface J2, when the carrier confinement layer CF close to the first surface J1 uses any material in Table 8 , since the carrier confinement layer CF has a large barrier to electrons (electron confinement layer), when electrons continue to move toward the GaAs substrate, the electrons will be confined by the carrier confinement layer (electron confinement layer) CF, thus improving the active layer Electronic limitations. It is worth mentioning that in the above situation, when the carrier confinement layer close to the first surface J1 is made of AlGaAsP in Table 8, and the epitaxial layer adjacent to the carrier confinement layer is made of AlGaAs or other appropriate materials, the electrical In terms of holes, since the hole barrier at the interface between AlGaAsP and AlGaAs is relatively small, holes can be injected into the active layer without hindrance, so the resistance in the laser element is not easy to increase. In this case, the upper DBR layer 105 is mainly N-type and the lower DBR layer 102 is mainly P-type.

[實施例11] [Example 11]

如圖13所示，實施例11包含兩載子侷限層CF1、CF2，兩載子侷限層CF1、CF2分別形成於靠近主動層20的第一面J1與第二面J2處。在電洞與電子是分別從第二面J2與第一面J1注入主動層的情形下，當載子侷限層(電洞侷限層)CF1與載子侷限層(電子侷限層)CF2是選用表7與表8的至少一材料，如此載子侷限層(電洞侷限層)CF1對電洞的位障與載子侷限層(電子侷限層)CF2對電子的位障均能提高，則電洞與電子的侷限性均得到提升，而能增進雷射元件的特性。 As shown in FIG. 13 , Embodiment 11 includes two carrier confinement layers CF1 and CF2. The two carrier confinement layers CF1 and CF2 are respectively formed near the first surface J1 and the second surface J2 of the active layer 20 . In the case where holes and electrons are injected into the active layer from the second surface J2 and the first surface J1 respectively, when the carrier confinement layer (hole confinement layer) CF1 and the carrier confinement layer (electron confinement layer) CF2 are selected, the table 7 and at least one material in Table 8, so that the potential barrier to the electron hole of the carrier confinement layer (hole confinement layer) CF1 and the potential barrier to electrons of the carrier confinement layer (electron confinement layer) CF2 can be improved, then the hole and electronic limitations are improved, thereby improving the characteristics of laser components.

同理，在電洞與電子是分別自第一面J1與第二面J2注入主動層的情形，當載子侷限層(電子侷限層)CF1、載子侷限層(電洞侷限層)CF2是選用表8與表7中的至少一材料，如此載子侷限層(電子侷限層)CF1對電子的位障(barrier height)與載子侷限層(電洞侷限層)CF2對電洞的位障(barrier height)均能提高，則電洞與電子的侷限性均得到提升，而能增進雷射元件的特性。 In the same way, when holes and electrons are injected into the active layer from the first surface J1 and the second surface J2 respectively, when the carrier confinement layer (electron confinement layer) CF1 and the carrier confinement layer (hole confinement layer) CF2 are Select at least one material from Table 8 and Table 7, so that the carrier confinement layer (electron confinement layer) CF1 has a barrier height for electrons and the carrier confinement layer (hole confinement layer) CF2 has a barrier height for holes. (barrier height) can be increased, the limitations of holes and electrons will be improved, and the characteristics of laser components can be improved.

在一較佳實施例中，當表7選用InGaP或AlGaInP且表8是選用AlGaAsP，且鄰近於載子侷限層CF1與CF2的磊晶層是選用AlGaAs或其他適當的材料，不僅電洞與電子的侷限性都得到明顯提升以外，而且能使電洞與電子較不受阻的注入於主動層中。 In a preferred embodiment, when InGaP or AlGaInP is selected in Table 7 and AlGaAsP is selected in Table 8, and the epitaxial layer adjacent to the carrier confinement layer CF1 and CF2 is selected from AlGaAs or other appropriate materials, not only holes and electrons In addition to significantly improving the limitations, holes and electrons can be injected into the active layer without any hindrance.

當選用表6、表7或表8所列之至少一種材料做為載子侷限層，並將載子侷限層設置在適當位置上，可表現出載子侷限效果，尤其能在高溫操作表現出載子侷限效果。在此情形下，主動層中的障壁層可以使用不會產生應力的材料，或者也可應用第一半導體層在主動層之上、之下或之中，以產生適當的應力而為應力補償，具體實施方式請參第一半導體層的相關實施例。 Selecting at least one of the materials listed in Table 6, Table 7 or Table 8 as the carrier confinement layer, and placing the carrier confinement layer at an appropriate position can exhibit the carrier confinement effect, especially during high temperature operations. Carrier localization effect. In this case, the barrier layer in the active layer can be made of a material that does not generate stress, or the first semiconductor layer can be applied above, below or in the active layer to generate appropriate stress for stress compensation. For specific implementation details, please refer to the related embodiments of the first semiconductor layer.

[實施例12] [Example 12]

圖14a~圖14c是顯示當主動區包含二主動層，載子侷限層設置於兩主動層之間的一些代表性實施例的簡單示意圖。如圖14a所示，主動區A’包含二主動層20’、21’，當載子侷限層CF’是位於主動區A’內時，載子侷限層CF’可位於第二面J2與第三面J3之間，載子侷限層CF’可與第二面J2或第三面J3相隔在能將載子侷限於主動層中的有效距離中；在三層主動層以上的情形，可以僅設置一或二載子侷限層於為相鄰的兩主動層之間，或者在任兩相鄰的主動層之間均可設置一或二載子侷限層。在其他一些實施例如圖14b、14c所示，載子侷限層CF’係直接接觸第二面J2或第三面J3。 Figures 14a to 14c are simple schematic diagrams showing some representative embodiments in which the active region includes two active layers and the carrier confinement layer is disposed between the two active layers. As shown in Figure 14a, the active area A' includes two active layers 20' and 21'. When the carrier confinement layer CF' is located in the active area A', the carrier confinement layer CF' can be located on the second surface J2 and the second surface. Between the three surfaces J3, the carrier confinement layer CF' can be separated from the second surface J2 or the third surface J3 by an effective distance that can confine the carriers in the active layer; in the case of three or more active layers, it can be only One or two carrier confinement layers are disposed between two adjacent active layers, or one or two carrier confinement layers can be disposed between any two adjacent active layers. In some other embodiments, as shown in Figures 14b and 14c, the carrier confinement layer CF' is directly in contact with the second surface J2 or the third surface J3.

必須再次說明，圖14a、14b、14c雖顯示載子侷限層CF’在兩主動層20’、21’之間，但不限於此；在替代的實施例中，載子侷限層CF’能設置於主動層中，若以圖14a而言，載子侷限層CF’是靠近於第二面J2或第三面J3。 It must be noted again that although Figures 14a, 14b, and 14c show that the carrier confinement layer CF' is between the two active layers 20' and 21', it is not limited thereto; in alternative embodiments, the carrier confinement layer CF' can be provided In the active layer, as shown in Figure 14a, the carrier confinement layer CF' is close to the second surface J2 or the third surface J3.

若在三層主動層以上的情形，載子侷限層能形成於每兩相鄰的主動層之間，或者能在一主動層、一些主動層之中分別設置載子侷限層，或者視情形應用以上兩者於具有多主動層的主動區中。 If there are more than three active layers, the carrier confinement layer can be formed between every two adjacent active layers, or the carrier confinement layer can be set separately in one active layer or some active layers, or it can be applied as appropriate. The above two are in an active zone with multiple active layers.

當半導體雷射元件是在兩主動層中設置載子侷限層時，載子侷限層原則上是使用表6所列之至少一種材料。 When a semiconductor laser element is provided with a carrier confinement layer in two active layers, in principle, the carrier confinement layer uses at least one material listed in Table 6.

[實施例13] [Example 13]

圖14d是顯示當主動區包含二主動層，兩載子侷限層設置於兩主動層之間的磊晶區中之一實施例的簡單示意圖。在實施例13，兩載子侷限層之一選自表7的至少一材料而另一是選自表8的至少一材料。 FIG. 14d is a simple schematic diagram showing an embodiment when the active region includes two active layers and two carrier localization layers are disposed in the epitaxial region between the two active layers. In Example 13, one of the two carrier confinement layers is selected from at least one material selected from Table 7 and the other is selected from at least one material selected from Table 8.

[實施例14] [Example 14]

圖14e~圖14h是顯示當主動區包含二主動層，載子侷限層設置於主動區外的一些代表性實施例的簡單示意圖。實施例14以實施例9為基礎，因此實施例14的實施方式請參照實施例9的各相關實施例；此外，在主動區A’之上與之下側能分別設置載子侷限層，兩載子侷限層之一是選自表7的至少一材料而另一是選自表8的至少一材料。 Figures 14e to 14h are simple schematic diagrams showing some representative embodiments in which the active area includes two active layers and the carrier localization layer is disposed outside the active area. Embodiment 14 is based on Embodiment 9, so for the implementation of Embodiment 14, please refer to the relevant embodiments of Embodiment 9; in addition, carrier confinement layers can be respectively provided above and below the active region A'. One of the carrier confinement layers is at least one material selected from Table 7 and the other is at least one material selected from Table 8.

[實施例15] [Example 15]

圖14a屬於原則性的實施例示意圖，而具體應用於VCSEL的實施例請參考圖15，圖15是顯示一載子侷限層設置於兩主動層間的一較佳實施例示意圖。如圖15所示，VCSEL包含兩主動層20、21，兩主動層之間20、21具有磊晶區，磊晶區是介於第二面J2與第三面J3之間；兩主動層20、21間的磊晶區的一種較佳結構如圖9所示，即包含穿隧接面層、氧化層與間隔層；其中，載子侷限層CF是設置於間隔層263的一部分且與第三面J3之間還設置有間隔層263，但不限於此，比如載子侷限層CF的一側也可做為跟主動層21相接觸的一面。圖16是顯示載子侷限層CF也可設置在第二面J2附近的間隔層261中，且載子侷限層CF是在間隔層261的中間部分。 Figure 14a is a schematic diagram of a principle embodiment, and for specific embodiments applied to VCSEL, please refer to Figure 15. Figure 15 is a schematic diagram showing a preferred embodiment in which a carrier confinement layer is disposed between two active layers. As shown in Figure 15, the VCSEL includes two active layers 20 and 21. There is an epitaxial region between the two active layers 20 and 21. The epitaxial region is between the second surface J2 and the third surface J3; the two active layers 20 A preferred structure of the epitaxial region between 21 and 21 is shown in Figure 9, which includes a tunnel junction layer, an oxide layer and a spacer layer; wherein the carrier confinement layer CF is provided in a part of the spacer layer 263 and is connected to the third spacer layer 263. A spacer layer 263 is also provided between the three surfaces J3, but it is not limited to this. For example, one side of the carrier confinement layer CF can also be used as the side in contact with the active layer 21. FIG. 16 shows that the carrier confinement layer CF can also be disposed in the spacer layer 261 near the second surface J2, and the carrier confinement layer CF is in the middle part of the spacer layer 261.

圖14d的一種可能實施例請參圖17a，在兩主動層20、21之間設置載子侷限層CF1、CF2，雖然圖17a是顯示載子侷限層CF1、CF2僅占間隔層261及間隔層263的一部分，但亦能為間隔層261及間隔層263的全部；在一實施例如圖17b所示，於主動區A之上與之下分別設置載子侷限層CF1、CF2，雖然圖17b是顯示載子侷限層CF1、CF2僅占下間隔層103及上間隔層104的一部分，但亦能為下間隔層103及上間隔層104的全部。在一些實施例，任一主動層之上及/或之下也能形成載子侷限層與載子侷限層。 For a possible embodiment of Figure 14d, please refer to Figure 17a. Carrier confinement layers CF1 and CF2 are provided between the two active layers 20 and 21. Although Figure 17a shows that the carrier confinement layers CF1 and CF2 only occupy the spacer layer 261 and the spacer layer. 263, but it can also be all of the spacer layer 261 and the spacer layer 263; in one embodiment, as shown in Figure 17b, carrier confinement layers CF1 and CF2 are respectively provided above and below the active area A, although Figure 17b is It is shown that the carrier confinement layers CF1 and CF2 only occupy a part of the lower spacer layer 103 and the upper spacer layer 104 , but they can also be the entire lower spacer layer 103 and the upper spacer layer 104 . In some embodiments, carrier confinement layers and carrier confinement layers can also be formed above and/or below any active layer.

在一些實施例中，如圖17c所示，在兩相鄰的主動層20、21之間設置載子侷限層CF2、CF3，與在主動區A之上與之下設置載子侷限層CF1、CF4；當電洞是經上間隔層104注入於第四面J4且電子是自第一面J1注入於主動層20，則載子侷限層(電洞侷限層)CF1與載子侷限層(電洞侷限層) CF3為表7中的至少一材料，載子侷限層(電子侷限層)CF2與載子侷限層(電子侷限層)CF4為選自表8的至少一材料。 In some embodiments, as shown in Figure 17c, carrier confinement layers CF2 and CF3 are disposed between two adjacent active layers 20 and 21, and carrier confinement layers CF1 and CF3 are disposed above and below the active region A. CF4; when holes are injected into the fourth surface J4 through the upper spacer layer 104 and electrons are injected into the active layer 20 from the first surface J1, then the carrier confinement layer (hole confinement layer) CF1 and the carrier confinement layer (electronic hole confinement layer) hole localization layer) CF3 is at least one material in Table 7, and the carrier confinement layer (electron confinement layer) CF2 and the carrier confinement layer (electron confinement layer) CF4 are at least one material selected from Table 8.

而電子若是經上間隔層104而注入於第四面J4且電洞則自第一面J1注入於主動層20，則載子侷限層(電子侷限層)CF1與載子侷限層(電子侷限層)CF3選自表8中的至少一材料，則載子侷限層CF2(電洞侷限層)與載子侷限層(電洞侷限層)CF4為選自表7與的至少一材料。 If electrons are injected into the fourth surface J4 through the upper spacer layer 104 and holes are injected into the active layer 20 from the first surface J1, then the carrier confinement layer (electron confinement layer) CF1 and the carrier confinement layer (electron confinement layer) ) CF3 is selected from at least one material in Table 8, then the carrier confinement layer CF2 (hole confinement layer) and carrier confinement layer (hole confinement layer) CF4 are at least one material selected from Table 7 and.

[實施例16] [Example 16]

參考圖18，圖18是顯示現有EEL的一種多層結構的示意圖，參考圖19a，圖19a是顯示EEL的主動層之上與之下皆設有第一半導體層之一實施例的示意圖，參考圖19b，圖19b是顯示EEL的主動層之上與之下皆設有載子侷限層之一實施例的示意圖。圖18所示的半導體雷射元件是EEL3，如圖18所示，EEL3包含GaAs基板10與多層結構300；多層結構300由下而上依序更包括下披覆層(lower cladding layer)301、下光電侷限層302(lower Separated Confinement Hetero-Structure)、主動層20、上光電侷限層303(upper Separated Confinement Hetero-Structure)、上披覆層(upper cladding layer)304與歐姆接觸層305，其中主動層20是介於下光電侷限層302與上光電侷限層303之間。 Referring to Figure 18, Figure 18 is a schematic diagram showing a multi-layer structure of a conventional EEL. Referring to Figure 19a, Figure 19a is a schematic diagram showing an embodiment of an EEL with a first semiconductor layer both above and below the active layer. Refer to Figure 19b. FIG. 19b is a schematic diagram showing an embodiment in which carrier confinement layers are provided above and below the active layer of the EEL. The semiconductor laser element shown in Figure 18 is EEL3. As shown in Figure 18, EEL3 includes a GaAs substrate 10 and a multilayer structure 300; the multilayer structure 300 further includes a lower cladding layer 301, The lower photoelectric confinement layer 302 (lower Separated Confinement Hetero-Structure), the active layer 20, the upper photoelectric confinement layer 303 (upper Separated Confinement Hetero-Structure), the upper cladding layer (upper cladding layer) 304 and the ohmic contact layer 305, among which the active layer Layer 20 is between the lower optoelectronic confinement layer 302 and the upper optoelectronic confinement layer 303 .

當EEL3與VCSEL1的主動層是量子井結構時，由於兩者的量子井結構相同，因此第一半導體層之實施於VCSEL之各實施例，亦能直接實施在EEL3中；比如EEL3的障壁層的一部分或全部設置第一半導體層，此外井層的優選材料亦相同，第一半導體層的設置原則與示範性的一些實施例在實施例1有詳盡的說明，請參照；或者，EEL3的障壁層的一部分或全部設置第二半導體層，且井層與中間層的優選材料亦相同於實施例3的井層與中間層，第二半導體層的設置原則與示範性的一些實施例在實施例3有詳盡的說明，請參照；或者，EEL3的主動層中更設置中間層，中間層的設置原則與示範性的一些實施例在實施例2有詳盡的說明，請參照；或者，EEL3之相鄰的兩主動層之間設置第一(二)半導體層，第一(二)半導體層於多主動層的設置原則與示範性的一些實施例在實施例6有詳盡的說明；或者，在具有多主動層的EEL，除了在兩主動層之間設置穿隧接面層之外，亦能進一步形成間隔層，兩主動層之間的磊晶區的較佳實施例在實施例6有詳盡的說明，請參照。實施例1~6中的一些實施例亦能一起應用於EEL的主動層中，雖實施例1~6是以應力補償為主要目的，但亦可能具有載子侷限效果。與VCSEL相同，EEL的雷射波長是在700nm或800nm以上。 When the active layers of EEL3 and VCSEL1 have quantum well structures, since the quantum well structures of the two are the same, the first semiconductor layer implemented in each embodiment of VCSEL can also be directly implemented in EEL3; for example, the barrier layer of EEL3 Part or all of the first semiconductor layer is provided. In addition, the preferred material of the well layer is also the same. The principle of setting the first semiconductor layer and some exemplary embodiments are described in detail in Embodiment 1, please refer to; or, the barrier layer of EEL3 Part or all of the second semiconductor layer is provided, and the preferred materials of the well layer and the intermediate layer are also the same as those of the well layer and the intermediate layer in Embodiment 3. The arrangement principles and some exemplary embodiments of the second semiconductor layer are in Embodiment 3. For a detailed description, please refer to it; or, the active layer of EEL3 is further provided with an intermediate layer. The setting principles of the intermediate layer and some exemplary embodiments are detailed in Embodiment 2, please refer to it; or, the adjacent layer of EEL3 The first (second) semiconductor layer is arranged between the two active layers. The principle and exemplary embodiments of the arrangement of the first (second) semiconductor layer in the multiple active layers are described in detail in Embodiment 6; or, in the case of having multiple active layers, For the EEL of the active layer, in addition to setting a tunnel junction layer between the two active layers, a spacer layer can also be further formed. The preferred embodiment of the epitaxial region between the two active layers is described in detail in Embodiment 6. , please refer to. Some of the embodiments in Embodiments 1 to 6 can also be applied to the active layer of EEL. Although the main purpose of Embodiments 1 to 6 is stress compensation, it may also have a carrier confinement effect. Like VCSEL, the laser wavelength of EEL is above 700nm or 800nm.

如應力補償為主要考量，且第一半導體層是設置於主動層之外時；在VCSEL方面，第一半導體層較佳的是設置於VCSEL的下間隔層或上間隔層，或者下間隔層與上間隔層均設置第一半導體層；在EEL方面，第一半導體層較佳的則是設置於EEL的下光電侷限層或上光電侷限層，或者下光電侷限層與上光電侷限層均設置第一半導體層如圖19a所示；第一半導體層能直接或間接的接觸主動層。根據應力種類及補償程度，第一半導體層的優選材料能選自表1或表4中的一材料，而所選材料的能隙較大且第一半導體層形成在適當位置，也可能會有明顯的載子侷限效果。 If stress compensation is the main consideration and the first semiconductor layer is arranged outside the active layer; in terms of VCSEL, the first semiconductor layer is preferably arranged on the lower spacer layer or upper spacer layer of the VCSEL, or the lower spacer layer and The upper spacer layer is provided with the first semiconductor layer; in terms of EEL, the first semiconductor layer is preferably provided in the lower photoelectric confinement layer or the upper photoelectric confinement layer of the EEL, or both the lower photoelectric confinement layer and the upper photoelectric confinement layer are provided with the third semiconductor layer. A semiconductor layer is shown in Figure 19a; the first semiconductor layer can directly or indirectly contact the active layer. Depending on the type of stress and the degree of compensation, the preferred material of the first semiconductor layer can be selected from one of the materials in Table 1 or Table 4. If the energy gap of the selected material is large and the first semiconductor layer is formed in an appropriate position, there may also be Obvious carrier localization effect.

在主動層之外的部份，如以載子侷限為主要考量，且載子侷限層是設置於主動層之外時；在VCSEL方面，載子侷限層較佳的是設置於VCSEL的下間隔層或上間隔層，或者下間隔層與上間隔層均設置載子侷限層；而在EEL方面，載子侷限層較佳的則是設置於EEL的下光電侷限層或上光電侷限層，或者下光電侷限層與上光電侷限層均設置載子侷限層如圖19b所示，載子侷限層能直接或間接的接觸主動層。載子侷限層的優選材料選自表6的至少一材料，若選擇的材料的晶格常數可被改變，甚至能對主動層或VCSEL的磊晶層提供適當的應力補償。或者，在具有多主動層的EEL，在主動區之外、在兩主動層之間或在任兩主動層之間能設置一或二載子侷限層，具體的實施方式請參照實施例11~15。 In the part outside the active layer, if carrier confinement is the main consideration, and the carrier confinement layer is arranged outside the active layer; in terms of VCSEL, the carrier confinement layer is preferably arranged at the lower interval of the VCSEL The carrier confinement layer or the upper spacer layer, or both the lower spacer layer and the upper spacer layer are provided with a carrier confinement layer; in terms of EEL, the carrier confinement layer is preferably provided in the lower photoelectric confinement layer or the upper photoelectric confinement layer of the EEL, or Both the lower photoelectric confinement layer and the upper photoelectric confinement layer are provided with carrier confinement layers, as shown in Figure 19b. The carrier confinement layer can directly or indirectly contact the active layer. The preferred material of the carrier confinement layer is selected from at least one material in Table 6. If the lattice constant of the selected material can be changed, it can even provide appropriate stress compensation for the active layer or the epitaxial layer of the VCSEL. Alternatively, in an EEL with multiple active layers, one or two carrier localization layers can be set outside the active area, between two active layers, or between any two active layers. For specific implementations, please refer to Embodiments 11 to 15. .

在一些實施例，下光電侷限層或上光電侷限層的厚度若夠薄，則載子侷限層亦可設置於下披覆層或上披覆層。 In some embodiments, if the thickness of the lower optoelectronic confinement layer or the upper optoelectronic confinement layer is thin enough, the carrier confinement layer can also be disposed on the lower cladding layer or the upper cladding layer.

在一些實施例，配合圖19b所示，EEL中包含兩載子侷限層CF1、CF2，下光電侷限層302的一部分是設置載子侷限層CF1，上光電侷限層303的一部分是設置載子侷限層CF2；圖19b中雖顯示兩載子侷限層，但亦可只在下光電侷限層或上光電侷限層的一部分或全部設置一載子侷限層，載子侷限層也能直接接觸於主動層。 In some embodiments, as shown in Figure 19b, the EEL includes two carrier confinement layers CF1 and CF2. A part of the lower optoelectronic confinement layer 302 is provided with a carrier confinement layer CF1, and a part of the upper optoelectronic confinement layer 303 is provided with a carrier confinement layer. Layer CF2; although two carrier confinement layers are shown in Figure 19b, one carrier confinement layer can also be provided only on part or all of the lower photoelectric confinement layer or the upper photoelectric confinement layer, and the carrier confinement layer can also be in direct contact with the active layer.

[實施例17] [Example 17]

VCSEL與EEL的主動區除量子井結構之外，另外也有量子點結構(圖未示)，量子點結構的一實施例是主要包含量子點(Quantum dot)、浸潤層(Wetting layer)以及覆蓋層(cap layer)；在量子點結構，量子點或浸潤層的優選材料是InGaAs、InAlGaAs、GaAsSb、GaAs、AlGaAs、AlGaAsSb、GaAsP、InGaAsP或以上材料的任意配合。 In addition to the quantum well structure, the active regions of VCSEL and EEL also have quantum dot structures (not shown). One embodiment of the quantum dot structure mainly includes quantum dots (Quantum dots), Wetting layer and cap layer; in the quantum dot structure, the preferred material for the quantum dot or wetting layer is InGaAs, InAlGaAs, GaAsSb, GaAs, AlGaAs, AlGaAsSb, GaAsP, InGaAsP or any combination of the above materials.

以VCSEL而言，在一些實施例中，VCSEL的量子點結構之上或之下會設置間隔層，而在複數量子點結構的實施例，兩量子點結構之間也能設置間隔層；其中第一半導體層(即表1的17種材料之一)或載子侷限層(即表6的17種材料之一)能形成於覆蓋層、間隔層或上述兩者；覆蓋層、間隔層或上述兩者的一部分或全部設置第一半導體層或載子侷限層。 In the case of VCSEL, in some embodiments, a spacer layer is provided above or below the quantum dot structure of the VCSEL, and in the embodiment of a plurality of quantum dot structures, a spacer layer can also be provided between two quantum dot structures; wherein the first A semiconductor layer (i.e., one of the 17 materials in Table 1) or a carrier confinement layer (i.e., one of the 17 materials in Table 6) can be formed on the covering layer, the spacer layer, or both; the covering layer, the spacer layer, or the above Part or all of them are provided with a first semiconductor layer or a carrier confinement layer.

在一些實施例中，VCSEL的量子點結構與之上或之下均設置間隔層。 In some embodiments, a spacer layer is disposed above or below the quantum dot structure of the VCSEL.

以EEL而言，在一些實施例中，EEL的量子點結構之下會設置下光電侷限層，或在EEL的量子點結構之上設置上光電侷限層，而在複數量子點結構的實施例，兩量子點結構之間設置下光電侷限層及/或上光電侷限層，其中覆蓋層、下光電侷限層或上光電侷限層的一部分或全部設置第一半導體層或載子侷限層。 For EELs, in some embodiments, an optoelectronic confinement layer is provided under the quantum dot structure of the EEL, or an optoelectronic confinement layer is provided above the quantum dot structure of the EEL. In embodiments of a plurality of quantum dot structures, A lower optoelectronic confinement layer and/or an upper optoelectronic confinement layer is disposed between the two quantum dot structures, and part or all of the covering layer, the lower optoelectronic confinement layer or the upper optoelectronic confinement layer is disposed with a first semiconductor layer or a carrier confinement layer.

在一些實施例中，EEL的量子點結構之下及之上會設置下光電侷限層及上光電侷限層；或者，覆蓋層、下光電侷限層與上光電侷限層之中皆設置於第一半導體層或載子侷限層。 In some embodiments, a lower optoelectronic confinement layer and an upper optoelectronic confinement layer are disposed under and above the quantum dot structure of the EEL; or, the covering layer, the lower optoelectronic confinement layer, and the upper optoelectronic confinement layer are all disposed in the first semiconductor layer or carrier confinement layer.

[實施例18] [Example 18]

半導體雷射元件如VCSEL與EEL，其基板材料也可以是InP，相較於GaAs基板，當半導體雷射元件的基板是InP基板時，基板上的各磊晶層的材料選擇較多，比如井層可以是含鋁或不含鋁的材料，不過適合作為磊晶層的材料的能隙都比較小，因此必需進一步增進高溫特性。 The substrate material of semiconductor laser elements such as VCSEL and EEL can also be InP. Compared with the GaAs substrate, when the substrate of the semiconductor laser element is an InP substrate, there are more material choices for each epitaxial layer on the substrate, such as Well The layer can be made of aluminum-containing or aluminum-free materials, but the energy gaps of materials suitable as epitaxial layers are relatively small, so the high-temperature characteristics must be further improved.

比如在主動層(區)中，在主動層的一障壁層、一些障壁層或各障壁層設置載子侷限層，或者在上磊晶區及/或下磊晶區中也能設置一或多個載子侷限層，載子侷限層的設置原則與較佳實施例在實施例11~15有詳盡敘述，請參照。要特別注意的是，因基板的材料為InP，載子侷限層的優選材料可以是InGaP、InAlGaP、InP、InAlAsP、AlAsSb、AlAsBi、AlGaAsSb、AlGaAsBi、AlPSb、AlPBi、InGaAsP或以上材料的任意配合，其中InGaAsP的PL峰值波長(peak wavelength)不超過900nm。 For example, in the active layer (region), a carrier confinement layer may be provided in a barrier layer, some barrier layers or each barrier layer of the active layer, or one or more carrier confinement layers may be provided in the upper epitaxial region and/or the lower epitaxial region. A carrier confinement layer. The arrangement principles and preferred embodiments of the carrier confinement layer are described in detail in Embodiments 11 to 15. Please refer to them. It is important to note that since the material of the substrate is InP, the preferred material for the carrier localization layer can be InGaP, InAlGaP, InP, InAlAsP, AlAsSb, AlAsBi, AlGaAsSb, AlGaAsBi, AlPSb, AlPBi, InGaAsP or any combination of the above materials. The PL peak wavelength of InGaAsP does not exceed 900nm.

以上材料中的InGaP、InAlGaP、InP、InGaAsP(電洞侷限層)對電洞的侷限效果佳；而InAlAsP、AlAsSb、AlAsBi、AlGaAsSb、AlGaAsBi、AlPSb、AlPBi(電子侷限層)則對電子的侷限效果佳。 Among the above materials, InGaP, InAlGaP, InP, and InGaAsP (hole confinement layers) have a good hole confinement effect; while InAlAsP, AlAsSb, AlAsBi, AlGaAsSb, AlGaAsBi, AlPSb, and AlPBi (electron confinement layers) have a good electron confinement effect. good.

載子侷限層跟主動層之間的距離通常不超過120m，載子侷限層的厚度大於2nm。 The distance between the carrier confinement layer and the active layer usually does not exceed 120m, and the thickness of the carrier confinement layer is greater than 2nm.

[實施例19、20] [Examples 19, 20]

在本說明書，VCSEL磊晶層中的缺陷或差排是以XRT顯像(X-ray topography)呈現比較例1、實施例19、20各自的差排，以呈現差排的改善，其中，比較例1、實施例19、20都是以VCSEL磊晶圓的中心區域來做XRT顯像。 In this specification, the defects or misalignment in the VCSEL epitaxial layer are represented by XRT imaging (X-ray topography) of Comparative Example 1, Embodiment 19, and 20, respectively, to show the improvement of misalignment. Among them, Comparative Example 1, Examples 19 and 20 all use the central area of the VCSEL epiwafer for XRT imaging.

主動層中各層所使用的材料及厚度請參照表9所示，藉此將本說明書的實施例與現有技術(比較例1)作比較。比較例1中為InGaAs井層與6nm的AlGaAs障壁層。實施例19中則為有一層4nm的AlGaAs中間層設置於厚度為2nm的GaAsP障壁層之中，因此在AlGaAs中間層兩側、並且與井層相鄰的二層GaAsP障壁層厚度分別為1nm(合計為2nm)。比較例1、實施例19及實施例20中的AlGaAs及AlGaAsP的Al含量均為20%。 The materials and thicknesses used for each layer in the active layer are shown in Table 9 to compare the embodiments of this specification with the prior art (Comparative Example 1). In Comparative Example 1, there is an InGaAs well layer and a 6 nm AlGaAs barrier layer. In Example 19, a 4 nm AlGaAs intermediate layer is disposed in a GaAsP barrier layer with a thickness of 2 nm. Therefore, the thickness of the two GaAsP barrier layers on both sides of the AlGaAs intermediate layer and adjacent to the well layer is 1 nm ( Total is 2nm). The Al content of AlGaAs and AlGaAsP in Comparative Example 1, Example 19 and Example 20 is all 20%.

圖20a至圖20c顯示根據比較例1與本說明書之實施例19、20的XRT顯像。圖20a為比較例1的XRT顯像圖，圖20b及圖20c分別為實施例19及實施例20的XRT顯像圖。藉由比較例1的XRT顯像，可觀察到比較例1出現多條明顯的暗線即明顯的差排(dislocation)。相對地，根據實施例19的XRT顯像，實施例19雖隱約能出現一些暗線但相對於比較例1並不明顯，而根據實施例20的XRT顯像，實施例20幾乎無法觀察到暗線(差排)，故相較於比較例1，實施例19與20能減少VCSEL的磊晶層的差排。 Figures 20a to 20c show XRT imaging according to Comparative Example 1 and Examples 19 and 20 of this specification. Figure 20a is the XRT imaging diagram of Comparative Example 1, and Figures 20b and 20c are the XRT imaging diagrams of Example 19 and Example 20 respectively. Through the XRT imaging of Comparative Example 1, it can be observed that Comparative Example 1 has multiple obvious dark lines, that is, obvious dislocations. In contrast, according to the XRT imaging of Example 19, although some dark lines can appear vaguely in Example 19, they are not obvious compared to Comparative Example 1. According to the XRT imaging of Example 20, almost no dark lines can be observed in Example 20 ( dislocation), therefore compared to Comparative Example 1, Examples 19 and 20 can reduce the dislocation of the epitaxial layer of the VCSEL.

比較例1的是以InGaAs與AlGaAs作為井層與障壁層，當基板為GaAs時，InGaAs與AlGaAs都會產生壓縮應力，過大的壓縮應力導致在VCSEL的磊晶層產生較多的差排或缺陷，如圖20a的XRT顯像之明顯可見的多條暗線。實施例19中透過以含磷材料如GaAsP做為障壁層及以AlGaAs做為中間層，而在障壁層提供拉伸應力，減少主動層的應力總和，因而減少VCSEL的磊晶層的差排或者缺陷，且能增進載子侷限能力。實施例20也是以含磷材料如AlGaAsP作為障壁層，而在障壁層提供拉伸應力，故相較於比較例1，能減少VCSEL的磊晶層的缺陷或差排。 Comparative Example 1 uses InGaAs and AlGaAs as the well layer and barrier layer. When the substrate is GaAs, both InGaAs and AlGaAs will generate compressive stress. Excessive compressive stress will cause more dislocations or defects in the epitaxial layer of the VCSEL. As shown in the XRT imaging of Figure 20a, multiple dark lines are clearly visible. In Embodiment 19, a phosphorus-containing material such as GaAsP is used as the barrier layer and AlGaAs is used as the intermediate layer to provide tensile stress in the barrier layer and reduce the stress sum of the active layer, thus reducing the misalignment or misalignment of the epitaxial layer of the VCSEL. defects and can improve carrier confinement capabilities. Example 20 also uses a phosphorus-containing material such as AlGaAsP as the barrier layer to provide tensile stress in the barrier layer. Therefore, compared with Comparative Example 1, defects or dislocations in the epitaxial layer of the VCSEL can be reduced.

透過實施例19、20的XRT顯像展現了使用含磷材料(表1的17種材料之一)於半導體雷射二極體中，確實能夠有效地減少半導體雷射二極體的差排或者缺陷。 The XRT imaging of Examples 19 and 20 shows that using phosphorus-containing materials (one of the 17 materials in Table 1) in semiconductor laser diodes can indeed effectively reduce the dislocation or dislocation of semiconductor laser diodes. defect.

[實施例21、22與比較例2] [Examples 21, 22 and Comparative Example 2]

圖21是實施例21、22與比較例2在不同溫度下最大功率轉換效率(maximum power conversion efficiency,PCE MAX)的比較圖，在比較例2的VCSEL，其中兩主動層之間未設置用以侷限電洞的載子侷限層；而實施例21的VCSEL則是在兩主動層之間設置用以侷限電洞的n型AlGaInP電洞侷限層，而實施例22的VCSEL則是在兩主動層之間設置用以侷限電洞的n型InGaP電洞侷限層，電洞侷限層的設置位置請參照圖15；根據實施例21、22，電洞是經由第四面J4注入於主動層21，而電子是經由第一面J1注入於主動層20；如圖21所示，在室溫下，比較例2跟實施例21、22的最大功率轉換效率無明顯差距，但在高溫時，實施例21、22的最大功率轉換效率明顯高於比較例2的最大功率轉換效率，且溫度越高最大功率轉換效率能進一步提升。 Figure 21 is a comparison diagram of the maximum power conversion efficiency (PCE MAX) of Embodiments 21 and 22 and Comparative Example 2 at different temperatures. In the VCSEL of Comparative Example 2, there is no active layer between the two active layers. A carrier confinement layer that confines holes; the VCSEL of Embodiment 21 is provided with an n-type AlGaInP hole confinement layer between two active layers to confine holes, while the VCSEL of Embodiment 22 is provided with an n-type AlGaInP hole confinement layer between the two active layers. An n-type InGaP hole confinement layer is disposed in between to confine holes. Please refer to Figure 15 for the location of the hole confinement layer. According to Embodiments 21 and 22, holes are injected into the active layer 21 through the fourth surface J4. The electrons are injected into the active layer 20 through the first surface J1; as shown in Figure 21, at room temperature, there is no obvious difference between the maximum power conversion efficiency of Comparative Example 2 and Embodiments 21 and 22, but at high temperatures, the The maximum power conversion efficiency of 21 and 22 is significantly higher than that of Comparative Example 2, and the higher the temperature, the maximum power conversion efficiency can be further improved.

[實施例23與比較例3] [Example 23 and Comparative Example 3]

圖22是實施例23與比較例3在不同溫度下最大功率轉換效率的比較圖，比較例3的VCSEL是包含五主動層且未設置用以侷限電洞的載子侷限層，而實施例23的VCSEL也是包含五主動層，且在每兩相鄰的主動層之間設置用以侷限電洞的n型InGaP電洞侷限層；根據實施例21、22，電洞是經由第四面J4注入於主動層21，而電子是經由第一面J1注入於主動層20；如圖22所示，在室溫下，比較例3跟實施例23的最大功率轉換效率亦無明顯差距，但在高溫時，實施例23的最大功率轉換效率明顯高於比較例2的最大功率轉換效率，且溫度越高最大功率轉換效率能進一步提升。 Figure 22 is a comparison chart of the maximum power conversion efficiency at different temperatures between Example 23 and Comparative Example 3. The VCSEL of Comparative Example 3 includes five active layers and is not provided with a carrier confinement layer for confining holes, while Example 23 The VCSEL also includes five active layers, and an n-type InGaP hole confinement layer is set between every two adjacent active layers to confine holes; according to Embodiments 21 and 22, holes are injected through the fourth surface J4 In the active layer 21, electrons are injected into the active layer 20 through the first surface J1; as shown in Figure 22, at room temperature, there is no significant difference in the maximum power conversion efficiency between Comparative Example 3 and Embodiment 23. distance, but at high temperature, the maximum power conversion efficiency of Example 23 is significantly higher than that of Comparative Example 2, and the higher the temperature, the maximum power conversion efficiency can be further improved.

由此可知，在三或四或更多主動層設置載子侷限層，亦有增進高溫特性的效果。一般而言，跟電子相比，電洞比較不活躍，在VCSEL只具有一主動層的情形，單一主動層的出光功率密度並不會使主動區溫度或接面溫度顯著提升，因此電洞相對下比較容易侷限於主動層中，而較不需對電洞加以侷限；然而在具有多主動層的VCSEL中，VCSEL的出光功率密度會大幅增加，因此主動區溫度或接面溫度也會大幅升高，電洞將因而變得比較活躍，因此必須對電洞加以侷限，若無法將電洞侷限於主動層中，VCSEL光特性就會容易受限或難以進一步增進。除此之外，具有多主動層的VCSEL是透過載子再利用(CARRIER RECYCLING)機制來實現高出光功率(high optical output power)或高功率轉換效率(具單一主動層的VCSEL並無載子再利用機制)，當兩主動層之間侷限電洞的能力不佳時(電洞就容易移動到穿隧接面層)，則載子再利用效果會變差，具有多主動層的VCSEL的特性容易在比較高的溫度下劣化。實施例22與實施例23因設置用於侷限電洞的InGaP電洞侷限層，因此在高溫時，具有兩主動層的VCSEL與具有五主動層的VCSEL的最大功率轉換效率確實得到明顯增進；同樣的，實施例21也因設置用於侷限電洞的AlInGaP電洞侷限層，因此在高溫時，具有兩主動層的VCSEL的最大功率轉換效率得到明顯增進。 It can be seen from this that providing carrier confinement layers in three, four or more active layers also has the effect of improving high-temperature characteristics. Generally speaking, compared with electrons, holes are relatively inactive. In the case of a VCSEL with only one active layer, the light output power density of a single active layer will not significantly increase the active area temperature or junction temperature, so holes are relatively inactive. It is easier to be localized in the active layer, and there is less need to limit the holes; however, in a VCSEL with multiple active layers, the light output power density of the VCSEL will increase significantly, so the active area temperature or junction temperature will also increase significantly. If it is high, the electric holes will become more active, so the electric holes must be limited. If the electric holes cannot be limited to the active layer, the optical characteristics of the VCSEL will be easily limited or difficult to further improve. In addition, VCSELs with multiple active layers achieve high optical output power or high power conversion efficiency through the carrier recycling (CARRIER RECYCLING) mechanism (VCSELs with a single active layer have no carrier recycling). Utilization mechanism), when the ability to confine holes between the two active layers is poor (holes can easily move to the tunnel junction layer), the carrier reuse effect will become worse. The characteristics of VCSEL with multiple active layers Easily degraded at relatively high temperatures. Since the InGaP hole confinement layer is provided in Embodiment 22 and 23 for confining holes, at high temperatures, the maximum power conversion efficiency of the VCSEL with two active layers and the VCSEL with five active layers is indeed significantly improved; similarly In Embodiment 21, the AlInGaP hole confinement layer for confining holes is also provided. Therefore, at high temperatures, the maximum power conversion efficiency of the VCSEL with two active layers is significantly improved.

[實施例24與比較例4] [Example 24 and Comparative Example 4]

圖23是實施例24與比較例4在室溫下測得的L-I-V曲線圖，圖24是實施例24與比較例4在高溫下測得的L-I-V曲線圖，其中室溫大約是25℃，高溫大約是65℃；實施例24是包含用以侷限電洞的電洞侷限層的EEL，而比較例4則是不包含用以侷限電洞的載子侷限層的EEL，實施例24與比較例4都是使用InP基板；用以侷限電洞的電洞侷限層的材料是n型InP(後稱InP載子侷限層)，n型InP電洞侷限層設置於主動層與下光電侷限層之間，且n型InP電洞侷限層的一側並實質接觸於主動層，亦即主動層是直接形成於InP電洞侷限層之上，其中主動層是含鋁材料，下光電侷限層之實質接觸於InP電洞侷限層的一側也是含鋁材料；如圖23與圖24所示，相較於未設置用以侷限電洞的載子侷限層的比較例4，實施例24在室溫跟高溫下因載子侷限能力皆有所提升，所以光功率與斜效率(Slope efficiency,SE)亦有所提升，其中斜效率SE為光功率與電流的斜率(W/A)。在實施例24中，雷射二極體的放光波長為1310nm。 Figure 23 is the L-I-V curve measured at room temperature in Example 24 and Comparative Example 4. Figure 24 is the L-I-V curve measured at high temperature in Example 24 and Comparative Example 4. The room temperature is about 25°C, and the high temperature It is about 65°C; Example 24 is an EEL that includes a hole confinement layer for confining holes, while Comparative Example 4 is an EEL that does not include a carrier confinement layer for confining holes. Example 24 and Comparative Example 4 all use InP substrates; the material of the hole confinement layer used to confine holes is n-type InP (hereinafter referred to as InP carrier confinement layer), and the n-type InP hole confinement layer is provided between the active layer and the lower optoelectronic confinement layer. space, and one side of the n-type InP hole confinement layer is actually in contact with the active layer, that is, the active layer is directly formed on the InP hole confinement layer, where the active layer is made of aluminum-containing material, and the underlying photoelectric confinement layer The side that is in contact with the InP hole confinement layer is also made of aluminum; as shown in Figures 23 and 24, compared with Comparative Example 4 which does not have a carrier confinement layer to confine holes, Example 24 is at room temperature. Both have the same effect due to carrier limitation at high temperatures. has been improved, so the optical power and slope efficiency (SE) have also been improved, where slope efficiency SE is the slope of optical power and current (W/A). In Example 24, the emission wavelength of the laser diode is 1310 nm.

承上段，以含鋁材料作為主動層中的障壁層與井層時，其導電帶不連續相對較高，價電帶不連續相對較小，因此含鋁材料的主動層的電子位障高度通常較高，但電洞位障高度較低，因此主動層的電洞侷限性通常較差。而透過在主動層之上或之下設置含磷的載子侷限層，由於含磷的載子侷限層與含鋁的主動層能形成較大的價電帶不連續，所以電洞位障高度得以提升，而增進主動層的電洞侷限性；實施例24是在含鋁的主動層與含鋁的下光電侷限層之間設置n型InP電洞侷限層，如此能把原本較低的價電帶不連續明顯提高以提高電洞位障高度，如此主動層的電洞侷限性得以增進，同時含磷的載子侷限層與含鋁的主動層及含鋁的下光電侷限層之間所形成的導電帶不連續又不會太大，因此電子能較不受阻的從下光電侷限層注入於主動層，所以電阻也不容易變大，有助於增進半導體雷射二極體的特性。 Continuing from the above section, when aluminum-containing materials are used as the barrier layer and well layer in the active layer, the conductive band discontinuity is relatively high and the valence band discontinuity is relatively small. Therefore, the electronic barrier height of the active layer of aluminum-containing materials is usually is higher, but the hole barrier height is lower, so the hole localization in the active layer is usually poor. By placing a phosphorus-containing carrier confinement layer above or below the active layer, the phosphorus-containing carrier confinement layer and the aluminum-containing active layer can form a large valence band discontinuity, so the hole barrier height can be improved to improve the hole localization of the active layer; Embodiment 24 is to provide an n-type InP hole localization layer between the aluminum-containing active layer and the aluminum-containing lower photoelectric localization layer, so that the originally lower price can be reduced. The electrical band discontinuity is significantly increased to increase the hole barrier height, so that the hole localization of the active layer is enhanced. At the same time, the phosphorus-containing carrier confinement layer and the aluminum-containing active layer and the aluminum-containing lower photoelectric confinement layer are The formed conductive band is discontinuous and not too large, so electrons can be injected into the active layer from the lower photoelectric localization layer without any hindrance, so the resistance is not easy to increase, which helps to improve the characteristics of the semiconductor laser diode.

以上所述者僅為用以解釋本發明之較佳實施例，並非企圖據以對本發明做任何形式上之限制，是以，凡有在相同之發明精神下所作有關本發明之任何修飾或變更，皆仍應包括在本發明意圖保護之範疇。 The above are only used to explain the preferred embodiments of the present invention, and are not intended to limit the present invention in any form. Therefore, any modifications or changes related to the present invention are made under the same spirit of the invention. , should still be included in the scope of protection intended by the present invention.

1’:半導體雷射元件 1’:Semiconductor laser element

10’:基板 10’:Substrate

100’:多層結構 100’:Multi-layer structure

A’:主動區 A’: Active area

S1’:半導體層 S1’: semiconductor layer

Claims

一種垂直共振腔表面放射雷射二極體，包含：一GaAs基板；以及一多層結構，位在該GaAs基板之上，該多層結構包含：一主動區，包含；複數主動層，至少包含兩主動層，該兩主動層包含一上主動層與一下主動層，該上主動層包含一或複數量子井層或者包含一或複數量子點結構，該下主動層包含一或複數量子井層或者包含一或複數量子點結構，該上主動層與該下主動層之間具有一磊晶區，該磊晶區中進一步包含：一穿隧接面層；以及一電洞侷限層，位於該上主動層與該穿隧接面層之間或位於該下主動層與該穿隧接面層之間。 A vertical resonant cavity surface emitting laser diode includes: a GaAs substrate; and a multi-layer structure located on the GaAs substrate. The multi-layer structure includes: an active region including; a plurality of active layers including at least two Active layers, the two active layers include an upper active layer and a lower active layer. The upper active layer includes one or more quantum well layers or one or more quantum point structures. The lower active layer includes one or multiple quantum well layers or includes One or a plurality of quantum dot structures, there is an epitaxial region between the upper active layer and the lower active layer, the epitaxial region further includes: a tunnel junction layer; and a hole localization layer located on the upper active layer between the lower active layer and the tunnel junction layer or between the lower active layer and the tunnel junction layer.

如請求項1所述之一種垂直共振腔表面放射雷射二極體，其中，該電洞侷限層係包含選自InAlGaP、InAlGaPN、InAlGaPSb、InAlGaPBi、InGaAsP、InGaAsPN、InGaAsPSb、InGaAsPBi、InGaP、InGaPN、InGaPSb、InGaPBi及InAlGaAsP所組成的群組的至少一種。 A vertical resonant cavity surface emitting laser diode as claimed in claim 1, wherein the hole localization layer is selected from the group consisting of InAlGaP, InAlGaPN, InAlGaPSb, InAlGaPBi, InGaAsP, InGaAsPN, InGaAsPSb, InGaAsPBi, InGaP, InGaPN, At least one of the group consisting of InGaPSb, InGaPBi and InAlGaAsP.

如請求項1所述之一種垂直共振腔表面放射雷射二極體，其中，該主動區更包含一電子侷限層，當該電洞侷限層位於該上主動層與該穿隧接面層之間時，該電子侷限層位於該下主動層與該穿隧接面層之間。 A vertical resonant cavity surface emitting laser diode as claimed in claim 1, wherein the active region further includes an electron confinement layer, and when the hole confinement layer is located between the upper active layer and the tunnel junction layer time, the electron confinement layer is located between the lower active layer and the tunnel junction layer.

如請求項1所述之一種垂直共振腔表面放射雷射二極體，其中，該主動區更包含一電子侷限層，當該電洞侷限層位於該下主動層與該穿隧接面層之間時，該電子侷限層位於該上主動層與該穿隧接面層之間。 A vertical resonant cavity surface emitting laser diode as claimed in claim 1, wherein the active region further includes an electron confinement layer, and when the hole confinement layer is located between the lower active layer and the tunnel junction layer time, the electron confinement layer is located between the upper active layer and the tunnel junction layer.

如請求項3或4所述之一種垂直共振腔表面放射雷射二極體，其中，該電子侷限層係選自AlGaAsP、AlGaAsPN、AlGaAsPSb、AlGaAsPBi、InAlGaP、InAlGaPN、InAlGaPSb、InAlGaPBi及InAlGaAsP所組成的群組的至少一種。 A vertical resonant cavity surface emitting laser diode as claimed in claim 3 or 4, wherein the electron localization layer is selected from the group consisting of AlGaAsP, AlGaAsPN, AlGaAsPSb, AlGaAsPBi, InAlGaP, InAlGaPN, InAlGaPSb, InAlGaPBi and InAlGaAsP At least one type of group.

如請求項1所述之一種垂直共振腔表面放射雷射二極體，其中，該兩主動層之間更包含一或複數間隔層，該穿隧接面層之上及/或之下設置該間隔層。 A vertical resonant cavity surface emitting laser diode as claimed in claim 1, wherein one or a plurality of spacer layers are further included between the two active layers, and the tunnel junction layer is provided with the spacer layer.

如請求項6所述之一種垂直共振腔表面放射雷射二極體，其中，該電洞侷限層係設置於該間隔層中。 A vertical resonant cavity surface emitting laser diode as claimed in claim 6, wherein the hole confinement layer is disposed in the spacer layer.

如請求項3或4所述之一種垂直共振腔表面放射雷射二極體，其中，該兩主動層之間更包含一或複數間隔層，該穿隧接面層之上及/或之下設置該間隔層，該電子侷限層係設置於該間隔層中。 A vertical resonant cavity surface emitting laser diode as claimed in claim 3 or 4, wherein one or a plurality of spacer layers are further included between the two active layers, above and/or below the tunnel junction layer The spacer layer is provided, and the electron confinement layer is provided in the spacer layer.

如請求項6或7所述之一種垂直共振腔表面放射雷射二極體，其中，該兩主動層之間更包含一氧化層；在該穿隧接面層與該氧化層之間、在該穿隧接面層與鄰近於該穿隧接面層的主動層之間或在該氧化層與鄰近於該氧化層的主動層之間設置該間隔層。 A vertical resonant cavity surface emitting laser diode as claimed in claim 6 or 7, wherein an oxide layer is further included between the two active layers; between the tunnel junction layer and the oxide layer, The spacer layer is disposed between the tunnel junction layer and the active layer adjacent to the tunnel junction layer or between the oxide layer and the active layer adjacent to the oxide layer.

如請求項1所述之一種垂直共振腔表面放射雷射二極體，其中，該兩主動層之間更包含一氧化層，當該電洞侷限層位於該上主動層與該穿隧接面層之間時，該氧化層係位於該下主動層與該穿隧接面層之間。 A vertical resonant cavity surface emitting laser diode as claimed in claim 1, wherein an oxide layer is further included between the two active layers, and when the hole localization layer is located at the interface between the upper active layer and the tunnel When between layers, the oxide layer is located between the lower active layer and the tunnel junction layer.

如請求項1所述之一種垂直共振腔表面放射雷射二極體，其中，該兩主動層之間更包含一氧化層，當該電洞侷限層位於該下主動層與該穿隧接面層之間時，該氧化層位於該上主動層與該穿隧接面層之間。 A vertical resonant cavity surface emitting laser diode as claimed in claim 1, wherein an oxide layer is further included between the two active layers, and when the hole localization layer is located at the interface between the lower active layer and the tunnel When between layers, the oxide layer is located between the upper active layer and the tunnel junction layer.

一種垂直共振腔表面放射雷射二極體，包含：一GaAs基板；以及一多層結構，在該GaAs基板之上，該多層結構包含：一主動區，包含；複數主動層，至少包含兩主動層，該兩主動層包含一上主動層與一下主動層，該上主動層包含一或複數量子井層或者包含一或複數量子點結構，該下主動層包含一或複數量子井層或者包含一或複數量子點結構，該上主動層與該下主動層之間具有一磊晶區，該磊晶區中進一步包含：一穿隧接面層；以及一電子侷限層，位於該上主動層與該穿隧接面層之間或位於該下主動層與該穿隧接面層之間。 A vertical resonant cavity surface emitting laser diode includes: a GaAs substrate; and a multilayer structure. On the GaAs substrate, the multilayer structure includes: an active region, including; a plurality of active layers, including at least two active layers. The two active layers include an upper active layer and a lower active layer. The upper active layer includes one or more quantum well layers or one or multiple quantum point structures. The lower active layer includes one or more quantum well layers or includes one Or a plurality of quantum dot structures, with an epitaxial region between the upper active layer and the lower active layer, and the epitaxial region further includes: a tunnel junction layer; and an electron confinement layer located between the upper active layer and the tunnel junction layer or between the lower active layer and the tunnel junction layer.

如請求項12所述之一種垂直共振腔表面放射雷射二極體，其中，該電子侷限層係選自AlGaAsP、AlGaAsPN、AlGaAsPSb、AlGaAsPBi、InAlGaP、InAlGaPN、InAlGaPSb、InAlGaPBi及InAlGaAsP所組成的群組的的至少一種。 A vertical resonant cavity surface emitting laser diode as claimed in claim 12, wherein the electron localization layer is selected from the group consisting of AlGaAsP, AlGaAsPN, AlGaAsPSb, AlGaAsPBi, InAlGaP, InAlGaPN, InAlGaPSb, InAlGaPBi and InAlGaAsP At least one of.

如請求項12所述之一種垂直共振腔表面放射雷射二極體，其中，該主動區更包含一電洞侷限層，當該電子侷限層位於該上主動層與該穿隧接面層之間時，該電洞侷限層位於該下主動層與該穿隧接面層之間。 A vertical resonant cavity surface emitting laser diode as claimed in claim 12, wherein the active region further includes a hole confinement layer, and when the electron confinement layer is located between the upper active layer and the tunnel junction layer time, the hole localization layer is located between the lower active layer and the tunnel junction layer.

如請求項12所述之一種垂直共振腔表面放射雷射二極體，其中，該主動區更包含一電洞侷限層，當該電子侷限層位於該下主動層與該穿隧接面層之間時，該電洞侷限層位於該上主動層與該穿隧接面層之間。 A vertical resonant cavity surface emitting laser diode as claimed in claim 12, wherein the active region further includes a hole confinement layer, and when the electron confinement layer is located between the lower active layer and the tunnel junction layer time, the hole localization layer is located between the upper active layer and the tunnel junction layer.

如請求項14或15所述之一種垂直共振腔表面放射雷射二極體，其中，該電洞侷限層係包含選自InAlGaP、InAlGaPN、InAlGaPSb、InAlGaPBi、InGaAsP、InGaAsPN、InGaAsPSb、InGaAsPBi、InGaP、InGaPN、InGaPSb、InGaPBi及InAlGaAsP所組成的群組的至少一種。 A vertical resonant cavity surface emitting laser diode as claimed in claim 14 or 15, wherein the hole localization layer is selected from the group consisting of InAlGaP, InAlGaPN, InAlGaPSb, InAlGaPBi, InGaAsP, InGaAsPN, InGaAsPSb, InGaAsPBi, InGaP, At least one of the group consisting of InGaPN, InGaPSb, InGaPBi and InAlGaAsP.

如請求項12所述之一種垂直共振腔表面放射雷射二極體，其中，該兩主動層之間更包含一或複數間隔層，該穿隧接面層之上及/或之下設置該間隔層。 A vertical resonant cavity surface emitting laser diode as claimed in claim 12, wherein one or a plurality of spacer layers are further included between the two active layers, and the tunnel junction layer is provided with the spacer layer.

如請求項17所述之一種垂直共振腔表面放射雷射二極體，其中，該電子侷限層係設置於該間隔層中。 A vertical resonant cavity surface emitting laser diode as claimed in claim 17, wherein the electron confinement layer is disposed in the spacer layer.

如請求項14或15所述之一種垂直共振腔表面放射雷射二極體，其中，該兩主動層之間更包含一或複數間隔層，該穿隧接面層之上及/或之下設置該間隔層，該電洞侷限層係設置於該間隔層中。 A vertical resonant cavity surface emitting laser diode as claimed in claim 14 or 15, wherein one or a plurality of spacer layers are further included between the two active layers, above and/or below the tunnel junction layer The spacer layer is provided, and the hole confinement layer is provided in the spacer layer.

如請求項17或18所述之一種垂直共振腔表面放射雷射二極體，其中，該兩主動層之間更包含一氧化層；在該穿隧接面層與該氧化層之間、在該穿隧接面層與鄰近於該穿隧接面層的主動層之間或在該氧化層與鄰近於該氧化層的主動層之間設置該間隔層。 A vertical resonant cavity surface emitting laser diode as claimed in claim 17 or 18, wherein an oxide layer is further included between the two active layers; between the tunnel junction layer and the oxide layer, The spacer layer is disposed between the tunnel junction layer and an active layer adjacent to the tunnel junction layer or between the oxide layer and an active layer adjacent to the oxide layer.

一種垂直共振腔表面放射雷射二極體，包含：一InP基板；以及一多層結構，在該InP基板之上，該多層結構包含：一主動區，包含：複數主動層，至少包含兩主動層，該兩主動層包含一上主動層與一下主動層，該上主動層包含一或複數量子井層或者包含一或複數量子點結構，該下主動層包含一或複數量子井層或者包含一或複數量子點結構，該上主動層與該下主動層之間具有一磊晶區，該磊晶區中進一步包含：一穿隧接面層；以及一電洞侷限層，位於該上主動層與該穿隧接面層之間或位於該下主動層與該穿隧接面層之間。 A vertical resonant cavity surface emitting laser diode includes: an InP substrate; and a multi-layer structure. On the InP substrate, the multi-layer structure includes: an active area including: a plurality of active layers, including at least two active layers. The two active layers include an upper active layer and a lower active layer. The upper active layer includes one or more quantum well layers or one or multiple quantum point structures. The lower active layer includes one or more quantum well layers or includes one Or a plurality of quantum dot structures, with an epitaxial region between the upper active layer and the lower active layer, and the epitaxial region further includes: a tunnel junction layer; and a hole localization layer located on the upper active layer between the tunnel junction layer or between the lower active layer and the tunnel junction layer.

如請求項21所述之半導體雷射二極體，其中，該電洞侷限層係選自由InGaP、InAlGaP、InP及InGaAsP所組成之群組的的至少一種，其中InGaAsP的PL峰值波長不超過900nm。 The semiconductor laser diode according to claim 21, wherein the hole localization layer is selected from at least one of the group consisting of InGaP, InAlGaP, InP and InGaAsP, wherein the PL peak wavelength of InGaAsP does not exceed 900 nm. .

如請求項21所述之一種垂直共振腔表面放射雷射二極體，其中，該主動區更包含一電子侷限層，當該電洞侷限層位於該上主動層與該穿隧接面層之間時，該電子侷限層位於該下主動層與該穿隧接面層之間。 A vertical resonant cavity surface emitting laser diode as claimed in claim 21, wherein the active region further includes an electron confinement layer, and when the hole confinement layer is located between the upper active layer and the tunnel junction layer time, the electron confinement layer is located between the lower active layer and the tunnel junction layer.

如請求項21所述之一種垂直共振腔表面放射雷射二極體，其中，該主動區更包含一電子侷限層，當該電洞侷限層位於該下主動層與該穿隧接面層之間時，該電子侷限層位於該上主動層與該穿隧接面層之間。 A vertical resonant cavity surface emitting laser diode as claimed in claim 21, wherein the active region further includes an electron confinement layer, and when the hole confinement layer is located between the lower active layer and the tunnel junction layer time, the electron confinement layer is located between the upper active layer and the tunnel junction layer.

如請求項23或24所述之一種垂直共振腔表面放射雷射二極體，其中，該電子侷限層係選自InAlAsP、AlAsSb、AlAsBi、AlGaAsSb、AlGaAsBi、AlPSb及AlPBi所組成之群組的的至少一種。 A vertical resonant cavity surface emitting laser diode as claimed in claim 23 or 24, wherein the electron confinement layer is selected from the group consisting of InAlAsP, AlAsSb, AlAsBi, AlGaAsSb, AlGaAsBi, AlPSb and AlPBi At least one.

如請求項21所述之垂直共振腔表面放射雷射二極體，其中，該兩主動層之間更包含一或複數間隔層，該穿隧接面層之上及/或之下設置該間隔層。 The vertical resonant cavity surface emitting laser diode as claimed in claim 21, wherein one or a plurality of spacer layers are further included between the two active layers, and the spacers are provided above and/or below the tunnel junction layer. layer.

如請求項26所述之一種垂直共振腔表面放射雷射二極體，其中，該電洞侷限層係設置於該間隔層中。 A vertical resonant cavity surface emitting laser diode as claimed in claim 26, wherein the hole confinement layer is disposed in the spacer layer.

如請求項23或24所述之一種垂直共振腔表面放射雷射二極體，其中，該兩主動層之間更包含一或複數間隔層，該穿隧接面層之上及/或之下設置該間隔層，該電子侷限層係設置於該間隔層中。 A vertical resonant cavity surface emitting laser diode as claimed in claim 23 or 24, wherein one or a plurality of spacer layers are further included between the two active layers, above and/or below the tunnel junction layer The spacer layer is provided, and the electron confinement layer is provided in the spacer layer.

如請求項26或27所述之一種半導體雷射二極體，其中，該兩主動層之間更包含一氧化層；在該穿隧接面層與該氧化層之間、在該穿隧接面層與鄰近於該穿隧接面層的主動層之間或在該氧化層與鄰近於該氧化層的主動層之間設置該間隔層。 A semiconductor laser diode as claimed in claim 26 or 27, wherein an oxide layer is further included between the two active layers; between the tunnel junction layer and the oxide layer, the tunnel junction The spacer layer is disposed between the surface layer and the active layer adjacent to the tunnel junction layer or between the oxide layer and the active layer adjacent to the oxide layer.

如請求項21所述之一種垂直共振腔表面放射雷射二極體，其中，該兩主動層之間更包含一氧化層，當該電洞侷限層位於該上主動層與該穿隧接面層之間時，該氧化層係位於該下主動層與該穿隧接面層之間。 A vertical resonant cavity surface emitting laser diode as claimed in claim 21, wherein an oxide layer is further included between the two active layers, and when the hole localization layer is located at the interface between the upper active layer and the tunnel When between layers, the oxide layer is located between the lower active layer and the tunnel junction layer.

如請求項21所述之一種垂直共振腔表面放射雷射二極體，其中，該兩主動層之間更包含一氧化層，當該電洞侷限層位於該下主動層與該穿隧接面層之間時，該氧化層位於該上主動層與該穿隧接面層之間。 A vertical resonant cavity surface emitting laser diode as claimed in claim 21, wherein an oxide layer is further included between the two active layers, and when the hole localization layer is located at the interface between the lower active layer and the tunnel When between layers, the oxide layer is located between the upper active layer and the tunnel junction layer.

一種垂直共振腔表面放射雷射二極體，包含：一InP基板；以及一多層結構，在該InP基板之上，該多層結構包含：一主動區，包含：複數主動層，至少包含兩主動層，該兩主動層包含一上主動層與一下主動層，該上主動層包含一或複數量子井層或者包含一或複數量子點結構，該下主動層包含一或複數量子井層或者包含一或複數量子點結構，該上主動層與該下主動層之間具有一磊晶區，該磊晶區中進一步包含：一穿隧接面層；以及一電子侷限層，位於該上主動層與該穿隧接面層之間或位於該下主動層與該穿隧接面層之間。 A vertical resonant cavity surface emitting laser diode includes: an InP substrate; and a multi-layer structure. On the InP substrate, the multi-layer structure includes: an active area including: a plurality of active layers, including at least two active layers. The two active layers include an upper active layer and a lower active layer. The upper active layer includes one or more quantum well layers or one or multiple quantum point structures. The lower active layer includes one or more quantum well layers or includes one Or a plurality of quantum dot structures, with an epitaxial region between the upper active layer and the lower active layer, and the epitaxial region further includes: a tunnel junction layer; and an electron confinement layer located between the upper active layer and the tunnel junction layer or between the lower active layer and the tunnel junction layer.

如請求項32所述之一種垂直共振腔表面放射雷射二極體，其中，該電子侷限層係選自InAlAsP、AlAsSb、AlAsBi、AlGaAsSb、AlGaAsBi、AlPSb及AlPBi所組成之群組的的至少一種。 A vertical resonant cavity surface emitting laser diode as claimed in claim 32, wherein the electron confinement layer is at least one selected from the group consisting of InAlAsP, AlAsSb, AlAsBi, AlGaAsSb, AlGaAsBi, AlPSb and AlPBi .

如請求項32所述之一種垂直共振腔表面放射雷射二極體，其中，該主動區更包含一電洞侷限層，當該電子侷限層位於該上主動層與該穿隧接面層之間時，該電洞侷限層位於該下主動層與該穿隧接面層之間。 A vertical resonant cavity surface emitting laser diode as claimed in claim 32, wherein the active region further includes a hole confinement layer, and when the electron confinement layer is located between the upper active layer and the tunnel junction layer time, the hole localization layer is located between the lower active layer and the tunnel junction layer.

如請求項32所述之一種垂直共振腔表面放射雷射二極體，其中，該主動區更包含一電洞侷限層，當該電子侷限層位於該下主動層與該穿隧接面層之間時，該電洞侷限層位於該上主動層與該穿隧接面層之間。 A vertical resonant cavity surface emitting laser diode as claimed in claim 32, wherein the active region further includes a hole confinement layer, and when the electron confinement layer is located between the lower active layer and the tunnel junction layer time, the hole localization layer is located between the upper active layer and the tunnel junction layer.

如請求項34或35所述之一種垂直共振腔表面放射雷射二極體，其中，該電洞侷限層係選自由InGaP、InAlGaP、InP及InGaAsP所組成之群組的的至少一種，其中InGaAsP的PL峰值波長不超過900nm。 A vertical resonant cavity surface emitting laser diode as claimed in claim 34 or 35, wherein the hole localization layer is selected from at least one of the group consisting of InGaP, InAlGaP, InP and InGaAsP, wherein InGaAsP The PL peak wavelength does not exceed 900nm.

如請求項32所述之一種垂直共振腔表面放射雷射二極體，其中，該兩主動層之間更包含一或複數間隔層，該穿隧接面層之上及/或之下設置該間隔層。 A vertical resonant cavity surface emitting laser diode as claimed in claim 32, wherein one or a plurality of spacer layers are further included between the two active layers, and the tunnel junction layer is provided with the spacer layer.

如請求項37所述之一種垂直共振腔表面放射雷射二極體，其中，該電子侷限層係設置於該間隔層中。 A vertical resonant cavity surface emitting laser diode as claimed in claim 37, wherein the electron confinement layer is disposed in the spacer layer.

如請求項34或35所述之一種垂直共振腔表面放射雷射二極體，其中，該兩主動層之間更包含一或複數間隔層，該穿隧接面層之上及/或之下設置該間隔層，該電洞侷限層係設置於該間隔層中。 A vertical resonant cavity surface emitting laser diode as claimed in claim 34 or 35, wherein one or a plurality of spacer layers are further included between the two active layers, above and/or below the tunnel junction layer The spacer layer is provided, and the hole confinement layer is provided in the spacer layer.

如請求項37或38所述之一種垂直共振腔表面放射雷射二極體，其中，該兩主動層之間更包含一氧化層；在該穿隧接面層與該氧化層之間、在該穿隧接面層與鄰近於該穿隧接面層的主動層之間或在該氧化層與鄰近於該氧化層的主動層之間設置該間隔層。A vertical resonant cavity surface emitting laser diode as claimed in claim 37 or 38, wherein an oxide layer is further included between the two active layers; between the tunnel junction layer and the oxide layer, The spacer layer is disposed between the tunnel junction layer and the active layer adjacent to the tunnel junction layer or between the oxide layer and the active layer adjacent to the oxide layer.